MOS Transistor Theory

• So far, we have viewed a MOS transistor as an

ideal switch (digital operation)
– Reality: less than ideal

EE 261 James Morizio 1

EE 261 James Morizio 2
 Introduction
• So far, we have treated transistors as ideal
switches
• An ON transistor passes a finite amount of current
– Depends on terminal voltages
– Derive current-voltage (I-V) relationships
• Transistor gate, source, drain all have capacitance
– I = C (∆V/∆t) -> ∆t = (C/I) ∆V
– Capacitance and current determine speed
• Also explore what a “degraded level” really means

EE 261 James Morizio 3

 MOS Transistor Theory
• Study conducting channel between source and drain
• Modulated by voltage applied to the gate (voltage-
controlled device)
• nMOS transistor: majority carriers are electrons
(greater mobility), p-substrate doped (positively doped)
• pMOS transistor: majority carriers are holes (less
mobility), n-substrate (negatively doped)

EE 261 James Morizio 4

 Terminal Voltages
Vg
• Mode of operation depends on Vg, Vd, Vs + +
– Vgs = Vg – Vs Vgs Vgd
- -
– Vgd = Vg – Vd
Vs Vd
– Vds = Vd – Vs = Vgs - Vgd - +
Vds

• Source and drain are symmetric diffusion terminals

– By convention, source is terminal at lower voltage
– Hence Vds ≥ 0
• nMOS body is grounded. First assume source is 0 too.
• Three regions of operation
– Cutoff
– Linear
– Saturation

EE 261 James Morizio 5

 Gate Biasing
Source Gate SiO2 Drain

n+ Channel n+ • Vgs=0: no current flows from

+ - source to drain (insulated by
two reverse biased pn
E junctions
p-substrate • Vgs>0: electric field created
across substrate
VSS (Gnd)
• Electrons accumulate under gate: region changes from p-type
to n-type
• Conduction path between source and drain
EE 261 James Morizio 6
 nMOS
p-substrate
Device
Polysilicon gate
Behavior Inversion
Region
Oxide insulator
(n-type)

Depletion region
Depletion region

Vgs << Vt Vgs = Vt Vgs > Vt

Accumulation Depletion mode Inversion mode
mode
• Enhancement-mode transistor: Conducts when gate bias
Vgs > Vt
• Depletion-mode transistor: Conducts when gate bias is zero
EE 261 James Morizio 7
 nMOS Cutoff
• No channel
• Ids = 0 Vgs = 0 Vgd
+ g +
- -
s d

n+ n+

p-type body
b

EE 261 James Morizio 8

 nMOS Linear
• Channel forms
• Current flows from d to s Vgs > Vt
+ g +
Vgd = Vgs

– e- from s to d - -
s d

• Ids increases with Vds n+ n+ Vds = 0

p-type body
• Similar to linear resistor b

Vgs > Vt
Vgs > Vgd > Vt
+ g +
- - Ids
s d
n+ n+
0 < Vds < Vgs-Vt
p-type body
b

EE 261 James Morizio 9

 nMOS Saturation
• Channel pinches off
• Ids independent of Vds
• We say current saturates
• Similar to current source
Vgs > Vt
g Vgd < Vt
+ +
- -
s d Ids

n+ n+
Vds > Vgs-Vt
p-type body
b

EE 261 James Morizio 10

 I-V Characteristics
• In linear region, Ids depends on
– How much charge is in the channel?
– How fast is the charge moving?

EE 261 James Morizio 11

 Channel Charge
• MOS structure looks like parallel plate capacitor
while operating in inversion
– Gate – oxide – channel
• Qchannel =
gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
channel
tox n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, εox = 3.9) p-type body
p-type body

EE 261 James Morizio 12

 Channel Charge
• MOS structure looks like parallel plate capacitor
while operating in inversion
– Gate – oxide – channel
• Qchannel = CV
• C= gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
channel
tox n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, εox = 3.9) p-type body
p-type body

EE 261 James Morizio 13

 Channel Charge
• MOS structure looks like parallel plate capacitor
while operating in inversion
– Gate – oxide – channel
• Qchannel = CV
• C = Cg = εoxWL/tox = CoxWL Cox = εox / tox

• V=
gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
channel
tox n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, εox = 3.9) p-type body
p-type body

EE 261 James Morizio 14

 Channel Charge
• MOS structure looks like parallel plate capacitor while
operating in inversion
– Gate – oxide – channel
• Qchannel = CV
• C = Cg = εoxWL/tox = CoxWL
Cox = εox / tox
• V = Vgc – Vt = (Vgs – Vds/2) – Vt

gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
channel
tox n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, εox = 3.9) p-type body
p-type body

EE 261 James Morizio 15

 Carrier velocity
• Charge is carried by e-
• Carrier velocity v proportional to lateral E-field
between source and drain
• v=

EE 261 James Morizio 16

 Carrier velocity
• Charge is carried by e-
• Carrier velocity v proportional to lateral E-field
between source and drain
• v = µE µ called mobility
• E=

EE 261 James Morizio 17

 Carrier velocity
• Charge is carried by e-
• Carrier velocity v proportional to lateral E-field
between source and drain
• v = µE µ called mobility
• E = Vds/L
• Time for carrier to cross channel:
– t=

EE 261 James Morizio 18

 Carrier velocity
• Charge is carried by e-
• Carrier velocity v proportional to lateral E-field
between source and drain
• v = µE µ called mobility
• E = Vds/L
• Time for carrier to cross channel:
– t=L/v

EE 261 James Morizio 19

 nMOS Linear I-V
• Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross
I ds =

EE 261 James Morizio 20

 nMOS Linear I-V
• Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross
Qchannel
I ds =
t
=

EE 261 James Morizio 21

 nMOS Linear I-V
• Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross
Qchannel
I ds =
t
W Vds
= µCox Vgs − Vt − Vds
L 2
V W
= β Vgs − Vt − ds Vds β = µCox
2 L

EE 261 James Morizio 22

 nMOS Saturation I-V
• If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
• Now drain voltage no longer increases current
I ds =

EE 261 James Morizio 23

 nMOS Saturation I-V
• If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
• Now drain voltage no longer increases current
V
I ds = β Vgs − Vt − dsat Vdsat
2

EE 261 James Morizio 24

 nMOS Saturation I-V
• If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
• Now drain voltage no longer increases current
Vdsat
I ds = β Vgs − Vt − V
2 dsat
β
( − Vt )
2
= Vgs
2

EE 261 James Morizio 25

 nMOS I-V Summary
• Shockley 1st order transistor models

0 Vgs < Vt cutoff

Vds
I ds = β Vgs − Vt − Vds Vds < Vdsat linear
2
β
( − Vt )
2
V gs Vds > Vdsat saturation
2

EE 261 James Morizio 26

 Current-Voltage Relations

EE 261 James Morizio 27

 Current-Voltage Relations
k n: transconductance of transistor
W : width-to-length ratio
L

• As W increases, more carriers available to conduct current

• As L increases, Vds diminishes in effect (more voltage

drop). Takes longer to push carriers across the transistor,
reducing current flow

EE 261 James Morizio 28

 Example
• For a 0.6 µm process
– From AMI Semiconductor
– tox = 100 Å 2.5
Vgs = 5
– µ = 350 cm2/V*s 2
– Vt = 0.7 V
1.5 Vgs = 4

Ids (mA)
• Plot Ids vs. Vds
1
– Vgs = 0, 1, 2, 3, 4, 5 Vgs = 3
0.5
– Use W/L = 4/2 λ Vgs = 2
Vgs = 1
0
0 1 2 3 4 5
W 3.9 • 8.85 ⋅ 10−14 W W Vds
β = µ Cox = ( 350 ) = 120 µ A / V 2
L 100 ⋅ 10−8 L L

EE 261 James Morizio 29

 pMOS I-V
• All dopings and voltages are inverted for pMOS
• Mobility µp is determined by holes
– Typically 2-3x lower than that of electrons µn
– 120 cm2/V*s in AMI 0.6 µm process
• Thus pMOS must be wider to provide same
current
– In this class, assume µn / µp = 2 to 3

EE 261 James Morizio 30

 Capacitance
• Any two conductors separated by an insulator
have capacitance
• Gate to channel capacitor is very important
– Creates channel charge necessary for operation
• Source and drain have capacitance to body
– Across reverse-biased diodes
– Called diffusion capacitance because it is associated
with source/drain diffusion

EE 261 James Morizio 31

 Gate Capacitance
• Approximate channel as connected to source
• Cgs = εoxWL/tox = CoxWL = CpermicronW
• Cpermicron is typically about 2 fF/µm

polysilicon
gate
W
tox
L SiO2 gate oxide
n+ n+ (good insulator, εox = 3.9ε0)
p-type body

EE 261 James Morizio 32

 The Gate Capacitance

EE 261 James Morizio 33

 Diffusion Capacitance
• Csb, Cdb
• Undesirable, called parasitic capacitance
• Capacitance depends on area and perimeter
– Use small diffusion nodes
– Comparable to Cg
for contacted diff
– ½ Cg for uncontacted
– Varies with process

EE 261 James Morizio 34

 Diffusion Capacitance

EE 261 James Morizio 35

 Parasitic Resistances
Polysilicon gate
Drain
contact
G LD
VGS,eff

S D
W
RS RD

Drain

RS = (LS/W)R + RC RC: contact resistance

RD = (LD/W)R + RC R : sheet resistance per square
of drain-source diffusion
EE 261 James Morizio 36
 Body Effect
• Many MOS devices on a common substrate
– Substrate voltage of all devices are normally equal
• But several devices may be connected in series
– Increase in source-to-substrate voltage as we proceed vertically
along the chain

g2 d2
s2 • Net effect: slight increase
g1 d1 Vsb2 = 0
V12 in threshold voltage Vt,
s1 Vsb1 = 0 Vt2>Vt1
V11

EE 261 James Morizio 37

 Pass Transistors
• We have assumed source is grounded VDD
• What if source > 0? VDD
– e.g. pass transistor passing VDD

EE 261 James Morizio 38

 Pass Transistors
• We have assumed source is grounded VDD
• What if source > 0? VDD
– e.g. pass transistor passing VDD
• Vg = VDD
– If Vs > VDD-Vt, Vgs < Vt
– Hence transistor would turn itself off
• nMOS pass transistors pull no higher than VDD-Vtn
– Called a degraded “1”
– Approach degraded value slowly (low Ids)
• pMOS pass transistors pull no lower than Vtp
EE 261 James Morizio 39
 Pass Transistor Ckts

V DD V DD V DD
V DD V DD
V DD

V DD

V DD
V SS

EE 261 James Morizio 40

 Pass Transistor Ckts

V DD V DD V DD
V DD V DD
V DD
V s = V DD -V tn V DD -V tn
V DD -V tn V DD -V tn

V DD
V s = |V tp | V DD -V tn
V DD V DD -2V tn
V SS

EE 261 James Morizio 41

 Effective Resistance
• Shockley models have limited value
– Not accurate enough for modern transistors
– Too complicated for much hand analysis
• Simplification: treat transistor as resistor
– Replace Ids(Vds, Vgs) with effective resistance R
• Ids = Vds/R
– R averaged across switching of digital gate
• Too inaccurate to predict current at any given time
– But good enough to predict RC delay

EE 261 James Morizio 42

 RC Delay Model
• Use equivalent circuits for MOS transistors
– Ideal switch + capacitance and ON resistance
– Unit nMOS has resistance R, capacitance C
– Unit pMOS has resistance 2R, capacitance C
• Capacitance proportional to width
• Resistance inversely proportional to width
d
s
kC
kC
R/k
d 2R/k
d
g k g kC
g k g
s kC kC
kC s
s
d

EE 261 James Morizio 43

 RC Values
• Capacitance
– C = Cg = Cs = Cd = 2 fF/µm of gate width
– Values similar across many processes
• Resistance
– R ≈ 6 KΩ in 0.6um process
– Improves with shorter channel lengths
• Unit transistors
– May refer to minimum contacted device (4/2 λ)
– Or maybe 1 µm wide device
– Doesn’t matter as long as you are consistent

EE 261 James Morizio 44

 Activity
1) If the width of a transistor increases, the current will
increase decrease not change
2) If the length of a transistor increases, the current will
increase decrease not change
3) If the supply voltage of a chip increases, the maximum transistor
current will
increase decrease not change
4) If the width of a transistor increases, its gate capacitance will
increase decrease not change
5) If the length of a transistor increases, its gate capacitance will
increase decrease not change
6) If the supply voltage of a chip increases, the gate capacitance of each
transistor will
increase decrease not change

EE 261 James Morizio 45

 Activity
1) If the width of a transistor increases, the current will
increase decrease not change
2) If the length of a transistor increases, the current will
increase decrease not change
3) If the supply voltage of a chip increases, the maximum transistor
current will
increase decrease not change
4) If the width of a transistor increases, its gate capacitance will
increase decrease not change
5) If the length of a transistor increases, its gate capacitance will
increase decrease not change
6) If the supply voltage of a chip increases, the gate capacitance of each
transistor will
increase decrease not change

EE 261 James Morizio 46

 DC Response
• DC Response: Vout vs. Vin for a gate
• Ex: Inverter
– When Vin = 0 -> Vout = VDD
– When Vin = VDD -> Vout = 0 VDD
– In between, Vout depends on
Idsp
transistor size and current Vin Vout
– By KCL, must settle such that Idsn
Idsn = |Idsp|
– We could solve equations
– But graphical solution gives more insight

EE 261 James Morizio 47

 Transistor Operation
• Current depends on region of transistor behavior
• For what Vin and Vout are nMOS and pMOS in
– Cutoff?
– Linear?
– Saturation?

EE 261 James Morizio 48

 nMOS Operation
Cutoff Linear Saturated
Vgsn < Vgsn > Vgsn >

Vdsn < Vdsn >

VDD

Idsp
Vin Vout
Idsn

EE 261 James Morizio 49

 nMOS Operation
Cutoff Linear Saturated
Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn

Vdsn < Vgsn – Vtn V > V – V

dsn gsn tn

VDD

Idsp
Vin Vout
Idsn

EE 261 James Morizio 50

 nMOS Operation
Cutoff Linear Saturated
Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn

Vdsn < Vgsn – Vtn V > V – V

dsn gsn tn

VDD
Vgsn = Vin Idsp
Vin Vout
Vdsn = Vout Idsn

EE 261 James Morizio 51

 nMOS Operation
Cutoff Linear Saturated
Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn
Vin < Vtn Vin > Vtn Vin > Vtn
Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn
Vout < Vin - Vtn Vout > Vin - Vtn

VDD
Vgsn = Vin Idsp
Vin Vout
Vdsn = Vout Idsn

EE 261 James Morizio 52

 pMOS Operation
Cutoff Linear Saturated
Vgsp > Vgsp < Vgsp <

Vdsp > Vdsp <

VDD

Idsp
Vin Vout
Idsn

EE 261 James Morizio 53

 pMOS Operation
Cutoff Linear Saturated
Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp

Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp

VDD

Idsp
Vin Vout
Idsn

EE 261 James Morizio 54

 pMOS Operation
Cutoff Linear Saturated
Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp

Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp

VDD
Vgsp = Vin - VDD Vtp < 0 Idsp
Vin Vout
Vdsp = Vout - VDD Idsn

EE 261 James Morizio 55

 pMOS Operation
Cutoff Linear Saturated
Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp
Vin > VDD + Vtp Vin < VDD + Vtp Vin < VDD + Vtp
Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp
Vout > Vin - Vtp Vout < Vin - Vtp

VDD
Vgsp = Vin - VDD Vtp < 0 Idsp
Vin Vout
Vdsp = Vout - VDD Idsn

EE 261 James Morizio 56

 I-V Characteristics
• Make pMOS wider than nMOS such that βn = βp
Vgsn5

Vgsn4
Idsn

Vgsn3
-Vdsp
-VDD Vgsn2
Vgsp1 Vgsn1
Vgsp2 0 VDD
Vgsp3 Vdsn

Vgsp4 -Idsp

Vgsp5

EE 261 James Morizio 57

 DC Transfer Curve
• Transcribe points onto Vin vs. Vout plot
VDD
A B

Vout
C

D
E
0 Vtn VDD/2 VDD+Vtp
VDD
Vin

EE 261 James Morizio 58

 Operating Regions
• Revisit transistor operating regions
VDD
Region nMOS pMOS
A B
A
Vout
B C

C
D D
E
0
E Vtn VDD/2 VDD+Vtp
VDD
Vin

EE 261 James Morizio 59

 Operating Regions
• Revisit transistor operating regions
Region nMOS pMOS VDD
A B
A Cutoff Linear
Vout
B Saturation Linear C
C Saturation Saturation
D Linear Saturation D
E
0
E Linear Cutoff Vtn VDD/2 VDD+Vtp
VDD
Vin

EE 261 James Morizio 60

 Beta Ratio
• If βp / βn ≠ 1, switching point will move from VDD/2
• Called skewed gate
• Other gates: collapse into equivalent inverter

VDD
βp
= 10
βn
Vout 2
1
0.5
βp
= 0.1
βn

0
VDD
Vin

EE 261 James Morizio 61

 Noise Margins
• How much noise can a gate input see before it
does not recognize the input?

Output Characteristics Input Characteristics

VDD
Logical High
Output Range VOH Logical High
Input Range
NMH
VIH
Indeterminate
VIL Region
NML
Logical Low
Logical Low VOL Input Range
Output Range
GND

EE 261 James Morizio 62

 Logic Levels
• To maximize noise margins, select logic levels at
Vout

VDD

βp/β n > 1

Vin Vout

Vin
0
VDD

EE 261 James Morizio 63

 Logic Levels
• To maximize noise margins, select logic levels at
– unity gain point of DC transfer characteristic
Vout

Unity Gain Points

VDD
Slope = -1
VOH

βp/β n > 1

Vin Vout

VOL
Vin
0
Vtn VIL VIH VDD- VDD
|Vtp|

EE 261 James Morizio 64

EE 261 James Morizio 65