6.

884 Lab Assignment 1, Spring 2005

pc_sel

4 pc_seq
Execute Stage

pc_branch

rd1[31] (bsign)
pc_f {14(inst_x[15])}
inst_x[15:0] reset_vec pc_next
Decoder
2’b0
Figure 5: SMIPS 2-Stage Pipeline Datapath for Lab 1.

except_vec

bneq
pc_f[31:28]
pc_jump
inst_x[25:0]
pc_jr
2’b0

logic_func
31
[15:11]

[20:16]
[20:16]
[25:21]

shift_func
alu_func
dest_sel

a_sel

wb_sel
Instruction
Memory inst_x

ra2
ra1
wa
iaddr inst rd1
16
Register
File shamt

Logic Unit
wd

Add/Sub

Shifter
wen
Fetch Stage rd2

inst_x[10:6]

inst_x[15]

imm_sel
Data
inst_x[15:0] addr
Memory
store_data
wdata rdata
signext_sel

wen

wen
tohost[7:0]
fromhost[7:0]
wen

System Coprocessor 0