VHDL 1

UNIVERSIDAD NACIONAL DE LOJA
Facultad de la Energía las Industrias y los Recursos Naturales no Renovables
DIGITAL DESIGN
VHDL
gaston.chamba@unl.edu.ec
Carrera de Ingenieria en Sistemas – UNL
Bloque 3.2 FEIRNNR – Loja - Ecuador
1
Implementation technology
Logic variables can be physically represented as signal in

electronics circuits, which can take on only the values 0
and 1.
These values can be represented either as levels of voltage

or current, both alternatives are used in different
technologies; the most popular representation is using
voltage levels.
The most obvious way for representation two logic values

as voltage levels is to define a threshold voltage.
2
INGENIERÍA EN SISTEMAS ABRIL- SEPTIEMBRE 2018
Implementation technology
Usually, logic 0 is represented by the low voltage levels

and logic 1 by the high voltages.
This is known as a positive logic system, the logic values o

and 1 are referred to simply as “low” and “high”.
The mínimum voltage is called Vss and the maximum

voltage is called Vdd.
The most common levels for Vdd are between 5 volts and
1 volt.
3
Transistor switches
Logic circuits are built with transistors. For the purpose of understanding how logic circuits are built, we can assume
that a transistor operates as a simple switch.
The most popular type of transistor for implementing a simple switch is the metal oxide semiconductor field-effect
transistor (MOSFET)
There are two different types of MOSFETs, known as n-channel, abbreviated NMOS, and p-channel, denoted PMOS
4
Transistor switches
In NMOS transistor if 𝑉𝐺 is low, then there is no connection between the source and drain,
and we say that the transistor is turned off. If 𝑉𝐺 is high, then the transistor is turned on and
acts as an closed switch that connects the source and drain terminals.
PMOS transistor have the opposite behavior of NMOS transistors.
5
Transistor switches
An NMOS transistor is turned on when its gate terminal is high, while a PMOS transistor is turned on when its
gate is low.
When the NMOS transistor is turned on, its drain is pulled down to GNG, and when the PMOS transistor is
turned on, its drain is pulled up to 𝑉𝐷𝐷
6
Transistor switches: physical structure of an NMOS transistor
7
Transistor switches: physical structure of an NMOS transistor
8
NMOS logic gates
The first schemes for building logic gates with MOSFETS became popular in the 1970s and relied on
either PMOS or NMOS transistors, but not both.
Since the early 1980s, a combination of both NMOS and PMOS transistors has been used.
In the circuit in the figure, when 𝑉𝑥 = 0 𝑉, the NMOS
transistor is turned off. No current flows through the
resistor R, and 𝑉𝑓 = 5 𝑉.
On the other hand, when 𝑉𝑥 = 5 𝑉, the transistor is

turned on and pulls 𝑉𝑓 to a low voltage level.
The exact voltage level of 𝑉𝑓 in this case depends on the

amount of current that flows through the resistor and
transistor.
9
NMOS logic gates
If 𝑉𝑓 is viewed as a function of 𝑉𝑥 , then the circuit is an NMOS implementation of a NOT gate.
The figure shows a simplified circuit

diagram in which the connection to the
positive terminal on the power supply is
indicated by an arrow labeled 𝑉𝐷𝐷 and
the connection to the negative power-
supply terminal is indicated by the GND
symbol
10
NMOS logic gates
The purpose of the resistor is to limit the amount of current that flows when 𝑉𝑥 = 5𝑉 . Rather than using
a resistor for this purpose, a transistor is normally used, a dashed box is drawn around the resistor as a
reminder that it is implemented using a transistor.
11
NMOS logic gates
A series connection of switches corresponds to the

logic NAND function.
12
NMOS logic gates
A parallel connection of switches corresponds to

the logic NOR function.
13
NMOS logic gates
An AND gate is built in NMOS technology by

following a NAND gate with an inverter.
14
NMOS logic gates
An OR gate is built in NMOS technology by following

a NOR gate with an inverter.
15
CMOS logic gates
For each of the circuits that has been presented, it is possible to derive an equivalent circuit that
uses PMOS transistors. However, it is more interesting to considerer how both NMOS and PMOS
transistors can be used together.
In CMOS technology we will refer to the part of the circuit that involves NMOS transistors as the
pull-down network (PDN).
16
CMOS logic gates
The concept of CMOS circuits is based on replacing the pull-up device with a
pull-up network that is built using PMOS transistors, such that the functions
realized by the PDN and PUN networks are complements of each other
17
CMOS logic gates
For any given evaluation of the inputs signals, either the PDN pulls 𝑉𝑓 down to GND or the PUN
pulls 𝑉𝑓 up to 𝑉𝐷𝐷 .
The PDN has NMOS transistors in series, the PUN has PMOS transistors in parallel, and vice versa.
18
CMOS logic gates
19
CMOS logic gates
The PDN has NMOS transistors in series, the PUN has PMOS
transistors in parallel.
20
CMOS logic gates
The PDN has NMOS transistors in parallel, the PUN has PMOS
transistors in series.
21
Standard Chips: 7400-Series Standard Chips
An approach used widely until the mid-1980s was to connect together multiple chips, each containing
only a few logic gates.
They are known as 7400-series parts because the chip part numbers always begin with the digits 74.
The figure shows a type of package that the chip is provided in, called a dual-inline package (DIP)
22
Standard Chips: 7400-Series Standard Chips
For each specific 7400-series chip, several variants are built with different technologies, for
instance, the part called 74LS00 is built with a technology called transistor-transistor logic
(TTL).
Whereas the 74HC00 is fabricated using CMOS technology. In general, the most popular
chips used today are the CMOS variants.
The function provided by each 7400-series device is fixed and each chip only provides a few
logic gates, these limitation make use of these chips inefficient for building large circuits.
23
Implementation of 𝐟 = 𝒙𝟏 𝒙𝟐 + 𝒙𝟐 𝒙𝟑
24
Programmable Logic Device
The function provided by each of the 7400-series parts is fixed and cannot be tailored to suit a particular design situation.
It is possible to manufacture chips that contain relatively large amounts of logic circuitry with a structure that is not fixed. Such
chips were first introduced in the 1970s and are called programmable logic devices (PLDs)
A PLD contains a collection of logic circuit

elements that can be customized in different
ways.
A PLD can be viewed as a “black box” that

contains logic gates and programmable
switches.
The programmable switches allow the logic

gates inside the PLD to be connected together
25
Programmable Logic Array (PLA)
Several types of PLDs are commercially available.

The first developed was the programmable logic
array (PLA).
A PLA comprises a collection of AND gates that

feeds a set of OR gates.
PLA’s inputs 𝑥1 , … , 𝑥𝑛 pass through a set of buffers

into a circuit block called an AND plane, or AND
array.
The AND plane produces a set of product terms

𝑃1 , … , 𝑃𝑘
26
Each of these terms can be configured to

implement any AND function of 𝑥1 , … , 𝑥𝑛 .
The product terms serve as the inputs to an OR

plane, which produces the outputs 𝑓1 , … , 𝑓𝑚 .
Each output can be configured to realize any sum

of 𝑃1 , … , 𝑃𝑘 and hence any sum-of-products
function of the PLA inputs.
27
In figure the AND gates produces:
𝑃1 = 𝑥1 𝑥2 𝑃2 = 𝑥1 𝑥3 ,
𝑃3 = 𝑥1 𝑥2 𝑥3 𝑃4 = 𝑥1 𝑥3
And the OR gates produces:
𝑓1 = 𝑥1 𝑥2 + 𝑥1 𝑥3 + 𝑥1 𝑥2 𝑥3
𝑓1 = 𝑥1 𝑥2 + 𝑥1 𝑥2 𝑥3 + 𝑥1 𝑥3
The only constraint on the functions that can be

implemented is the size of the AND plane.
Commercially available PLAs come in larger sizes,

typical parameters are 16 inputs, 32 products terms,
and eight outputs.
28
In previous slide, the style of drawing is

awkward for larger chips.
Instead, it is better to use the style showing in

the figure.
The PLA is efficient in terms of the area

needed for its implementations on an
integrated circuit chip. For these reason, PLA
are often included as part of larger chips, such
as microprocessors.
29
Programmable Array Logic (PAL)
In a PLA both the AND and OR planes are programmable, that presented two difficulties for
manufacturers of these devices:
They were hard to fabricate correctly

They reduced the speed-performance of circuits implemented in the PLAs.
These drawbacks led to the development of a similar device in which the AND plane is
programmable, but the OR plane is fixed.
Such a chip is known as a programmable array logic (PAL) device.
30
The product terms 𝑃1 and 𝑃2 are

hardwired to one OR gate, and 𝑃3 and 𝑃4
are hardwired to the other OR gate.
The PAL is shown programmed to realize

the two logic function:
𝑓1 = 𝑥1 𝑥2 𝑥3 + 𝑥1 𝑥2 𝑥3
𝑓2 = 𝑥1 𝑥2 + 𝑥1 𝑥2 𝑥3
31
PAL offers less flexibility; the PLA

allows up to four product terms per OR
gate, whereas the OR gates in the PAL
have only two inputs.
To compensate for the reduced flexibility,

PALs are manufactured in a range of
sizes, with various numbers of inputs and
outputs, and different numbers of inputs
to the OR gates.
32
So far we have assumed that the OR gates in

a PAL, as in a PLA, connected directly to the
input pins of the chip.
In many PALs extra circuitry is added at the

output of each OR gate to provide additional
flexibility.
It is customary to use the term macrocell to

refer to the OR gate combined with the extra
circuitry
33
VHDL: Introduction
VHDL is a hardware description languaje. It describes the behavior of an electronic circuit

or system, from which the physical circuit or system can then be implemented.
VHDL stands for VHSIC Hardware Description Languaje. VHSIC is itself an abbreviation
for Very High Speed Integrated Circuits, an initiative funded by the United States
Department of Defense in the 1980s that led to the creation of VHDL.
VHDL was the original and first hardware description language to be standardized by the
Institute of Electrical and Electronics Engineers, through the IEEE 1076 standard.
An additional standard, the IEEE 1164, was later added to introduce a multi-valued logic
system.
34
VHDL: Introduction
VHDL is NOT a programming language; is a language of HARDWARE DESCRIPTION.
VHDL is used to write Synthesis is used to

code to simulate the implement the
behavior of the design hardware in the FPGA
35
VHDL: Introduction
The two main immediate applications of VHDL are in the field of Programmable Logic Devices
(CPLDs – Complex Programmable Logic Devices and FPGAs – Field Programmable Gate Arrays)
and in the field of ASICs (Application Specific Integrated Circuits).
Once the VHDL has been written, it can be used either to implement the circuit in a programmable
device (from Altera, Xilinx, Atmel, etc.).
VHDL contrary to regular computer programs which are sequential, its statements are inherently
concurrent. For that reason, VHDL is usually referred to as a code rather than a program.
In VHDL only statements placed inside a PROCESS, FUNCTION, or PROCEDURE are executed
sequentially.
36
VHDL: Design Flow
We start the design by writing the VHDL

code, which is saved in a file with the
extension .vhd and the same name as its
ENTITY’s name.
The first step in the synthesis process is

compilation. Compilation is conversion of
the high-level VHDL languaje, which
describes the circuit at the Register Transfer
Level (RTL), into a netlist at the gate level.
37
VHDL: Design Flow
The second step is optimization, which is

performed on the gate-level netlist for
speed or for area. At this stage, the design
can be simulated.
Finally, a placed and route software will

generate the physical layout for a
PLD/FPGA chip.
38
Fundamental VHDL Units
A standalone piece of VHDL code is

composed of at least three fundamental
sections:
LIBRARY declarations: Contains a list of
all libraries to be used in the design. For
example: ieee, std, work, etc.
ENTITY: Specifies the I/O pins of the

circuit.
ARCHITECTURE: Contains the VHDL

code proper, which describes how the
circuit should behave (function)
39
Library Declarations
To declare a LIBRARY two lines of code are needed, one containing the name of the
library, and the other a use clause
At least three packages, from three different libraries, are usually needed in a design:
40
Their declarations are as follows: A semi-colon ( ; ) indicates the end of a statement

or declaration.
A double dash ( - - ) indicates a comment.
The libraries std and work shown are made visible

by default, so there is no need to declare them;
only the ieee library must be explicitly written.
However, the library ieee is only necessary when

the STD_LOGIC (or STD_ULOGIC) data type in
employed.
41
The purpose of the three packages/libraries is the following:
The std_logic_1164 package of the ieee library

specifies a multi-level logic system.
The std is a resource library (data types, text i/o,

etc.) for the VHDL design environment.
The work library is where we save our design (the

.vhd file, plus all files created by the compiler,
simulator, etc.)
42
ENTITY
An ENTITY is a list with specifications of all input and output pins (PORTS) of the circuit
The mode of the signal can be IN,

OUT, INOUT, or BUFFER.
IN and OUT are truly unidirectional

pins, while INOUT is bidirectional.
BUFFER is employed when the
signal must be used internally.
The type of the signal can be BIT, STD_LOGIC, INTEGER, etc.
Finally, the name of the entity can be basically any name, except VHDL reserved words.
43
ENTITY
Let us consider the NAND gate. Its ENTITY can be specified as:
The meaning of the ENTITY above is the following: the circuit has three I/O pins, being
two inputs (a and b, mode IN) and one output (x, mode OUT). All three signals are of
type BIT. The name chosen for the entity was nand_gate.
44
ARCHITECTURE
The ARCHITECTURE is a description of how the circuit should behave (function)
An architecture has two parts: a declarative part (optional), where signals and constants
(among others) are declared, an the code part (from BEGIN down). The name of an
architecture can be basically any name (except VHDL reserve words), including the
same name as the entity’s.
45
ARCHITECTURE
Let us consider the NAND gate once again
The meaning of the ARCHITECTURE above is the following: the circuit must perform
the NAND operation between the two input signals (a,b) and assign (“<=”) the result to
the output pin (x). The name chosen for this architecture was myarch. In this example,
there is no declarative part, and the code contains just a single assignment.
46
ARCHITECTURE
Let us consider the NAND gate once again
The meaning of the ARCHITECTURE above is the following: the circuit must perform
the NAND operation between the two input signals (a,b) and assign (“<=”) the result to
the output pin (x). The name chosen for this architecture was myarch. In this example,
there is no declarative part, and the code contains just a single assignment.
47
Identifiers
A basic identifier:
May only contain alphabetic letters (A to Z and a to z), decimal digits (0 to 9) and the underline
character (_)
Must start with an alphabetic letter
May not end with an underline character
 May not include two successive underline characters
VHDL is not case-sensitive
No blank space(s) are allowed
Examples
Same identifier
Txclk, TxClk, TXCLK, TxCLK
Legal identifiers
Rst, Three_State_Enable, CS_244, Sel7D
Illegal identifiers
_Set, 80X86, large#bits, m__RAM, add_
48
Data Types:
Pre-Defined Data Types (specified through the IEEE 1076 and IEEE 1164 standards)
Package standard of library std: Defines BIT, BOOLEAN, INTEGER, and REAL data types:
BIT
Based on the signals showing in the

left side, the following assignments
would be legal (to assign a value to a
signal, the “<=” operator must be
used):
x <= ‘1’: x is a single-bit signal, whose value is ‘1’. Notice that single quotes (‘ ’) are used for a
single bit.
y <= “0111”: y is a 4-bit signal, whose value is “0111” (MSB=‘0’). Notice that double quotes (“ ”)
are used for vectors.
w <= “01110001”: w is an 8-bit signal, whose value is “01110001” (MSB=‘1’)
49
Data Types:
STD_LOGIC (and STD_LOGIC_VECTOR): 8-valued logic system introduced in the IEEE

1164 standard.
‘X’ Forcing Unknown (synthesizable unknown)

‘0’ Forcing Low (synthesizable logic ‘1’)
‘1’ Forcing High (synthesizable logic ‘0’)
‘Z’ High Impedance (synthesizable tri-state buffer)
‘W’ Weak unknown
‘L’ Weak low
‘H’ Weak high
‘_’ Don’t care
50
Data Types:
STD_LOGIC (and STD_LOGIC_VECTOR): 8-valued logic system introduced in the IEEE 1164 standard.
x is declared as a one-digit (scalar) signal of type

STD_LOGIC.
y is declared as a 4-bit vector, with the leftmost

bit being the MSB. The initial value (optional) of
y is “0001”. Notice that the “:=” operator is used
to establish the initial value
51
Writing simple VHDL code
Consider the logic circuit show in figure below
If we wish to write VHDL code to represent this circuit the first step is to declare the input
and output signals.
This done using a construct called an entity
52
An appropriate entity for this example is:
ENTITY example1 IS
PORT (x1, x2, x3 : IN BIT;
f : OUT BIT);
END example1;
An entity must be assigned a name; in this case we have chosen the name example1.
The input and output signals for the entity are called its ports, and thy are identified by the
keyword PORT.
53
ENTITY example1 IS
f : OUT BIT);
END example1;
From the electrical jargon the word port refers to an input or output connection to an
electronic circuit.
Each port has an associated mode that specifies whether it is an input (IN) to the entity or an
output (OUT) from the entity.
Each port represents a signal, hence it has an associated type.

54
ENTITY example1 IS
f : OUT BIT);
END example1;
The entity example1 has four ports in total. The first three, x1, x2, and x3, are inputs signals of type
BIT. The port named f is an output of type BIT.
VHDL has rules that specify which characters are allowed in signals names. A simple guideline is
that signal names can include any letters or number, as well as the underscore character ‘_’.
There are two caveats: a signal name must begin with a letter, and a signal name cannot be a VHDL
keyword.
55
ARCHITECTURE LogicFunc OF example1 IS

BEGIN
f < = (x1 AND x2) OR (NOT x2 AND x3);
END LogicFunc;
An entity specifies the input and output signals for a circuit, but it does not give any details
as to what the circuit represent.
The circuit’s functionality must be specified with a VHDL construct called an architecture.
In the architecture for our example we have chosen the name LogicFunc.
56

BEGIN
END LogicFunc;
VHDL has built-in support for the following Boolean operators: AND, OR, NOT, NAND,
NOR, XOR and XNOR.
Following the BEGIN keyword, our architecture specifies, using the VHDL signal
assignment operator <=, that output f should be assigned the result of the logic expression on
the right-hand side of the operator.
57
ENTITY example1 IS
f : OUT BIT);
END example1;

BEGIN
END LogicFunc; A simple analogy for what section
represents is that the Entity is
equivalent to a symbol in a schematic
Complete VHDL code for the circuit diagram and the Architecture specifies
the logic circuitry inside the symbol
58
DFF (D-type flip-flop) with Asynchronous Reset
Figure shows the diagram of a D-type flip-flop (DFF), triggered at

the rising-edge of the clock signal (clk), and with an asynchronous
reset input (rst). When rst = ‘1’, the output must be turned low,
regardless of clk.
If we wish to write VHDL code to represent this circuit the first step is to declare the input
and output signals.
This done using a construct called an entity
59
RIPPLE CARRY ADDER
To perform addition by hand, we start from the least-significant digit and add pairs of digits,
progressing to the most-significant digit.
If a carry is produced in position i, then this carry is added to the operands in position i+1.
The same arrangement can be used in a logic circuit that performs additions.
60
RIPPLE CARRY ADDER
For each bit position we can use a full-adder circuit, connected as shown in figure.
The least-significant bit position is on the right. Carries that are produced by the full-adders
propagate to the left.
61
RIPPLE CARRY ADDER
When the operands X and Y are applied as input to the adder, it takes some time before the
output sum, S, is valid.
Each full-adder introduces a certain delay before its 𝑠𝑖 and 𝑐𝑖+1 outputs are valid. Let this
delay be denoted as ∆𝑡
62
RIPPLE CARRY ADDER
Thus the carry-out from the first stage, 𝑐1 , arrives at the second stage ∆𝑡 after the application
of the 𝑥0 and 𝑦0 inputs.
The carry-out from the second stage, 𝑐2 , arrives at the third stage with a 2∆𝑡 delay, and so
on.
63
RIPPLE CARRY ADDER
The signal 𝑐𝑛−1 is valid after a delay of (n − 1)∆𝑡, which means that the complete sum is
available after a delay of n∆𝑡.
Because of the way the carry signals “ripple” through the full-adder stages, the circuit is
called a ripple-carry adder.
64
DESIGN OF RIPPLE CARRY ADDER USING VHDL
An obvious way to create an n-bit adder is to draw a hierarchical schematic that contains n
full-adders. This approach can also be followed by using VHDL, by first creating a VHDL
entity for a full-adder and then creating a higher-level entity that uses four instances of the
full-adder
65
An obvious way to create an n-bit adder is to draw a hierarchical schematic that contains n
full-adders. This approach can also be followed by using VHDL, by first creating a VHDL
entity for a full-adder and then creating a higher-level entity that uses four instances of the
full-adder.
66
A full-adder circuit is a combinational circuit that produces the arithmetic addition of three
input bits, where the first and second bit represents the addends, and the third bit represents
the carry from the previous lower significant bit position.
67
The complete code for a full-adder entity is given that:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fulladd IS
PORT ( Cin, x, y : IN STD_LOGIC;
s, Cout : OUT STD_LOGIC);
END fulladd;
It has the inputs 𝐶𝑖𝑛 , 𝑥 and 𝑦
ARCHITECTURE LogicFunc OF fulladd IS and produces the outputs 𝑠
BEGIN and 𝐶𝑜𝑢𝑡 . The sum, 𝑠, and
s <= x XOR y XOR Cin;
carry-out, 𝐶𝑜𝑢𝑡 , are described
Cout <= (x AND y) OR (Cin AND x) OR (Cin AND y);
by logic equations.
END LogicFunc;
68
LIBRARY ieee;
We now need to create a separate VHDL entity
USE ieee.std_logic_1164.all; for the ripple-carry adder, which uses the fulladd
ENTITY adder4 IS entity as a subcircuit.
PORT ( Cin : IN STD_LOGIC;
x3, x2, x1, x0 : IN STD_LOGIC;
y3, y2, y1, y0 : IN STD_LOGIC;
s3, s2, s1, s0 : OUT STD_LOGIC; The code for a four-bit ripple-carry adder entity is
Cout : OUT STD_LOGIC);
END adder4; called adder4 . One of the four-bit numbers to be
ARCHITECTURE Structure OF adder4 IS added is represented by the four signals 𝑥3 , 𝑥2 ,
SIGNAL c1, c2, c3 : STD_LOGIC;
COMPONENT fulladd 𝑥1 , 𝑥0 , and the other number is represented by
PORT (Cin, x, y : IN STD_LOGIC ;
s, Cout : OUT STD_LOGIC ); 𝑦3 , 𝑦2 , 𝑦1 , 𝑦0 . The sum is represented by 𝑠3 , 𝑠2 ,
END COMPONENT;
BEGIN 𝑠1 , 𝑠0 ,
stage0: fulladd PORT MAP (Cin, x0, y0, s0, c1);
stage1: fulladd PORT MAP (c1, x1, y1, s1, c2);
stage0: fulladd PORT MAP (
Cin => c3, Cout => Cout, x => x3, y => y3, s =>s3);
END Structure;
69
LIBRARY ieee; Observe that the architecture body has the name
Structure. We chose this name because the style of code
ENTITY adder4 IS in which a circuit is described in a hierarchical fashion,
PORT ( Cin : IN STD_LOGIC;
x3, x2, x1, x0 : IN STD_LOGIC; by connecting together subcircuits, is usually called the
y3, y2, y1, y0 : IN STD_LOGIC; structural style.
s3, s2, s1, s0 : OUT STD_LOGIC;
Cout : OUT STD_LOGIC);
END adder4; Signals can also be declared preceding the BEGIN
ARCHITECTURE Structure OF adder4 IS keyword in the architecture body. The three signals
SIGNAL c1, c2, c3 : STD_LOGIC; declared, called 𝑐1 , 𝑐2 and 𝑐3 , are used as carry-out
COMPONENT fulladd
PORT (Cin, x, y : IN STD_LOGIC ; signals from the first three stages of the adder.
s, Cout : OUT STD_LOGIC );
END COMPONENT;
BEGIN
The next statement is called component declaration
stage0: fulladd PORT MAP (Cin, x0, y0, s0, c1); statement. It uses syntax similar to that in an entity
stage1: fulladd PORT MAP (c1, x1, y1, s1, c2); declaration. This statement allows the fulladd entity to
stage0: fulladd PORT MAP ( be used as a component (subcircuit) in the architecture
Cin => c3, Cout => Cout, x => x3, y => y3, s =>s3); body.
END Structure;
70
LIBRARY ieee;
The four-bit adder is described using four
ENTITY adder4 IS
PORT ( Cin : IN STD_LOGIC; instantiation statements. Each statement begins
x3, x2, x1, x0 : IN STD_LOGIC;
y3, y2, y1, y0 : IN STD_LOGIC; with an instance name, which can be any legal
s3, s2, s1, s0 : OUT STD_LOGIC;
Cout : OUT STD_LOGIC); VHDL name, followed by the colon character.
END adder4;
The names must be unique.
ARCHITECTURE Structure OF adder4 IS
COMPONENT fulladd
PORT (Cin, x, y : IN STD_LOGIC ;
The least-significant stage in the adder is names
s, Cout : OUT STD_LOGIC ); stage0, and the most-significant stage is stage3.
END COMPONENT;
BEGIN
Cin => c3, Cout => Cout, x => x3, y => y3, s =>s3);
END Structure;
71
ARCHITECTURE Structure OF adder4 IS The colon later of the instance name is

COMPONENT fulladd
followed by the name of the component,
PORT (Cin, x, y : IN STD_LOGIC ; fulladd, and then the keyword PORT MAP.
END COMPONENT;
BEGIN The signal names in the adder4 entity that are
stage0: fulladd PORT MAP (Cin, x0, y0, s0, c1); to be connected to each input and output port
stage2: fulladd PORT MAP (c2, x2, y2, s2, c3); on the fulladd component are then listed.
Cin => c3, Cout => Cout, x => x3, y => y3, s =>s3); Observe than in the first three instantiation
END Structure;
statements, the signals are listed in the same
order as in the fulladd COMPONENT
declaration statement, namely, the order
𝐶𝑖𝑛 , 𝑥, 𝑦, 𝑠, 𝐶𝑜𝑢𝑡
72
ARCHITECTURE Structure OF adder4 IS It is also possible to list the signal names in other
SIGNAL c1, c2, c3 : STD_LOGIC; orders by specifying explicitly which signal is to be
COMPONENT fulladd connected to which port on the component. An
PORT (Cin, x, y : IN STD_LOGIC ; example of this style is shown for the stage3
s, Cout : OUT STD_LOGIC ); instance.
END COMPONENT;
BEGIN This style of component instantiation is known as
stage0: fulladd PORT MAP (Cin, x0, y0, s0, c1); named association in the VHDL jargon, whereas the
stage1: fulladd PORT MAP (c1, x1, y1, s1, c2); style used for the other three instances is called
stage2: fulladd PORT MAP (c2, x2, y2, s2, c3); positional association.
Cin => c3, Cout => Cout, x => x3, y => y3, s =>s3); Note that for the stage3 instance, the signal mane
END Structure; 𝐶𝑜𝑢𝑡 is used as both the name of the component port
and the name of the signal in the adder4 entity. This
does not cause problem for the VHDL compiler,
because the component port name is always the one
on the left side of the => characters.
73
ARCHITECTURE Structure OF adder4 IS The signal names associated with each

COMPONENT fulladd instance of the fulladd component
PORT (Cin, x, y : IN STD_LOGIC ; implicitly specify how the full-adders are
END COMPONENT; connected together.
BEGIN
stage1: fulladd PORT MAP (c1, x1, y1, s1, c2); For example, the carry-out of the stage0
instance is connected to the carry-in of
Cin => c3, Cout => Cout, x => x3, y => y3, s =>s3); the stage1 instance.
END Structure;
When the code is analyzed by the VHDL

compiler, it automatically searches for the
code to use for the fulladd component.
74

VHDL 1

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UNIVERSIDAD NACIONAL DE LOJA

Facultad de la Energía las Industrias y los Recursos Naturales no Renovables

Logic variables can be physically represented as signal in

These values can be represented either as levels of voltage

The most obvious way for representation two logic values

Usually, logic 0 is represented by the low voltage levels

This is known as a positive logic system, the logic values o

The mínimum voltage is called Vss and the maximum

PMOS transistor have the opposite behavior of NMOS transistors.

On the other hand, when 𝑉𝑥 = 5 𝑉, the transistor is

The exact voltage level of 𝑉𝑓 in this case depends on the

If 𝑉𝑓 is viewed as a function of 𝑉𝑥 , then the circuit is an NMOS implementation of a NOT gate.

The figure shows a simplified circuit

A series connection of switches corresponds to the

A parallel connection of switches corresponds to

An AND gate is built in NMOS technology by

An OR gate is built in NMOS technology by following

A PLD contains a collection of logic circuit

A PLD can be viewed as a “black box” that

The programmable switches allow the logic

Several types of PLDs are commercially available.

A PLA comprises a collection of AND gates that

PLA’s inputs 𝑥1 , … , 𝑥𝑛 pass through a set of buffers

The AND plane produces a set of product terms

Each of these terms can be configured to

The product terms serve as the inputs to an OR

Each output can be configured to realize any sum

In figure the AND gates produces:

And the OR gates produces:

The only constraint on the functions that can be

Commercially available PLAs come in larger sizes,

In previous slide, the style of drawing is

Instead, it is better to use the style showing in

The PLA is efficient in terms of the area

They were hard to fabricate correctly

Such a chip is known as a programmable array logic (PAL) device.

The product terms 𝑃1 and 𝑃2 are

The PAL is shown programmed to realize

PAL offers less flexibility; the PLA

To compensate for the reduced flexibility,

So far we have assumed that the OR gates in

In many PALs extra circuitry is added at the

It is customary to use the term macrocell to

VHDL is a hardware description languaje. It describes the behavior of an electronic circuit

VHDL is NOT a programming language; is a language of HARDWARE DESCRIPTION.

VHDL is used to write Synthesis is used to

We start the design by writing the VHDL

The first step in the synthesis process is

The second step is optimization, which is

Finally, a placed and route software will

A standalone piece of VHDL code is

ENTITY: Specifies the I/O pins of the

ARCHITECTURE: Contains the VHDL

Their declarations are as follows: A semi-colon ( ; ) indicates the end of a statement

A double dash ( - - ) indicates a comment.

The libraries std and work shown are made visible

However, the library ieee is only necessary when

The purpose of the three packages/libraries is the following:

The std_logic_1164 package of the ieee library

The std is a resource library (data types, text i/o,

The work library is where we save our design (the

The mode of the signal can be IN,

IN and OUT are truly unidirectional