Lecture 240 – Simulation and Measurement of Op Amps (2/25/02) Page 240-1

LECTURE 240 – SIMULATION AND MEASUREMENTS OF OP AMPS

(READING: AH – 310-323)
Simulation and Measurement Considerations
Objectives:
• The objective of simulation is to verify and optimize the design.
• The objective of measurement is to experimentally confirm the specifications.
Similarity Between Simulation and Measurement:
• Same goals
• Same approach or technique
Differences Between Simulation and Measurement:
• Simulation can idealize a circuit
• Measurement must consider all nonidealities

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 240 – Simulation and Measurement of Op Amps (2/25/02) Page 240-2

Simulating or Measuring the Open-Loop Transfer Function of the Op Amp

Circuit (Darkened op amp identifies the op amp under test):

vIN +VOS - VDD

vOUT
Simulation:
This circuit will give the voltage transfer CL RL VSS
function curve. This curve should identify:
1.) The linear range of operation Fig. 240-01
2.) The gain in the linear range
3.) The output limits
4.) The systematic input offset voltage
5.) DC operating conditions, power dissipation
6.) When biased in the linear range, the small-signal frequency response can be
obtained
7.) From the open-loop frequency response, the phase margin can be obtained (F = 1)
Measurement:
This circuit probably will not work unless the op amp gain is very low.

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 240 – Simulation and Measurement of Op Amps (2/25/02) Page 240-3

A More Robust Method of Measuring the Open-Loop Frequency Response

Circuit:

VDD
vIN vOUT

CL RL VSS
C R

Fig. 240-02
Resulting Closed-Loop Frequency Response:
dB Op Amp
Av(0) Open Loop
Frequency
Response

0dB log10(w)
1 Av(0)
RC RC Fig. 240-03

Make the RC product as large as possible.

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 240 – Simulation and Measurement of Op Amps (2/25/02) Page 240-4

Simulation and Measurement of Open-Loop Frequency Response with Moderate

Gain Op Amps

R
R VDD
vIN vOUT
+
vi
CL RL VSS
-
Fig. 240-04

Make R as large and measure vout and vi to get the open loop gain.

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 240 – Simulation and Measurement of Op Amps (2/25/02) Page 240-5

Simulation or Measurement of the Input Offset Voltage of an Op Amp

VDD
vOUT=VOS
+
VOS
- VSS
R CL RL

Fig. 240-05
Types of offset voltages:
1.) Systematic offset - due to mismatches in current mirrors, exists even with ideally
matched transistors.
2.) Mismatch offset - due to mismatches in transistors (normally not available in
simulation except through Monte Carlo methods).

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 240 – Simulation and Measurement of Op Amps (2/25/02) Page 240-6

Simulation of the Common-Mode Voltage Gain

V
+ OS- VDD
vout
+
vcm VSS
- CL RL
R
Fig. 240-06

Make sure that the output voltage of the op amp is in the linear region.

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 240 – Simulation and Measurement of Op Amps (2/25/02) Page 240-7

Measurement of CMRR and PSRR

Configuration: - 100kΩ
vOS vOS +
Note that vI ≈ 1000 or vOS ≈ 1000vI 100kΩ
vSET

How Does this Circuit Work? 10kΩ

CMRR: PSRR:
VDD
1.) Set 1.) Set vOUT
VDD’ = VDD + 1V VDD’ = VDD + 1V +
VSS’ = VSS + 1V VSS’ = VSS 10Ω vI
-
VSS
vOUT’ = vOUT + 1V vOUT’ = 0V CL RL
2.) Measure vOS 2.) Measure vOS Fig. 240-07
called vOS1 called vOS3 Note:
3.) Set 3.) Set 1.) PSRR- can be measured similar to
VDD’ = VDD - 1V VDD’ = VDD - 1V PSRR+ by changing only VSS.
VSS’ = VSS - 1V VSS’ = VSS 2.) The ±1V perturbation can be
vOUT’ = vOUT - 1V vOUT’ = 0V replaced by a sinusoid to measure
4.) Measure vOS 4.) Measure vOS CMRR or PSRR as follows:
called vOS2 called vOS4 1000·vdd 1000·vss
5.) 5.) PSRR+ = vos , PSRR- = vos
2000 2000 1000·vcm
CMRR=|vOS2-vOS1| PSRR+=|vOS4-vOS3| and CMRR = v
os
ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 240 – Simulation and Measurement of Op Amps (2/25/02) Page 240-8

How Does the Previous Idea Work?

100kΩ
A circuit is shown which is used to measure -
the CMRR and PSRR of an op amp. Prove vos +
that the CMRR can be given as vicm
100kΩ
1000 vicm 10kΩ
CMRR = vos
VDD
Solution vOUT
The definition of the common-mode rejection +
ratio is 10Ω vi vicm
 Avd  (vout/vid) - CL RL VSS
CMRR = Acm = (vout/vicm)
  Fig. 240-08
However, in the above circuit the value of vout
is the same so that we get
vicm
CMRR = v
id
vos
But vid = vi and vos ≈ 1000vi = 1000vid ⇒ vid = 1000
vicm 1000 vicm
Substituting in the previous expression gives, CMRR = v = vos
os
1000

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 240 – Simulation and Measurement of Op Amps (2/25/02) Page 240-9

Simulation of CMRR of an Op Amp

None of the above methods are really suitable for simulation of CMRR.
Consider the following:
Vcm
V2
Vcm VDD Av(V1-V2)
V2 -
Vout
V1 + V1 Vout

VSS Vcm
Vcm ±AcVcm
Fig. 240-09
V1+V2 

Vout = Av(V1-V2) ±A 2  = -AvVout ± AcmVcm
cm

±Acm ±Acm
Vout = 1+Av Vcm ≈ Av Vcm
Av Vcm
∴ |CMRR| = A = V
cm out

(However, PSRR+ = PSRR-)

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 240 – Simulation and Measurement of Op Amps (2/25/02) Page 240-10

CMRR of Ex. 6.3-1 using the Above Method of Simulation

85 200

80 150
Arg[CMRR] Degrees

75 100
|CMRR| dB

70 50
65 0
60 -50
55 -100
50 -150
45 -200
10 100 1000 104 105 106 107 108 10 100 1000 104 105 106 107 108
Frequency (Hz) Frequency (Hz) Fig. 240-10

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 240 – Simulation and Measurement of Op Amps (2/25/02) Page 240-11

Simulation or Measurement of ICMR

vOUT

IDD 1
VDD
vOUT 1
+ vIN
vIN ICMR
- VSS
CL RL
ISS
Also, monitor
IDD or ISS. Fig.240-11
Initial jump in sweep is due to the turn-on of M5.
Should also plot the current in the input stage (or the power supply current).

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 240 – Simulation and Measurement of Op Amps (2/25/02) Page 240-12

Measurement or Simulation of the Open-Loop Output Resistance

Method 1:
vOUT
Without RL
VO1
+ VDD VO2 With RL
+ vOUT
vI - VOS
- vI(mV)
RL
VSS
Fig. 240-12

 V 01 
Rout = RL V02 − 1 or vary RL until VO2 = 0.5VO1 ⇒ Rout = RL
 

Method 2:
R 100R

- VDD Rout
vIN
+
Ro
VSS
Fig. 240-13
1 1 Av -1 100Ro
Rout = Ro + 100R + 100Ro ≅ Av
 

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 240 – Simulation and Measurement of Op Amps (2/25/02) Page 240-13

Measurement or Simulation of Slew Rate and Settling Time

Volts Peak Overshoot
vin
IDD Settling Error
VDD Tolerance
vout +SR -SR
+
vout
vin 1 1
- VSS t
CL RL
Settling Time
Feedthrough Fig. 240-14
If the slew rate influences the small signal response, then make the input step size small
enough to avoid slew rate (i.e. less than 0.5V for MOS).

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 240 – Simulation and Measurement of Op Amps (2/25/02) Page 240-14

Phase Margin and Peak Overshoot Relationship

It can be shown (Appendix C) that:
Phase Margin (Degrees) = 57.2958cos-1[ 4ζ 4+1 - 2ζ 2]
 -πζ 
Overshoot (%) = 100 exp  80 100

 1-ζ 2 70
Phase Margin (Degrees)

60
10
Overshoot (%)

50

40 Phase Margin Overshoot

For example, a 5% overshoot
corresponds to a phase margin of 30
approximately 64°. 1.0
20

10

0 0.1
0 0.2 0.4 0.6 0.8 1
ζ= 1 Fig. 240-15
2Q

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 240 – Simulation and Measurement of Op Amps (2/25/02) Page 240-15

Example 1 Simulation of the CMOS Op Amp of Ex. 6.3-1.

The op amp designed in Example 6.3- VDD = 2.5V
1 and shown in Fig. 6.3-3 is to be analyzed 15µm
M3 M4
15µm
M6
94µm
by SPICE to determine if the specifications 1µm 1µm 1µm
Cc = 3pF
are met. The device parameters to be used vout
are those of Tables 3.1-2 and 3.2-1. In 30µA M1
3µm 3µm
M2
CL =
-
addition to verifying the specifications of vin
1µm 1µm 95µA 10pF
Example 6.3-1, we will simulate PSRR+ +
and PSRR-. 4.5µm
30µA
14µm
Solution/Simulation 1µm 4.5µm 1µm
M8 M5 1µm M7
Fig. 240-16
The op amp will be treated as a VSS = -2.5V
subcircuit in order to simplify the repeated analyses. The table on the next page gives the
SPICE subcircuit description of Fig. 6.3-3. While the values of AD, AS, PD, and PS could
be calculated if the physical layout was complete, we will make an educated estimate of
these values by using the following approximations.
AS = AD ≅ W[L1 + L2 + L3]
PS = PD ≅ 2W + 2[L1 + L2 + L3]
where L1 is the minimum allowable distance between the polysilicon and a contact in the
moat (Rule 5C of Table 2.6-1), L2 is the length of a minimum-size square contact to moat
(Rule 5A of Table 2.6-1), and L3 is the minimum allowable distance between a contact to
moat and the edge of the moat (Rule 5D of Table 2.6-1).

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 240 – Simulation and Measurement of Op Amps (2/25/02) Page 240-16

Example 1 - Continued
Op Amp Subcircuit:
8 VDD
- 2 -
vin 6 vout
+
+ 1
9 VSS Fig. 240-17

.SUBCKT OPAMP 1 2 6 8 9
M1 4 2 3 3 NMOS1 W=3U L=1U AD=18P AS=18P PD=18U PS=18U
M2 5 1 3 3 NMOS1 W=3U L=1U AD=18P AS=18P PD=18U PS=18U
M3 4 4 8 8 PMOS1 W=15U L=1U AD=90P AS=90P PD=42U PS=42U
M4 5 4 8 8 PMOS1 W=15U L=1U AD=90P AS=90P PD=42U PS=42U
M5 3 7 9 9 NMOS1 W=4.5U L=1U AD=27P AS=27P PD=21U PS=21U
M6 6 5 8 8 PMOS1 W=94U L=1U AD=564P AS=564P PD=200U PS=200U
M7 6 7 9 9 NMOS1 W=14U L=1U AD=84P AS=84P PD=40U PS=40U
M8 7 7 9 9 NMOS1 W=4.5U L=1U AD=27P AS=27P PD=21U PS=21U
CC 5 6 3.0P
.MODEL NMOS1 NMOS VTO=0.70 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7
+MJ=0.5 MJSW=0.38 CGBO=700P CGSO=220P CGDO=220P CJ=770U CJSW=380P
+LD=0.016U TOX=14N
.MODEL PMOS1 PMOS VTO=-0.7 KP=50U GAMMA=0..57 LAMBDA=0.05 PHI=0.8
+MJ=0.5 MJSW=.35 CGBO=700P CGSO=220P CGDO=220P CJ=560U CJSW=350P +LD=0.014U TOX=14N
IBIAS 8 7 30U
.ENDS

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 240 – Simulation and Measurement of Op Amps (2/25/02) Page 240-17

Example 1 - Continued
PSPICE Input File for the Open-Loop Configuration:
EXAMPLE 1 OPEN LOOP CONFIGURATION
.OPTION LIMPTS=1000
VIN+ 1 0 DC 0 AC 1.0
VDD 4 0 DC 2.5
VSS 0 5 DC 2.5
VIN - 2 0 DC 0
CL 3 0 10P
X1 1 2 3 4 5 OPAMP
..
.
(Subcircuit of previous slide)
..
.
.OP
.TF V(3) VIN+
.DC VIN+ -0.005 0.005 100U
.PRINT DC V(3)
.AC DEC 10 1 10MEG
.PRINT AC VDB(3) VP(3)
.PROBE (This entry is unique to PSPICE)
.END

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 240 – Simulation and Measurement of Op Amps (2/25/02) Page 240-18

Example 1 - Continued
Open-loop transfer characteristic of Example 6.3-1:

2.5
2

VOS
1
vOUT(V)

-1

-2
-2.5
-2 -1.5 -1.0 -0.5 0 0.5 1 1.5 2
vIN(mV) Fig. 240-18

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 240 – Simulation and Measurement of Op Amps (2/25/02) Page 240-19

Example 1 - Continued
Open-loop transfer frequency response of Example 6.3-1:

100 200
80 150

Phase Shift (Degrees)

60 100
Magnitude (dB)

40 50
0
20
-50
0
-100
-20
GB -150 Phase Margin GB
-40 -200
10 100 1000 104 105 106 107 108 10 100 1000 104 105 106 107 108
Frequency (Hz) Frequency (Hz) Fig. 240-19

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 240 – Simulation and Measurement of Op Amps (2/25/02) Page 240-20

Example 1 - Continued
Input common mode range of Example 6.3-1: 4
VDD
-
3 vout
EXAMPLE 6.6-1 UNITY GAIN CONFIGURATION.
Subckt. 3
.OPTION LIMPTS=501 1 +
VIN+ 1 0 PWL(0 -2 10N -2 20N 2 2U 2 2.01U -2 4U -2 4.01U
+ -.1 6U -.1 6.0 1U .1 8U .1 8.01U -.1 10U -.1) vin 5
VDD 4 0 DC 2.5 AC 1.0
VSS 0 5 DC 2.5 VSS
Fig. 240-20
CL 3 0 20P
X1 1 3 3 4 5 OPAMP
.. 4 40
. ID(M5)
(Subcircuit of Table 6.6-1)
ID(M5) µA

.. 3 30
.
.DC VIN+ -2.5 2.5 0.1 2 20
Input CMR
vOUT (V)

.PRINT DC V(3)
.TRAN 0.05U 10U 0 10N 1 10
.PRINT TRAN V(3) V(1)
0 0
.AC DEC 10 1 10MEG
.PRINT AC VDB(3) VP(3) -1
.PROBE (This entry is unique to PSPICE)
.END -2

-3
-3 -2 -1 0 1 2 3
vIN(V) Fig. 240-21

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 240 – Simulation and Measurement of Op Amps (2/25/02) Page 240-21

Example 1 - Continued
Positive PSRR of Example 6.3-1:

100 100

80

Arg[PSRR+(jω)] (Degrees)
50
|PSRR+(jω)| dB

60

40 0

20
-50
0

-20 -100
10 100 1000 104 105 106 107 108 10 100 1000 104 105 106 107 108
Frequency (Hz) Frequency (Hz) Fig. 240-22

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 240 – Simulation and Measurement of Op Amps (2/25/02) Page 240-22

Example 1 - Continued
Negative PSRR of Example 6.3-1:

120 200

150
Arg[PSRR-(jω)] (Degrees)

100
100
|PSRR-(jω)| dB

80 50

0
60 -50
PSRR+
-100
40
-150
20 -200
10 100 1000 104 105 106 107
10 8
10 100 1000 104 105 106 107 108
Frequency (Hz) Frequency (Hz) Fig. 240-23

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 240 – Simulation and Measurement of Op Amps (2/25/02) Page 240-23

Example 1 – Continued
Large-signal and small-signal transient response of Example 6.3-1:
1.5 0.15

1 0.1 vin(t)

0.5 0.05
vout(t)
vout(t)
Volts

Volts
0 0

-0.5 -0.05
vin(t)
-1 -0.1

-1.5 -0.15
0 1 2 3 4 5 2.5 3.0 3.5 4.0 4.5
Time (Microseconds) Time (Microseconds) Fig. 240-24

Why the negative overshoot on the slew rate? VDD

If M7 cannot sink sufficient current then the output stage M6

slews and only responds to changes at the output via the Cc iCc iCL dvout
vout
feedback path which involves a delay. dt

Note that -dvout/dt ≈ -2V/0.3µs = -6.67V/µs. For a 10pF CL

95µA
capacitor this requires 66.7µA and only 95µA-66.7µA = 28µA
is available for Cc. For the positive slew rate, M6 can provide + M7
VBias
whatever current is required by the capacitors and can -
VSS
immediately respond to changes at the output. Fig. 240-25

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 240 – Simulation and Measurement of Op Amps (2/25/02) Page 240-24

Example 1 - Continued VDD = 2.5V

Why is the negative-going overshoot 94/1 0.1V

larger than the positive-going overshoot M6 i6
iCc
on the small-signal transient response of iCL
vout t
the last slide? Cc
CL
Consider the following circuit and 95µA
waveform: M7
-0.1V
VBias 0.1µs 0.1µs

VSS = -2.5V Fig. 240-26

During the rise time,
iCL =material
(The CL(dvout /dt )= 10pF(0.2V/0.1µs)
beneath this box is part of =a homework
20µA and iCc = 3pf(2V/µs) = 6µA
solution)
∴ i6 = 95µA + 20µA + 6µA = 121µA ⇒ gm6 = 1066µS (nominal was 942.5µS)
During the fall time, iCL = CL(-dvout/dt) = 10pF(-0.2V/0.1µs) = -20µA
and iCc = -3pf(2V/µs) = -6µA
∴ i6 = 95µA - 20µA - 6µA = 69µA ⇒ gm6 = 805µS
The dominant pole is p1 ≈ (RIgm6RIICc)-1 where RI = 0.694MΩ, RII = 122.5kΩ
and Cc = 3pF.
∴ p1(95µA) = 4,160 rads/sec, p1(121µA) = 3,678 rads/sec, and p1(69µA) = 4,870
rads/sec.
Thus, the phase margin is less during the fall time than the rise time.

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 240 – Simulation and Measurement of Op Amps (2/25/02) Page 240-25

Example 1 - Continued
Comparison of the Simulation Results with the Specifications of Example 6.3-1:

Specification Design Simulation

(Power supply = ±2.5V) (Ex. 6.3-1) (Ex. 1)
Open Loop Gain >5000 10,000
GB (MHz) 5 MHz 5 MHz
Input CMR (Volts) -1V to 2V -1.2 V to 2.4 V,
Slew Rate (V/µsec) >10 (V/µsec) +10, -7(V/µsec)
Pdiss (mW) < 2mW 0.625mW
Vout range (V) ±2V +2.3V, -2.2V
PSRR+ (0) (dB) - 87
PSRR- (0) (dB) - 106
Phase margin (degrees) 60° 65°
Output Resistance (kΩ) - 122.5kΩ

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 240 – Simulation and Measurement of Op Amps (2/25/02) Page 240-26

SUMMARY
Simulation is a key step in electrical design - it is the step to verify and optimize
Measurement is a key step in the overall design - electrical→physical→measurement
Similarities between simulation and measurement:
• Same desired responses
• Same general method to approach the result
Dissimilarities between simulation and measurement:
• Measurement using nonideal components and simulation has ideal components
• Can access internal nodes with simulation
• Can create artificial configurations with simulation
• Parasitics are a problem with measurement

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002