Name: Umesh Reddy

Nimmathi StudID: 1649330

1sol)

A) Pseudo Vectors

Advantages: Pseudo vectors are very easy to generate whereas custom made vectors are hard to
generate. Most of the faults which are easy to detect will be detected by Pseudo vectors. Computing
time will be reduced when we use pseudo vectors (As we are selecting few vectors from a given
sample). When there is less time for the tester to do the testing then selecting pseudo vectors over
man made vectors will be a good strategy.

Disadvantages: Although Pseudo vectors are easy to generate, they are not that efficient (Efficiency
will be less than 100%) as we are taking random vectors. We have to use test generation algorithms
in order to detect Hard-to-detect faults.

B) In order to find effective test vectors, the pseudo vectors and deterministic test vectors needs to
be fault simulated in the reverse order.

2sol)

True Value Simulator: A simulator is said to be true value simulator if it computes the given input
stimuli with out adding any faults in the design. The effective way is to verify all functions with only
critical data patterns which depends on designer’s heuristics. Hence, TVS can only be used to know
the presence of design errors.

Generally, Adequate set of vectors can be selected from the verification vectors using fault simulator
by removing the vectors that does not increase the fault coverage. If it is found to be inadequate
then we can add fault coverage vectors by using test generation algorithms.

3sol)

Zero Delay: The assumption is that all the gates and interconnects have no delay. This model is
suitable for the combinational circuit as it does not have any feedback or memory. It is also used for
sequential circuit but with no feedback. If there is a change in signal then it is determined by the
logic function of the gates.

Unit Delay (One Delay): The assumption is that the gate has one unit of delay (which is
heuristic/fictitious) and interconnect does not have any delay. This model is suitable for the circuits
which has memory unit and feedback.

Example: Flip-Flops represented by component gates.

4sol)

Simulation of sequential circuits is represented by three states i.e. 0, 1, ‘X’. X is basically an unknown
state (If the output of the circuit/logic gate is not determined). At the beginning of the simulation we
assume that the internal state of the sequential to be ‘X’.
 Name: Umesh Reddy
Nimmathi StudID: 1649330
The symbol ‘Z’ is used to indicate the high-impedance (if we have a tristate input) in the mixed-level
circuit.

a b NOR a b c XOR (A XOR B) XOR C

~(a+b)
0 0 1 0 0 0 0
0 1 0 0 0 1 1
0 X ~X 0 0 X X
1 0 0 0 1 0 1
1 1 0 0 1 1 0
1 X 0 0 1 X ~X
X 0 ~X 0 X 0 X
X 1 0 0 X 1 ~X
X X ~X 0 X X 0
1 0 0 1
1 0 1 0
1 0 X ~X
1 1 0 0
1 1 1 1
1 1 X X
1 X 0 ~X
1 X 1 X
1 X X 1
X 0 0 X
X 0 1 ~X
X 0 X 0
X 1 0 ~X
X 1 1 X
X 1 X 1
X X 0 0
X X 1 1
X X X X

5Sol)

In Event-driven simulation, the simulation happens only on the faulty circuits that differ in signal
states from the fault-free circuits. The information is stored in the data structure called linked list
which contains fault ID, gate input and output values and internal states if any.
 Name: Umesh Reddy
Nimmathi StudID: 1649330
In the Given example below, Signal ‘c’ is changed from logic 1 to logic 0 at t=0 which will affect the
signals ‘e’ and ‘d’. Both the gates have a delay of 2 time slots. Hence, they are scheduled in the time
wheel after two time slots and these two events will be stored in the linked list. Similarly, the
procedure is continued till we complete 8 time slots(d+f+g).

(Image Source: Essential of Electronic Testing eBook by Bushnell, Michael Lee)

In compiled-code simulators it is hard to model timing problems, glitches etc. Also, the efficiency is
not good as it evaluates the entire code when only few signals are changing (i.e. 1-10% of signals are
changed). Delayed timings like multiple delay and minmax delay are impossible to simulate in
compiled-code simulators whereas in event-drive simulation it is easy and effective.

6Sol) In serial fault simulation, the good circuit is first simulated for all vectors and the output values
will be stored in a file. After that, each faulty circuit is simulated and the output is compared with
the good circuit one by one. Serial fault simulation implementation is easy as it uses a true-value
simulator. This simulation is effective for analog circuit faults. Let’s say for n number of faults, the
serial fault simulation will take CPU time of n times that of the true-value simulator. The time
complexity is more for serial fault simulation.

Whereas in parallel simulation, we assume that all the gates have same delay and also signals can
take only binary values 0,1. These assumptions will make parallel simulation the most effective one
when compared to serial fault simulation as all the faulty circuits are almost equal to the fault-free
circuits except the stuck-at fault. Therefore, Parallel simulation can process w-1 faults in just one
pass (w is machine word size). Let’s say for n number of faults, the parallel simulation will take the
same CPU time of a true-value simulation.

7Sol)

Deductive Fault simulation:

- Uses true value simulation

- Circuit assumptions are similar to event-driven simulation
- Fault-list is for a signal and contains only information about the faults that affected the
signal.
 Name: Umesh Reddy
Nimmathi StudID: 1649330
- Fault-list size is less than concurrent fault simulation.
- Cannot handle variable rise/fall delays

Concurrent Fault simulation:

- Uses true value simulation

- Extends event-driven simulation
- Fault-list is for gate and event faults that affects the gate input.
- Fault-list size is more than deductive fault simulation.
- Can handle variable rise/fall delays.

8Sol)

Let X be the output of the circuit (A.B) +C.

CC0(A),CC1(A) are difficulty of setting circuit line to logic 0 and logic 1 at A

CC0(B),CC1(B) are difficulty of setting circuit line to logic 0 and logic 1 at B

CC0(C),CC1(C) are difficulty of setting circuit line to logic 0 and logic 1 at C

CC0(X),CC1(X) are difficulty of setting circuit line to logic 0 and logic 1 at X

Controllability:

First, we need to find the controllability CC0 for (A.B) will be min(CC0(A), CC0(B) ) + 1 (AND gate
controllability formula)

Now we can find the output controllability for the (A.B) + C or X which will be

CC0(X) = min(CC0(A), CC0(B) ) + 1 + CC0(C) + 1 ( Every time we process a logic gate we have to add
‘1’)

Similarly, controllability CC1 for (A.B) will be CC1(A) + CC1(B) + 1.

The controllability CC1 of the output Z will the minimum value of CC1(A.B) and CC1(C)

CC1(X) = min(CC1(A) + CC1(B) + 1, CC1(C)) + 1

Observability:

Co(A) is the combination observability of A

CO(B) is the combination observability of B

CO(C) is the combination observability of C

Observing A: In order to observe A at the output, we need to make C as ‘0’ and B as ‘1’. Therefore
we have to add CC0(C) and CC1(B) to our controllability

CO(A) = CO(X) + CC0(C) + CC1(B) + 1 + 1 (As two gates have processed)

Observing B: In order to observe B at the output, we need to make C as ‘0’ and A as ‘1’. Therefore
we have to add CC0(C) and CC1(A) to our controllability

CO(B) = CO(X) + CC0(C) + CC1(A) + 1 + 1 ( AS two gates have processed)

 Name: Umesh Reddy
Nimmathi StudID: 1649330
Observing C: In order to observe C at the output, we need to make either A as ‘0’ or B as ‘0’. The
minimum cost will be considered for our controllability.

CO(C) = CO(X) + min ( CCO(A),CCO(B) ) +1 +1( AS two gates have processed)

9Sol)

(Image Source: Essential of Electronic Testing eBook by Bushnell, Michael Lee)

The fundamental assumption is that the signals at reconvergent fanout stems are independent. But
most of the circuits have this dependency by which we can get the incorrect values for the
controllability and observability. In such cases SCOAP found to be inaccurate (The above image
shows the reconverging fanout stem).