NATIONAL ENGINEERING COLLEGE, K.R.

NAGAR, KOVILPATTI – 628503

(An Autonomous Institution Affiliated to Anna University, Chennai)
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
15EC81C – PROJECT WORK

Team No. B2

Name and Designation of the Guide Mr.I.Vivek Anand AP/ECE

Presence during Project Hour Along with the Guide
Design and Implementation of Floating Point
Title of the Project
Parallel Processing operation for RISC Processor

Details of Student Team Member:

S. No. REGISTER NUMBER NAME OF THE STUDENT
1 1611015 Balasaraswathi. R
2 1611022 Divya.D
3 1611027 Harini Kalyani.M

Abstract:
The development of processors with various suggestions have been made regarding a
precise definition of RISC, but in general a computer supports small set of simple instruction
rather than large set of complex and specialized instructions. Existing 64 bit RISC
processors suffers from high power and delay as more number of registers are employed.
This project proposes the design of high speed 64 bit RISC processor. The features of this
processor are it consumes less power and operates with high speed. Other features of
prposed RISC are uniform instruction format, identical general purpose registers and simple
addressing modes. It also offers reduced number of instruction, fixed instruction length,
more general purpose register which are organized into register file, load – store
architecture and simplified addressing modes which makes individual instruction execute
faster and achieve a net gain in performance. The proposed RISC architecture are written
using Verilog HDL and area, power report and timing report are observed in Encounter RTL
using Cadence and finally implemented using Spartan 3E FPGA kit.

Work Plan:
Details of the work plan to be presented in the review meeting
Architecture and block diagram for memory -ALU interface and
Review 0
coding for memory block , Coding for ALU and ALU-memory interface
Coding for floating point addition ,subtraction with double precision
Review 1
and Coding for floating point ALU
Cascading the above blocks into single architecture and
Review 2
implementation can be done using SPARTAN 3E-FPGA kit.

Signature of Students Signature of the Supervisor HOD/ECE