Class 2

Functional
Block
Diagram
28027
28027-48 pin PT LQFP
28027-38 pin DA TSSOP
 General Instruction
• With the exception of the JTAG pins, the GPIO function
is the default at reset, unless otherwise mentioned.
• The peripheral signals that are listed under them are
alternate functions.
• All GPIO pins are I/O/Z and have an internal pullup,
which can be selectively enabled/disabled on a per-pin
basis.
• The pullups on the PWM pins are not enabled at reset.
The pullups on other GPIO pins are enabled upon reset.
The AIO pins do not have an internal pullup.
 General Instruction
• NOTE: When the on-chip VREG is used, the
GPIO19, GPIO34, GPIO35, GPIO36, GPIO37, and
GPIO38 pins could glitch during power up.
• If this is unacceptable in an application, 1.8 V
could be supplied externally. Alternatively, adding
a current-limiting resistor (for example, 470 Ω) in
series with these pins and any external driver
could be considered to limit the potential for
degradation to the pin and/or external circuitry
Emulator Connection
 Flash Memory
• Multiple sectors
• The minimum amount of flash memory that can be erased is a sector. Having multiple
sectors provides `the option of leaving some sectors programmed and only erasing
specific sectors.

• Code security
• The flash is protected by the Code Security Module (CSM). By programming a password
into the flash, the user can prevent access to the flash by unauthorized persons

• Low power modes

• To save power when the flash is not in use, two levels of low power modes are available

• Configurable wait states

• Configurable wait states can be adjusted based on CPU frequency to give the best
performance for a given execution speed.

• Enhanced performance
– A flash pipeline mode is provided to improve performance of linear code execution
 OTP Memory
• The 1K x 16 block of one-time programmable
(OTP) memory is uniformly mapped in both
program and data memory space. Thus, the
OTP can be used to program data or code. This
block, unlike flash, can be programmed only
one time and cannot be erased.
 Flash and OTP Power Modes
• Reset or Standby State
• Sleep State
 Flash and OTP Power Mode
• To move to a lower power state
– PWR mode bits from a higher power mode to a lower
power mode
• To move to a higher power state
– Change the FPWR register from a lower state to a
higher state. This access brings the flash/OTP memory
to the higher state.
– Access the flash or OTP memory by a read access or
program opcode fetch access. This access
automatically brings the flash/OTP memory to the
active state.
Flash and OTP Power Mode
 Accesses to flash and OTP are one of
three types
• Flash Memory Random Access
• The first access to a 2048 bit row is considered a random access.

• Flash Memory Paged Access

• While the first access to a row is considered a random access, subsequent accesses
within the same row are termed paged accesses
– The number of wait states for both a random and a paged access can be configured by programming the
FBANKWAIT register. The number of wait states used by a random access is controlled by the RANDWAIT
bits and the number of wait states used by a paged access is controlled by the PAGEWAIT bits. The
FBANKWAIT register defaults to a worst-case wait state count and, thus, needs to be initialized for the
appropriate number of wait states to improve performance based on the CPU clock rate and the access time of
the flash. The flash supports 0-wait accesses when the PAGEWAIT bits are set to zero.

• OTP Access
• Read or fetch accesses to the OTP are controlled by the OTPWAIT bits in the
FOTPWAIT register. Accesses to the OTP take longer than the flash and there is no
paged mode.
 Flash Pipeline Mode
• To improve the performance of linear code
execution, a flash pipeline mode has been
implemented.
• ENPIPE bit in the FOPT register enables this
mode.
Flash Pipeline Mode
Flash and OTP Registers
Flash Options Register (FOPT)
Flash Power Register (FPWR)
Flash Status Register (FSTATUS)
Flash Standby Wait Register
(FSTDBYWAIT)
Flash Wait-State Register
OTP Wait-State Register (FOTPWAIT)
Class 3
 Code Security Module (CSM)
• Prevents access/visibility to on chip memory to
unauthorized persons.
• Prevents duplication/ reverse engineering of
proprietary code.
• The device is secure when CPU access to the on
chip secure memory location is restricted.
• When code is running inside secure memory ,
access through JTAG is blocked(emulator).
• User code can be jump in and out of secure
memory , there by allowing secure function calls
from non secure memory.
 Password
• Password is 128 bit of data
• Stored at the end of flash in 8 words referred
to as the password locations
• Device is unsecured by executing the
password mach flow(PMF).
Security Levels
 Password Locations(PWL)
• Password locations 0x3F 7FF8 – 0x3F 7FFF
• If the password locations have all 128 bits as
ones, the device is labelled as unsecure.
• If the password locations have all 128 bits as
zeros, the device is secure, regardless of the
contents on the KEY registers.
• Using all zeros as password seriously limit you
ability to debug secure code or reprogram the
flash.
 KEY Register
• User accessible register( eight 16 bit words) that are
used to unsecure the device referred as key register.
• Register location 0x000AE0 – 0x000AE7
• In addition to the code secure module, the emulator
code security logic (ECSL)has implemented to prevent
unauthorized users from stepping through secure code.
• Write correct value into lower 64 bit of KEY register =
64 bit password location within flash.
• Lower 64 bits are ones then KEY value does not need to
match.
CSM impact on other on- chip
Resources
Resource not effected by CSM
Code Security Module (CSM) Registers
Code Secure Module Register
Password Match Flow(PMF)
Clock
PLL, Clocking, watchdog and low –
power modes Register
 PCLKCR0/1/3
• Register enables/disable clocks to the various
peripheral modulates.
• 2 SYSCLKOUT cycle delay from when a write to
the PCLKCR0/1/3 register occurs to when the
action is valid.
• Turn on the clocks to all the peripherals
cannot be used at the same time.
• GPIO pins are multiplexed with other
functions.
Peripheral Clock Control 0 Register
(PCLKCR0)
Peripheral Clock Control 0 Register
(PCLKCR0)
Peripheral Clock Control 1 Register
(PCLKCR1)
Peripheral Clock Control 3 Register
(PCLKCR3)
Low-Speed Peripheral Clock Prescaler
Register (LOSPCP)
 OSC and PLL Block
• On chip OSC and PLL provide the clock signal
to device and low power mode entry /exit.
• Input clock options
– INTOSC1(Internal Zero pin Oscillator 1)
– INTOSC2(Internal Zero pin Oscillator 2)
• Both provide the clock for the watchdog block and core
and CPU-Timer 2, both can independently chosen
 Input Clock
• Crystal/Resonator operation: Use an external
crystal/resonator to provide time base using X1/X2 pin.
• External clock source operation: If the on-chip crystal
oscillator is not used, this mode allows it to be
bypassed. The device clock is generated from an
external clock source input on the XCLKIN pin. Note
that the XCLKIN is multiplexed with a GPIO19 or
GPIO38 pin. The XCLKIN input can be selected as
GPIO19 or GPIO38 via the XCLKINSEL bit in the XCLK
register. The CLKCTL[XCLKINOFF] bit disables this clock
input (forced low). If the clock source is not used or the
respective pins are used as GPIOs, the user should
disable it at boot time.
Clock options