Lecture 20

Today we will

Look at why our NMOS and PMOS inverters might
not be the best inverter designs

Introduce the CMOS inverter

Analyze how the CMOS inverter works

NMOS Inverter

5V 5V
When VIN is logic 1,
VOUT is logic 0.
R R
Constant nonzero
ID = 5/R D VOUT current flows through D VOUT
transistor. ID = 0
VIN 0V VIN
+ Power is used even 5V
+
5V
VDS
though no new 0V
computation is being VDS
_
_
performed.

When VIN changes to logic 0, transistor gets cutoff. ID goes to 0.

Resistor voltage goes to zero. VOUT “pulled up” to 5 V.
 PMOS Inverter

5V 5V
When VIN is logic 0,
VOUT is logic 1.

VIN Constant nonzero

- VIN -
VDS current flows through
V VDS
+ OUT transistor. VOUT
0V 5V +
ID = -5/R 5V Power is used even ID = 0 0V
though no new
computation is being
R R
performed.

When VIN changes to logic 1, transistor gets cutoff. ID goes to 0.

Resistor voltage goes to zero. VOUT “pulled down” to 0 V.

Analysis of CMOS Inverter

VDD (Logic 1)
We can follow the same

S procedure to solve for currents
and voltages in the CMOS
D VOUT inverter as we did for the single
NMOS and PMOS circuits.
D
VIN
Remember, now we have two
transistors so we write two I-V
S
relationships and have twice
the number of variables.
NMOS is “pull-down device”

We can roughly analyze the
PMOS is “pull-up device”
CMOS inverter graphically.
Each shuts off when not pulling
 NMOS Inverter

ID saturation mode

VGS = 3 V

X
Linear ID vs VDS given
by surrounding circuit

X VGS = 1 V

VDS

Linear KVL and KCL Equations

- VDD (Logic 1) VGS(n) = VIN
(p)
+ V GS S
VGS(p) = VIN – VDD
D VOUT VGS(p) = VDS(n) - VDD

VIN
D + ID(p) = -ID(n)
VDS(n)
+V _
GS(n
) - S
VDS(n) = VOUT

VDS(p) = VOUT – VDD

Use these equations
to write both I-V equations in VDS(p) = VDS(n) - VDD
terms of VDS(n) and ID(n)
 CMOS Analysis
ID(n)
As VIN goes up, VGS(n) gets bigger NMOS I-V curve
and VGS(p) gets less negative.
PMOS I-V curve
(written in terms of
NMOS variables)

VIN =
VGS(n) =
0.9 V

VDS(n)
VDD

CMOS Analysis
ID(n)
As VIN goes up, VGS(n) gets bigger NMOS I-V curve
and VGS(p) gets less negative.
PMOS I-V curve
(written in terms of
NMOS variables)

VIN =
VGS(n) =
1.5 V

VDS(n)
VDD
 CMOS Analysis
ID(n)
As VIN goes up, VGS(n) gets bigger NMOS I-V curve
and VGS(p) gets less negative.
PMOS I-V curve
(written in terms of
NMOS variables)

VIN =
VGS(n) =
2.0 V

VDS(n)
VDD

CMOS Analysis
ID(n)
As VIN goes up, VGS(n) gets bigger NMOS I-V curve
and VGS(p) gets less negative.
PMOS I-V curve
(written in terms of
NMOS variables)

VIN =
VGS(n) =
2.5 V

VDS(n)
VDD
 CMOS Analysis
ID(n)
As VIN goes up, VGS(n) gets bigger NMOS I-V curve
and VGS(p) gets less negative.
PMOS I-V curve
(written in terms of
NMOS variables)

VIN =
VGS(n) =
3.0 V

VDS(n)
VDD

CMOS Analysis
ID(n)
As VIN goes up, VGS(n) gets bigger NMOS I-V curve
and VGS(p) gets less negative.
PMOS I-V curve
(written in terms of
NMOS variables)

VIN =
VGS(n) =
3.5 V

VDS(n)
VDD
 CMOS Analysis
ID(n)
As VIN goes up, VGS(n) gets bigger NMOS I-V curve
and VGS(p) gets less negative.
PMOS I-V curve
(written in terms of
NMOS variables)

VIN =
VGS(n) =
4.1 V

VDS(n)
VDD

CMOS Inverter VOUT vs. VIN

VOUT
both curve very
VDD sat. steep here;
only in “C” for
small interval
NMOS: of VIN
cutoff
NMOS: NMOS:
PMOS:
triode triode
triode
PMOS: PMOS:
NMOS: cutoff
saturation
saturation
PMOS:
triode
VIN
A B C D E VDD
 CMOS Inverter ID
ID

VIN
A B C D E VDD

Important Points

No ID current flow in Regions A and E if nothing attached to

output; current flows only during logic transition

If another inverter (or other CMOS logic) attached to output,
transistor gate terminals of attached stage do not permit
current: current still flows only during logic transition
VDD VDD
S S

D VOUT1 D VOUT2

VIN D D

S S