2018 31th International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems

A Temperature Compensated Read Assist for Low Vmin and High Performance High Density 6T
SRAM in FinFET Technology
1
Vinay kumar , 1Ravindra Kumar Shrivastava , 1Madhav Mansukh Padaliya
1
Synopsys India Pvt. Ltd. vikumar@synopsys.com

Abstract - A low Vmin, 6T-SRAM is realized in 7nm FinFET
Technology using read and write assist methods. Read margin of
the SRAM cell is recovered using a temperature compensated
wordline lowering scheme. This temperature compensated Read
Assist provides additional advantage that lowering on wordline is
almost process independent that makes Read Assist very robust.
This scheme makes design free from tuning after post silicon.
Since Proposed Read Assist circuit lowers Wordline at high
temperature while lowering at low temperature is very minimal,
SRAM writability is not impacted by Read Assist Circuity at low
temperature. At low voltage, SRAM performance is limited by
Read cycle time. The proposed Read Assist scheme improves
Read performance by 200%, which in-turn reflects the gain in
operating frequency up to 100%. In the proposed Read assist
implementation operating frequency is almost comparable to
system when Read Assist is not enabled with added advantage of
low voltage enablement.
Keywords— 7nm FINFET, Low Power, SRAM, High Density
(HD), low Vmin, Write Assist (WA), Read Assist (RA), Write
Margin (WM), High Performance (HP), Wordline Underdrive ,
Static Noise Margin (SNM) .
lowering scheme that does not result in performance loss. The
Scheme proposed here avoids under-drive at performance
critical low temperature and provides required under-drive at
high temperature to enhance SNM. This scheme minimizes
under-drive at low temperatures where writability is major
concern. This helps to avoid a penalty on the required negative
bitline (used as WA) requirement.
II. Proposed Temperature Compensated Read Assist
To minimize the impact of Read Assist on Write Margin and
Performance, temperature compensated RA scheme is
implemented in 7nm FinFET technology so that WL dips only
at higher temperatures to recover the SNM (WM and cell
current should not see WL voltage drop at critical/low
temperatures since both Write Margin and Read current
degrades at Low temperature). In Conventional RA, Word line
is lowered by PMOS whose gate is VSS as shown in Fig2(a),
its impact on Word line Lowering across Process and
temperature is shown in Figure 2(b).

I. INTRODUCTION
Careful co-optimization between technology and design of
memory assist circuits is required to deliver dense, low power
memory operation at low voltages. High-density (HD) 6T
SRAM cell is formed using single fins for each device in the
bitcell which has 20-25% better bitcell area efficiency over
High Performance (HP) SRAM bitcell in addition to leakage (a)WLUD Conventional Circuit.
advantage. High Density SRAM bitcell has around 40-50%
leakage advantage as compared to High Current bitcell.
With the process variations, the strength of PU transistor can
be much stronger than the PG transistor. A stronger PU
degrades the write margin significantly and results in severe
write ability issue. In addition to writability issue, SNM study
shows that it needs Read assist to enable SRAM operation
beyond 0.65v. Word line lowering [1-4] is considered most (b)WLUD across different PVT
prominent Read Assist technique in FinFET technology to Figure2 Conventional WLUD Read Assist.
enable low voltage operation. Read Assist further degrades To ensure that WL lowering is dominant only at high
writability for HD bitcell as shown in Figure 1. temperature, a temperature sensitive RA circuit is designed as
shown in Figure 3.
In Proposed Read Assist the gate drive of PMOS “MRA” is
used to lower the Wordline (Fig 3) which varies with
temperature. When SRAM operating at Low temperature,
PMOS “MCOM” threshold voltage is high and its drive
strength is very weak. Due to the weak drive for “MCOMP” at
low temperature, the signal “TEMP_COMP” settles at a value
higher than VSS. In SMM worst condition when SRAM
operates at high temperature, the drive for “MCOMP”
Figure 1. 7nm FinFET High Density SRAM SNM and Write Margin. improves and Signal “TEMP_COMP” value settles closer to
Wordline lowering RA scheme results in performance loss and VSS that provides strong gate drive to assist PMOS “MRA”
reduces the efficiency of WA. This work presents a WL and Wordline lowers sufficiently to improve SNM as shown in

2380-6923/17 $31.00 © 2017 IEEE 447

DOI 10.1109/VLSID.2018.106
Fig 4. RA circuit in the proposed scheme is almost insensitive
to memory periphery process variation to avoid post silicon
issues/complexities when process mismatch occurs across
SRAM and memory periphery devices. The sensitivity of
proposed Wordline lowering scheme for node
“TEMP_COMP” across different process and temperatures is
shown in Figure4.
Figure 3 Proposed Temp Compensated Wordline Lowering Read Assist.
Figure 4 voltage Level for signal “TEMP_COMP”
Simulation results show that the WL drop is almost nil in case
of write margin (SF/-40C) and speed critical PVT (SS/-40) as
shown in Table 1. The circuit is designed to ensure the
required WL lowering at SNM critical PVT (FS/125).
Compensation Block is designed to ensure least WL lowering
at SF and SS conditions when temperature is low. The
variation of WL lowering/drop across process and voltage is
shown Table1 for 125C and -40C. This is observed that WL
lowering is suppressed at lower temperatures.
Table 1 Proposed WL Lowering RA Circuit Monte Carlo Analysis
Sensitivity for implemented WL lowering scheme with
temperature is shown in Figure 5. SNM analysis for this bitcell
shows that WL lowering requirement increases with
temperature. Monte Carlo analysis performed on Read Assist
circuitry, “Mean - 2*Sigma” value is considered to qualify
SNM criteria while “Mean + 2*Sigma” is considered for
448
writability and performance analysis to safeguard design
against variation of proposed implementation.
Figure 5 SNM sigma qualification with Temperature
III DISCUSSION AND CONCLUSION
Implementing temperature compensated WL lowering
scheme, read stability at low voltage is ensured. Scheme uses
~40mV of WL lowering to achieve Vmin up to 0.5V. Stability
of cell increases from 4 sigma to 6 sigma, ensuring 99% yield
for a 256 Mb. The RA scheme is implemented with an area
overhead of 2 percent. Vmin of the cell is 750mV without any
read and write assist. In a conventional WL lowering scheme,
underdrive at SS/-40C and SF/-40C is almost comparable to
what is designed for FS/125C. This puts a performance
penalty on memory. Considering similar degradation using
conventional WL lowering scheme, cell current would have
been reduced to one forth, resulting into severe penalty on
operating frequency and access time. This performance loss is
recovered using proposed temperature compensated WL
lowering scheme. The improved read current values are shown
in Figure 6. This improvement of read current (up to ~4x)
results in the improvement of the access time for SRAM by
more than 150%. In addition to access time, operating
frequency is also improved up to 100% for low voltage range
operation as reflected in Fig 6.
Figure 6 Timing Gain with Proposed Read Assist WL Lowering
References
[1] Jonathan Chang et al, “A 20nm 112Mb SRAM in High-κ Metal-Gate with
Assist Circuitry for Low-Leakage and Low-VMIN Applications”, ISSCC
2013, p.p. 316-317.
[2] Makoto Yabuuchi et al, “20nm High-Density Single-Port and Dual-Port
SRAMs with Wordline-Voltage-Adjustment System for Read/Write Assists”,
ISSCC 2014, p.p. 234-235.
[3] Mudit Bhargawa et al, “Low VMIN 20nm Embedded SRAM with Multi-
voltage Wordline Control based Read and Write Assist Techniques”,
Symposium on VLSI Circuits Digest of Technical Papers, 2014.
[4] Jonathan chang,A 7nm 256Mb SRAM in high-k metal-gate FinFET
technology with write-assist circuitry for low-VMIN applications, ISSCC
2017