End Semester Examination, Autumn’18 Full Mark: 50,

Department of Electronics and Communication Engg., Time: 3hrs.

National Institute of Technology, ROURKELA
Sub: Reconfigurable System Design (EC-623, EC-6203)
Class: 1stsem M.Tech, (VLSI & ESD) and 7th Sem Dual degree VLSI.
Answer all questions
Figures in the right hand margin indicate marks.
This question paper contains 2 pages
Q No. Marks
1. a. What are the two ways of zeroing a Flip-Flop? List with examples. 3
b. Design a synchronous read 8x16 Read Only Memory using Verilog. 7

2. a. Generate a clock waveform with an off-period of 15 ns and on-period of 20 ns using

3

behavioral modeling in Verilog.

b. Draw the output signal X.
assign #4 X = Y;
2
Y
6 9 14 19 21 27
c. Design a module using Verilog coding that counts the Number of “1”s in an input 8bit
5
vector. Assume a suitable output vector to display the result.

3. 3
a. Draw the waveform of the following code: Assume the initial value as “X”.
Initial Initial
begin begin
A= #20 0; B<= #23 0;
A= #3 1; B<= #13 1;
A = #10 0; B<= #35 1;
end end

b. How is the connectivity established in Verilog when connecting wires of different widths? 2

c. Write a Verilog code that compares two 8-bit vectors, a and b. The design must have 5
three outputs, x1, x2, and x3, corresponding to a > b, a=b, and a < b, respectively.

1
4. a. Describe the Xilinx FPGA design flow with suitable diagram. Compare FPGA vs. ASIC 4
based system design.

b. Design of the 11011 Sequence Detector using Verilog behavioral modeling style. 6
5.
a. What is set-up and hold time of a Flip Flop. Explain about hold violation and how to fix 5
the hold violation.

b. The following are the specification of a two back to back synchronous FFs (FF1 and FF2)
connected with each other by a combinational logic path. Draw the logic diagram and
verify for the setup and hold time violation of the logic circuit.
Setup= 12ns, Hold = 11ns, Clock period= 20ns, Tclk-Q Delay =1 ns.
Combinational path delay= 1.5ns. 5