FPGA-Based Digital Control Implementation of a

Power Converter for Teaching Purposes

José I. Artigas, Luis A. Barragán, Isidro, Urriza, Denis Navarro, and Óscar Lucía
Department of Electronic Engineering and Communications. University of Zaragoza.
María de Luna, 1. 50018, Zaragoza. Spain
E-mail: jiartigas@unizar.es

Abstract- - European universities are nowadays immersed in There are DSPs that include a floating point unit (FPU) to
curricula changes to adapt them to the European Higher speed up floating point operations in software [13]. This way,
Education Area commitments. The new criteria give significant
importance to hands-on training sessions in order to develop
the control algorithm can be written in C language using float
specific skills of the students according to their professional type variables, what is straightforward with regard to a fixed-
training. point implementation. The advances in silicon technology
This paper presents the development and application of a have resulted in FPGAs, which in addition to the configurable
digital controller of a power converter for teaching purposes. logic elements integrate several hardware multipliers, RAM
This design if based on an FPGA and its development is made as blocks, embedded processors… [14], [15]. This technology
close as possible to a real design. The digital controller is allows the designer to use an FPGA to efficiently implement
implemented using three different approaches. Firstly, two real-time controllers.
hardware implementations using fixed-point and floating-point
arithmetic are proposed. The use of the VHDL 1076-2008 Following this trend, this work presents an FPGA-based
standard that includes fixed and floating point packages digital control implementation for a dc-dc converter using
shortens the design cycle. The third approach is a software three different approaches for teaching purposes (Fig. 1). The
implementation based on the embedded soft-core first two approaches are hardware implementations using
microprocessor MicroBlaze. The design of the proposed fixed-point and floating-point arithmetic [16], respectively.
platform is explained, and its use in the hands-on training
sessions is detailed. The third approach is a software implementation using the
embedded soft-core microprocessor MicroBlaze from Xilinx.
I. INTRODUCTION In order to verify the functionality, the power converter,
the analog to digital converter (ADC), and the digital
Electronics curricula in European universities are evolving controller are simulated in closed-loop using VHDL [17].
to converge in common criteria according to the European This paper is organized as follows. Section II describes the
Higher Education Area [1]. The new trends emphasize the power converter selected as a case of study for digital control
importance of developing specific skills of the students, design, along with its implementation. Section III explains
where hands-on training sessions play a key role [2]. In the digital controller design and the three proposed
particular, an applied and professional orientation of the implementation approaches. Section IV describes the use of
developed activities is desired. the proposed platform in a digital control course and, finally,
This paper is focused on the digital control applied to Section V summarizes the main conclusions of this paper.
power converters. Digital control has become a key aspect of
the power converter design process [3], determining the final
reliability and performance. In order to cover the whole
controller design process, a hands-on training tool is
proposed.
Most of the digital controllers developed up to now have
been implemented on Digital Signal Processors (DSPs) [4]-
[6], or Field-Programmable Gate Arrays (FPGAs) [7]-[9].
The DSP user develops software code using high level
languages, such as C. The FPGA user describes digital
hardware using a Hardware Description Language (HDL)
[10].
Control algorithms are usually designed in a floating-point
format often using tools, such as MATLAB. The conversion
of these algorithms to run on a fixed-point DSP is a laborious
and time-consuming task [11]. In the same line, [12] Fig. 1. Reference example: Buck converter digitally controlled.
identifies floating-point to fixed-point conversion as a
difficult aspect of implementing an algorithm on an FPGA.

978-1-4577-0133-7/11/$26.00 ©2011 IEEE 55

 II. SYSTEM DESCRIPTION
Fig. 1 shows the reference example used along the paper.
The power stage is a synchronous buck converter with the
following parameters: input voltage VIN = 5 V, L = 68 H,
C = 220 F, capacitor ESR (equivalent series resistance)
RC = 80 m, inductor DC resistance RL = 98 m, load
resistances RO = 5 , and switching frequency
fsw = 100 kHz. The output voltage vo has to be regulated at
Vo_ref = 2.5 V. Switch Q3 is included to produce load
transients.
The output voltage is measured by using an ADC with full
scale voltage VFS = 3.3 V. A current shunt monitor with a
second ADC is also included to sense the inductor current in
order to evaluate different control strategies.
This paper describes a voltage control strategy, where the
voltage ADC converts the output voltage to a digital word.
Fig. 2. Proposed buck-converter board schematic.
56
The error between the desired and measured output voltage is
processed by a digital controller C(z) to determine the value
of the switch duty ratio. The digital pulse width modulator
(DPWM) generates the driving signals that control the buck
switches.
A printed circuit board including the buck converter,
ADCs, and conditioning circuits has been developed for lab
exercises. Fig. 2 shows a detailed schematic of the board.
Two ADCS7476 12-bit serial A/D converter chips are
included. The circuitry around IC3 and IC5 conform 2-pole
Bessel low-pass anti-aliasing filters. Connector JP2 fits to the
12-pin Pmod connectors available in several low cost Digilent
FPGA development boards, like Nexys2, Atlys or Genesys.
Next Section describes the digital controller designed, and
the different implementations considered for digital control
courses.
 III. FGPA-BASED DIGITAL CONTROL
The continuous time transfer function of the plant Gp(s),
including the buck converter, the ADC gain Kadc, and the
PWM gain Kpwm is:
Gp ( s )  K pwm  Gvd  s   K adc .
The small signal model of the buck converter in s domain
[18] is shown in (2) where R  R0 2 or R  R0 depending
on the state of the switch Q3.
R
VIN  RCCs 1
R  RL
Gvd  s  
 R  RC  2 
LC   s   RCC   R / / RL  C 
 R  RL   R  RL 
With R  R0 2 :
8.468 105 s  4.811
Gvd ( s )  . (3)
1.486 10 8 s 2  6.452 105 s  1
In a simple counter-based implementation, the DPWM
resolution is equal to the FPGA clock frequency (50 MHz)
divided by the switching frequency (100 kHz), yielding 500
in this case. The 9-bit duty cycle command is regarded as an
unsigned fraction. Thus, the gain is [6]:
512
K pwm  . (4)
500
The ADC resolution must be lower than the DPWM in
order to avoid limit-cycling oscillations. Then, only the 8
most significant bits of the ADC are used. The 8-bit ADC
measures analog voltages in the range [0.0, 3.3 V]. The result
is considered as an unsigned integer. Thus, the gain is [6]:
28 1
K adc  V .
3.3
For a better performance, the ADC resolution could be
increased by implementing a high-resolution DPWM.
Several methods can be used in order to design the digital
controller. A digital redesign of a suitable analog controller
GC(s) has been used here. The transfer function of the
proposed analog controller is:
k ( s  z1 )( s  z L )
GC ( s ) 
s ( s  pL )
The system bandwidth is set at 5 kHz with a phase margin
(PM) of 60º. Then, the analog controller must be designed
with a PM of 69º to take into account the phase lag
introduced by the DPWM. The discrete-time controller GC(z)
obtained by using the bilinear transformation from the former
analog controller is:
(1)
. (2)
L 
 s 1
Fig. 3. Open-loop Bode plot.
b0  b1 z 1  b2 z 2
C ( z)  , (7)
1  a1 z 1  a2 z 2
where:
 b0 , b1 , b2    0.0528,  0.0964, 0.0438 ,
(8)
 a1 , a2    1.5182, 0.5182  .
Fig. 3 shows the open loop frequency response of the
discretized plant with the controller. Notice that the frequency
domain performance parameters agree quite well with the
specifications.
After obtaining the digital controller, the next step is the
FPGA implementation of the control system. Next
subsections describe the different proposed implementations.
A Fixed-Point and Floating-Point Implementations
Fig. 4 shows the block diagram of the digital circuit to be
implemented in the FPGA. It consists basically of five
(5)
blocks: the DPWM generator, the ADC interface, the digital
controller, the user interface, and the control unit.
A counter-based DPWM has been implemented, with a
free-running counter CNT_D, a register REG_D that stores
the duty command, and a digital comparator. The signal Q1
that controls the converter switch is set to turn on it when the
duty command is greater than the counter value. The ADC
interface block generates the NCS and SCLK signals that
control the ADC converter, reads its serial data output
(6)
SDATA, and stores the conversion result in ADCREG register.
The user interface block reads four slide switches (SW1 to
SW4) connected to the FPGA. SW1 allows the circuit to
operate on closed-loop or open-loop mode. In the last mode,
the duty-cycle is held constant. SW2 allows generating load
transients by controlling Q3. SW3 increments, and SW4
decrements the reference command (Vref) in closed-loop, or
the duty command (REG_D) in open-loop. The ADC
57
measures are displayed in the four-digit seven-segment The custom peripherals are DPWM and ADC Interface.
display included in the FPGA board. The control unit The DPWM block generates the gating signal Q1 of the
synchronizes all the blocks by means of a finite state machine power converter. Besides, it also generates an interrupt signal
(FSM). at the end of the switching period in order to implement the
The digital controller reads the conversion result closed-loop control. The ADC Interface block generates the
(ADCREG), computes the error between the desired (Vref) NCS and SCLK signals that control the ADC converter, reads
and measured output voltage, and calculates the new duty its serial data output SDATA, and stores the conversion result
command DUTY. The block ToInt is included to perform the in a register.
format conversion from DUTY to the DPWM input register 2) Software platform: This platform contains the program
REG_D. The implementation of the controller, including the which runs on the MicroBlaze processor. This interrupt-
word-length selection and the format-conversion tasks can be driven program implements two main tasks. Firstly, it
carried out as explained in [19], [20]. Besides, the VHDL manages the user interface in background. Secondly, it
1076-2008 [21] fixed_pkg and float_pkg are used to obtain executes the closed-loop control algorithm associated to the
straight-forward fixed-point and floating-point DPWM interrupt, in order to obtain a new duty command
implementations respectively. every switching cycle. The proposed controller can be
implemented either using fixed-point arithmetic or floating-
B Embedded-Processor Implementation
point arithmetic. For this design, floating-point arithmetic is
used taken advantage of the floating point unit (FPU).
Fig. 5 shows the block diagram of the FPGA embedded
processor implementation. A System on Programmable Chip
(SoPC) arquitecture based on the soft-core processor IV. CASE STUDY
MicroBlaze from Xilinx has been implemented [22], [23].
The system consist therefore of the processor plus a set of A Background
peripherals which are connected to MicroBlaze through the
Processor Local Bus (PLB). The implementation is therefore The proposed teaching tool has been developed for the
divided into two platforms: Hardware platform, and Software subject Digital Control of Power Converters of the
platform. Electronics Master taught in the University of Zaragoza,
1) Hardware platform: This platform contains the digital Spain. This is an elective subject included in the Power
hardware of the system. It consists of two types of hardware Electronics curricula of the master. The main skill to be
blocks: Intellectual Property (IP) cores, which are provided developed by the students is the implementation of digital
by Xilinx through the library of components; and custom controllers for power converters, focusing on the FPGA
hardware peripherals, which have been described in VHDL technology. In this subject, the hardware implementation
language and implement specific tasks. using fixed-point arithmetic is proposed.
The following IP cores have been used: The MicroBlaze
processor, which is an embedded 32-bit RISC (Reduced
Instruction Set Computer) soft-core optimized for Xilinx
FPGAs; Block RAM (BRAM), memory block of 32 kB that Software Platform (C)
includes program data and instructions; and Watchdog, timer 4
SW1-SW4
module which helps ensure that the processor is running. CLOSED–LOOP
CONTROL
USER
INTERFACE
12
Display
Q1 Q3

IP CORES CUSTOM HW
DPWM Control Unit
FPGA

A>B
Interrupt

A B
Modulator

4
SW1-SW4 LMB
DPWM
BRAM

CNT_D User 12 MicroBlaze Q1

LD
FSM Display 32
®
REG_D Interface
Q3
9
FPGA

Processor Local Bus 32

ToInt EndC StartC
2 NCS,
Watchdog ADC Control SCLK
DUTY Vref SDATA
2
ADCREG

NCS
1
b0  b1z  b2 z 2
e(k) + 8 8 Interface SCLK
-
1  a1z 1  a2 z 2 Control SDATA
Hardware Platform (VHDL)

Digital controller ADC Interface

Fig. 5. FPGA embedded processor implementation of the digital
control.
Fig. 4. FPGA hardware implementation of the digital control.

58
 B Hands-on Training Sessions

The materials required for the sessions are the power

converter board, the FPGA board, a 5 V, 1 A power supply,
and an oscilloscope; apart from the Integrated Design
Environment (ISE) tools from the FPGA vendor. The power
converter has been designed and implemented in the
University, whereas affordable Digilent FPGA boards are
used to implement the digital controller. Fig. 6 shows the
final aspect of the buck converter attached to a Nexys2 FPGA
board.
The hands-on training sessions are divided into 3 major
topics:
(a)
1. A/D Converter Interface and DPWM
This topic is divided into two 2-hours sessions where the
students design and test the A/D converter interface and the
DPWM, as shown in Fig. 4. The A/D converter interface is
tested by measuring and displaying the buck output voltage
from a constant duty-cycle, i.e., from an open-loop buck
control. The measures are displayed in the four-digit seven-
segment display included in the FPGA board. Besides, some
guidelines about the need and implementation of high-
resolution DPWMs are given.

2. VHDL Modeling of Power Converters (b)

In this session the students learn how to model a power
converter by using a hardware description language, VHDL.
The aim of this session is to obtain a VHDL model of the
power converter, which will be used to simulate the whole
system including the digital control hardware and the power
converter.
Fig. 7. Load transient. (a) Simulation results. (b) Experimental
measurements (50 mV/div, 50 µs/div).
3. Digital Control of the Buck Converter
This session is also divided into two 2-hours sessions. The
students learn how to design and implement a digital
controller. A special emphasis is placed on the arithmetic
implementation using fixed-point representation. The students
simulate the complete system by using the VHDL model
obtained in previous sessions. Besides, the final controller is
tested by using the experimental platform previously
described.

C Future Developments

The proposed platform has been introduced during the

2010-2011 academic year with a group of 15 students,
obtaining a positive feedback from them. Future
developments include an analysis including both teachers and
students to assess the main benefits and drawbacks of the
proposed platform. This will allow improving the hands-on
training sessions for teaching digital controller design.
Several features included in the converter board have not
tested yet. Switch Q2 can be controlled in order to have a
Fig. 6. Buck converter prototype and Nexys2 FPGA board used in synchronous buck. Besides, advanced control strategies may
hands-on training sessions.
be implemented by using the available current loop.
In addition to this, the platform is intended to be also used

59
 for teaching the elective subject Embedded Systems. In this
subject, the FPGA-based control architecture includes an
embedded processor and additional digital hardware. The
buck converter and the proposed digital controller can be
introduced as an easy to understand application example.
V. CONCLUSIONS
In this paper, a hands-on training platform for teaching
digital control applied to power converters has been
proposed. It is composed of a buck converter and an FPGA-
based control architecture.
Three different implementations of the digital control have
been proposed. Two of them are hardware implementations
using fixed-point and floating-point arithmetic, and the third
is a software implementation using a soft-core embedded
processor.
The proposed platform has been introduced during the
academic year 2010-2011 in the elective subject Digital
Control of Power Converters obtaining positive results.
Future improvements based on the assessment of this
methodology will be performed, and the proposed platform
will be extended to other subjects.
ACKNOWLEDGMENT
This research was supported in part by the Spanish
MICINN under Project TEC2010-19207 and Project
CSD2009-00046, by DGA under Project PI065/09, and by
the Bosch and Siemens Home Appliances Group.
The authors are with the Department of Electronic
Engineering and Communications and the Aragon Institute of
Engineering Research (I3A).
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