UNIT-I

1) Acronym of VLSI ( a )
a) Very large scale integration b) Very length semiconductor & Insulator
c) Very large size insulator d) none

2) What is meant by the term VLSI ( c )

a) a device containing 100 no of transistors
b) a device containing 10 no of transistors
c) a device containing 100000 no of transistors
d) a device containing 1million no of transistors

3) Which law describes the exponential growth of IC complex city? ( c )

a) Lenz’s law b) Faraday’s law c) Moore’s law d) Nyquists theorem

4) The mode of MOSFET when Vgs<<Vt ( a )

a) Accumulation b) Depletion c) Weak Inversion d) Strong Inversion

5) Fluid model assumes electrical charge as (b )

a) Geometry of container b) Fluid c) Tub d) Bath tub curve

6) Silicon dioxide serves as ( d )

a) Mask against implant b) Isolate one device from another
c) Provides surface passivation d) All the above

7) Poly silicon is used as ( b )

a) Source electrode b) Gate electrode c) Drain electrode d) None

8) Th region of MOSFET when Vds > Vgs – Vt ( b )

a) Non saturation b) Saturation c) Cut off d) none

9) Advantage of CMOS technology (a )

a) Low power consumption b) High gain
c) High speed d) High load driving capability

10) Which of the following technology has high output drive current ( d )
a) nMOS b) pMOS c) CMOS d) Bipolar

11) Which of the following is true for an nMOS transistor operating in its linear (or) triode
mode? ( a )
a) Vds <(Vgs -Vt) b) Vds>(Vgs-Vt) c) Vgs<Vt d) Vgs=0v

12 ) Which of the following reduces latch up ( d )

a) Twin tub b) BiCMOS
c) SOI d) All the above
13) The capacitance of transistor gate is proportional to what? ( a )
a) The width of the gate b) The length of the gate
c) The area of the gate d) The depth of the gate

14) Switch logic is based on ( a )

a) Pass transistor b) Invertors c) Gates d) none

15) Figure of merit of MOS transistor is ( d )

a) gm b) L c) Cg d) ω0

16) The problem of forming low resistance path between VDD and Vss due to parasitic
components in well CMOS structures is called ( b )
a) Body effect b) Latch up c) Cross talk d) Channel length modulation

17) The changes in threshold voltage Vt due to voltage difference between the substrate
and the source of MOS transistor called ( a )
a) Body effect b) Latch up c) Cross talk d) Channel length modulation

18) Identify the basic requirement for producing a complete range of logic circuits (b )
a) AND gate b) Inverter c) Amplifier d) NAND gate

19) In nMOS inverter the pull-up transistor is (b )

a) pMOS b) Depletion nMOS c) Enhance nMOS d) none

20 BiCMOS is a combination of ( d )
a) nMOS & pMOS b) Bipolar & nMOS c) nMOS & CMOS d) Bipolar & CMOS

21) In saturation region Id independent on ( c )

a) Vgs b) Vgs & Vds c) Vds d) none

22) The condition to be satisfied for βn=βp is of CMOS ( c )

a) ωP/LP=ωn/Ln b) ωp/Lp=2.5ωn/Ln
c) ωn/Ln=2.5 ωp/Lp d) ωP/LP=5 ωn/Ln

23) The pull up to pull down ratio of an nMOS inverter driven by another nMOS inverter is
( a )
a) 4 b) 1/4 c) 8 d) 1/8

24) nMOS pass transistor good at ( a )

a) Logic ‘0’ b) Logic ‘1’ c) Either logic’0’ or ‘1’ d) Neither logic ‘0’ or ‘1’

25) CMOS pull-up transistor is ( b )

a) nMOS b) pMOS c) Bipolar d) SCR
26) Which of the following gate is good at both (0 & 1) logic levels ( c )
a) nMOS b) pMOS c) Transition gate d) Passive

27) Low level noise margin is (c)

a) VOH-VIL b) VIL-VOH c)VIL-VOL d) VOL-VIL

28) Sub threshold current is ( a )

a) Current before Vt b) Current After Vt c) Pinch off current d) none

29) Typical value of Vt for nMOS enhancement (d )

a) 0.4 Vdd b) Vdd c) 0.3Vdd d) 0.2Vdd

30) While driving very low capacitive loads TG MOSFETS can operates in ( c )
a) Linear, Saturation & cut off b) Saturation & Cut off
c) Linear & Cut off d) none
UNIT- 2

1) Which of the following layer isolates the layers of MOS circuits ( c )

a) n diffusion b) Metal
c) Sio2 d) Poly silicon

2) Area capacitance is given by ( a )

a) C= ЄA/D b) C= Є/D c) C= A/D d) none

3) The combination of silicon and tantalum is known as (a )

a) Silicide b) Poly silicon c) Implant d) Burried contact

4) Typical value of poly silicon sheet resistance ( c)

a)1- 2ohms b) 5-10 ohms c)15-100 ohms d) 1 kohm

5) Unit of layer area capacitance ( b )

a) F/m2 b) pF/µm2 c) F/cm2 d)m2

6) Relative permittivity of Sio2 ( d )

a) 1 b) 2 c) 3 d) 4

7) The delay through a pair of similar nMOS inverters is ( a )

a) (1+Zpu/Zpd)τ b) (1+Zpd/Zpu)τ c) (Zpu/Zpd)τ d) (Zpd/Zpu)τ

8) The delay for BiCMOS inverter is reduced by a factor of ----- compared with a CMOS
inverter( c )
a) hie b) hre c) hfe d) hoe

9) The relation between rise time, fall time and βp and βn given as ( b )
a) 𝜏𝑓 /τr = βn/βp b) τr/τf = βn/βp c) τf/τr = βp/βn d) τr/τf = βp/βn

10) For equal n and p transistor generators the relation between τr and τf is ( a )
a) τr=2.5Ƭ𝑓 b) τf=2.5τr c) τr=5τf d) 𝜏𝑓 =5τr

11) With respect to VLSI, the time constant τ is defined as (a )

a) Rs x Cg b) RC c) RCL d) RsC

12) Which of the following layer is preferred for Vdd & Vss ( b )
a) Diffusion layers b) Metal layers c) Poly silicon bias d) Implants

13) Pass transistor logic suffers with ( b )

a) Latch up b) Threshold drop c) Two power supplies d) Leakage
14) Charge sharing sharing observed in ( c )
a) Static nMOS b) Static CMOS c) Dynamic CMOS d) BiCMOS

15) Identify the technique to drive large capacitive loads ( d )

a) Supper buffer b) Cascading inverter as drivers c) BiCMOS d) All the above

16) 2 phase clocking generator includes ( a )

a) Inverters b) capacitors c) Inductors d) only Resistors

17) The total no.of transistors in N input static CMOS is ( c )

a) N b) N+1 c) 2N d) N/2

18) The relation between Vinv and βn/βp is ( b )

a) Direct b) Inverse c) Independent d)None

19) Ring oscillator consists of ( a )

a) Odd no.of inverters b) Even no.of inverters
c) Either odd or even no.of nverters d) none

20) The time period of 3 stage ring oscillator is ( b )

a) td b) 2.3 td c) 2td d) 4td

21) The expanded function of two variable using Shahnon’s expansion theorem ( a )
a) f(a,b)=goa’b’+g1 a’b+g2 a b’+g3 a b b) f(a,b)=goa’b’+g1 a’b+g2 a b’
’ ’ ’
c) f(a,b)=goa b +g1 a b d) none

22) Identify the advantage of pass transistor logic ( d )

a) Ration less b) Power less c) Lower area d) All the above

23) The purpose of PMOS in CPL structure is ( a )

a) Swing restoration b) To compliment the input
c) To realize the logic d) none

24) Cross coupled inverters exists in ( a )

a) Swing-Restored Pass-Transistor Logic b) Double Pass-Transistor Logic
c) Complementary pass-transistor logic d) none

25) Fan in of 4 input NOR gate is ( b )

a) 2 b) 4 c) 8 d) 1

26) The preferable gates in CMOS logic is ( b )

a) NOR gate b) NAND gate c) either NOR or NAND gate d)none

27) Which of the following uses clock ( d )

a) nMOS logic b) pseudo nMOS logic c) Static CMOS d) Dynamic CMOS
28) The delay in clock signal during its journey through a no. of stages is called ( b )
a) Clock delay b) Clock skew c) Clock glitch d) none

29) The no.of transistors required in dynamic CMOS if fan in N is ( a )

a) N+1 b) N2 c) 2N d) N

30) Transconductance ration of CMOS NOR gate is ( a )

a) n2βn/βp b) n βn/βp c) n2βp/βn d)2 n βn/βp