PCS-985GE

PCS-985GE
Generator Relay
Instruction Manual
NR Electric Co., Ltd.

Preface
Preface
Introduction
This guide and the relevant operating or service manual documentation for the equipment provide
full information on safe handling, commissioning and testing of this equipment.
Documentation for equipment ordered from NR is dispatched separately from manufactured goods
and may not be received at the same time. Therefore, this guide is provided to ensure that printed
information normally present on equipment is fully understood by the recipient.
Before carrying out any work on the equipment, the user should be familiar with the contents of
this manual, and read relevant chapter carefully.
This chapter describes the safety precautions recommended when using the equipment. Before
installing and using the equipment, this chapter must be thoroughly read and understood.
Health and Safety

The information in this chapter of the equipment documentation is intended to ensure that
equipment is properly installed and handled in order to maintain it in a safe condition.
When electrical equipment is in operation, dangerous voltages will be present in certain parts of
the equipment. Failure to observe warning notices, incorrect use, or improper use may endanger
personnel and equipment and cause personal injury or physical damage.
Before working in the terminal strip area, the equipment must be isolated.
Proper and safe operation of the equipment depends on appropriate shipping and handling,
proper storage, installation and commissioning, and on careful operation, maintenance and
servicing. For this reason, only qualified personnel may work on or operate the equipment.
Qualified personnel are individuals who:
 Are familiar with the installation, commissioning, and operation of the equipment and of the
system to which it is being connected;
 Are able to safely perform switching operations in accordance with accepted safety
engineering practices and are authorized to energize and de-energize equipment and to
isolate, ground, and label it;
 Are trained in the care and use of safety apparatus in accordance with safety engineering
practices;
 Are trained in emergency procedures (first aid).
Instructions and Warnings

The following indicators and standard definitions are used:
PCS-985GE Generator Relay i
Date: 2019-02-21
Preface
DANGER! means that death, severe personal injury and considerable equipment damage
will occur if safety precautions are disregarded.
WARNING! means that death, severe personal and considerable equipment damage
could occur if safety precautions are disregarded.
CAUTION! means that light personal injury or equipment damage may occur if safety
precautions are disregarded.
NOTICE! is particularly applies to damage to device and to resulting damage of the protected
equipment.
DANGER!
NEVER allow a open current transformer (CT) secondary circuit connected to this
device while the primary system is live. Open CT circuit will produce a dangerously high
voltage that cause death.
WARNING!
ONLY qualified personnel should work on or in the vicinity of this device. This personnel
MUST be familiar with all safety regulations and service procedures described in this
manual. During operating of electrical device, certain part of the device is under high
voltage. Severe personal injury and significant device damage could result from
improper behavior.
WARNING!
Do NOT touch the exposed terminals of this device while the power supply is on. The
generated high voltage causes death, injury, and device damage.
WARNING!
Thirty seconds is NECESSARY for discharging the voltage. Hazardous voltage can be
present in the DC circuit just after switching off the DC power supply.
CAUTION!
 Earthing
Securely earthed the earthing terminal of the device.
 Operating environment
ONLY use the device within the range of ambient environment and in an
environment free of abnormal vibration.
 Ratings
ii PCS-985GE Generator Relay
Date: 2019-02-21
Preface
Check the input ratings BEFORE applying AC voltage/current and power supply to
the device.
 Printed circuit board
Do NOT attach or remove printed circuit board if the device is powered on.
 External circuit
Check the supply voltage used when connecting the device output contacts to
external circuits, in order to prevent overheating.
 Connection cable
Carefully handle connection cables without applying excessive force.
NOTICE!
The firmware may be upgraded to add new features or enhance/modify existing

features, please MAKE SURE that the version of this manual is compatible with the
product in your hand.
Copyright © 2016 NR. All rights reserved.
We reserve all rights to this document and to the information contained herein. Improper use in particular reproduction and dissemination
to third parties is strictly forbidden except where expressly authorized.
The information in this manual is carefully checked periodically, and necessary corrections will be included in future editions. If
nevertheless any errors are detected, suggestions for correction or improvement are greatly appreciated.
We reserve the rights to make technical improvements without notice.
NR ELECTRIC CO., LTD. Tel: +86-25-87178888

Headquarters: 69, Suyuan Avenue, Jiangning, Nanjing 211102, China Fax: +86-25-87178999
Manufactory: 18, Xinfeng Road, Jiangning, Nanjing 211111, China Website: www.nrelect.com, www.nrec.com
P/N: ZL_PCS-985GE_X_Instruction Manual_EN_Overseas General_X Version: R1.02
PCS-985GE Generator Relay iii
Date: 2019-02-21
Preface
Documentation Structure
The manual provides a functional and technical description of this relay and a comprehensive set
of instructions for the relay’s use and application.
All contents provided by this manual are summarized as below:
1 Introduction
Briefly introduce the application, functions and features about this relay.
2 Technical Data
Introduce the technical data about this relay, such as electrical specifications, mechanical
specifications, ambient temperature and humidity range, communication port parameters, type
tests, setting ranges and accuracy limits and the certifications that our products have passed.
3 Operation Theory
Introduce a comprehensive and detailed functional description of all protective elements.
4 Supervision
Introduce the automatic self-supervision function of this relay.
5 Management
Introduce the management function (measurment and recording) of this relay.
6 Hardware
Introduce the main function carried out by each plug-in module of this relay and providing the
definition of pins of each plug-in module, typical wiring is provided.
7 Settings
List settings including system settings, communication settings and etc.
8 Human Machine Interface

Introduce the hardware of the human machine interface (HMI) module and a detailed guide for the
user how to use this relay through HMI. It also lists all the information which can be view through
HMI, such as settings, measurements, all kinds of reports etc.
9 Configurable Function
Brief introduction of configurable functions and configuration software.
10 Communication
Introduce the communication port and protocol which this relay can support, IEC60970-5-103,
IEC61850 and DNP3.0 protocols are introduced in details.
11 Installation
iv PCS-985GE Generator Relay
Date: 2019-02-21
Preface
Introduce the recommendations on unpacking, handling, inspection and storage of this relay. A
guide to the mechanical and electrical installation of this relay is also provided, incorporating
earthing recommendations.
12 Commissioning
Introduce how to commission this relay, comprising checks on the calibration and functionality of
this relay.
13 Maintenance
A general maintenance policy for this relay is outlined.
14 Decommissioning and Disposal

A general decommissioning and disposal policy for this relay is outlined.
15 Manual Version History

List the instruction manual version and the modification history records.
Typographic and Graphical Conventions
Deviations may be permitted in drawings and tables when the type of designator can be obviously
derived from the illustration.
The following symbols are used in drawings:
&
AND gate
≥1
OR gate
Comparator
BI Binary signal via opto-coupler
SET I> Input signal from comparator with setting
EN Input signal of logic setting for function enabling
SIG Input of binary signal except those signals via opto-coupler
OTH Input of other signal
PCS-985GE Generator Relay v
Date: 2019-02-21
Preface
XXX Output signal
Timer
t
Time (optional definite-time or inverse-time characteristic)
t
10ms 2ms
Timer [delay pickup (10ms), delay dropoff (2ms), non-settable]
[XXX] 0ms
Timer (delay pickup, settable)
0ms [XXX]
Timer (delay drop off, settable)
[XXX] [XXX]
Timer (delay pickup, delay drop off, settable)
IDMT Timer (inverse-time characteristic)
---xxx is the symbol
Symbol Corresponding Relationship
Basic
A, B, C L1, L2, L3 R, Y, B
AN, BN, CN L1N, L2N, L3N RN,YN, BN
ABC L123 RYB
U (voltage) V U
Example
Ia, Ib, Ic, I0 IL1, IL2, IL3, IN IR, IY, IB, IN
Ua, Ub, Uc VL1, VL2, VL3 UR, UY, UB
Uab, Ubc, Uca VL12, VL23, VL31 URY, UYB, UBR
U0, U1, U2 VN, V1, V2 UN, U1, U2
vi PCS-985GE Generator Relay
Date: 2019-02-21
1 Introduction
1 Introduction
Table of Contents
1.1 Application ....................................................................................................... 1-1

1.2 Functions ......................................................................................................... 1-2
1.3 Features ............................................................................................................ 1-5
List of Figures
Figure 1.1-1 Typical protection scheme 1 of PCS-985GE........................................................... 1-1
List of Tables
Table 1.2-1 Protective functions of PCS-985GE....................................................................... 1-3
Table 1.2-2 Miscellaneous functions of PCS-985GE ............................................................... 1-4
PCS-985GE Generator Relay 1-a
Date: 2016-08-16
1 Introduction
1-b PCS-985GE Generator Relay
Date: 2016-08-16
1 Introduction
1.1 Application
PCS-985GE is a kind of high performance numerical generator protection device, which integrates
main and backup protection into one device. It provides complete protection of a generator in
power plant, and it also provides basic protection of a generator and an excitation transformer.
PCS-985GE can be applied for turbo-dynamo generator, gas-turbine generator, hydro generator
and nuclear power generator with different connection modes.
PCS-985GE provides up to 28 analog input channels including current and voltage inputs. The
generator protections are configurable. Ancillary functions of fault diagnostic, disturbance records,
event records and communication function are integrated in the device.
Figure 1.1-1 ~ Figure 1.1-3 show typical protection schemes of PCS-985GE.
NOTICE!
Current transformers (CT) used for differential protection may be DIFFERENT from
those for backup protection.
PCS-985GE
MR 51GS
Generator Busbar
GCB 81O
24 59P 27P
81U
ncba n l
VT
*
Exciting 32R
87G 50P,51P 21 49S 46G 59N 40G 78 50/27 50BF
Transformer 32F
+
Generator
_
64R 51GN StShut
Low Resistance
Figure 1.1-1 Typical protection scheme 1 of PCS-985GE
PCS-985GE Generator Relay 1-1
Date: 2016-08-16
1 Introduction
PCS-985GE
MR 51GS
Generator Busbar
GCB 81O
24 59P 27P
81U
ncba n l
VT
32R
87G 50P,51P 21 49S 46G 51G/67G 40G 78 50/27 50BF
* Exciting 32F
Transformer
+
Generator
_
*
64R StShut
Busbar 1
Busbar 2
Busbar VT
TCB
l n abcn
PCS-985GE
MR
Main
Transformer
GCB 81O
24 59P 59NIT 64S1
81U
ncba n l
*
VT1
ncba n l
VT2 Exciting 87ET 50P,51P 49E 87G 50P,51P 21 64S2 40G 78 49S 46G 32R 50/27 50BF
* Transformer
+
Generator *
_
64R
1.2 Functions
 Protective Functions
1-2 PCS-985GE Generator Relay
Date: 2016-08-16
1 Introduction
The protective functions listed in following table are available for PCS-985GE, the functions can be
configured according to user’s requirement.
Table 1.2-1 Protective functions of PCS-985GE
No. Function ANSI

1 Generator current differential protection 87G
2 Generator neutral point transverse differential protection 87NTG
3 Generator inter-turn protection 59NIT
4 Generator stator overload protection 49S
5 Generator fundamental zero-sequence stator ground fault protection 64S1
rd
6 Generator 3 harmonic stator ground fault protection 64S2
7 Generator Ping-Pang type rotor ground fault protection 64R
Generator rotor ground fault protection with low-frequency square-wave voltage
8 64RInj
injection
9 Generator rotor winding overload protection 49E
10 Generator inadvertent energization protection 50/27
11 Generator out-of-step protection 78
12 Generator startup and shutdown protection StShut
13 Generator shaft overcurrent protection 51GS
14 Generator negative-sequence overload protection 46G
15 Generator reverse power protection 32R
16 Generator low forward power protection 32F
Definite-time overexcitation protection
17 24
Inverse-time overexcitation protection
18 Loss of excitation protection protection 40G
Definite-time phase overcurrent protection
19 50/51P
Inverse-time phase overcurrent protection
Definite-time phase overvoltage protection
20 59P
Inverse-time phase overvoltage protection
Definite-time phase undervoltage protection
21 27P
Inverse-time phase undervoltage protection
22 Underfrequency protection 81U
23 Overfrequency protection 81O
Phase-to-phase impedance protection
24 21
Phase-to-earth impedance protection
25 Circuit breaker failure protection 50BF
26 Mechanical protection MR
27 Excitation transformer current differential protection 87ET
28 Fault recorder FR
29 VT circuit supervision VTS
30 CT circuit supervision CTS
 Miscellaneous functions
Date: 2016-08-16
1 Introduction
Miscellaneous functions are listed in the following table, such as measurement, self-supervision
and oscillography, communication functions, and etc.
Table 1.2-2 Miscellaneous functions of PCS-985GE
Miscellaneous functions
Measurement 24 samples per cycle for current and voltage measurement
Programmable binary inputs
Programmable binary outputs

Configurable function
Programmable LED indicators
Configurable protection functions
Self-supervision Relay hardware supervision and secondary circuit supervision
Disturbance 64 fault reports

recording 64 disturbance waveforms
Oscillography function (1) Protection picks up to trigger
Trigger mode (2) Manually trigger on keypad
(3) Remotely trigger through PCS-Explorer2 software
1024 supervision alarm events
Event recording 1024 binary input events
1024 device log events
Local HMI LCD and keypad
PCS-Explorer2 software or substation automation system

Remote HMI
software
Serial port
Ports type Electrical Ethernet port
Optical Ethernet port
Rear communication IEC 60870-5-103 (Ethernet port or serial port)
ports to host IEC 61850-8-1 (Ethernet port)
Protocol type Modbus (Serial port)
DNP 3.0 (Ethernet port)
(Specified when ordering)
Rear communication port to printer One RS-232 port
Four kinds of clock synchronization methods:

1) Conventional
 PPS (RS-485): Pulse per second (PPS) via RS-485
differential level
Time synchronization  IRIG-B (RS-485): IRIG-B via RS-485 differential level
 PPM (DIN): Pulse per minute (PPM) via the optical
coupler
 PPS (DIN): Pulse per second (PPS) via the optical
coupler
Date: 2016-08-16
1 Introduction
Miscellaneous functions
2) SAS
 SNTP (PTP): Unicast (point-to-point) SNTP mode via
Ethernet network
 SNTP (BC): Broadcast SNTP mode via Ethernet network
 Message (IEC103): Clock messages through IEC103
protocol
3) Advanced
 IEEE1588: Clock message via IEEE1588
 IRIG-B (Fiber): IRIG-B via optical-fibre interface
 PPS (Fiber) PPS: Pulse per second (PPS) via
optical-fibre interface
4) NoTimeSyn
Friendly HMI interface with LCD and 9-button keypad on the

front panel.
1 front multiplex RJ45 port for testing and setting
User Interface
1 RS-232 rear ports for printer
Language switchover—English+ selected language
Auxiliary software—PCS-Explorer2
10 setting groups are available
Voltage and current drift auto-adjustment
1.3 Features
 Configurable Function
Modules of the device adopt intelligent design, amount of input and output modules and module
slot position are configurable. User can increase or decrease the amount of AC input module,
binary input module and binary output module, and terminals of those modules can be defined
according to actual requirement. Besides, configurability is also reflected in software design of
device, which means that user can hide the protective element not used or add new protective
module not in standard configuration.
 Parallel calculation of double DSP system
The hardware of the device comprises a 32-bit microprocessor and two 32-bit digital signal
processors (DSP). Those processors can operate in parallel companied by fast A/D converter. The
32-bit microprocessor performs logic calculation and the DSP performs the protection calculation.
High performance hardware ensures real time calculation of all protection relays within a sampling
interval.
On the premise of 24 samples per cycle, all data measurement, calculation and logic
discrimination could be done within one sampling period. The event recording and protection logic
calculation are completed simultaneously.
Date: 2016-08-16
1 Introduction
 Independent fault detector
Independent fault detectors in fault detector DSP module for connecting power supply of output
relays. The relay can drive a tripping output only when protection element on protection DSP
module operates with the fault detector in the fault detector DSP module operating simultaneously.
This kind of independent supervision of tripping outputs using fault detectors can avoid any
mal-operation possibly caused by any hardware component failure. This highly increases the
security. Please refer to Chapter 6 for details.
 Configurable tripping output
The tripping output contacts can be configured by tripping matrix and suitable to any mode of
tripping.
 Fault recording function
Event records include 1024 binary input events and 1024 alarm events. Disturbance records
including 64 fault reports, and 64 disturbance waveforms, and file format of waveform is
compatible with international COMTRADE91 and COMTRADE99 file. Analog inputs and binary
inputs can be recorded, and three oscillography triggering mode are supported, which are
protection pickup triggering, manual triggering on keypad of device, and remote triggering through
PCS-Explorer2 software.
 Powerful PC tool software
Powerful PC tool software (PCS-Explorer2) can fulfill protection function configuration, modify
setting and waveform analysis.
 Integration of main and backup protection
Main and backup protection are integrated in one set of protection device. Protection information
is shared by all parts. The device can record all relevant waveforms of any fault.
 High sensitive and securable DPFC biased differential protection
DPFC (deviation of power frequency component) biased current differential protection element is
regardless of the load current and is sensitive to small internal fault current within the generator. Its
performance against current transformer saturation is also good.
 Reliable CT Saturation Detection
Based on the operation sequence of DPFC restraint current element and DPFC differential current
element of differential protection, external fault with CT saturation or internal fault can be
distinguished correctly.
Date: 2016-08-16
2 Technical Data
2 Technical Data
Table of Contents
2.1 Electrical Specifications ................................................................................. 2-1

2.1.1 AC Current Input ................................................................................................................... 2-1
2.1.2 Sensitive AC Current Input (5mA/350mV-G-2 and 0.25A/1.52V) ........................................ 2-1
2.1.3 AC Voltage Input ................................................................................................................... 2-1
2.1.4 Power Supply ....................................................................................................................... 2-2
2.1.5 Transducer Input .................................................................................................................. 2-2
2.1.6 Binary Input .......................................................................................................................... 2-2
2.1.7 Binary Output........................................................................................................................ 2-2
2.2 Mechanical Specifications .............................................................................. 2-3

2.3 Ambient Temperature and Humidity Range .................................................. 2-4
2.4 Communication Port ....................................................................................... 2-4
2.4.1 EIA-485 Port ......................................................................................................................... 2-4
2.4.2 Ethernet Port ........................................................................................................................ 2-4
2.4.3 Optical Fiber Port ................................................................................................................. 2-4
2.4.4 Print Port ............................................................................................................................... 2-4
2.4.5 Clock Synchronization Port .................................................................................................. 2-5
2.5 Type Tests ........................................................................................................ 2-5

2.5.1 Environmental Tests ............................................................................................................. 2-5
2.5.2 Mechanical Tests .................................................................................................................. 2-5
2.5.3 Electrical Tests ...................................................................................................................... 2-5
2.5.4 Electromagnetic Compatibility .............................................................................................. 2-5
2.6 Certifications .................................................................................................... 2-6

2.7 Terminals .......................................................................................................... 2-6
2.8 Measurement Scope and Accuracy ............................................................... 2-7
2.9 Management Function..................................................................................... 2-7
Date: 2016-08-16
2 Technical Data
2.9.1 Control Performance ............................................................................................................ 2-7
2.9.2 Clock Performance ............................................................................................................... 2-7
2.9.3 Fault and Disturbance Recording......................................................................................... 2-7
2.9.4 Binary Input Signal ............................................................................................................... 2-7
2.10 Protective Functions ..................................................................................... 2-7

2.10.1 Generator Current Differential Protection .......................................................................... 2-8
2.10.2 Generator Neutral Point Transverse Differential Protection .............................................. 2-8
2.10.3 Generator Inter-Turn Protection ......................................................................................... 2-8
2.10.4 Generator Stator Overload Protection ................................................................................ 2-8
2.10.5 Generator Fundamental Zero-sequence Stator Ground fault Protection........................... 2-9
2.10.6 Generator 3rd Harmonic Stator Ground Fault Protection .................................................. 2-9
2.10.7 Generator Ping-Pang Type Rotor Ground Fault Protection ............................................... 2-9
2.10.8 Generator Rotor Ground Fault Protection with Low-frequency Square-wave Voltage
Injection ......................................................................................................................................... 2-9
2.10.9 Generator Rotor Winding Overload Protection .................................................................. 2-9
2.10.10 Generator Inadvertent Energization Protection ............................................................. 2-10
2.10.11 Generator Out-of-Step Protection................................................................................... 2-10
2.10.12 Generator Startup and Shutdown protection.................................................................. 2-10
2.10.13 Generator Shaft Overcurrent Protection ........................................................................ 2-10
2.10.14 Generator Negative-sequence Overload Protection ...................................................... 2-11
2.10.15 Generator Reverse Power Protection ............................................................................ 2-11
2.10.16 Generator Low Forward Power Protection..................................................................... 2-11
2.10.17 Overexcitation Protection ............................................................................................... 2-11
2.10.18 Loss-of-excitation Protection .......................................................................................... 2-12
2.10.19 Phase Overcurrent Protection ........................................................................................ 2-12
2.10.20 Overvoltage Protection ................................................................................................... 2-12
2.10.21 Undervoltage Protection ................................................................................................. 2-13
2.10.22 Overfrequency Protection .............................................................................................. 2-13
2.10.23 Underfrequency Protection ............................................................................................ 2-13
2.10.24 Impedance Protection .................................................................................................... 2-13
Date: 2016-08-16
2 Technical Data
2.10.25 Breaker Failure Protection ............................................................................................. 2-13
2.10.26 Mechanical Protection .................................................................................................... 2-14
2.10.27 Excitation Transformer Current Differential Protection .................................................. 2-14
PCS-985GE Generator Relay 2-c
Date: 2016-08-16
2 Technical Data
2-d PCS-985GE Generator Relay
Date: 2016-08-16
2 Technical Data
2.1 Electrical Specifications

2.1.1 AC Current Input
Phase rotation ABC
Nominal frequency 50Hz, 60Hz
Application object For protection For metering
Rated Current (In) 1A 5A 1A 5A
Linear to 0.05In~40In 0.05In~40In 0.05In~2In 0.05In~2In
Thermal withstand
-continuously 4In 2In
-for 10s 30In 12In
-for 1s 100In 30In
-for half a cycle 250In 75In
Burden <0.15VA/phase <0.25VA/phase <0.20VA/phase <0.40VA/phase
@In @In @In @In
Current input channel Maximum 13 Maximum 3
2.1.2 Sensitive AC Current Input (5mA/350mV-G-2 and 0.25A/1.52V)

Phase rotation ABC
Rated Current (In) 5mA 250mA
Linear to 5mA~150mA 0.05In~1.20In
Thermal withstand
-continuously 150mA 1.2In
-for 10s 4A 10In
-for 1s 10A
-for half a cycle
Burden < 0.8VA/phase @In < 0.50VA/phase @In
Current input channel Maximum 1 Maximum 1
2.1.3 AC Voltage Input

Phase rotation ABC
Rated Voltage (Un) 100V~130V
Linear to 1~170V
Thermal withstand
-continuously 200V
-10s 260V
-1s 300V
Burden at rated < 0.20VA/phase @Un
Voltage input channel Maximum 9
Date: 2016-08-16
2 Technical Data
2.1.4 Power Supply

Standard IEC 60255-11:2008
Rated Voltage 110Vdc/125Vdc, 220Vdc/250Vdc
Variation 88~300Vdc
Permissible AC ripple voltage ≤15% of the nominal auxiliary voltage
Burden
Quiescent condition <35W
Operating condition <65W
2.1.5 Transducer Input

Standard IEC 60255-1: 2009
Input range 0-20mA 0-5V
Input resistance 235Ω 20kΩ
Accuracy 0.5% 0.5%
Transducer input channel 6
2.1.6 Binary Input

Rated voltage 110Vdc 125Vdc 220Vdc 250Vdc
Rated current drain 1.1mA 1.25mA 2.2mA 2.5mA
On value 77-132Vdc 87.5-150Vdc 154-264Vdc 175-300Vdc
Off value <55Vdc <62.5Vdc <110Vdc <125Vdc
Maximum permissible voltage 300Vdc
Withstand voltage 2000Vac, 2800Vdc (continuously )
Response time for logic input ≤1ms
Up to 40 binary input (including 8 mechnical relays) according to various
Number
hardware configurations
2.1.7 Binary Output

1. Tripping contact
Output mode Potential free contact

8A@380Vac
Continuous carry
8A@250Vdc
Pickup time (Typical) <8ms (typical 3ms)
Drop-off time <5ms
0.65A@48Vdc
0.35A@110Vdc
Breaking capacity (L/R=40ms) 0.30A@125Vdc
0.20A@220Vdc
0.15A@250Vdc
Burden 300mW
380Vac
Maximal system voltage
250Vdc
Date: 2016-08-16
2 Technical Data
Test voltage across open contact 1000V RMS for 1min

12A@3s
18A@1s
Short duration current
24A@0.5s
40A@0.2s
Durability (Loaded contact) 10000 operations
Number Up to 44 trip output according to various hardware configurations
2. Signal contact
Output mode Potential free contact

8A@380Vac
Continuous carry
8A@250Vdc
Pickup time (Typical) <10 ms (typical 3ms)
Drop-off time <10 ms
0.65A@48Vdc
0.35A@110Vdc
Breaking capacity (L/R=40ms) 0.30A@125Vdc
0.20A@220Vdc
0.15A@250Vdc
Burden 400mW
380Vac
Maximal system voltage
250Vdc
Test voltage across open contact 1200V RMS for 1min
12A@3s
15A@1s
Short duration current
20A@0.5s
30A@0.2s
Durability (Loaded contact) 10,000 operations minimum
Number Up to 44 signal output according to various hardware configurations
2.2 Mechanical Specifications

Mounting Way Flush mounted
Chassis color Silver grey
Weight per device Approx. 25kg
Chassis material Aluminum alloy
Location of terminal Rear panel of the device
Device structure Plug-in modular type @ rear side, integrated front plate
Protection class
Front side IP40
Other sides IP30
Rear side, connection terminals IP20
Date: 2016-08-16
2 Technical Data
2.3 Ambient Temperature and Humidity Range

Standard IEC 60225-1: 2009
Operating temperature -40°C to +70°C (Readability of display may be impaired below -20°C)
Transport and storage temperature
-40°C to +70°C
range
Permissible humidity 5%-95%, without condensation
Pollution degree 2
Altitude <3000m
2.4 Communication Port

2.4.1 EIA-485 Port
Baud rate 4.8kbit/s, 9.6kbit/s, 19.2kbit/s, 38.4kbit/s, 57.6kbit/s, 115.2kbit/s
Protocol IEC 60870-5-103:1997
Maximal capacity 32
Transmission distance <500m
Safety level Isolation to ELV level
Twisted pair Screened twisted pair cable
2.4.2 Ethernet Port

Connector type RJ-45 ST, SC (Multi mode)
Transmission rate 100Mbits/s
Transmission standard 100Base-TX 100Base-FX
Transmission distance <100m <2km (1310nm)
Protocol IEC 60870-5-103:1997, DNP 3.0 or IEC 61850
2.4.3 Optical Fiber Port

2.4.3.1 For Station Level
Characteristic Glass optical fiber

Connector type ST
Fiber type Multi mode
Transmission distance <2km
Wave length 1310nm
Transmission power Min. -20.0dBm
Minimum receiving power Min. -30.0dBm
Margin Min +3.0dB
2.4.4 Print Port

Type RS-232
Baud Rate 4.8kbit/s, 9.6kbit/s, 19.2kbit/s, 38.4kbit/s, 57.6kbit/s, 115.2kbit/s
Date: 2016-08-16
2 Technical Data
®
Printer type EPSON 300K printer
2.4.5 Clock Synchronization Port

Type RS-485
Transmission distance <500m
Maximal capacity 32
Timing standard PPS, IRIG-B
2.5 Type Tests

2.5.1 Environmental Tests
Dry cold test IEC60068-2-1:2007
Dry heat test IEC60068-2-2:2007
Damp heat test, cyclic IEC60068-2-30:2005
2.5.2 Mechanical Tests

Vibration IEC 60255-21-1:1988 Class I
Shock and bump IEC 60255-21-2:1988 Class I
2.5.3 Electrical Tests

Dielectric tests Test voltage 2kV, 50Hz, 1min
Impulse voltage tests Test voltage 5kV
Overvoltage category III
Insulation resistance measurements Isolation resistance >100MΩ@500VDC
2.5.4 Electromagnetic Compatibility

IEC 60255-22-1:2007
1MHz burst disturbance test Common mode: class Ⅲ 2.5kV
Differential mode: class Ⅲ 1.0kV
IEC60255-22-2:2008 class Ⅳ
Electrostatic discharge test For contact discharge: 8kV
For air discharge: 15kV
IEC 60255-22-3:2007 class Ⅲ
Frequency sweep
Radiated amplitude-modulated
Radio frequency interference tests
10V/m (rms), f=80~1000MHz
Spot frequency
Radiated amplitude-modulated
Date: 2016-08-16
2 Technical Data
10V/m (rms), f=80MHz/160MHz/450MHz/900MHz

Radiated pulse-modulated
10V/m (rms), f=900MHz
IEC 60255-22-4:2008
Fast transient disturbance tests Power supply, I/O, Earth: class Ⅳ, 4kV, 2.5kHz, 5/50ns
Communication terminals: class Ⅳ, 2kV, 5kHz, 5/50ns
IEC 60255-22-5:2008
Power supply, AC input, I/O port: class Ⅳ, 1.2/50us
Surge immunity test
Common mode: 4kV
Differential mode: 2kV
IEC 60255-22-6:2001
Conducted RF Electromagnetic
Power supply, AC, I/O, Comm. Terminal: Class Ⅲ , 10Vrms, 150
Disturbance
kHz~80MHz
Power Frequency Magnetic Field IEC 61000-4-8:2001
Immunity Class Ⅴ, 100A/m for 1min, 1000A/m for 3s
IEC 61000-4-9:2001
Pulse Magnetic Field Immunity
Class Ⅴ, 6.4/16μs, 1000A/m for 3s
Damped oscillatory magnetic field IEC 61000-4-10:2001
immunity Class Ⅴ, 100kHz & 1MHz–100A/m
Auxiliary power supply performance IEC60255-11: 2008

- Voltage dips Up to 200ms for dips to 40% of rated voltage without reset
-Voltage short interruptions 100ms for interruption without rebooting
2.6 Certifications
 ISO9001: 2008
 ISO14001:2004
 OHSAS18001: 2007
 ISO10012:2003
 CMMI L5
 EMC: 2014/30/EU, EN60255-26: 2013
 Products safety(LVD): 2014/35/EU, EN60255-27: 2014
2.7 Terminals
Connection Type Wire Size
Crimp terminals, 1.5mm ~4.0mm2 lead
2
AC current If using 4.0mm2 lead, only dedicated terminal cable lug provided by NR
can be adopted.
2 2
AC voltage Crimp terminals, 1.0mm ~2.5mm lead
Power supply Crimp terminals, 1.0mm ~2.5mm2 lead
2
Date: 2016-08-16
2 Technical Data
2 2
Contact I/O Crimp terminals, 1.0mm ~2.5mm lead
2
Grounding (Earthing) Connection BVR type, 2.5mm²~6.0mm lead
2.8 Measurement Scope and Accuracy

Item Range Accuracy
Phase range 0°~ 360° ≤±3°
Frequency fn±3 Hz ≤ 0.02Hz
Currents from protection measurement current transformers
≤ 2.0% of rating (0.05~1.00In)
Current 0.05~5.00 In
≤ 2.0% of applied quantities (1.00~5.00In)
≤ 1.0% of rating (0.05~1.00Un)
Voltage 0.05~1.50 Un
≤ 1.0% of applied quantities (1.00~1.50Un)
2.9 Management Function

2.9.1 Control Performance
Control mode Local or remote
Accuracy of local control ≤ 1s
Accuracy of remote control ≤ 3s
2.9.2 Clock Performance

Real time clock accuracy ≤ 3s/day
Accuracy of GPS synchronization ≤ 1ms
External time synchronization IRIG-B (200-98), PPS, IEEE1588 or SNTP protocol
2.9.3 Fault and Disturbance Recording

Maximum duration 2048 sampled points (24 sampled points per cycle)
Recording position 3 cycles before pickup of trigger element
2.9.4 Binary Input Signal

Resolution of binary input signal ≤ 1ms
Binary input mode Potential-free contact
Resolution of SOE ≤ 2ms
2.10 Protective Functions
There are some symbols mentioned in the following sections and the meaning of them is given
here.
Un – the secondary rated voltage of VT
In – the secondary rated current of CT
pu – per-unit value
Date: 2016-08-16
2 Technical Data
Id – the differential current
U* / f* – the overexcitation multiples
2.10.1 Generator Current Differential Protection

2.10.1.1 Biased Differential Element
Pickup up current setting 0.1~1.5 pu, steps 0.01 pu
Drop-off current 0.95×Setting
Tolerance of operating current ≤5% of operating current or 0.02 pu, whichever is greater
Slope 1 setting 0.01~0.50, steps 0.01
50Hz: ≤ 30ms (Id>2xSetting)

Operating time (Without blocking criteria)
2.10.1.2 Instantaneous Differential Element
Current setting 2~14 pu, 0.01pu steps
Tolerance of current setting ≤2.5%xSetting or 0.02 pu, whichever is greater
50Hz: ≤ 20ms (Id>1.5xSetting)

Operating time
60Hz: ≤20ms (Id>1.5xSetting)
2.10.2 Generator Neutral Point Transverse Differential Protection
Current setting 0.1~10In, steps 0.01 A
Tolerance of current setting ≤ 2.5% Setting or 0.02 In, whichever is greater
Sensitive stage time delay 0.00~30.00 s
Tolerance of sensitive stage time delay ≤1%Setting+30ms

Operating time of insensitive stage
2.10.3 Generator Inter-Turn Protection

Longitudinal zero-sequence voltage setting 1.00~10.00V, steps 0.01 V
Tolerance of voltage setting ≤2.5% Setting or 0.1V whichever is greater
Time delay 0.10~30.00s
Tolerance of time delay ≤1%Setting + 40ms
2.10.4 Generator Stator Overload Protection

Definite-time current setting 0.10~20.00In, steps 0.01 A
Inverse-time pickup current setting 0.10~20.00In, steps 0.01 A
Date: 2016-08-16
2 Technical Data
Tolerance of current setting ≤2.5% Setting or 0.02In whichever is greater

Definite-time time delay 0~30.00s
Tolerance of time delay ≤1%Seting + 40ms
Setting of thermal capacity of stator windings 1.00~320.00
Setting of heat dissipation factor 1.02~2.00
2.10.5 Generator Fundamental Zero-sequence Stator Ground fault Protection

Setting of zero-sequence voltage blocking
1.00~100.00V, steps 0.01 V
element
Setting of zero-sequence voltage element 0.10~50.00V, steps 0.01 V
Tolerance of voltage setting ≤2.5% Setting or 0.1V whichever is greater
Setting of zero-sequence current element 0.00~10.00A, steps 0.01A
Tolerance of zero-sequence current setting ≤2.5% Setting or 0.02In whichever is greater
Time delay 0~30.00s
2.10.6 Generator 3rd Harmonic Stator Ground Fault Protection

Setting range of third harmonic ratio element 0.50~10.00, steps 0.01
Setting range of third harmonic differential
0.05~2.00, steps 0.01
element
Setting accuracy ≤5%
Time delay 0~30.00s
2.10.7 Generator Ping-Pang Type Rotor Ground Fault Protection

Resistance setting of one-point ground fault 0.10~100.00kΩ, steps 0.01 kΩ
Tolerance of resistance setting ≤10% or 0.5kΩ whichever is greater
Setting range of switchover cycle 0.50~10.00s
Time delay 0~30.00s
Tolerance of time delay ≤1%Setting + 1s
2.10.8 Generator Rotor Ground Fault Protection with Low-frequency

Square-wave Voltage Injection
Resistance setting 0.10~100.00kΩ, steps 0.01 kΩ
Tolerance of resistance setting ≤10% or 0.5kΩ whichever is greater
Setting range of switchover cycle 0.50~10.00s
Time delay 0~30.00s
Tolerance of time delay ≤1%Setting + 1s
2.10.9 Generator Rotor Winding Overload Protection

Definite-time current setting 0.10~20.00In, steps 0.01 A
Inverse-time pickup current setting 0.10~20.00In, steps 0.01 A
Tolerance of current setting ≤2.5% or 0.02In whichever is greater
Date: 2016-08-16
2 Technical Data

Tolerance of time delay ≤1%Seting + 40ms
Setting range of thermal capacity factor 1.00~320.00
Setting range of reference current 0.10~10.00In, steps 0.01 A
2.10.10 Generator Inadvertent Energization Protection

Current setting of overcurrent element 0.10 ~10.00In, steps 0.01 A
Voltage setting of low-voltage element 6.00~100.00V
Tolerance of voltage setting ≤2.5% or 0.1V whichever is greater
40 ~ 50Hz (for 50Hz system)
Frequency setting of low-frequency element
Time delay of inadvertent energization
0.01~1.00s
protection
2.10.11 Generator Out-of-Step Protection

Impedance setting Za 0~200.00Ω
Impedance setting Zb 0~200.00Ω
Impedance setting Zc 0~200.00Ω
Tolerance of impedance setting ≤2.5% or 0.1Ω whichever is greater
Setting range of sensitive angle setting 0 ~ 90.00°
Setting range of lens interior angle setting 0 ~ 150.00°
Tolerance of angle setting ≤3°
Setting range of pole slipping number 1 ~ 1000
Setting range of permissive tripping current 0.10 ~20.00In, steps 0.01 A
2.10.12 Generator Startup and Shutdown protection

Blocking frequency setting
Current setting 0.10~20.00In, steps 0.01 A
Tolerance of current setting ≤5% or 0.02In whichever is greater
Residual voltage setting 5.00 ~25.00V
Tolerance of voltage setting ≤5% or 0.02Un whichever is greater
Time delay 0~30.00s
2.10.13 Generator Shaft Overcurrent Protection

Current setting 0.10~100.00mA
Time delay 0~30.00s
Date: 2016-08-16
2 Technical Data
2.10.14 Generator Negative-sequence Overload Protection

Definite-time negative-sequence current
0.10~4.00In, steps 0.01 A
setting
Inverse-time negative-sequence pickup
0.05~1.00In, steps 0.01 A
current setting
Setting range of long-term permissive
0.05~1.00In, steps 0.01 A
negative-sequence current setting
Inverse-time minimum time delay 0.10~10.00s
Inverse-time maximum time delay 0.1~5000.0s
Setting range of rotor heat capacity 1.00~320.00
2.10.15 Generator Reverse Power Protection

Power setting of reverse power element 0.50 ~ 50.00%Pn
Power setting of sequence tripping reverse
0.50 ~ 10.00%Pn
power element
Tolerance of power setting ≤10% or 0.002Pn whichever is greater
Time delay of reverse power element 0.10 ~ 3000.00s
Time delay of sequence tripping reverse
0.01~30.00s
power element
2.10.16 Generator Low Forward Power Protection

Power setting 0.50~100.00%Pn
Tolerance of power setting ≤10% or 0.002Pn whichever is greater
2.10.17 Overexcitation Protection
Definite time U* / f* setting 1.00~2.00
Inverse-time time delay for trip 0.1 ~3000.0s
Inverse-time time delay for alarm 0.1~30.0s
Inverse time U* / f* setting 1.00~2.00
Inverse-time time delay 1.0~3000.0s
Tolerance of U* / f* setting ≤2.5% of Setting or 0.01 whichever is greater
Date: 2016-08-16
2 Technical Data
Tolerance of operating time of definite-time

≤1% of Setting +40ms (at 1.5 times U* / f* setting)
overexcitation protection
Tolerance of operating time of inverse-time

≤2.5% operating time or 40ms, whichever is greater
2.10.18 Loss-of-excitation Protection

Impedance setting range (Za) 0 ~ 200 ohm
Impedance setting range (Zb) 0 ~ 200 ohm
Tolerance of impedance setting ≤2.5% or 0.1ohm whichever is greater
Reverse reactive power setting range 0 ~ 50%Pn
Tolerance of reverse reactive power setting ≤1% or 0.002Pn whichever is greater
Rotor low voltage setting range 0.1 ~ 500V
No-load rated excitation voltage setting range 0.1 ~ 500V
Tolerance of voltage setting ≤5% or 0.1Un whichever is greater
Rotor low-voltage coefficient range 0 ~ 10
Time delay 0.1 ~ 3000s
Tolerance of time setting ≤1%Setting + 40ms
2.10.19 Phase Overcurrent Protection
Current setting 0.05~20.00In, steps 0.01 A
Tolerance of current setting ≤2.5% of setting or 0.02In, whichever is greater
Drop-off to pickup ratio ≥95%
Tolerance of definite-time time delay ≤1% of setting +40ms (at 2 times current setting)
Phase-to-phase undervoltage setting of

2.00~120.00V, steps 0.01 V
voltage controlled element
Negative-sequence overvoltage setting of

1.00~120.00V, steps 0.01 V
voltage controlled element
Tolerance of voltage setting ≤2.5% of setting or 0.01Un, whichever is greater
Setting range of relay characteristic angle of

-90.00~90.00deg, steps 0.01 deg
direction element
Tolerance of relay characteristic angle ≤3 deg
Operating time of inverse-time overcurrent ≤2.5% operating time or 40ms, whichever is greater(for current
element between 1.2 and 20 multiples of pickup)
2.10.20 Overvoltage Protection

Voltage setting 0.10~200.00V, steps 0.01V
Tolerance of voltage setting ≤2.5% of setting or 0.1V, whichever is greater
Tolerance of definite-time time delay ≤1%Setting+40ms (at 1.2 times voltage setting)
Date: 2016-08-16
2 Technical Data
Operating time of inverse-time overvoltage ≤2.5% operating time or 40ms, whichever is greater (for voltage
element between 1.2 and 2 multiples of pickup)
2.10.21 Undervoltage Protection

Voltage setting 0.10~120.00V, steps 0.01V
Tolerance of voltage setting ≤2.5% of setting or 0.1V, whichever is greater
Drop-off to pickup ratio ≤105%
Tolerance of definite-time time delay ≤1%Setting+40ms (at 0.8 times voltage setting)
Operating time of inverse-time overvoltage ≤2.5% operating time or 40ms, whichever is greater (for voltage
element between 0.5 and 0.8 multiples of pickup)
2.10.22 Overfrequency Protection

50.00 ~ 60.00Hz (for 50Hz system)
Overfrequency setting
60.00 ~ 70.00Hz (for 60Hz system)
Tolerance of frequency setting ≤ 0.02Hz
Tolerance of time setting ≤1%Setting+40ms (at 1.2 times frequency setting)
Time delay for overfrequency band
0.10~300.00min
accumulate protection
2.10.23 Underfrequency Protection

45.00 ~ 51.00Hz (for 50Hz system)
Underfrequency setting
55.00~ 61.00Hz (for 60Hz system)
Tolerance of frequency setting ≤ 0.02Hz
Tolerance of time setting ≤1%Setting+40ms (at 0.8 times frequency setting)
Time delay for underfrequency band
0.10~300.00min
accumulate protection
2.10.24 Impedance Protection

Impedance characteristic angle 0.00~ 90.00deg, steps 0.01deg
Impedance setting 0.05 ~ 200.00Ω, steps 0.01Ω
Tolerance of impedance setting ≤2.5% of setting or 0.1Ω, whichever is greater
Tolerance of time delay ≤1%Setting + 40ms (at 0.8 times impedance setting)
Current setting of PSBR element 0.05~20In, 0.01A steps
Tolerance of current setting ≤2.5% of setting or 0.02In, whichever is greater
2.10.25 Breaker Failure Protection
Current setting of phase current criterion 0.05~10.00In, steps 0.01A
Current setting of negative-sequence current

0.05~4In, steps 0.01A
criterion
Date: 2016-08-16
2 Technical Data
Tolerance of current setting ≤2.5% of setting or 0.02×In, whichever is greater
Tolerance of time delay ≤1% of setting +40ms (at 2 times current setting)
2.10.26 Mechanical Protection
Delay pickup up time delay 0~6000.00s
Tolerance of time delay ≤1% of Setting +40ms
2.10.27 Excitation Transformer Current Differential Protection

2.10.27.1 Biased Differential Element
Pickup up current setting 0.1~1.5 pu, steps 0.01 pu
Tolerance of operating current ≤5% of operating current or 0.02 pu, whichever is greater

Operating time (Without blocking criteria)
2.10.27.2 Instantaneous Differential Element
Current setting 2~14 pu, steps 0.01pu
Tolerance of current setting ≤2.5%xSetting or 0.02 pu, whichever is greater

Operating time
Date: 2016-08-16
3 Operation Theory
3 Operation Theory
Table of Contents
3.1 Overview ........................................................................................................... 3-1

3.2 Generator Current Differential Protection (87G) ........................................... 3-1
3.2.1 Application ............................................................................................................................ 3-1
3.2.2 Function Description............................................................................................................. 3-1
3.2.3 Protection Principle .............................................................................................................. 3-2
3.2.4 Logic ................................................................................................................................... 3-12
3.2.5 Inputs and Outputs ............................................................................................................. 3-14
3.2.6 Settings ............................................................................................................................... 3-17
3.3 Generator Neutral Point Transverse Differential Protection (87NTG) ....... 3-18
3.3.1 Application .......................................................................................................................... 3-18
3.3.2 Function Description........................................................................................................... 3-19
3.3.3 Protection Principle ............................................................................................................ 3-19
3.3.4 Logic ................................................................................................................................... 3-21
3.3.6 Settings ............................................................................................................................... 3-23
3.4 Generator Inter-Turn Protection (59NIT) ...................................................... 3-24

3.4.1 Application .......................................................................................................................... 3-24
3.4.4 Logic ................................................................................................................................... 3-27
3.4.6 Settings ............................................................................................................................... 3-30
3.5 Generator Stator Overload Protection (49S) ............................................... 3-31

3.5.1 Application .......................................................................................................................... 3-31
Date: 2016-08-16
3 Operation Theory
3.5.4 Logic ................................................................................................................................... 3-33
3.5.6 Settings ............................................................................................................................... 3-36
3.6 Generator Fundamental Zero-sequence Stator Ground Fault Protection

(64S1) .................................................................................................................... 3-36
3.6.1 Application .......................................................................................................................... 3-36
3.6.4 Logic ................................................................................................................................... 3-42
3.6.6 Settings ............................................................................................................................... 3-47
3.7 Generator 3rd Harmonic Stator Ground Fault Protection (64S2) ................ 3-49
3.7.1 Application .......................................................................................................................... 3-49
3.7.4 Logic ................................................................................................................................... 3-53
3.7.6 Settings ............................................................................................................................... 3-57
3.8 Generator Ping-Pang Type Rotor Ground Fault Protection (64R) ............. 3-58
3.8.1 Application .......................................................................................................................... 3-58
3.8.4 Logic ................................................................................................................................... 3-59
3.8.6 Settings ............................................................................................................................... 3-63
3.9 Generator Rotor Ground Fault Protection with Low-frequency Square-wave

Voltage Injection (64RInj) .................................................................................... 3-64
3.9.1 Application .......................................................................................................................... 3-64
Date: 2016-08-16
3 Operation Theory
3.9.4 Logic ................................................................................................................................... 3-66
3.9.6 Settings ............................................................................................................................... 3-70
3.10 Generator Rotor Winding Overload Protection (49E) ............................... 3-71

3.10.1 Application ........................................................................................................................ 3-71
3.10.2 Function Description......................................................................................................... 3-72
3.10.3 Protection Principle .......................................................................................................... 3-72
3.10.4 Logic ................................................................................................................................. 3-74
3.10.5 Inputs and Outputs ........................................................................................................... 3-75
3.10.6 Settings............................................................................................................................. 3-76
3.11 Generator Inadvertent Energization Protection (50/27) ............................ 3-77

3.11.1 Application ........................................................................................................................ 3-77
3.11.2 Function Description ......................................................................................................... 3-77
3.11.3 Protection Principle........................................................................................................... 3-77
3.11.4 Logic ................................................................................................................................. 3-79
3.11.6 Settings ............................................................................................................................. 3-81
3.12 Generator Out-of-Step Protection (78) ....................................................... 3-82

3.12.1 Application ........................................................................................................................ 3-82
3.12.4 Logic ................................................................................................................................. 3-84
3.12.6 Settings............................................................................................................................. 3-87
3.13 Generator Startup and Shutdown protection (StShut) ............................. 3-88

3.13.1 Application ........................................................................................................................ 3-88
3.13.4 Logic ................................................................................................................................. 3-89
Date: 2016-08-16
3 Operation Theory
3.13.6 Settings............................................................................................................................. 3-92
3.14 Generator Shaft Overcurrent Protection (51GS) ....................................... 3-93

3.14.1 Application ........................................................................................................................ 3-93
3.14.4 Logic ................................................................................................................................. 3-94
3.14.6 Settings............................................................................................................................. 3-97
3.15 Generator Negative-sequence Overload Protection (46G)....................... 3-97

3.15.1 Application ........................................................................................................................ 3-97
3.15.4 Logic ............................................................................................................................... 3-100
3.15.5 Inputs and Outputs ......................................................................................................... 3-101
3.15.6 Settings........................................................................................................................... 3-103
3.16 Generator Reverse Power Protection (32R) ............................................ 3-104

3.16.1 Application ...................................................................................................................... 3-104
3.16.2 Function Description....................................................................................................... 3-104
3.16.3 Protection Principle ........................................................................................................ 3-104
3.16.4 Logic ............................................................................................................................... 3-105
3.16.6 Settings........................................................................................................................... 3-108
3.17 Generator Low Forward Power Protection (32F) .................................... 3-108

3.17.1 Application ...................................................................................................................... 3-108
3.17.3 Logic ............................................................................................................................... 3-109
3.17.5 Settings............................................................................................................................3-111
3.18 Generator Overexcitation Protection (Gen.24) ......................................... 3-111
Date: 2016-08-16
3 Operation Theory
3.18.1 Application .......................................................................................................................3-111
3.18.4 Logic ............................................................................................................................... 3-114
3.18.6 Settings........................................................................................................................... 3-117
3.19 Loss of Excitation Protection (40G) ..........................................................3-118

3.19.1 Application ...................................................................................................................... 3-118
3.19.2 Function .......................................................................................................................... 3-118
3.19.4 Logic ............................................................................................................................... 3-123
3.19.6 Settings........................................................................................................................... 3-126
3.20 Generator Phase Overcurrent Protection (Gen.50/51P) ......................... 3-129

3.20.1 Application ...................................................................................................................... 3-129
3.20.4 Logic ............................................................................................................................... 3-134
3.20.6 Settings........................................................................................................................... 3-138
3.21 Generator Phase Overvoltage Protection (Gen.59P) .............................. 3-140

3.21.1 Application ...................................................................................................................... 3-140
3.21.4 Logic ............................................................................................................................... 3-142
3.21.6 Settings........................................................................................................................... 3-144
3.22 Phase Undervoltage Protection (27P) ...................................................... 3-145

3.22.1 Application ...................................................................................................................... 3-145
PCS-985GE Generator Relay 3-e
Date: 2016-08-16
3 Operation Theory
3.22.3 Operation Principle ......................................................................................................... 3-145
3.22.4 Logic ............................................................................................................................... 3-147
3.22.6 Settings........................................................................................................................... 3-149
3.23 Overfrequency Protection (81O)............................................................... 3-150

3.23.1 Application ...................................................................................................................... 3-150
3.23.4 Logic ............................................................................................................................... 3-152
3.23.6 Settings........................................................................................................................... 3-156
3.24 Underfrequency Protection (81U)............................................................. 3-158

3.24.1 Application ...................................................................................................................... 3-158
3.24.4 Logic ............................................................................................................................... 3-159
3.24.6 Settings........................................................................................................................... 3-164
3.25 Impedance Protection (21) ........................................................................ 3-166

3.25.1 Application ...................................................................................................................... 3-166
3.25.4 Logic ............................................................................................................................... 3-171
3.25.6 Settings........................................................................................................................... 3-175
3.26 Breaker Failure Protection (50BF) ............................................................ 3-176

3.26.1 Application ...................................................................................................................... 3-176
3.26.4 Logic ............................................................................................................................... 3-177
3-f PCS-985GE Generator Relay
Date: 2016-08-16
3 Operation Theory
3.26.5 Input and Output ............................................................................................................. 3-178
3.26.6 Settings........................................................................................................................... 3-179
3.27 Mechanical Protection (MR) ...................................................................... 3-180

3.27.1 Application ...................................................................................................................... 3-180
3.27.4 Logic ............................................................................................................................... 3-181
3.27.6 Settings........................................................................................................................... 3-183
3.28 Excitation Transformer Current Differential Protection (87ET).............. 3-184

3.28.1 Application ...................................................................................................................... 3-184
3.28.4 Logic ............................................................................................................................... 3-198
3.28.6 Settings........................................................................................................................... 3-203
3.29 Excitation Transformer Overcurrent Protection (Exc.50/51P)................ 3-204

3.29.1 Application ...................................................................................................................... 3-204
3.29.3 Logic ............................................................................................................................... 3-205
3.29.5 Settings........................................................................................................................... 3-206
3.30 Interconnection Status Element (CBStatus) ............................................ 3-207

3.30.1 Application ...................................................................................................................... 3-207
3.30.4 Logic ............................................................................................................................... 3-208
3.30.5 Input and Output ............................................................................................................. 3-208
3.30.6 Settings........................................................................................................................... 3-209
3.31 Voltage Balance Protection (60) ............................................................... 3-209
PCS-985GE Generator Relay 3-g
Date: 2016-08-16
3 Operation Theory
3.31.1 Application ...................................................................................................................... 3-209
3.31.4 Logic ............................................................................................................................... 3-213
3.31.5 Input and Output ............................................................................................................. 3-214
3.31.6 Settings........................................................................................................................... 3-215
3.32 Three-Phase Current Element (Curr3P) ................................................... 3-215

3.32.1 Application ...................................................................................................................... 3-216
3.32.3 Principle .......................................................................................................................... 3-216
3.32.4 Logic ............................................................................................................................... 3-216
3.32.6 Settings........................................................................................................................... 3-219
3.33 Three-Phase Voltage Element (Volt3P) .................................................... 3-220

3.33.1 Application ...................................................................................................................... 3-220
3.33.3 Principle .......................................................................................................................... 3-220
3.33.4 Logic ............................................................................................................................... 3-221
3.33.6 Settings........................................................................................................................... 3-223
3.34 Single Current Element with Filter (CurrFilt1P)....................................... 3-224

3.34.1 Application ...................................................................................................................... 3-224
3.34.4 Settings........................................................................................................................... 3-225
3.35 Residual Voltage Element with Filter (VoltFilt1P) .................................... 3-225

3.35.1 Application ...................................................................................................................... 3-225
3.35.4 Settings........................................................................................................................... 3-227
3-h PCS-985GE Generator Relay
Date: 2016-08-16
3 Operation Theory
List of Figures
Figure 3.2-1 Current calculation process of generator current differential protection ....... 3-4
Figure 3.2-2 Operation characteristic curve of steady-state differential element of generator

....................................................................................................................................................... 3-9
Figure 3.2-3 Operation characteristic curve of DPFC differential element of generator..... 3-9
Figure 3.2-4 Logic diagram of startup of generator current differential protection .......... 3-12
Figure 3.2-5 Logic diagram of steady-state current differential element of generator...... 3-13
Figure 3.2-6 Logic diagram of DPFC current differential element of generator ................. 3-14
Figure 3.2-7 Function block diagram of generator current differential protection ............ 3-14
Figure 3.3-1 Current calculation process of neutral point transverse differential protection
..................................................................................................................................................... 3-19
Figure 3.3-2 Logic diagram of generator neutral point transverse differential protection 3-21
Figure 3.3-3 Function block diagram of generator neutral point transverse differential
protection ................................................................................................................................... 3-22
Figure 3.4-1 Calculation process of longitudinal zero-sequence voltage inter-turn element

..................................................................................................................................................... 3-25
Figure 3.4-2 Logic diagram of generator inter-turn protection ............................................ 3-28
Figure 3.4-3 Function block diagram of generator inter-turn protection ............................ 3-29
Figure 3.5-1 Operation characteristic of inverse-time stator overload protection ............ 3-32
Figure 3.5-2 Logic diagram of generator stator overload protection .................................. 3-34
Figure 3.5-3 Function block diagram of generator stator overload protection .................. 3-34
Figure 3.6-1 Calculation process of fundamental zero-sequence stator ground fault

protection ................................................................................................................................... 3-38
Figure 3.6-2 Characteristic of the zero sequence directional element ................................ 3-40
Figure 3.6-3 Logic diagram of generator fundamental zero-sequence stator ground fault
protection ................................................................................................................................... 3-44
Figure 3.6-4 Function block diagram of generator fundamental zero-sequence stator

ground fault protection ............................................................................................................. 3-44
Figure 3.7-1 Calculation process of generator 3rd harmonic stator ground fault protection
..................................................................................................................................................... 3-50
Figure 3.7-2 Logic diagram of generator 3rd harmonic stator ground fault protection ..... 3-54
Figure 3.7-3 Function block diagram of generator 3rd harmonic stator ground fault
PCS-985GE Generator Relay 3-i
Date: 2016-08-16
3 Operation Theory
protection ................................................................................................................................... 3-55
Figure 3.8-1 Schematic diagram of Ping-Pang type rotor ground fault protection ........... 3-59
Figure 3.8-2 Logic diagram of generator Ping-Pang type rotor ground fault protection .. 3-60
Figure 3.8-3 Function block diagram of generator Ping-Pang type rotor ground fault
protection ................................................................................................................................... 3-61
Figure 3.9-1 Schematic diagram of rotor ground fault protection with low-frequency
square-wave voltage injection ................................................................................................. 3-65
Figure 3.9-2 Logic diagram of generator rotor ground fault protection (with low-frequency
square-wave voltage injection) ................................................................................................ 3-67
Figure 3.9-3 Function block diagram of generator rotor ground fault protection (with
low-frequency square-wave voltage injection) ...................................................................... 3-68
Figure 3.10-1 Operation characteristic of inverse-time rotor winding overload protection

..................................................................................................................................................... 3-73
Figure 3.10-2 Logic diagram of rotor winding overload protection..................................... 3-74
Figure 3.10-3 Function block diagram of rotor winding overload protection..................... 3-75
Figure 3.11-1 Logic diagram of inadvertent energization protection .................................. 3-80
Figure 3.11-2 Function block diagram of inadvertent energization protection .................. 3-80
Figure 3.12-1 Operation characteristic of out-of-step protection ........................................ 3-83
Figure 3.12-2 Logic diagram of generator out-of-step protection ....................................... 3-85
Figure 3.12-3 Function block diagram of generator out-of-step protection ....................... 3-86
Figure 3.13-1 Logic diagram of generator startup and shutdown protection .................... 3-90
Figure 3.13-2 Function block diagram of generator startup and shutdown protection .... 3-90
Figure 3.14-1 Logic diagram of generator shaft overcurrent protection ............................ 3-95
Figure 3.14-2 Function block diagram of generator shaft overcurrent protection ............ 3-95
Figure 3.15-1 Operation characteristic of inverse-time negative-sequence overload

protection ................................................................................................................................... 3-99
Figure 3.15-2 Logic diagram of generator negative-sequence overload protection ....... 3-101
Figure 3.15-3 Function block diagram of generator negative-sequence overload protection

................................................................................................................................................... 3-101
Figure 3.16-1 Logic diagram of generator reverse power protection................................ 3-106
Figure 3.16-2 Function block diagram of generator reverse power protection ............... 3-106
Figure 3.17-1 Logic diagram of generator low forward power protection ........................ 3-110
3-j PCS-985GE Generator Relay
Date: 2016-08-16
3 Operation Theory
Figure 3.17-2 Function block diagram of generator low forward power protection ........ 3-110
Figure 3.18-1 Inverse-time overexcitation characteristic curve ......................................... 3-114
Figure 3.18-2 Logic diagram of overexcitation protection.................................................. 3-115
Figure 3.18-3 Function block diagram of overexcitation protection ................................. 3-115
Figure 3.19-1 Function diagram of loss of excitation protection ....................................... 3-119
Figure 3.19-2 Impedance circle of loss of excitation protection ........................................ 3-121
Figure 3.19-3 Logic diagram of loss of excitation protection ............................................ 3-124
Figure 3.19-4 Function block diagram of loss of excitation protection ............................ 3-124
Figure 3.20-1 Function diagram of generator phase overcurrent protection ................... 3-130
Figure 3.20-2 Connection of VT and CT of direction element ............................................ 3-134
Figure 3.20-3 Direction characteristic of generator phase overcurrent protection ......... 3-134
Figure 3.20-4 Logic diagram of generator phase overcurrent protection (n=1,2,3) ......... 3-135
Figure 3.20-5 Logic diagram of phase-to-phase VCE of generator phase overcurrent

protection ................................................................................................................................. 3-135
Figure 3.20-6 Logic diagram of negative-sequence VCE of generator phase overcurrent

protection ................................................................................................................................. 3-136
Figure 3.20-7 Logic diagram of direction element of generator phase overcurrent protection
................................................................................................................................................... 3-136
Figure 3.20-8 Function block diagram of generator phase overcurrent protection ........ 3-137
Figure 3.21-1 Logic diagram of phase overvoltage protection .......................................... 3-142
Figure 3.21-2 Function block diagram of phase overvoltage protection .......................... 3-143
Figure 3.22-1 Logic diagram of undervoltage protection ................................................... 3-147
Figure 3.22-2 Function block diagram of undervoltage protection ................................... 3-148
Figure 3.23-1 Logic diagram of stage x of overfrequency protection ............................... 3-152
Figure 3.23-2 Logic diagram of stage 1 of overfrequency band accumulate protection 3-152
Figure 3.23-3 Logic diagram of stage 4 of overfrequency band accumulate protection 3-153
Figure 3.23-4 Function block diagram of overfrequenncy protection............................... 3-153
Figure 3.24-1 Logic diagram of stage x of underfrequency protection (x=1~4) ............... 3-160
Figure 3.24-2 Logic diagram of stage 1 of underfrequency band accumulate protection

................................................................................................................................................... 3-160
PCS-985GE Generator Relay 3-k
Date: 2016-08-16
3 Operation Theory
................................................................................................................................................... 3-161
Figure 3.24-4 Function block diagram of underfrequency protection............................... 3-161
Figure 3.25-1 Connection of VT and CT of direction element ............................................ 3-168
Figure 3.25-2 Operating characteristic of phase-to-phase impedance relay.................... 3-168
Figure 3.25-3 Operating characteristic of phase-to-earth impedance relay ..................... 3-169
Figure 3.25-4 Logic diagram of FD PSBR ............................................................................. 3-170
Figure 3.25-5 Logic diagram of stage 1 of phase-to-phase impedance protection ......... 3-172
Figure 3.25-6 Function block diagram of impedance protection ....................................... 3-173
Figure 3.26-1 Logic diagram of breaker failure protection ................................................. 3-178
Figure 3.26-2 Function block diagram of breaker failure protection ................................. 3-178
Figure 3.27-1 Logic diagram of channel 1 of mechanical protection 1 ............................. 3-181
Figure 3.27-2 Function block diagram of mechanical protection (x=1, 2)......................... 3-181
Figure 3.28-1 Excitation transformer current compensation calculation process .......... 3-190
Figure 3.28-2 Operation characteristic curve of differential protection of excitation

transformer .............................................................................................................................. 3-193
Figure 3.28-3 Logic diagram of startup of excitation transformer current differential

protection ................................................................................................................................. 3-199
Figure 3.28-4 Logic diagram of excitation transformer current differential protection... 3-199
Figure 3.28-5 Function block diagram of excitation transformer current differential

protection ................................................................................................................................. 3-200
Figure 3.29-1 Logic diagram of excitation transformer phase overcurrent protection (n=1,2)
................................................................................................................................................... 3-205
Figure 3.29-2 Function block diagram of excitation transformer phase overcurrent

protection ................................................................................................................................. 3-205
Figure 3.30-1 Logic diagram of interconnection status element ([En_GCB]=1) .............. 3-208
Figure 3.30-2 Logic diagram of interconnection status element ([En_GCB]=0) .............. 3-208
Figure 3.30-3 Function block diagram of interconnection status element ....................... 3-208
Figure 3.31-1 Logic diagram of voltage balance protection ............................................... 3-213
Figure 3.31-2 Function block diagram of voltage balance protection ............................... 3-214
Figure 3.32-1 Current pre-processing logic diagram .......................................................... 3-216
Figure 3.32-2 Function block diagram of three-phase current element ............................ 3-217
3-l PCS-985GE Generator Relay
Date: 2016-08-16
3 Operation Theory
Figure 3.33-1 Voltage pre-processing logic diagram .......................................................... 3-221
Figure 3.33-2 Function block diagram of three-phase voltage element ............................ 3-221
Figure 3.34-1 Function block diagram of single current element with filter ..................... 3-224
Figure 3.35-1 Function block diagram of residual voltage element .................................. 3-226
List of Tables
Table 3.2-1 Input signals of generator current differential protection ................................ 3-14
Table 3.2-2 Output signals of generator current differential protection ............................. 3-15
Table 3.2-3 Output signals of generator current differential protection (event recorder) 3-15
Table 3.2-4 Output signals of generator current differential protection (measurements) 3-15
Table 3.2-5 Settings list of generator current differential protection .................................. 3-17
Table 3.3-1 Input signals of generator neutral point transverse differential protection ... 3-22
Table 3.3-2 Output signals of generator neutral point transverse differential protection 3-22
Table 3.3-3 Output signals of generator neutral point transverse differential protection
(event recorder) ......................................................................................................................... 3-23
(measurements) ......................................................................................................................... 3-23
Table 3.3-5 Settings list of generator neutral point transverse differential protection ..... 3-23
Table 3.4-1 Input signals of generator inter-turn protection ................................................ 3-29
Table 3.4-2 Output signals of generator inter-turn protection ............................................. 3-29
Table 3.4-3 Output signals of generator inter-turn protection (event recorder)................. 3-29
Table 3.4-4 Output signals of generator inter-turn protection (measurements) ................ 3-30
Table 3.4-5 Settings list of generator inter-turn protection .................................................. 3-30
Table 3.5-1 Input signals of generator stator overload protection ...................................... 3-34
Table 3.5-2 Output signals of generator stator overload protection ................................... 3-35
Table 3.5-3 Output signals of generator stator overload protection (event recorder) ...... 3-35
Table 3.5-4 Output signals of generator stator overload protection (measurements) ...... 3-35
Table 3.5-5 Settings list of generator stator overload protection ........................................ 3-36
Table 3.6-1 Input signals of generator fundamental zero-sequence stator ground fault
protection ................................................................................................................................... 3-45
Table 3.6-2 Output signals of generator fundamental zero-sequence voltage stator ground
PCS-985GE Generator Relay 3-m
Date: 2016-08-16
3 Operation Theory
fault protection .......................................................................................................................... 3-45
fault protection (event recorder) .............................................................................................. 3-45
fault protection (measurements) ............................................................................................. 3-46
Table 3.6-5 Settings list of generator fundamental zero-sequence voltage stator ground
fault protection .......................................................................................................................... 3-47
Table 3.7-1 Input signals of generator 3rd harmonic stator ground fault protection.......... 3-55
Table 3.7-2 Output signals of generator 3rd harmonic stator ground fault protection....... 3-56
Table 3.7-3 Output signals of generator 3rd harmonic stator ground fault protection (event
recorder) ..................................................................................................................................... 3-56
Table 3.7-4 Output signals of generator 3rd harmonic stator ground fault protection
(measurements) ......................................................................................................................... 3-56
Table 3.7-5 Settings list of generator 3rd harmonic stator ground fault protection ........... 3-57
Table 3.8-1 Input signals of generator Ping-Pang type rotor ground fault protection ...... 3-61
Table 3.8-2 Output signals of generator Ping-Pang type rotor ground fault protection ... 3-61
Table 3.8-3 Output signals of generator Ping-Pang type rotor ground fault protection (event
recorder) ..................................................................................................................................... 3-62
Table 3.8-4 Output signals of generator Ping-Pang type rotor ground fault protection
(measurements) ......................................................................................................................... 3-62
Table 3.8-5 Settings list of generator Ping-Pang type rotor ground fault protection ........ 3-63
Table 3.9-1 Input signals of generator rotor ground fault protection (with low-frequency
Table 3.9-2 Output signals of generator rotor ground fault protection (with low-frequency
square-wave voltage injection) (event recorder) ................................................................... 3-69
square-wave voltage injection) (measurements) ................................................................... 3-69
Table 3.9-5 Settings list of generator rotor ground fault protection (with low-frequency
Table 3.10-1 Input signals of rotor winding overload protection ......................................... 3-75
Table 3.10-2 Output signals of rotor winding overload protection ...................................... 3-75
Table 3.10-3 Output signals of rotor winding overload protection (event recorder) ......... 3-75
3-n PCS-985GE Generator Relay
Date: 2016-08-16
3 Operation Theory
Table 3.10-4 Output signals of rotor winding overload protection (measurements)......... 3-76
Table 3.10-5 Settings list of rotor winding overload protection........................................... 3-76
Table 3.11-1 Input signals of inadvertent energization protection ...................................... 3-80
Table 3.11-2 Output signals of inadvertent energization protection ................................... 3-81
Table 3.11-3 Output signals of inadvertent energization protection (event recorder) ...... 3-81
able 3.11-4 Output signals of inadvertent energization protection (measurements) ........ 3-81
Table 3.11-5 Settings list of inadvertent energization protection ........................................ 3-81
Table 3.12-1 Input signals of generator out-of-step protection ........................................... 3-86
Table 3.12-2 Output signals of generator out-of-step protection ........................................ 3-86
Table 3.12-3 Output signals of generator out-of-step protection (event recorder)............ 3-86
Table 3.12-4 Output signals of generator out-of-step protection (measurements) ........... 3-87
Table 3.12-5 Settings list of generator out-of-step protection ............................................. 3-87
Table 3.13-1 Input signals of generator startup and shutdown protection ........................ 3-91
Table 3.13-2 Output signals of generator startup and shutdown protection ..................... 3-91
Table 3.13-3 Output signals of generator startup and shutdown protection (event recorder)
..................................................................................................................................................... 3-91
Table 3.13-4 Output signals of generator startup and shutdown protection (measurements)
..................................................................................................................................................... 3-92
Table 3.13-5 Settings list of generator startup and shutdown protection .......................... 3-92
Table 3.14-1 Input signals of generator shaft overcurrent protection ................................ 3-95
Table 3.14-2 Output signals of generator shaft overcurrent protection ............................. 3-96
Table 3.14-3 Output signals of generator shaft overcurrent protection (event recorder) . 3-96
Table 3.14-4 Output signals of generator shaft overcurrent protection (measurements) 3-96
Table 3.14-5 Settings list of generator shaft overcurrent protection .................................. 3-97
Table 3.15-1 Input signals of generator negative-sequence overload protection ........... 3-101
Table 3.15-2 Output signals of generator stator overload protection ............................... 3-102
Table 3.15-3 Output signals of generator negative-sequence overload protection (event

recorder) ................................................................................................................................... 3-102
Table 3.15-4 Output signals of generator negative-sequence overload protection

(measurements) ....................................................................................................................... 3-102
Table 3.15-5 Settings list of generator negative-sequence overload protection ............. 3-103
PCS-985GE Generator Relay 3-o
Date: 2016-08-16
3 Operation Theory
Table 3.16-1 Input signals of generator reverse power protection .................................... 3-106
Table 3.16-2 Output signals of overexcitation protection................................................... 3-107
Table 3.16-3 Output signals of generator reverse power protection (event recorder) .... 3-107
Table 3.16-4 Output signals of generator reverse power protection (measurements).... 3-107
Table 3.16-5 Settings list of generator reverse power protection...................................... 3-108
Table 3.17-1 Input signals of generator low forward power protection ............................ 3-110
Table 3.17-2 Output signals of generator low forward power protection ......................... 3-110
Table 3.17-3 Output signals of generator low forward power protection (event recorder)
................................................................................................................................................... 3-111
Table 3.17-4 Settings list of generator low forward power protection .............................. 3-111
Table 3.18-1 Input signals of overexcitation protection...................................................... 3-115
Table 3.18-2 Output signals of overexcitation protection................................................... 3-116
Table 3.18-3 Output signals of overexcitation protection (event recorder) ...................... 3-116
Table 3.18-4 Output signals of overexcitation protection (measurements) ..................... 3-116
Table 3.18-5 Settings list of overexcitation protection ....................................................... 3-117
Table 3.19-1 Input signals of loss of excitation protection................................................. 3-125
Table 3.19-2 Output signals of loss of excitation protection ............................................. 3-125
Table 3.19-3 Output signals of loss of excitation protection (event recorder)................. 3-125
Table 3.19-4 Output signals of loss of excitation protection (measurements) ................ 3-125
Table 3.19-5 Settings list of loss of excitation protection .................................................. 3-126
Table 3.20-1 Inverse-time curve parameters of stage 3 of generator phase overcurrent

protection ................................................................................................................................. 3-131
Table 3.20-2 Input signals of generator phase overcurrent protection............................. 3-137
Table 3.20-3 Output signals of generator phase overcurrent protection.......................... 3-137
Table 3.20-4 Output signals of generator phase overcurrent protection (event recorder)
................................................................................................................................................... 3-137
Table 3.20-5 Output signals of generator phase overcurrent protection (measurements)

................................................................................................................................................... 3-138
Table 3.20-6 Settings list of generator phase overcurrent protection .............................. 3-138
Table 3.21-1 Input signals of phase overvoltage protection .............................................. 3-143
Table 3.21-2 Output signals of phase overvoltage protection ........................................... 3-143
3-p PCS-985GE Generator Relay
Date: 2016-08-16
3 Operation Theory
Table 3.21-3 Output signals of phase overvoltage protection (event recorder) .............. 3-143
Table 3.21-4 Output signals of phase overvoltage protection (measurements) .............. 3-144
Table 3.21-5 Settings list of phase overvoltage protection ................................................ 3-144
Table 3.22-1 Input signals of undervoltage protection ....................................................... 3-148
Table 3.22-2 Output signals of undervoltage protection .................................................... 3-148
Table 3.22-3 Output signals of phase undervoltage protection (event recorder) ............ 3-148
Table 3.22-4 Output signals of phase undervoltage protection (measurements)............ 3-149
Table 3.22-5 Settings list of undervoltage protection ......................................................... 3-149
Table 3.23-1 Input signals of overfrequenncy protection ................................................... 3-154
Table 3.23-2 Output signals of overfrequenncy protection ................................................ 3-154
Table 3.23-3 Output signals of overfrequency protection (event recorder) ..................... 3-154
Table 3.23-4 Output signals of overfrequency protection (measurements) ..................... 3-155
Table 3.23-5 Settings list of overfrequency protection ....................................................... 3-156
Table 3.24-1 Input signals of underfrequency protection ................................................... 3-162
Table 3.24-2 Output signals of underfrequency protection................................................ 3-162
Table 3.24-3 Output signals of underfrequency protection (event recorder) ................... 3-162
Table 3.24-4 Output signals of underfrequency protection (measurements)................... 3-164
Table 3.24-5 Settings list of underfrequency protection..................................................... 3-164
Table 3.25-1 Input signals of impedance protection ........................................................... 3-173
Table 3.25-2 Output signals of impedance protection ........................................................ 3-173
Table 3.25-3 Output signals of impedance protection (event recorder) ........................... 3-173
Table 3.25-4 Output signals of impedance protection (measurements) ........................... 3-174
Table 3.25-5 Settings list of impedance protection ............................................................. 3-175
Table 3.26-1 Input signals of breaker failure protection ..................................................... 3-178
Table 3.26-2 Output signals of breaker failure protection .................................................. 3-179
Table 3.26-3 Output signals of breaker failure protection (event recorder) ..................... 3-179
Table 3.26-4 Output signals of breaker failure protection (measurements) ..................... 3-179
Table 3.26-5 Settings list of breaker failure protection ....................................................... 3-179
Table 3.27-1 Input signals of mechanical protection (x=1, 2) ............................................. 3-182
Table 3.27-2 Output signals of mechanical protection (x=1, 2) .......................................... 3-182
PCS-985GE Generator Relay 3-q
Date: 2016-08-16
3 Operation Theory
Table 3.27-3 Output signals of mechanical protection (event recorder) (x=1, 2) ............. 3-182
Table 3.27-4 Settings list of mechanical protection ............................................................ 3-183
Table 3.28-1 Phase shift matrix for phase compensation .................................................. 3-187
Table 3.28-2 Input signals of excitation transformer current differential protection....... 3-200
Table 3.28-3 Output signals of excitation transformer current differential protection.... 3-201
Table 3.28-4 Output signals of excitation transformer current differential protection (event
recorder) ................................................................................................................................... 3-201
Table 3.28-5 Output signals of excitation transformer current differential protection.... 3-201
Table 3.28-6 Settings list of excitation transformer current differential protection ........ 3-203
Table 3.29-1 Input signals of excitation transformer phase overcurrent protection ....... 3-205
Table 3.29-2 Output signals of excitation transformer phase overcurrent protection .... 3-206
Table 3.29-3 Output signals of excitation transformer phase overcurrent protection (event
recorder) ................................................................................................................................... 3-206
Table 3.29-4 Settings list of excitation transformer phase overcurrent protection ......... 3-206
Table 3.30-1 Input signals of interconnection status element ........................................... 3-208
Table 3.30-2 Output signals of interconnection status element ........................................ 3-209
Table 3.30-3 Output signals of interconnection status element (measurements) ........... 3-209
Table 3.30-4 Settings list of interconnection status element ............................................. 3-209
Table 3.31-1 Input signals of voltage balance protection ................................................... 3-214
Table 3.31-2 Output signals of voltage balance protection ................................................ 3-214
Table 3.31-3 Output signals of voltage balance protection (event recorder) ................... 3-214
Table 3.31-4 Output signals of voltage balance protection (measurements) ................... 3-215
Table 3.31-5 Settings list of voltage balance protection ..................................................... 3-215
Table 3.32-1 Input signals of three-phase current element ................................................ 3-217
Table 3.32-2 Output signals of three-phase current element ............................................. 3-217
Table 3.32-3 Output signals of three-phase current element (event recorder) ................ 3-217
Table 3.32-4 Output signals of three-phase current element (measurements) ................ 3-217
Table 3.32-5 Settings list of three-phase current element .................................................. 3-219
Table 3.33-1 Input signals of three-phase voltage element ................................................ 3-221
Table 3.33-2 Output signals of three-phase voltage element ............................................. 3-222
3-r PCS-985GE Generator Relay
Date: 2016-08-16
3 Operation Theory
Table 3.33-3 Output signals of three-phase voltage element (event recorder) ................ 3-222
Table 3.33-4 Output signals of three-phase voltage element (measurements) ................ 3-222
Table 3.33-5 Settings list of three-phase voltage element .................................................. 3-223
Table 3.34-1 Input signals of single current element with filter ......................................... 3-224
Table 3.34-2 Output signals of single current element with filter ...................................... 3-224
Table 3.34-3 Output signals of single current element with filter (measurements) ......... 3-225
Table 3.34-4 Settings list of single current element with filter ........................................... 3-225
Table 3.35-1 Input signals of residual voltage element....................................................... 3-226
Table 3.35-2 Output signals of residual voltage element.................................................... 3-226
Table 3.35-3 Output signals of residual voltage element (measurements) ...................... 3-226
Table 3.35-4 Settings list of residual voltage element ........................................................ 3-227
PCS-985GE Generator Relay 3-s
Date: 2016-08-16
3 Operation Theory
3-t PCS-985GE Generator Relay
Date: 2016-08-16
3 Operation Theory
3.1 Overview
The device has 2 plug-in modules (protection DSP module and fault detector DSP module) for
protection calculation. Protection DSP module is responsible for calculation of protection elements,
and fault detector DSP module is responsible for calculation of general fault detector element to
determine fault appearance on the protected power system. General fault detector picks up to
provide positive supply to output relays. The output relays can only operate when both a protection
element and the corresponding general fault detector operate simultaneously. Otherwise, the
output relays would not operate. An alarm message will be issued with blocking output if a
protection element operates while the corresponding general fault detector does not operate.
The fault detector of fault detector DSP module consists of several independent fault detector
elements, which can monitor corresponding protection elements without influence to other
protection elements. For example, biased current differential protection will not release tripping
command until both protection element of protection DSP module and the corresponding fault
detector of fault detector DSP module operate simultaneously. Furthermore, if there is a hardware
fault on one DSP module or the differential current is at the trip boundary, the inconsistent pickup
of fault detectors of biased current differential protection on two DSP modules will occur.
3.2 Generator Current Differential Protection (87G)
3.2.1 Application
Generator current differential protection is the main protection for the internal short-circuit fault of
generator stator winding. Current differential protection can operate quickly to clear the internal
fault to avoid the generator from damages or reduce the maintenance cost as low as possible.
3.2.2 Function Description
 Reliable biased differential element
Biased current differential element with initial restraint slope is adopted, it consists of sensitive
and conventional biased differential elements as well as independent CT saturation criterion.
 High sensitive DPFC differential element
DPFC current differential element can fully reflect the change of differential current and
restraint current, and it is not affected by the load current and is sensitive to small internal fault
current within the generator. Its performance against CT saturation is also good.
 Unrestrained instantaneous differential element is equipped
For internal serious fault, once the differential current is larger than the current setting of
instantaneous differential element, the current differential element will operate to cut off the
fault quickly.
 Reliable differential CT circuit abnormality detection
Date: 2016-08-16
3 Operation Theory
Voltage is also used to judge the abnormality of differential CT circuit, multi-phase CT circuit
failure, multi-side CT circuit failure and short-circuit condition can be detected.
3.2.3 Protection Principle

3.2.3.1 Overview
Current differential protection includes three operation elements: biased differential element,
unrestrained differential element and DPFC differential element. When the differential current is
larger than the corresponding current threshold, current differential protection will operate, and it
will drop off if the fault current disappears.
Sensitive biased differential element is variable slope differential element with initial restraint slope.
Conventional biased differential element is differential element with two broken lines. Unrestrained
differential element is used to cut off the serious fault quickly and there is no any blocking element
for it. DPFC differential element adopts the current change to calculate, it is very sensitive to slight
fault under heavy loading condition. The three differential elements coordinate with each other, so
quick and high sensitive differential protection can be realized.
3.2.3.2 Amplitude Compensation
Generally, the CT ratio of the two sides of the generator is the same, as long as the polarity of CT
is correct, the secondary currents of two CTs will be balanced automatically. In some cases (such
as some hydropower units), the magnitudes of secondary current of two CTs are different due to
the difference of CT ratio. Then the secondary currents of two CTs should be balanced by
amplitude adjustment of software (i.e. CT ratio adjustment).
 Calculate rated primary current of generator
Pn / cos θ
I1b = Equation 3.2-1
3U1n
Where:
Pn is the rated capacity of the generator.
cos θ is the power factor of the generator.
U1n is rated primary voltage of the generator.
I1b is rated primary current of the generator.
 Calculate rated secondary current of each side
I1b I
I 2b _ Br1 = , I 2b _ Br 2 = 1b Equation 3.2-2
CT1 CT2
Date: 2016-08-16
3 Operation Theory
Where:
I 2b _ Br1 is rated secondary current of generator terminal side.
I 2b _ Br 2 is rated secondary current of generator neutral point side.
CT1 is the CT ratio of generator terminal side.
CT2 is the CT ratio of generator neutral point side.
 Calculate differential adjust coefficient
k _ Br1 = 1
I 2b _ Br1
k _ Br 2 =
I 2b _ Br 2 Equation 3.2-3
( I 2b _ Br1 / I 2 n _ Br1 )
≤ 16
( I 2b _ Br 2 / I 2 n _ Br 2 )
Where:
I 2b _ Br1 , I 2b _ Br 2 are rated secondary current of generator terminal side and generator neutral
point side.
I 2 n _ Br1 , I 2 n _ Br 2 are rated secondary current of CT of generator terminal side and generator
neutral point side (1A or 5A).
k _ Br1 , k _ Br 2 are adjust coefficient of generator terminal side and generator neutral point side.
Generator terminal side is the referenced side fixedly. If Equation 3.2-3 is not met, the setting error
alarm signals [87G.Fail_Settings] will be issued and displayed on LCD with the protective device
being blocked.
3.2.3.3 Calculations of Differential Current and Restraint Current
The calculation equation of differential current and restraint current is:
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3 Operation Theory
 I1cr = I1 / I 2b _ Br1


 I2 cr = I2 / I 2b _ Br 2

 I =| I − I | Equation 3.2-4
 d 1cr 2 cr
 | I1cr + I2 cr |
I
 r =
2
Where:
I1 , I2 are the secondary current of generator terminal side and generator neutral point side.
I 2 n _ Br1 , I 2 n _ Br 2 are rated secondary current of CT of generator terminal side and generator
neutral point side.
I1cr , I2 cr are the corrected secondary current of generator terminal side and generator neutral
point side.
I d is differential current.
I r is restraint current.
Current adjustment process is shown in the flowing figure. The symbol “*” represents the polarity
of CT. If current flowing into the polarity side of CT, the current direction is defined as positive
direction. In an ideal situation, the differential current should be zero during the normal operation
of the generator or an external fault occurring.
Generator Ip1 Ip2 Neutral

* * *
* * *
terminal CT1 CT2 point

G
I1 I2
PCS-985GE
Magnitude compensation Magnitude compensation

(/I2b_Br1) (/I2b_Br2)
I1cr I2 cr
Calculate differential current and restraint current
Figure 3.2-1 Current calculation process of generator current differential protection
In above figure:
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3 Operation Theory
IP1 , IP2 are primary current vectors of generator terminal side and generator neutral point side
respectively.
I1 , I2 are the secondary current of generator terminal side and generator neutral point side.
I1cr , I2 cr are the corrected secondary current of generator terminal side and generator neutral
point side.
To clarify the principle, in an ideal situation, three important operation conditions are considered.
1. Through-fault current under undisturbed conditions or external fault:
The current directions of two sides are the same with the defined direction. The corrected
secondary current amplitude of two sides are equal.
I1cr = I2 cr
| I1cr + I2 cr | 
The differential current: I d =| I1cr − I2 cr |= 0 , the restraint current: I r = =| I 2 cr | .
2
No differential current, restraint current (Ir) is equal to the through-fault current, and current
differential protection will not operate.
2. Internal short-circuit fault, e.g. the fed currents of two sides are equal:
The current direction of generator terminal side is reverse with the defined direction.
I1cr = − I2 cr
| I1cr + I2 cr |
The differential current: I d =| I1cr − I2 cr |= 2 | I2 cr | , the restraint current: I r = = 0.
2
No restraint current, differential current is the total fault current, current differential protection
operates sensitively.
3. Internal short-circuit fault, current is only fed from one side:
Assuming that the current of generator terminal side is zero. IP1 = 0 , so I1cr = 0
| I1cr + I2 cr | | I2 cr |

The differential current: I d =| I1cr − I2 cr |=| I2 cr | , the restraint current: I r = =
2 2
Differential current is two times of restraint current, current differential protection operates
sensitively.
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3 Operation Theory
3.2.3.4 Sensitive Biased Differential Element
The operation equation of sensitive biased differential element is:
 I d > K bl × I r + I Diff . Pickup ( I r < nI e )


 K bl = K bl1 + K blr × ( I r / I e )

 I d > K bl 2 × ( I r − nI e ) + b + I Diff .Pickup ( I r ≥ nI e )

 K blr = ( K bl 2 − K bl1 ) /(2 × n)
b = ( K bl1 + K blr × n) × nI e Equation 3.2-5
 I1 + I2
I r =
 2
 I = I − I
 d 1 2
Where:
I 1 , I 2 are the corrected secondary currents of generator terminal side and generator neutral
point side respectively.
I d is the differential current.
I r is the restraint current.
I e is the rated current of generator.
I Diff . Pckup is the pickup current setting of generator biased differential element [87G.I_Biased].
K b1 is the restraint coefficient of biased differential element.
K b1r is the restraint coefficient increment of biased differential element.
K bl1 is the initial slope setting of biased differential element [87G.Slope1], the setting range is
0.01~0.50, it takes 0.05 generally.
K bl 2 is the maximum slope setting [87G.Slope2] of biased differential element, the setting range
is 0.30~0.80, it takes 0.50 generally.
n is the restraint current multiple when the restraint coefficient reach to the maximum value. This
internal value is set as 4 fixedly.
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3.2.3.5 Conventional Biased Differential Element
Conventional biased differential element with higher pickup current and higher restraint coefficient
comparing with sensitive biased differential element is equipped. Its biased restraint characteristic
can make the differential element not operate due to CT transient and steady-state saturation
during external fault, and it can operate reliably even the CT is seriously saturated during internal
fault. Operation criterion of conventional biased differential element is:
 I d > 1.2 × I e

I d > I r Equation 3.2-6
Where:
I d and I r have the same definitions as mentioned above.
NOTICE!
The related parameters of conventional biased differential element are set FIXEDLY in
the device. Therefore, the slope and the knee point with constant values do not need to
be set by user.
3.2.3.6 Unrestrained Instantaneous Differential Element
Unrestrained instantaneous differential element of generator is used to accelerate the operation

speed for serious internal fault. The element has no blocking element and the current setting is
very high. If differential current of any phase is larger than the current setting of unrestrained
instantaneous differential element, the protection will operate to trip the circuit breaker of generator
each side instantaneously. Its operation criterion is:
I dφ max > [87G.I_Inst] Equation 3.2-7
Where:
I dφ max is the maximum value of three phase differential currents.
[87G.I_Inst] is the current setting of the unrestrained instantaneous differential element.
3.2.3.7 DPFC Differential Element
If internal slight fault occurs in generator, sensitive and conventional biased differential element
may not response sensitively due to the influence of load current. DPFC (Deviation of Power
Frequency Component) biased differential element of generator is equipped with the device for
that and it can significantly improve the sensitivity of the protection during small current internal
fault of generator. It can be enabled or disabled conveniently by the corresponding logic setting.
The operation criteria of DPFC differential element are as follows:
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3 Operation Theory
∆I d > 1.25 * ∆I dt + I dth


∆I d > 0.6 * ∆I r ∆I r < 2 I e
∆I > 0.75 * ∆I − 0.3 * I ∆I r > 2 I e
 d r e
Equation 3.2-8
∆I r = ∆I1 + ∆I 2
∆I d = ∆I1 + ∆I2
Where:
∆I dt is the floating threshold varied with the change of differential current. Take its multiple as
1.25 can ensure the threshold value always a bit higher than the unbalance current. So that
unwanted operation of the device can be avoided during power swing or frequency deviation
condition.
∆I1 , ∆I 2 are the DPFC current of generator terminal side and generator neutral point side
respectively.
∆I d is the DPFC differential current.
I dth is the fixed threshold.
∆I r is the DPFC restraint current, the maximum value of three-phase DPFC current of two sides
are used as the restraint current.
NOTICE!
Calculation of restraint current of generator DPFC differential element is DIFFERENT

from steady-state biased differential element, all the settings about DPFC differential
element is FIXED in the program, it is difficult to test the characteristic at site.
If the above criteria are met, CT saturation detection and CT circuit failure detection are also
adopted to control generator DPFC differential element.
For the restraint coefficient of generator DPFC differential element can take a higher value, so it
has high ability to eliminate the effect of transient and steady-state CT saturation during an
external fault. Generator DPFC differential element improves the sensitivity for detecting generator
internal slight fault.
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3 Operation Theory
3.2.3.8 Operation Characteristic of Generator Differential Protection
Id
Tripping area of
instantaneous diff.
[87G.I_Inst]
Tripping area of
conventional biased diff.
.0
ed of
=1
ff.
K
di
as a
[87G.Slope2]
bi are
ve g
iti in
p
ns i p
se Tr
1.2Ie
[87G.I_Biased]
[87G.Slope1]
0 nIe
1.2Ie Ir
Figure 3.2-2 Operation characteristic curve of steady-state differential element of generator
△ Id
m
K=
K=0.75
1.2Ie
K=0.6
[87G.I_Biased]
2Ie
△ Ir
Figure 3.2-3 Operation characteristic curve of DPFC differential element of generator
Current differential protection carries out the fault discrimination according to the current of each
phase. If the current criteria are met and no related blocking element(s) operate, differential
protection will operate to trip.
1) Sensitive biased differential element will send tripping signal monitored by CT saturation and
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3 Operation Theory
CT circuit failure (optional). It can ensure the sensitivity of differential protection and avoid the
unwanted operation when CT is saturated during an external fault. Its operation area is the tint
shadow area in the figure above.
2) Conventional biased differential element will send tripping signal monitored by CT circuit
failure (optional). It eliminates the influence of transient and steady-state saturations of CT
during an external fault and ensures differential protection can operate reliably even if CT is
saturated during an internal fault by means of its biased characteristic. Its operation area is the
deeper shadow area in the figure above.
3) Unrestrained instantaneous differential element will send tripping signal without any blocking
element if differential current of any phase is larger than corresponding current setting.
Unrestrained instantaneous differential element is used to cut off the internal serious fault
quickly. Its operation area is the non-shaded area that located in the top of the figure.
3.2.3.9 CT Saturation Detection
When an generator external fault happens, great through-fault current will flowing through the CT,
if the saturation degree of generator terminal side CT is inconsistent with that of generator neutral
point side CT, great unbalance differential current will generate in the differential circuit, which will
lead to the mal-operation of differential protection. So the CT saturation detection function is
required for generator differential protection.
There is a certain time before the CT falling into saturated state, so the changing characteristic of
differential current and restraint current within the initial time of the fault can be used to judge
whether it is an external fault. For an external fault, the deviation of power frequency component
(DPFC) of restraint current appears before the appearance of DPFC of differential current; for an
internal fault, DPFC of restraint current and differential current appear almost simultaneously. If
external fault is detected, CT saturation blocking criterion is enabled.
In order to prevent an unwanted operation of sensitive biased differential protection caused by

transient state saturation of CT during an external fault, the second harmonic of current is used for
the protection device to discriminate saturation of three-phase CT.
Iϕ 2 > kϕ 2 xb * Iϕ1 Equation 3.2-9
Where:
Iφ1 is the fundamental component of one phase differential current.
Iφ 2 is the secondary harmonic of the corresponding phase differential current.
kϕ 2 xb is an internal fixed coefficient.
If secondary harmonic of one phase differential current meets the above equation, it will be
considered that it is CT saturation to cause this phase differential current and sensitive biased
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3 Operation Theory
differential element will be blocked. The criterion is only enabled when the generator is in service.
3.2.3.10 Differential Circuit CT Supervision
3.2.3.10.1 Differential Circuit CT Abnormality Alarm
If the generator differential current of any phase meets the following criteria and corresponding
differential element is enabled, the generator differential current abnormality alarm [87G.Alm_Diff]
with a time delay of 300ms, this alarm signal will not block the differential element. The signal will
reset if the differential current disappears with a time delay of 10s.
 I d > [87G.I _ Alm]

 Equation 3.2-10
I d > k * I r
k is the restraint coefficient of differential current abnormality alarm.
[87G.I_Alm] is the current setting of differential current abnormality alarm.
3.2.3.10.2 Differential Circuit CT Circuit Failure Alarm
If any one of following four conditions is satisfied after the fault detector of biased differential
current picks up, it will be determined as fault and differential protection is released, otherwise it
will be determined that the fault detector of biased differential current picks up due to differential
CT circuit failure or short-circuit.
 Negative-sequence voltage of generator terminal side is larger than 1V.
 Any phase current of any side increases after the fault detector picks up.
 The maximum phase current is larger than 1.2Ie after the fault detector picks up.
 Among all the current channels, any three phases of the current decrease after fault
detector picks up.
If none of above four conditions is satisfied within 40ms after the fault detector of biased
differential current picks up, it will be determined as differential CT circuit failure and CT circuit
failure alarm will be issued. Then if the logic setting [87G.En_CTS_Blk] is set as “1”, sensitive and
conventional biased differential element will be blocked, if the logic setting [87G.En_CTS_Blk] is
set as “0”, sensitive and conventional biased differential element will not be blocked. Generator
unrestrained instantaneous differential element will not be blocked during CT circuit failure.
Generator CT circuit failure alarm and blocking function will quit automatically if the generator is
not connected to the power grid.
The above conditions contain the voltage criteria and current criteria, which realizes the high
accuracy and sensitivity of the CT circuit failure detection.
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3 Operation Theory
The CT circuit failure alarm is latched once issued, it can be reset only after the failure is cleared
and the device is reset (i.e. the binary input [BI_RstTarg] is energized).
No matter whether the abnormality alarm signal makes the differential protection picks up, there
must be some problems in the differential circuit. For example, when the differential circuit fails,
the differential protection will not pick up for light-loaded condition, but the differential current
abnormality alarm signal will be issued. If the abnormality is treated in time, the mal-operation of
differential protection due to increase of load or external fault can be avoided (if the logic setting
[87G.En_CTS_Blk] is set as “0”).
Once the differential CT circuit failure alarm is issued, the CT circuit should be check carefully, only
if the fault is cleared, the reset operation can be conducted.
3.2.4 Logic
For generator current differential protection, if following three conditions are met, the protection will
be enabled.
(1) Logic setting [87G.En] is set as “1”.
(2) The protection function enabling inputs [87G.En1], [87G.En2] are “1”
(3) The protection function blocking input [87G.Blk] is “0”.
If generator differential protection is disabled, all the related output signals will be reset. If no
external input is configured to [87G.En1] ([87G.En2]), the default initial value of [87G.En1]
([87G.En2]) is “1”; if no external input is configured to [87G.Blk], the default initial value of [87G.Blk]
is “0”.
SIG [87G.En1] &

SIG [87G.En2]
SIG [87G.Blk]
En 87G.En_Inst & &

[87G.St]
SIG Idmax>[87G.I_Inst]
En 87G.En_Biased & ≥1
SIG Idmax>[87G.I_Biased]
En 87G.En_DPFC &
SIG ΔId>1.25ΔIdt+Idth
Figure 3.2-4 Logic diagram of startup of generator current differential protection
Where:
Idmax is the maximum value of three phase differential currents.
∆I d is the DPFC differential current.
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3 Operation Theory
∆I dt is the floating threshold varied with the change of differential current.
I dth is the fixed threshold.
EN [87G.En_Inst]
SIG [87G.En1] &
&
SIG [87G.En2]
[87G.Op_Inst]
SIG [87G.Blk]
SIG Idmax>[87G.I_Inst]
0ms 500ms
SIG 87G.FD_Inst
EN [87G.En_Biased]
SIG [87G.En1] &
SIG [87G.En2] &

SIG [87G.Blk]
SIG Flg_ConvBiasDiff
SIG Flg_CTS &
SET [87G.En_CTS_Blk] ≥1
[87G.Op_Biased]
0ms 500ms
SIG 87G.FD_Biased
EN [87G.En_Biased]
SIG [87G.En1] &
SIG [87G.En2]
SIG [87G.Blk]
&
SIG Flg_SensBiasDiff
SIG Flg_CTSaturation &
SIG Flg_CTS &
SET [87G.En_CTS_Blk]
SIG 87G.FD_Biased 0ms 500ms
Figure 3.2-5 Logic diagram of steady-state current differential element of generator
Where:
Flg_ConvBiasDiff is the internal flag indicating that the operation criteria of conventional biased
differential element are satisfied.
Flg_SensBiasDiff is the internal flag indicating that operation criteria of sensitive biased differential
element are satisfied.
Flg_CTS is the internal flag indicating that differential CT circuit failure is detected.
Flg_CTSaturation is the internal flag indicating that CT saturation is detected.
87G.FD_Inst is the signal indicating that the fault detector of unrestrained instantaneous
differential element picks up (the fault detector of fault detector DSP module).
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87G.FD_Biased is the signal indicating that the fault detector of steady-state biased differential
element picks up (the fault detector of fault detector DSP module).
EN [87G.En_DPFC]
SIG [87G.En1] &
SIG [87G.En2]
SIG [87G.Blk]
&
SIG Flg_DPFC_Diff [87G.Op_DPFC]
SIG Flg_CTSaturation &
SIG Flg_CTS &
SET [87G.En_CTS_Blk]
SIG 87G.FD_DPFC 0ms 500ms
Figure 3.2-6 Logic diagram of DPFC current differential element of generator
Where:
Flg_DPFC_Diff is the internal flag indicating that the operation criteria of DPFC differential element
are satisfied.
87G.FD_DPFC is the signal indicating that the fault detector of DPFC differential element picks up
(the fault detector of fault detector DSP module).
3.2.5 Inputs and Outputs
87G
87G.I3P1 87G.St
87G.I3P2 87G.Op_Biased
87G.En1 87G.Op_Inst
87G.En2 87G.Op_DPFC
87G.Blk 87G.Alm_Diff
87G.Alm_CTS
Figure 3.2-7 Function block diagram of generator current differential protection
Table 3.2-1 Input signals of generator current differential protection
No. Signal Description

1 87G.I3P1 Three-phase current data input 1
2 87G.I3P2 Three-phase current data input 2
3 87G.En1 Protection function enabling input1 and input 2, it can be binary inputs or settings,
4 87G.En2 such as function enabling binary inputs, logic links, etc.
5 87G.Blk Protection function blocking input, such as function blocking binary input.
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3 Operation Theory
Table 3.2-2 Output signals of generator current differential protection

1 87G.St Generator current differential protection starts.
2 87G.Op_Inst Instantaneous differential element of generator operates.
3 87G.Op_Biased Steady-state biased differential element of generator operates.
4 87G.Op_DPFC DPFC differential element of generator operates.
Alarm message indicating CT secondary circuit of generator differential protection is
5 87G.Alm_Diff
abnormal.
Alarm message indicating that CT secondary circuit of generator differential
6 87G.Alm_CTS
protection fails.
Above input and output signals can be used for programmable logic, and following output signals
are only for LCD display and waveform recording function of the device.
Table 3.2-3 Output signals of generator current differential protection (event recorder)
Tripping reports
1 87G.Op_Inst Instantaneous differential protection of generator operates.
2 87G.Op_Biased Steady-state biased differential element of generator operates.
3 87G.Op_DPFC DPFC differential element of generator operates.
Start signals
4 87G.St Generator current differential protection starts.
Alarm signals
Alarm message indicating CT secondary circuit of generator differential

5 87G.Alm_Diff
protection is abnormal.
Alarm message indicating that CT secondary circuit of generator differential

6 87G.Alm_CTS
protection fails.
Waveform recording
7 87G.TrigDFR Generator differential protection operates to trigger waveform recording.
Binary change report
8 87G.St_Biased Generator biased differential element starts instantaneously.
9 87G.St_DPFC Generator DPFC differential element starts instantaneously.
Table 3.2-4 Output signals of generator current differential protection (measurements)
No. Signal Description Unit
87G.Ida
Three-phase differential current amplitude for generator
1 87G.Idb pu
current differential protection.
87G.Idc
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87G.Ira
Three-phase restraint current amplitude for generator
2 87G.Irb pu
87G.Irc
Access path:
Main menu -> Measurements -> Measurements1-> Gen Values-> Gen Diff Values
87G.Ang(Ia_Br1-Br2) Phase angle between generator terminal side corrected

3 87G.Ang(Ib_Br1-Br2) current and generator neutral point side corrected current of deg
87G.Ang(Ic_Br1-Br2) the same phase.
Access path:
Main menu -> Measurements -> Measurements2-> Phase Angle-> Gen PhaseAngleValues
4 87G.I2b_Br1 The secondary rated current of generator terminal side. A
5 87G.I2b_Br2 The secondary rated current of generator neutral point side. A
Access path:
Main menu -> Measurements -> Measurements2-> Cal Param Display-> Sec Rated Curr Values
Adjust coefficient of generator terminal side for generator

6 87G.K_Br1
differential protection
Adjust coefficient of generator neutral point side for

7 87G.K_Br2
generator differential protection
Access path:
Main menu -> Measurements -> Measurements2-> Cal Param Display-> Diff Corr Coef Values
87G.Ida
Three-phase differential current amplitude for generator
8 87G.Idb pu
87G.Idc
87G.Ida_HalfCycle
Three-phase differential current half-cycle integral amplitude
9 87G.Idb_HalfCycle pu
of generator current differential protection.
87G.Idc_HalfCycle
87G.Ira
Three-phase restraint current amplitude for generator
10 87G.Irb pu
87G.Irc
87G.Ia_Cr_Br1
Three-phase corrected current of generator terminal side
11 87G.Ib_Cr_Br1 pu
that used for generator differential protection.
87G.Ic_Cr_Br1
87G.Ia_Cr_Br2
Three-phase corrected current of generator neutral point
12 87G.Ib_Cr_Br2 pu
side that used for generator differential protection.
87G.Ic_Cr_Br2
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87G.Ia_Th_Biased_L
Three-phase current threshold for generator sensitive
13 87G.Ib_Th_Biased_L pu
biased current differential element.
87G.Ic_Th_Biased_L
87G.Ia_Th_Biased_H
Three-phase current threshold for generator conventional
14 87G.Ib_Th_Biased_H pu
biased current differential element.
87G.Ic_Th_Biased_H
87G.Ida_Hm2
Second harmonic amplitude of three-phase differential
15 87G.Idb_Hm2 pu
current for generator current differential protection.
87G.Idc_Hm2
Access path:
Main menu -> Measurements -> Measurements2-> Prot Values-> Gen Diff Prot Values
3.2.6 Settings
Table 3.2-5 Settings list of generator current differential protection
No. Setting Item Range Step Unit Description
0: disable The logic setting of enabling/disabling generator

1 87G.En 1
1: enable differential protection.
Pickup current setting of generator biased

2 87G.I_Biased 0.10~1.5 0.01 pu
differential element.
Current setting of generator unrestrained

3 87G.I_Inst 2~14 0.01 pu
instantaneous differential element
4 87G.I_Alm 0.05~1.0 0.01 pu Differential current alarm setting of generator.
Slope 1 of biased differential element of

5 87G.Slope1 0.01~0.5 0.01
generator.

6 87G.Slope2 0.3~0.8 0.01
generator.
Tripping logic setting of generator current

7 87G.OutMap 0~3FFFFFFF
differential protection.
0: disable Logic setting of enabling/disabling generator

8 87G.En_Inst 1
1: enable unrestrained instantaneous differential element.

9 87G.En_Biased 1
1: enable biased differential element.

10 87G.En_DPFC 1
1: enable DPFC differential element.
Logic setting of enabling/disabling generator

0: disable
11 87G.En_CTS_Blk 1 biased differential element being blocked by CT
1: enable
circuit failure.
Access path: Settings-> Prot Settings -> Gen Diff Settings
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3 Operation Theory
[87G.OutMap]
The tripping logic setting is used to specify which breaker(s) will be tripped when corresponding
protection element operates. This logic setting comprises 32 binary bits as follows and is
expressed by a hexadecimal number of 8 digits from 0H to 3FFFFFFFH. The tripping logic setting
of the device is specified as follows:
bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TrpOutput15
TrpOutput14
TrpOutput13
TrpOutput12
TrpOutput11
TrpOutput10
TrpOutput09
TrpOutput08
TrpOutput07
TrpOutput05
TrpOutput04
TrpOutput03
TrpOutput02
TrpOutput01
TrpOutput06
Enable trip
Function
matrix
bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TrpOutput016
TrpOutput29
TrpOutput28
TrpOutput27
TrpOutput26
TrpOutput25
TrpOutput24
TrpOutput23
TrpOutput22
TrpOutput20
TrpOutput19
TrpOutput18
TrpOutput17
TrpOutput21
Function
Spare
Spare
“TrpOutput01” just means to drive tripping output channel 1. Set bit0 as “1” means this protection
element can operate to trip breaker(s). The bit corresponding to the breaker to be tripped shall be
set as “1” and other bits shall be “0”. For example, if generator differential protection is defined to
trip breaker 3 (tripping output channel 3) and breaker 5 (tripping output channel 5), the bit0, bit3
and bit5 shall be set as “1” and other bits shall be set as “0”. Then a hexadecimal number
00000029H is formed as the tripping output logic setting of generator differential protection.
Please note that tripping output logic settings of the equipment have to be set on basis of
application-specific drawings.
All the tripping logic settings mentioned below should be defined with the same method.
3.3 Generator Neutral Point Transverse Differential Protection
(87NTG)
3.3.1 Application
When generator winding of one phase has several parallel branches, all the branches can be
divided into two or several groups (the parallel branch number of each group is the same), the
branch groups corresponds to three-phase winding will be connected to form one neutral point,
two or several neutral points can be connected to form the final neutral point. In theory, if no
internal fault happens at generator stator winding, the fundamental potential of two neutral points
are the same, the fundamental current of the connection line between the two neutral points is
zero. If an internal short-circuit fault happens or the welding between branches has open, there will
be a fundamental potential difference between the two neutral points, then a larger fundamental
current will be generated.
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3 Operation Theory
One CT can be equipped at the connection line between the two neutral points to constitute
neutral point transverse differential protection. The protection is the main protection for generator
stator winding internal (phase-to-phase, different branches of the same phase and inter-turn of the
same branch) short-circuit fault and branches welding open fault. Neutral point transverse
differential protection can operate quickly to clear the internal fault to avoid the generator from
damages or reduce the maintenance cost as low as possible.
Neutral point transverse differential protection includes two operation elements:
 Sensitive neutral point transverse differential element
 Insensitive neutral point transverse differential element

3.3.3.1 Current Calculation Process
One CT is equipped at the connection line between the two neutral points, the device measure the
fundamental component of the current, there will be a slight unbalance current during operation.
Generator
CT Ip
Neutral * Generator
point * CT1 terminal
Ipo
Io I1
PCS-985GE
Filtering
Calculate Id and Imax
Figure 3.3-1 Current calculation process of neutral point transverse differential protection
Where:
IP is the primary value of generator terminal three-phase current and I1 is the corresponding
secondary value;
IPo is the primary value of the connection line current between the two neutral points and IO is
the corresponding secondary value;
I d is the neutral point transverse differential current;
I max is the maximum value of generator terminal three-phase current.
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3 Operation Theory
3.3.3.2 Sensitive Neutral Point Transverse Differential Element
The current setting of sensitive neutral point transverse differential element only should be larger
than the unbalance current during normal operation.
In order to prevent sensitive neutral point transverse differential element from mal-operation due to
generator rotor two-point ground fault, sensitive neutral point transverse differential element can
be switching to a settable time delay pick-up protection after the operation of generator rotor
one-point ground fault element.
When an internal slight fault happens to the generator stator winding, the phase current of
generator terminal does not change almost; but when an external short-circuit fault happens, the
phase current of generator terminal will increased significantly. So the phase current of generator
terminal is adopted as the restraint current, it can improve the sensitivity of sensitive neutral point
transverse differential element on the premise of making sure the reliability. Sensitive neutral point
transverse differential element mainly reflects the internal short-circuit fault for a small number of
turns or branches welding open fault.
The operation equation of sensitive neutral point transverse differential element is:
 I d ≥ I Sens ( I max ≤ I e )

  K hczd (I max − I e )  Equation 3.3-1
 I d > 1 +  I Sens ( I max > I e )
  I e 
Where:
I d is the neutral point transverse differential current;
I Sens is the current setting of sensitive neutral point transverse differential element;
I e is the generator rated current;
K hczd is an internal fixed coefficient.
3.3.3.3 Insensitive Neutral Point Transverse Differential Element
Insensitive neutral point transverse differential element without any blocking element can reflect
generator internal serious fault, once the transverse differential current is larger than the current
setting of high setting neutral point transverse differential element, the protection will operate
immediately to cut off the fault.
The operation equation of sensitive neutral point transverse differential element is:
I d > I Insense
Equation 3.3-2
Where:
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3 Operation Theory
I Insens is the current setting of insensitive neutral point transverse differential element.
3.3.4 Logic
For generator neutral point transverse differential protection, if following three conditions are met,
the protection will be enabled.
(1) Logic setting [87NTG.En] is set as “1”.
(2) Protection function enabling inputs [87NTG.En1], [87NTG.En2] are “1”
(3) Protection function blocking input [87NTG.Blk] is “0”.
If generator neutral point transverse differential protection is disabled, all the related output signals
will be reset. If no external input is configured to [87NTG.En1] ([87NTG.En2]), the default initial
value of [87NTG.En1] ([87NTG.En2]) is “1”; if no external input is configured to [87NTG.Blk], the
default initial value of [87NTG.Blk] is “0”.
SIG [87NTG.En1] &

SIG [87NTG.En2]
SIG [87NTG.Blk]
&
SIG Id>[87NTG.I_L] [87NTG.St]
&
En 87NTG.En_L ≥1
En 87NTG.En_H
EN [87NTG.En]
&
SIG [87NTG.En1]
SIG [87NTG.En2]
SIG [87NTG.Blk]
&
EN [87NTG.En_L] &
SIG Flg_I_L
>
& [87NTG.t_Op_L] 0s &
[87NTG.Op_L]
SIG [BI_1PEF_Rot]
0ms 500ms
SIG 87NTG.FD_L
EN [87NTG.En]
&
SIG [87NTG.En1]
SIG [87NTG.En2]
SIG [87NTG.Blk]
&
EN [87NTG.En_H] &
SIG Flg_I_H [87NTG.Op_H]
0ms 500ms
SIG 87NTG.FD_H
Figure 3.3-2 Logic diagram of generator neutral point transverse differential protection
Where:
I d is the neutral point transverse differential current.
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3 Operation Theory
Flg_I_L is the internal signal indicating that the operation equation of sensitive neutral point
transverse differential element is met;
BI_1PEF_Rot is the generator rotor one-point ground binary input;
87NTG.FD_L is the internal signal indicating that the sensitive neutral point transverse differential
element picks up (the fault detector of fault detector DSP module);
Flg_I_H is the internal signal indicating that the operation equation of insensitive neutral point
transverse differential element is met;
87NTG.FD_H is the internal signal indicating that the insensitive neutral point transverse
87NTG
87NTG.I1P_Hm 87NTG.St
87NTG.U3P 87NTG.Op_L
87NTG.I3P 87NTG.Op_H
87NTG.En1
87NTG.En2
87NTG.Blk
BI_1PEF_Rot
Figure 3.3-3 Function block diagram of generator neutral point transverse differential protection
Table 3.3-1 Input signals of generator neutral point transverse differential protection

1 87NTG.I1P_Hm Neutral point transverse differential current input.
2 87NTG.U3P Generator terminal three-phase voltage input.
3 87NTG.I3P Generator terminal three-phase current input.
4 87NTG.En1 Protection function enabling input1 and input 2, it can be binary inputs or settings,
5 87NTG.En2 such as function enabling binary inputs, logic links, etc.
6 87NTG.Blk Protection function blocking input, such as function blocking binary input.
7 BI_1PEF_Rot The generator rotor one-point ground binary input.

1 87NTG.St Generator neutral point transverse differential protection starts.
2 87NTG.Op_L The sensitive neutral point transverse differential element operates to trip.
3 87NTG.Op_H The insensitive neutral point transverse differential element operates to trip.
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3 Operation Theory
Table 3.3-3 Output signals of generator neutral point transverse differential protection (event recorder)
Tripping reports
1 87NTG.Op_L The sensitive neutral point transverse differential element operates to trip.
2 87NTG.Op_H The insensitive neutral point transverse differential element operates to trip.
Start signals
3 87NTG.St Generator neutral point transverse differential protection starts.
Waveform recording
Generator neutral point transverse differential protection operates to trigger

4 87NTG.TrigDFR
waveform recording.
Table 3.3-4 Output signals of generator neutral point transverse differential protection (measurements)
1 87NTG.I_Hm1 The fundamental component of neutral point transverse differential current. A

rd
2 87NTG.I_Hm3 The 3 harmonic of neutral point transverse differential current. A
Access path:
4 87NTG.I_Hm3 The 3rd harmonic of neutral point transverse differential current. A
The current threshold for sensitive neutral point transverse differential

5 87NTG.I_Th_L A
element.
Access path:
Main menu -> Measurements -> Measurements2-> Prot Values-> Gen IntTurn Prot Values
3.3.6 Settings
Table 3.3-5 Settings list of generator neutral point transverse differential protection

1 87NTG.En 1
1: enable neutral point transverse differential protection.
Current setting of sensitive neutral point
2 87NTG.I_L 0.10~50.00 0.01 A
transverse differential element.
Current setting of insensitive neutral point
3 87NTG.I_H 0.10~50.00 0.01 A
Time delay setting of sensitive neutral point
4 87NTG.t_Op_L 0.00~30.00 0.01 s
Tripping logic setting of generator neutral point
5 87NTG.OutMap 0~3FFFFFFF
transverse differential protection.
6 87NTG.En_L 0: disable 1 Logic setting of enabling/disabling sensitive
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3 Operation Theory
1: enable neutral point transverse differential element.

0: disable Logic setting of enabling/disabling insensitive
7 87NTG.En_H 1
1: enable neutral point transverse differential element.
Access path: Settings-> Prot Settings -> Gen NPTrvDiff Settings
3.4 Generator Inter-Turn Protection (59NIT)
3.4.1 Application
Generator inter-turn protection is used to detect the inter-turn fault of generator stator winding. If
an inter-turn fault happens at generator stator winding, relatively large circulating current flows
among the short-circuit turns, so the generator stator winding and iron core will be damaged.
Conventional generator differential protection can not detect the inter-turn fault of generator stator
winding, so a dedicated inter-turn protection should be configured.

3.4.3.1 Overview
Generator inter-turn protection includes two operation elements: longitudinal zero-sequence

voltage inter-turn element and negative-sequence DPFC direction inter-turn element.
After filtering, if the broken-delta zero-sequence voltage of the dedicated VT is larger than the
voltage setting of longitudinal zero-sequence voltage inter-turn element, longitudinal
zero-sequence voltage inter-turn element will operate. Negative-sequence DPFC direction
inter-turn element adopts generator terminal voltage and current directly, so dedicated VT is not
needed for it. If the negative-sequence voltage variation, the negative-sequence current variation
and the negative-sequence power direction conditions are all met, Negative-sequence DPFC
direction inter-turn element will operate.
3.4.3.2 Longitudinal Zero-sequence Voltage Inter-turn Element
Longitudinal zero-sequence voltage inter-turn element adopts the broken-delta zero-sequence

voltage of the generator terminal dedicated VT, the neutral point of the primary side of the
dedicated VT should not be grounded and it is connected with the neutral point of generator stator
winding via HV cable. The typical wiring of longitudinal zero-sequence voltage inter-turn element is
shown as below. If an inter-turn fault happens at generator stator winding, corresponding
broken-delta zero-sequence voltage will be output from the dedicated VT, it can be used to detect
the inter-turn fault of generator stator winding.
During normal operation, there will be a relatively large third harmonic zero- sequence voltage on
the broken-delta of the dedicated VT, it will affect the sensitivity of the protection. PCS-985 adopts
frequency tracking, digital filtering and full cycle Fourier algorithm, so the filtered ratio of the
zero-sequence voltage relative to the 3rd harmonic is larger than 100, and the protection only
reflects the fundamental component.
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3 Operation Theory
If a generator external asymmetric short-circuit fault happens, a considerable amount of zero-

sequence voltage will be generated on the broken-delta of the dedicated VT, then
negative-sequence power direction element can be used to judge whether it is an external fault.
Longitudinal zero-sequence voltage inter-turn element should be blocked for external fault, and it
should be released only when an internal inter-turn fault happens.
The voltage setting of longitudinal zero-sequence voltage inter-turn element only should be larger
than the maximum unbalance voltage during normal operation, so it can improve the sensitivity of
the element.
For the increase of longitudinal unbalance zero-sequence voltage for other normal operation
conditions, a floating threshold is adopted for longitudinal zero-sequence voltage inter-turn
element.
Generator longitudinal zero-sequence voltage inter-turn element will operate with a short time
delay (0.10s~0.20s).
Generator Main transformer

Neutral
point
Filtering 3rd harmonic
Calculate fundamental zero

sequence voltage amplitude
PCS-985
Figure 3.4-1 Calculation process of longitudinal zero-sequence voltage inter-turn element
3.4.3.3 VT2 Primary Circuit Failure Alarm and Blocking
Longitudinal zero-sequence voltage inter-turn element should be blocked when VT2 (i.e.
generator terminal dedicated VT) primary circuit failure happens.
(1) If there have two groups of three-phase voltage transformers, the voltage balance function is
in service. The operation criterion is as below.
Criterion 1:
Negative-sequence voltage of VT1: 3U2<U2_set1 or negative-sequence voltage of VT2:

3U2′<U2_set2, and broken-delta zero-sequence voltage of VT2: 3U0′>U0set (zero-sequence voltage
setting)
Criterion 2:
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3 Operation Theory
U AB − U ab > 5V or U BC − U bc > 5V or U CA − U ca > 5V , and broken-delta zero-sequence
voltage of VT2: 3U0′>U0set (zero-sequence voltage setting).
Where:
U AB , U BC , U CA are phase-to-phase voltages of VT1
U ab , U bc , U ca are phase-to-phase voltages of VT2
When any of criterion 1 and criterion 2 operates, VT2 primary circuit failure alarm will be issued
with a time delay of 40ms and longitudinal zero-sequence voltage inter-turn element will be
blocked.
(2) If there only has one group of three-phase voltage transformer, the voltage balance function is
not in service. The operation criterion is as below.
Criterion:
Negative-sequence voltage of VT1: 3U2<U2_set1 and broken-delta zero-sequence voltage of VT2:

3U0′>U0set (zero-sequence voltage setting)
When the criterion operates, VT2 primary circuit failure alarm will be issued with a time delay of
40ms and longitudinal zero-sequence voltage inter-turn element will be blocked.
After VT2 circuit restores to normal condition, the blocking for zero-sequence voltage inter-turn
element can be released by pressing the reset button.
3.4.3.4 Negative-sequence DPFC Direction Inter-turn Element
The operation criterion is:
 ∧

ΔF＝ Re ΔU 2 × Δ I 2 × e jΦ  > ε + 1.25 × dF
 
Equation 3.4-1
∆U 2 > 0.5V + 1.25du
∆I 2 > 0.02In + 1.25di
If the above three criterions are met simultaneity, the direction condition is met. Be broadened by
negative-sequence voltage and negative-sequence current, the negative-sequence DPFC
direction inter-turn element operates with a time delay of 0.2~0.5s.
Negative-sequence DPFC direction inter-turn element adopts generator terminal voltage and
current directly, so dedicated VT is not needed for it. If generator terminal VT1 circuit failure
happens, negative-sequence DPFC direction inter-turn element will be blocked. All the settings for
negative-sequence DPFC direction inter-turn element have been set in the device, users need not
to set them.
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3 Operation Theory
Negative-sequence DPFC direction inter-turn element can not reflect the inter-turn fault before the
generator is connected into the power system.
Negative-sequence DPFC direction inter-turn element can operate to alarm or trip.
3.4.4 Logic
For generator inter-turn protection, if following three conditions are met, the protection will be
enabled.
(1) Logic setting [59NIT.En] is set as “1”.
(2) Protection function enabling inputs [59NIT.En1], [59NIT.En2] are “1”.
(3) Protection function blocking input [59NIT.Blk] is “0”.
If generator inter-turn protection is disabled, all the related output signals will be reset. If no
external input is configured to [59NIT.En1] ([59NIT.En2]), the default initial value of [59NIT.En1]
([59NIT.En2]) is “1”; if no external input is configured to [59NIT.Blk], the default initial value of
[59NIT.Blk] is “0”.
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3 Operation Theory
SIG [59NIT.En1] &

SIG [59NIT.En2]
SIG [59NIT.Blk]
En [59NIT.En_ROV_Longl] & &

[59NIT.St]
SIG Flg_ROV_Longl
En [59NIT.En_P2_DPFC] ≥1
&
SIG 59NIT.Dir_P2_DPFC
EN [59NIT.OutMap].bit0
EN [59NIT.En]
SIG [59NIT.En1] &
SIG [59NIT.En2] & [59NIT.t_Op] 0ms [59NIT.Op_ROV_Longl]

SIG [59NIT.Blk]
SIG Flg_ROV_Longl &
EN [59NIT.En_ROV_Longl]
SIG 59NIT.Dir_P2_DPFC
SIG G_Term.VT2.VTS_Pri.Blk]
0ms 500ms
SIG 59NIT.FD_ROV_Longl
EN [59NIT.OutMap].bit0
EN [59NIT.En]
SIG [59NIT.En1] &
SIG [59NIT.En2] &
[59NIT.t_Op] 0ms [59NIT.Op_P2_DPFC]
SIG [59NIT.Blk]
SIG 59NIT.Dir_P2_DPFC &
EN [59NIT.En_P2_DPFC]
SIG G_Term.VT1.Alm_VTS]
0ms 500ms
SIG 59NIT.FD_P2_DPFC
EN [59NIT.OutMap].bit0 &
EN [59NIT.En] &
[59NIT.t_Op] 0ms
SIG [59NIT.Blk] [59NIT.Alm_P2_DPFC]
SIG 59NIT.Dir_P2_DPFC &
EN [59NIT.En_P2_DPFC]
SIG G_Term.VT1.Alm_VTS]
Figure 3.4-2 Logic diagram of generator inter-turn protection
Where:
Flg_ROV_Longl is the internal signal indicating that the zero-sequence voltage condition for
longitudinal zero-sequence voltage inter-turn element is met.
59NIT.Dir_P2_DPFC is the internal signal indicating that the negative-sequence power direction
condition is met.
59NIT.FD_ROV_Longl is the internal signal indicating that the longitudinal zero-sequence voltage
inter-turn element picks up (the fault detector of fault detector DSP module).
59NIT.FD_P2_DPFC is the internal signal indicating that the negative-sequence DPFC direction
Date: 2016-08-16
3 Operation Theory
inter-turn element picks up (the fault detector of fault detector DSP module).
59NIT
59NIT.U1P_Hm 59NIT.St
59NIT.U3P 59NIT.Op_ROV_Longl
59NIT.I3P 59NIT.Op_P2_DPFC
59NIT.En1 59NIT.Alm_P2_DPFC
59NIT.En2
59NIT.Blk
G_Term.VT2.VTS_Pri.Blk
Figure 3.4-3 Function block diagram of generator inter-turn protection
Table 3.4-1 Input signals of generator inter-turn protection

1 59NIT.U1P_Hm Longitudinal zero-sequence voltage input.
Three-phase current input 1, it is configured as generator terminal current by
2 59NIT.I3P
default, and it can be changed by PCS-Explorer2.
Three-phase voltage input 1, it is configured as generator terminal VT1 voltage
3 59NIT.U3P
by default, and it can be changed by PCS-Explorer2.
4 59NIT.En1 Protection function enabling input1 and input 2, it can be binary inputs or
5 59NIT.En2 settings, such as function enabling binary inputs, logic links, etc.
6 59NIT.Blk Protection function blocking input, such as function blocking binary input.
Generator inter-turn protection dedicated VT (VT2) primary circuit failure
7 G_Term.VT2.VTS_Pri.Blk
blocking input
Table 3.4-2 Output signals of generator inter-turn protection

1 59NIT.St Generator inter-turn protection starts.
2 59NIT.Op_ROV_Longl Longitudinal zero-sequence voltage inter-turn element operates to trip.
3 59NIT.Op_P2_DPFC Negative-sequence DPFC direction inter-turn element operates to trip.
4 59NIT.Alm_P2_DPFC Negative-sequence DPFC direction inter-turn element to issue alarm signal.
Table 3.4-3 Output signals of generator inter-turn protection (event recorder)
Tripping reports
1 59NIT.Op_ROV_Longl Longitudinal zero-sequence voltage inter-turn element operates to trip.
2 59NIT.Op_P2_DPFC Negative-sequence DPFC direction inter-turn element operates to trip.
Start signals
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3 Operation Theory
3 59NIT.St Generator inter-turn protection starts.
Alarm signals
4 59NIT.Alm_P2_DPFC Negative-sequence DPFC direction inter-turn element to issue alarm signal.
Waveform recording
5 59NIT.TrigDFR Generator inter-turn protection operates to trigger waveform recording.
6 59NIT.St_ROV_Longl Longitudinal zero-sequence voltage inter-turn element starts.
7 59NIT.St_P2_DPFC Negative-sequence DPFC direction inter-turn element starts.
Table 3.4-4 Output signals of generator inter-turn protection (measurements)
The fundamental residual voltage amplitude of VT2 of generator

1 G_Term.VT2.3U0_Hm1 V
terminal
The 3rd harmonic residual voltage amplitude of VT2 of generator V

2 G_Term.VT2.3U0_Hm3
terminal
The internal signal indicating that the negative-sequence power

3 59NIT.Dir_P2_DPFC
direction condition is met
Access path:
Main menu -> Measurements -> Measurements2-> Prot Values-> Gen IntTurn Prot Values
3.4.6 Settings
Table 3.4-5 Settings list of generator inter-turn protection

0: disable Logic setting of enabling/disabling
1 59NIT.En 1
1: enable generator inter-turn protection.
Residual voltage setting for longitudinal
2 59NIT.3U0_ROV_Longl 1~10 0.01 V zero-sequence voltage inter-turn
element
Time delay setting of generator
3 59NIT.t_Op 0.10~30 0.01 s
inter-turn protection.
Tripping logic setting of generator
4 59NIT.OutMap 0~3FFFFFFF
inter-turn protection.
Logic setting of enabling/disabling
0: disable
5 59NIT.En_ROV_Longl 1 longitudinal zero-sequence voltage
1: enable
inter-turn element
0: disable
6 59NIT.En_P2_DPFC 1 negative-sequence DPFC direction
1: enable
inter-turn element
7 G_Term.VT2.En_Alm_VTS_Delt 0: disable 1 Logic setting of enabling/disabling VT2
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3 Operation Theory
1: enable broken-delta circuit failure alarm

function
Access path: Settings-> Prot Settings -> Gen IntTurn Settings
3.5 Generator Stator Overload Protection (49S)
3.5.1 Application
Generator stator overload protection is equipped to reflect the average heating condition of
generator stator winding.
 Stator definite-time overload protection.
 Stator inverse-time overload protection.

Generator stator overload protection comprises definite-time overload protection and inverse-time
overload protection. The low-setting stage of definite-time overload protection is used for alarm
and the high-setting stage of definite-time overload protection is used for tripping. Inverse-time
overload protection can simulate the heat accumulation process of the stator winding.
3.5.3.1 Stator Overload Protection Calculation Process
The temperature change of generator stator winding is mainly caused by copper loss. The copper
loss is proportional to the square of current, so there is a certain proportional relationship between
the temperature change of generator stator winding and the square of current. Via checking the
change of generator stator current can reflect the temperature change of stator winding indirectly.
For a given temperature increase (Δθ), the corresponding expression between permissive time (t)
and current can be got:
A
t=
(I )
∗ 2
−1
Equation 3.5-1
Where:
A is the heat capacity for the generator stator winding.
I ∗ is the per-unit value of stator current (the rated stator current is taken as the referenced value).
Generally the overload multiple and the corresponding duration of the generator is provided. For
example, a directly cooled turbo-generator, the permissive duration is 60s corresponds to 1.3
times of rated current, the heat capacity of the generator stator winding A can be calculated
according to Equation 3.5-1, then the permissive duration corresponds to a given current can be
calculated.
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3 Operation Theory
3.5.3.2 Generator Stator Definite-time Overload Protection
There are two stages of stator definite-time overload protection. The low-setting stage of
definite-time overload protection is used for alarm, and the settings should be set to make the
protection can drop off reliably for long-term permissive load current. The high-setting stage of
definite-time overload protection is used for tripping, and the settings should be set according to
the permissive time for more serious overload condition.
3.5.3.3 Generator Stator Inverse-time Overload Protection
Inverse-time stator overload protection consists of three parts: lower-limit initiation part,
inverse-time part and upper limit definite-time part. Minimum operation time delay setting
[49S.IDMT.tmin] is provided for upper limit definite-time part.
When the stator current is over the low setting [49S.IDMT.I_Set], the heat accumulation starts.
When the heat accumulation reaches its setting [49S.IDMT.A_Therm], inverse-time stator
overload protection can operate to trip. The inverse time protection can simulate the heat
accumulation and dissipation process of the generator. If the stator current is larger than the low
setting [49S.IDMT.I_Set], the heat accumulation starts; if the stator current is lower than the low
setting [49S.IDMT.I_Set], the heat dissipation starts.
The operation characteristic of inverse-time stator overload protection is as follows:
I
IU pper−limit
I P ickup
t min tmax t
Figure 3.5-1 Operation characteristic of inverse-time stator overload protection
Where:
t min is the minimum time delay for upper limit definite-time part, i.e. the setting [49S.IDMT.tmin].
t max is maximum time delay for lower-limit initiation part
I Pickup is the pickup current setting of inverse-time stator overload protection, i.e. the setting
[49S.IDMT.I_Set]
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3 Operation Theory
I Upper −lim it is the current that corresponds to the minimum time delay for upper limit definite-time
part.
Its operation criterion is:
[( I I b） − (k Disspt ) ] × t ≥ ATherm
2 2
Equation 3.5-2
Where:
I is the stator current.
k Disspt is the heat dissipation coefficient of the generator, i.e. the setting [49S.IDMT.K_Disspt]. In
order to make sure that the heat accumulation can be dissipated after an external fault, the heat
dissipation coefficient of the generator is recommended to be set as “1.02~1.05”.
I b is the secondary rated current of generator.
ATherm is the heat capacity of generator stator winding, i.e. the setting [49S.IDMT.A_Therm].
3.5.4 Logic
For each stage of generator stator overload protection, if following three conditions are met, the
protection will be enabled.
(1) Logic setting [49S.En] is set as “1”.
(2) Protection function enabling inputs [49S.En1], [49S.En2] are “1”
(3) Protection function blocking input [49S.Blk] is “0”.
If generator stator overload protection is disabled, all the related output signals will be reset. If no
external input is configured to [49S.En1] ([49S.En2]), the default initial value of [49S.En1]
([49S.En2]) is “1”; if no external input is configured to [49S.Blk], the default initial value of [49S.Blk]
is “0”.
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3 Operation Theory
SIG [49S.En1] &

SIG [49S.En2]
SIG [49S.Blk]
En [49S.DT.OutMap].bit0 & &

[49S.St]
SIG I>[49S.DT.I_Set]
En [49S.IDMT.OutMap].bit0 ≥1
&
SIG I>[49S.IDMT.I_Set]
SIG I>[49S.I_Alm] &

[49S.t_Alm] 0ms [49S.Alm]
EN [49S.En]
SIG [49S.Blk]
EN [49S.En]
SIG [49S.En1] &
& [49S.DT.t_Op] 0ms
SIG [49S.En2] [49S.DT.Op]
SIG [49S.Blk]
SIG I>[49S.DT.I_Set]
0ms 500ms
SIG 49S.DT.FD
EN [49S.En]
SIG [49S.En1] &
SIG [49S.En2] &
IDMT
[49S.IDMT.Op]
SIG [49S.Blk]
SIG I>[49S.IDMT.I_Set]
0ms 500ms
SIG 49S.IDMT.FD
Figure 3.5-2 Logic diagram of generator stator overload protection
Where:
49S.DT.FD is the internal signal indicating that the stator definite-time overload protection picks up
49S.IDMT.FD is the internal signal indicating that the stator inverse-time overload protection picks
up (the fault detector of fault detector DSP module).
49S
49S.I3P1 49S.St
49S.I3P2 49S.DT.Op
49S.En1 49S.IDMT.Op
49S.En2 49S.Alm
49S.Blk
Figure 3.5-3 Function block diagram of generator stator overload protection
Table 3.5-1 Input signals of generator stator overload protection

1 49S.I3P1 Three-phase current input 1, it is configured as generator terminal current by default,
Date: 2016-08-16
3 Operation Theory

and it can be changed by PCS-Explorer2.
Three-phase current input 2, it is configured as generator neutral point side current by
2 49S.I3P2
3 49S.En1 Protection function enabling input1 and input 2, it can be binary inputs or settings,
4 49S.En2 such as function enabling binary inputs, logic links, etc.
5 49S.Blk Protection function blocking input, such as function blocking binary input.
Table 3.5-2 Output signals of generator stator overload protection

1 49S.St Tripping stage of stator overload protection starts.
2 49S.DT.Op Definite-time stator overload protection operates to trip.
3 49S.IDMT.Op Inverse-time stator overload protection operates to trip.
4 49S.Alm The alarm stage of stator overload protection operates to issue alarm signal
Table 3.5-3 Output signals of generator stator overload protection (event recorder)
Tripping reports
1 49S.DT.Op Definite-time stator overload protection operates to trip.
2 49S.IDMT.Op Inverse-time stator overload protection operates to trip.
Start signals
3 49S.St Tripping stage of stator overload protection starts.
Alarm signals
4 49S.Alm The alarm stage of stator overload protection operates to issue alarm signal
Waveform recording
5 49S.TrigDFR Tripping stage of stator overload protection operates to trigger waveform recording.
6 49S.DT.St Tripping stage of definite-time stator overload protection starts.
7 49S.IDMT.St Tripping stage of inverse-time stator overload protection starts.
Table 3.5-4 Output signals of generator stator overload protection (measurements)
1 49S.IDMT.ThermAccu Overload heat accumulation of stator %
Access path:
Main menu -> Measurements -> Measurements1-> Gen Values-> Gen Misc Values
Date: 2016-08-16
3 Operation Theory
3.5.6 Settings
Table 3.5-5 Settings list of generator stator overload protection

0: disable Logic setting of enabling/disabling stator
1 49S.En
1: enable overload protection.
Current setting of the tripping stage of

2 49S.DT.I_Set 0.10~20In 0.01 A
definite-time stator overload protection.
Time delay setting of the tripping stage of
3 49S.DT.t_Op 0.00~30.00 0.01 s
Tripping logic setting of definite-time stator
4 49S.DT.OutMap 0~3FFFFFFF
overload protection.
Current setting of the alarm stage of
5 49S.I_Alm 0.10~20In 0.01 A
Time delay setting of the alarm stage of
6 49S.t_Alm 0.00~30.00 0.01 s
Pickup current setting of inverse-time stator
7 49S.IDMT.I_Set 0.10~20In 0.01 A
The minimum time delay for upper limit
8 49S.IDMT.tmin 0.10~10.00 0.01 s definite-time part of inverse-time stator
The heat capacity of stator for inverse-time
9 49S.IDMT.A_Therm 1.00~320.00 0.01 s
stator overload protection.
The heat dissipation coefficient of the
10 49S.IDMT.K_Disspt 1.02~2.00 0.01 s generator for inverse-time stator overload
protection.
Tripping logic setting of inverse-time stator
11 49S.IDMT.OutMap 0~3FFFFFFF
Stator overload protection current source
selection.
0: Source1
12 49S.Opt_Source_I 0: Source1 (three-phase current input 1)
1: BothSources
1: BothSources (three-phase current input 1
and 2)
Access path: Settings-> Prot Settings -> Gen StaOvLd Settings
3.6 Generator Fundamental Zero-sequence Stator Ground Fault
Protection (64S1)
3.6.1 Application
Generator stator ground fault protection is used to detect the ground fault of generator stator
winding, it can be realized by detecting the displacement voltage of secondary side of neutral point
Date: 2016-08-16
3 Operation Theory
grounding VT or grounding transformer or by detecting the broken-delta zero-sequence voltage of

generator terminal VT or the secondary voltage of generator terminal grounding transformer. It
also can be realized by detecting the zero sequence current of the stator of generator.
Fundamental zero-sequence voltage stator ground fault protection can detect the ground fault of
85%~95% of stator winding of generator terminal side.
Fundamental zero-sequence current stator ground fault protection can detect the ground fault of

3.6.3.1 Overview
Generator fundamental zero-sequence voltage stator ground fault protection includes two
operation elements: sensitive fundamental zero-sequence voltage stator ground fault element and
conventional fundamental zero-sequence voltage stator ground fault element.
Generator fundamental zero-sequence current stator ground fault protection includes one
operation element: fundamental zero-sequence current stator ground fault element.
3.6.3.2 Calculation Process of Fundamental Zero-sequence Voltage Stator Ground Fault

Protection
The calculation process of fundamental zero-sequence voltage stator ground fault protection is
shown in following figure. The generator neutral point is grounded via grounding transformer, it
can also be grounded via grounding VT. For the secondary side rated voltage of neutral point
grounding transformer is usually higher, so the tap voltage (generally it is 100V or 173V) of the
secondary winding load resistance is connected to the device. The generator system parameter
[G_NP.U1n] should be set according to the primary side voltage of the grounding transformer, and
[G_NP.U2n_Delt] should be set according to the actual tap voltage.
Date: 2016-08-16
3 Operation Theory
Generator CM
CT2
*
CT1
RB Main
CG Cl CTr transformer
UN0 In0.Roc IT0.Dir UT0 UH0
Filtering
Calculate the fundamental zero-sequence voltage amplitude
PCS-985
Figure 3.6-1 Calculation process of fundamental zero-sequence stator ground fault protection
Where:
RB is the secondary load resistance of neutral point grounding transformer;
UN0 is the tap voltage (it is 100V or 173V generally) of secondary load resistance of neutral point
grounding transformer;
UT0 is the broken-delta zero-sequence voltage of generator terminal VT;
UH0 is the broken-delta zero-sequence voltage of main transformer HV side VT;
CT1 is the current transformer of neutral point of generator and for zero sequence current ground
fault protection;
CT2 is the current transformer of generator terminal for zero sequence directional element;
CG is the generator stator winding ground capacitance;
Cl is the ground capacitance of the outgoing line of generator terminal;
CTr is the main transformer ground capacitance;
CM is the coupling capacitance between the HV winding and LV winding of main transformer.
3.6.3.3 Fundamental Zero-sequence Voltage Stator Ground Fault Protection
When a stator ground fault happens, the displacement voltage of neutral point and generator
terminal contains a relatively large 3rd harmonic voltage, which will affect the sensitivity of the
protection. The device adopts frequency tracking, digital filtering and full cycle Fourier algorithm,
so the filtered ratio of the zero-sequence voltage relative to the 3rd harmonic is larger than 100, and
the protection only reflects the fundamental component.
The zero sequence voltage can be selected from the generator terminal or one side of the neutral
point through the setting [64S1.Opt_Source_3U0]. If the setting [64S1.Opt_Source_3U0] is set as
Date: 2016-08-16
3 Operation Theory
“Source1”, the No.1 zero sequence voltage input is from the generator terminal or the neutral point,
and the No.2 zero sequence voltage input is not used. If the setting [64S1.Opt_Source_3U0] is set
as “BothSources”, the No.1 zero sequence voltage input is from the neutral point, and the No.2
zero sequence voltage input is from the generator terminal. It can be configured through
PCS-Explorer2.
3.6.3.3.1 Sensitive Stage
If sensitive stage of fundamental zero-sequence voltage stator ground fault protection operates to
issue alarm signal, the operation criterion is:
3U 0 > U 0Set_Sen Equation 3.6-1
Where:
3U 0 is fundamental zero-sequence voltage of the No.1 zero sequence voltage input;
U 0Set_Sen is voltage setting of sensitive stage of fundamental zero-sequence voltage stator ground
fault protection.
If the sensitive stage operates to trip, in order to prevent the sensitive stage of fundamental
zero-sequence voltage stator ground fault protection from undesired tripping due to external fault,
it can be blocked by main transformer HV side zero-sequence voltage, and the zero-sequence
voltage blocking setting [64S1.3U0_Tr_Blk] is settable. If the No.2 zero sequence voltage input is
not used and the setting [64S1.3U0_Tr_Blk] is set as non-zero value, this function is in service
automatically.
If the setting [64S1.Opt_Source_3U0] is set as “BothSources” and the sensitive stage operates to
trip, it will be blocked by broken-delta zero-sequence voltage of generator terminal, the
zero-sequence voltage blocking setting need not to be set, it can be converted automatically by
the device according to the VT ratio of generator terminal and neutral point. The calculation result
of the ratio of VT of generator terminal and neutral point is described as generator zero-sequence
voltage correlation coefficient [K_Delt&NP_VT_Gen].
Generator terminal zero-sequence voltage can adopts broken-delta zero-sequence voltage of VT1
or calculated zero-sequence voltage of VT1.
3.6.3.3.2 Insensitive Stage
Insensitive stage of fundamental zero-sequence voltage stator ground fault protection only take
the zero sequence voltage of No.1 zero sequence voltage input as the operation quantity, the
operation criterion is:
3U 0 > U 0Set_Insen Equation 3.6-2
Where:
3U 0 is fundamental zero-sequence voltage of the No.1 zero sequence voltage input;
Date: 2016-08-16
3 Operation Theory
U 0Set_Insen is voltage setting of insensitive stage of fundamental zero-sequence voltage stator
ground fault protection.
The insensitive stage can be set to trip independently.
3.6.3.3.3 Zero-sequence Current Blocking Element
If a single-phase ground fault of the stator of generator is occurred, and the zero sequence current
of ground fault can be detected, the zero sequence voltage stator ground fault protection can be
blocked by the zero sequence.
The settings [64S1.ROC_Ctrl_ROV_L] and [64S1.ROC_Ctrl_ROV_H] are used to enable or

disable the zero-sequence current blocking element for the sensitive stage and insensitive stage
respectively.
3.6.3.3.4 Zero-sequence Directional Element
The zero sequence directional element is calculated through the zero sequence current and the
zero sequence voltage of generator terminal.
The settings [64S1.Dir_Ctrl_ROV_L] and [64S1.Dir_Ctrl_ROV_H] are used to enable or disable

the zero-sequence directional element for the sensitive stage and insensitive stage respectively.
The 3U0 should be greater than 2V and the 3I0 should be greater than the setting
[64S1.3I0_Th_Dir].
The characteristic of the zero sequence directional element is shown as below.
3I0
phi_Reach
3U0
Figure 3.6-2 Characteristic of the zero sequence directional element
3.6.3.4 Fundamental Zero-sequence Current Stator Ground Fault Protection
Fundamental zero-sequence current stator ground fault protection can detect the ground fault of
3I0 >3I0_Set Equation 3.6-3
Date: 2016-08-16
3 Operation Theory
Where:
3I0 is fundamental zero-sequence current of generator;
3I0_Set is current setting of fundamental zero-sequence current stator ground fault protection.
3.6.3.5 Generator Neutral Point VT or Generator Terminal Broken-delta VT Circuit Failure

Alarm
For fundamental zero-sequence voltage stator ground fault protection adopts the generator neutral
point zero-sequence voltage and generator terminal broken-delta zero-sequence voltage, VT
circuit failure of corresponding VT will lead to miss-operation of the protection. So alarm signal
should be issued if generator neutral point VT or generator terminal broken-delta VT circuit fails.
The operation criteria for generator neutral point VT circuit failure are:
1) Positive-sequence voltage of generator terminal secondary winding is larger than 0.8Un
2) 3rd harmonic zero-sequence voltage of generator neutral point VT is less than 0.1V
The operation criteria for generator terminal broken-delta VT circuit failure are:
1) Positive-sequence voltage of generator terminal secondary winding is larger than 0.8Un
2) 3rd harmonic zero-sequence voltage of generator terminal broken-delta VT is less than 0.1V
If the operation criteria are met, the corresponding VT circuit failure alarm signal will be issued with
a time delay of 10s, and the signal can be reset automatically with a time delay of 10s if the
abnormality disappears.
If generator terminal zero-sequence voltage is derived from the calculated zero-sequence voltage,
the device will not detect generator terminal VT1 broken-delta circuit failure.
Generator neutral point VT or generator terminal broken-delta VT circuit failure alarm function can
be enabled or disabled by respective logic setting.
3.6.3.6 VT Circuit Failure at Generator Terminal Blocking Zero Sequence Voltage Protection
of Stator
If the setting [64S1.Opt_Source_3U0] is set as “Source1” and the zero sequence voltage is from
the zero sequence voltage of the generator terminal, the VT circuit failure of the generator terminal
maybe cause the mal-operation of the zero sequence voltage protection of stator. So, it is
necessary to block the zero sequence voltage protection of stator when the VT circuit failure of
generator terminal is occurred.
Criterion:
Negative-sequence voltage of VT1: 3U2>U0zd and zero-sequence voltage of VT1: 3U0>U0zd

(zero-sequence fundamental voltage setting of the sensitive stage)
If above two conditions are satisfied, the VT1 circuit failure alarm signal is issued with a short time
delay, and the sensitive and insensitive stages of fundamental zero sequence voltage protection
will be blocked.
Date: 2016-08-16
3 Operation Theory
3.6.4 Logic
For fundamental zero-sequence voltage stator ground fault protection, if following three conditions
are met, the protection will be enabled.
(1) Logic setting [64S1.En] is set as “1”.
(2) Protection function enabling inputs [64S1.En1], [64S1.En2] are “1”.
(3) Protection function blocking input [64S1.Blk] is “0”.
If fundamental zero-sequence voltage stator ground fault protection is disabled, all the related
output signals will be reset. If no external input is configured to [64S1.En1] ([64S1.En2]), the
default initial value of [64S1.En1] ([64S1.En2]) is “1”; if no external input is configured to [64S1.Blk],
the default initial value of [64S1.Blk] is “0”.
Date: 2016-08-16
3 Operation Theory
SIG [64S1.En1] &

SIG [64S1.En2]
SIG [64S1.Blk]
&
SIG 3U0>[64S1.3U0_L] [64S1.St]
En &
[64S1.En_Trp_ROV_L] ≥1
≥1
En [64S1.En_Trp_ROV_H]
SIG 3I0>[64S1.3I0_Set] &
En [64S1.En_Trp_ROC]
Flg_ROV
EN [64S1.En] &
SIG 3U0>[64S1.3U0_L]
&
SIG [64S1.Blk] [64S1.t_ROV_L] 0ms [64S1.Alm_ROV_L]
EN [64S1.En_Alm_ROV_L]
EN [64S1.En
SIG [64S1.En1] &
SIG [64S1.En2]
SIG [64S1.Blk]
SIG Flg_ROV &

&
EN [64S1.En_Trp_ROV_L]
SIG Flg_ROV_Term ≥1 & [64S1.t_ROV_L] 0ms [64S1.Op_ROV_L]
EN [64S1.Opt_Source_3U0]
SIG Flg_Dir ≥1
EN [64S1.Dir_Ctrl_ROV_L]
SIG 3I0>[64S1.3I0_Set] ≥1
EN [64S1.ROC_Ctrl_ROV_L]
SIG 3Uh0>[64S1.3U0_Tr_Blk]
SIG 0ms 500ms

64S1.FD
EN [64S1.En
SIG [64S1.En1] &
SIG [64S1.En2]
SIG [64S1.Blk]
SIG 3U0>[64S1.3U0_H] & &

[64S1.t_Op_ROV_H] 0ms
[64S1.Op_ROV_H]
EN [64S1.En_Trp_ROV_H]
SIG Flg_Dir ≥1 &
EN [64S1.Dir_Ctrl_ROV_H]
SIG 3I0>[64S1.3I0_Set] ≥1
EN [64S1.ROC_Ctrl_ROV_H]
0ms 500ms
SIG 64S1.FD
Date: 2016-08-16
3 Operation Theory
Flg_ROC
EN [64S1.En] &
SIG 3I0>[64S1.3I0_Set]
&
SIG [64S1.Blk] [64S1.t_ROC] 0ms [64S1.Alm_ROC]
EN [64S1.En_Alm_ROC]
EN [64S1.En
SIG [64S1.En1] &
SIG [64S1.En2]
SIG [64S1.Blk]
SIG 3I0>[64S1.3I0_Set] & &

[64S1.t_ROC] 0ms
[64S1.Op_ROC]
EN [64S1.En_Trp_ROC]
0ms 500ms
SIG 64S1.FD
Figure 3.6-3 Logic diagram of generator fundamental zero-sequence stator ground fault protection
Where:
Flg_ROV is the internal signal indicating that the operation criterion of sensitive stage of
fundamental zero-sequence voltage stator ground fault protection is met, i.e. Equation 3.6-1 is
met.
Flg_ROV_Term is the internal signal indicating that the generator terminal broken-delta residual
voltage criterion is met.
Flg_Dir is the internal signal indicating that the zero sequence directional element is met.
Flg_ROC is the internal signal indicating that the zero sequence current stator ground fault
protection is met.
64S1.FD is the internal signal indicating that the fundamental zero-sequence voltage stator ground
fault protection picks up (the fault detector of fault detector DSP module).
3Uh0 is the residual voltage of HV side of the main transformer.
3U0 is the residual voltage of the neutral point of the No.1 zero sequence voltage input.
3I0 is the zero sequence current of the generator.
64S1
64S1.U1P1_Hm 64S1.St
64S1.U1P2_Hm 64S1.Op_ROV_L
64S1.U1P3_Hm 64S1.Op_ROV_H
64S1.Alm_ROV_L
I1P_Hm
64S1.Alm_ROC
64S1.En1
64S1.Op_ROC
64S1.En2
64S1.Blk
Figure 3.6-4 Function block diagram of generator fundamental zero-sequence stator ground fault
Date: 2016-08-16
3 Operation Theory
protection
Table 3.6-1 Input signals of generator fundamental zero-sequence stator ground fault protection

Zero-sequence voltage input 1, generally it is generator neutral point
1 64S1.U1P1_Hm
zero-sequence voltage or generator terminal zero-sequence voltage.
Zero-sequence voltage input 2, generally it is generator terminal
2 64S1.U1P2_Hm
zero-sequence voltage or has no input.
Zero-sequence voltage input 3, generally it is main transformer HV side
3 64S1.U1P3_Hm
zero-sequence voltage.
Zero-sequence current input, generally it is the zero sequence current of
4 64S1.I1P_Hm
terminal side or neutral point.
5 64S1.En1 Protection function enabling input1 and input 2, it can be binary inputs or
6 64S1.En2 settings, such as function enabling binary inputs, logic links, etc.
7 64S1.Blk Protection function blocking input, such as function blocking binary input.
8 G_Term.VT1.VTS_Pri.Blk Generator terminal VT1 primary circuit failure blocking input.
Table 3.6-2 Output signals of generator fundamental zero-sequence voltage stator ground fault protection

Generator fundamental zero-sequence voltage stator ground fault protection
1 64S1.St
starts.
The sensitive stage of fundamental zero-sequence voltage stator ground fault
2 64S1.Alm_ROV_L
protection operates to issue alarm signal.
The sensitive stage of fundamental zero-sequence voltage stator ground fault
3 64S1.Op_ROV_L
protection operates to trip.
The insensitive stage of fundamental zero-sequence voltage stator ground fault
4 64S1.Op_ROV_H
The fundamental zero-sequence current stator ground fault protection operates to
5 64S1.Alm_ROC
issue alarm signal.
The fundamental zero-sequence current stator ground fault protection operates to
6 64S1.Op_ROC
trip.
(event recorder)
Tripping reports
The sensitive stage of fundamental zero-sequence voltage stator ground

1 64S1.Op_ROV_L
fault protection operates to trip
The insensitive stage of fundamental zero-sequence voltage stator

2 64S1.Op_ROV_H
ground fault protection operates to trip
Date: 2016-08-16
3 Operation Theory
The fundamental zero-sequence current stator ground fault protection

3 64S1.Op_ROC
operates to trip.
Start signals
Generator fundamental zero-sequence voltage stator ground fault

4 64S1.St
protection starts.
Alarm signals
The sensitive stage of fundamental zero-sequence voltage stator ground

5 64S1.Alm_ROV_L
fault protection operates to issue alarm signal
The fundamental zero-sequence current stator ground fault protection

6 64S1.Alm_ROC
operates to issue alarm signal.
Waveform recording
Generator fundamental zero-sequence voltage stator ground fault

7 64S1.TrigDFR
protection operates to trigger waveform recording.
(measurements)
The fundamental residual voltage amplitude of VT1 of

generator terminal
The fundamental residual voltage amplitude of generator

2 G_NP.3U0_Hm1 V
neutral point
The phase angle between the fundamental component of

3 Ang(3U0_Hm1_Term&NP_Gen) deg
residual voltage of generator terminal and neutral point
4 64S1.3I0_Hm1_ROC The fundamental zero sequence current amplitude of generator A
The fundamental current amplitude of zero sequence

5 64S1.3I0_Hm1_Dir mA
directional element
The phase angle between the zero sequence current and the
6 Ang(3I0-3U0_Hm1) deg
zero sequence voltage of generator
7 K_Delt&NP_VT_Gen Generator zero-sequence voltage correlation coefficient.
The internal signal indicating that the operation criterion of

8 64S1.Flg_ROV sensitive stage of fundamental zero-sequence voltage stator
ground fault protection is met
The internal signal indicating that the operation criterion of

9 64S1.Flg_ROC fundamental zero-sequence current stator ground fault
protection is met
Access Path:
Main menu -> Measurements -> Measurements2-> Prot Values-> Gen StaEF Prot Values
Date: 2016-08-16
3 Operation Theory
3.6.6 Settings
Table 3.6-5 Settings list of generator fundamental zero-sequence voltage stator ground fault protection

0: disable
1 64S1.En 1 generator fundamental zero-sequence
1: enable
voltage stator ground fault protection.
Main transformer zero-sequence
2 64S1.3U0_Tr_Blk 1~100 0.01 V
voltage blocking setting
Current threshold of the zero
3 64S1.3I0_Th_Dir 0.0~100 0.01 mA
sequence directional element
4 64S1.phi_Reach 0~360 1 deg Sensitive angle setting
Voltage setting for sensitive stage of
5 64S1.3U0_L 0.1~50 0.01 V fundamental zero-sequence voltage
stator ground fault protection
Time delay setting for sensitive stage
6 64S1.t_ROV_L 0.1~30 0.01 s of fundamental zero-sequence voltage
Voltage setting for insensitive stage of
7 64S1.3U0_H 0.1~50 0.01 V fundamental zero-sequence voltage
Time delay setting for insensitive stage
8 64S1.t_Op_ROV_H 0.1~30 0.01 s of fundamental zero-sequence voltage
Current setting for fundamental
9 64S1.3I0_Set 0.05~10 0.01 A zero-sequence current stator ground
fault protection
Time delay setting for fundamental
10 64S1.t_ROC 0.1~30 0.01 s zero-sequence current stator ground
fault protection
11 64S1.OutMap 0~3FFFFFFF 1 fundamental zero-sequence voltage
stator ground fault protection.
0: disable sensitive stage of fundamental
12 64S1.En_Alm_ROV_L 1
1: enable zero-sequence voltage stator ground
fault protection operates to alarm.
0: disable sensitive stage of fundamental
13 64S1.En_Trp_ROV_L 1
1: enable zero-sequence voltage stator ground
fault protection operates to trip.
0: disable
14 64S1.En_Trp_ROV_H 1 insensitive stage of fundamental
1: enable
zero-sequence voltage stator ground
Date: 2016-08-16
3 Operation Theory
fault protection operates to trip.

0: disable fundamental zero-sequence voltage
15 64S1.En_Alm_ROC 1
1: enable stator ground fault protection operates
to issue alarm signal.
0: disable fundamental zero-sequence current
16 64S1.En_Trp_ROC 1
1: enable stator ground fault protection operates
to trip.
0: disable directional element for sensitive stage
17 64S1.Dir_Ctrl_ROV_L 1
1: enable of fundamental zero-sequence voltage
0: disable directional element for insensitive
18 64S1.Dir_Ctrl_ROV_H 1
1: enable stage of fundamental zero-sequence
voltage stator ground fault protection
zero sequence current blocking
0: disable
19 64S1.ROC_Ctrl_ROV_L 1 element for sensitive stage of
1: enable
fundamental zero-sequence voltage
zero sequence current blocking
0: disable
20 64S1.ROC_Ctrl_ROV_H 1 element for insensitive stage of
1: enable
fundamental zero-sequence voltage
0: disable
21 G_Term.VT1.En_Alm_VTS_Delt 1 generator terminal broken-delta VT
1: enable
circuit failure alarm function
0: disable
22 G_NP.En_Alm_VTS 1 generator neutral point VT circuit
1: enable
failure alarm function
Fundamental zero-sequence voltage
stator ground fault protection voltage
source selection.
0: Source1
23 64S1.Opt_Source_3U0 1 0: Source1 (zero-sequence voltage
1: BothSources
input 1)
1: BothSources (zero-sequence
voltage input 1 and 2)
Access path: Settings-> Prot Settings -> Gen Hm1StaEF Settings
Date: 2016-08-16
3 Operation Theory
3.7 Generator 3rd Harmonic Stator Ground Fault Protection (64S2)
3.7.1 Application
Fundamental zero-sequence voltage stator ground fault protection can only detect the ground fault
of 85%~95% of stator winding of generator terminal side, for the ground fault that near the
generator neutral point, it can be detected by 3rd harmonic stator ground fault protection.

 3rd harmonic ratio stator ground fault element: it can detect the ground fault of approximately
25% of stator winding of generator neutral point side.
 3rd harmonic differential stator ground fault element: theoretically it can detect the ground fault
of the whole stator winding.

3.7.3.1 Overview
Generator 3rd harmonic stator ground fault protection includes two operation elements: 3rd
harmonic ratio stator ground fault element and 3rd harmonic differential stator ground fault element.
Fundamental zero sequence voltage stator ground fault protection coordinate with 3rd harmonic
ratio stator ground fault element can constitute 100% stator ground fault protection. 3rd harmonic
differential stator ground fault element can reflect the ground fault of the whole stator winding, but
it is very sensitive, so generally it is only for alarm.
3.7.3.2 Calculation Process of 3rd Harmonic Stator Ground Fault Protection
The calculation process of 3rd harmonic stator ground fault protection is shown in following figure.
The generator neutral point is grounded via grounding transformer, it can also be grounded via
grounding VT. When a ground fault happens at generator stator winding, the distribution of the
circuit ground capacitance will change, by detecting the 3rd harmonic zero sequence voltage of
generator terminal and neutral point, the device can judge whether a stator ground fault happens.
Date: 2016-08-16
3 Operation Theory
Generator CM
RB
Main transformer
CG Cl CTr
UN0 UT0
Filtering
Calculate the 3rd harmonic zero-sequence voltage amplitude
PCS-985
Figure 3.7-1 Calculation process of generator 3rd harmonic stator ground fault protection
Where:
RB is the secondary load resistance of neutral point grounding transformer;
UN0 is the tap voltage (it is 100V or 173V generally) of secondary load resistance of neutral point
grounding transformer;
UT0 is the broken-delta zero-sequence voltage of generator terminal VT;
CG is the generator stator winding ground capacitance;
Cl is the ground capacitance of the outgoing line of generator terminal;
CTr is the main transformer ground capacitance;
CM is the coupling capacitance between the HV winding and LV winding of main transformer.
3.7.3.3 3rd Harmonic Ratio Stator Ground Fault Element
3rd harmonic ratio stator ground fault element can only detect the ground fault of approximately
25% of stator winding of generator neutral point side, generator terminal 3rd harmonic voltage is
derived from generator terminal broken-delta zero-sequence voltage or calculated zero-sequence
voltage of VT1, generator neutral point side 3rd harmonic voltage is derived from generator neutral
point VT or the tap voltage of load resistance of grounding transformer.
The operation criterion of 3rd harmonic ratio stator ground fault element is:
U 3T
> K 3 wzd Equation 3.7-1
U 3N
Where:
Date: 2016-08-16
3 Operation Theory
U 3T and U 3 N are 3rd harmonic voltage value of generator terminal and neutral point
respectively;
K 3 wzd is the ratio setting of 3rd harmonic ratio stator ground fault element.
Generator terminal equivalent capacitance has a greater change before and after the unit is
connected with the power grid, so the 3rd harmonic voltage ratio will change with it. So two different
ratio settings are configured for the 3rd harmonic ratio stator ground fault element respectively for
the conditions before and after the unit is connected with the power grid, the two settings are
switched over automatically with the position contact change of generator terminal circuit breaker.
For 3rd harmonic voltage has a close relationship with the generator operating conditions, so 3rd
harmonic ratio stator ground fault element is only enabled when the generator positive-sequence
voltages are respectively larger than a certain threshold value. If the generator frequency shifts
near the power frequency, the ratio setting will add a frequency additional restraint threshold. If the
generator frequency seriously deviates from the power frequency, 3rd harmonic ratio stator ground
fault element will quit automatically.
3rd harmonic ratio stator ground fault element can operate to trip or alarm.
3.7.3.4 3rd Harmonic Differential Stator Ground Fault Element
The operation criterion of 3rd harmonic differential stator ground fault element is:
U 3 N − kt × U 3T > K re × U 3 N Equation 3.7-2
Where:
U 3T and U 3 N are 3rd harmonic voltage vector of generator terminal and neutral point
respectively;
U 3 N are 3rd harmonic voltage value of generator neutral point;
kt is the automatic tracking adjustment coefficient vector, it equals to the ratio between U 3T and
U 3 N during normal operation. If the automatic tracking adjustment coefficient is larger than the
maximum permissive adjustment multiple (i.e. the configuration setting
[64S2.Kmax_U_Hm3_Diff]), 3rd harmonic differential stator ground fault element will quit.
K re is the differential ratio setting of 3rd harmonic differential stator ground fault element.
The criterion is only enabled after the generator unit is connected with the power grid and the load
current is larger than 0.2Ie (Ie is the rated current of generator).
Date: 2016-08-16
3 Operation Theory
For 3rd harmonic voltage has a close relationship with the generator operating conditions, so 3rd
harmonic differential stator ground fault element is only enabled when the generator
positive-sequence voltages are respectively larger than a certain threshold value. If the generator
frequency seriously deviates from the power frequency, 3rd harmonic differential stator ground fault
element will quit automatically.
3rd harmonic differential stator ground fault element can operate to alarm.
3.7.3.5 Generator Terminal VT1 Primary Circuit Failure Alarm
Generator terminal VT1 secondary circuit failure will not affect stator ground fault protection, if
generator terminal VT1 primary circuit failure happens, the fundamental component of generator
terminal zero-sequence voltage will increase, but the neutral point zero-sequence voltage will not
change, it will not lead to mal-operation of fundamental zero-sequence voltage protection, but it
maybe lead to mal-operation of 3rd harmonic ratio stator ground fault element and 3rd harmonic
differential stator ground fault element, so 3rd harmonic ratio stator ground fault element and 3rd
harmonic differential stator ground fault element should be blocked if generator terminal VT1
primary circuit failure happens.
1) Negative-sequence voltage of VT2 3U2' < 3V
2) Negative-sequence voltage of VT1 3U2 > 8V
3) The calculated zero-sequence voltage of VT1 3U0zc > 8V
4) The broken-delta zero-sequence voltage of VT1 3U0 > 8V
If above four conditions are met, generator terminal VT1 primary circuit failure alarm signal will be
issued with a short time delay, the 3rd harmonic ratio stator ground fault element and 3rd harmonic
differential stator ground fault element are blocked.
1) Neutral point zero-sequence voltage 3U0' < 4V
2) Negative-sequence voltage of VT1 3U2 > 8V
3) The calculated zero-sequence voltage of VT1 3U0zc > 8V
4) The broken-delta zero-sequence voltage of VT1 3U0 > 8V
If above four conditions are met, generator terminal VT1 primary circuit failure alarm signal will be
issued with a short time delay, the 3rd harmonic ratio stator ground fault element and 3rd harmonic
differential stator ground fault element are blocked.
If generator terminal zero-sequence voltage is derived from the calculated zero-sequence voltage,
the device will not detect generator terminal VT1 primary circuit failure.
Date: 2016-08-16
3 Operation Theory
3.7.4 Logic
For generator 3rd harmonic stator ground fault protection, if following three conditions are met, the
(1) Logic setting [64S2.En] is set as “1”.
(2) Protection function enabling inputs [64S2.En1], [64S2.En2] are “1”
(3) Protection function blocking input [64S2.Blk] is “0”.
If generator 3rd harmonic stator ground fault protection is disabled, all the related output signals will
be reset. If no external input is configured to [64S2.En1] ([64S2.En2]), the default initial value of
[64S2.En1] ([64S2.En2]) is “1”; if no external input is configured to [64S2.Blk], the default initial
value of [64S2.Blk] is “0”.
Date: 2016-08-16
3 Operation Theory
SIG [64S2.En1] &

SIG [64S2.En2]
SIG [64S2.Blk] &
[64S2.St]
&
EN [64S2.En_Trp_U_Hm3_Ratio]
SIG Flg_V3rdHRatio
Flg_U_Hm3_Ratio
EN [64S2.En] &
SIG Flg_Blk_U1
SIG Flg_Blk_f
&
SIG U3T/U3N>[64S2.K_Pre_U_Hm3_Ratio] & SIG Flg_V3rdHRatio
SIG Flg_52a
SIG ≥1
&
SIG U3T/U3N>[64S2.K_Post_U_Hm3_Ratio]
EN [64S2.En_Alm_U_Hm3_Ratio] &
& [64S2.t_Op] 0ms [64S2.Alm_U_Hm3_Ratio]
SIG Flg_V3rdHRatio
SIG [64S2.Blk]
SIG [64S2.En1] &

SIG [64S2.En2]
SIG [64S2.Blk]
& [64S2.t_Op] 0ms [64S2.Op_U_Hm3_Ratio]
&
EN [64S2.En_Trp_U_Hm3_Ratio]
SIG Flg_V3rdHRatio
0ms 500ms
SIG 64S2.FD_U_Hm3_Ratio
SIG Flg_52a&Flg_Curr &

SIG Flg_Blk_U1&F
SIG G_Term.VT1.VTS_Pri.Blk Flg_U_Hm3_Diff
&
EN [64S2.En]
SIG [64S2.En1] & &
SIG [64S2.En2] SIG Flg_V3rdHDiff
SIG [64S2.Blk]
SIG Abs(U3N-Kt*U3T)/U3N>[64S2.K_U_Hm3_Diff]
EN [64S2.En_Alm_U_Hm3_Diff] &
[64S2.t_Op] 0ms
[64S2.Alm_U_Hm3_Diff]
SIG Flg_V3rdHDiff
rd
Figure 3.7-2 Logic diagram of generator 3 harmonic stator ground fault protection
Where:
Flg_Blk_U1 is the internal signal indicating that the generator positive-sequence voltage is lower
than a certain threshold value.
Flg_Blk_f is the internal signal indicating that the generator frequency seriously deviates from the
power frequency.
Flg_Blk_U1&F is the internal signal indicating that the generator positive-sequence voltage is
lower than a certain threshold value and the generator frequency seriously deviates from the
power frequency.
Date: 2016-08-16
3 Operation Theory
Flg_52a&Flg_Curr is the internal signal indicating that the generator unit is connected with the
power grid and the load current is larger than 0.2Ie (Ie is the generator rated current).
Flg_U_Hm3_Ratio is the internal signal indicating that 3rd harmonic ratio stator ground fault
element is released.
Flg_V3rdHRatio is the internal signal indicating that the operation criterion of 3rd harmonic ratio
stator ground fault element is met, i.e. Equation 3.7-1 is met.
Flg_U_Hm3_Diff is the internal signal indicating that 3rd harmonic differential stator ground fault
element is released.
Flg_V3rdHDiff is the internal signal indicating that the operation criterion of 3rd harmonic differential
stator ground fault element is met, i.e. Equation 3.7-2 is met.
G_Term.VT1.VTS_Pri.Blk is generator terminal VT1 primary circuit failure blocking input.
64S2.FD_U_Hm3_Ratio is the internal signal indicating that the 3rd harmonic ratio stator ground
fault element picks up (the fault detector of fault detector DSP module).
64S2.FD_U_Hm3_Diff is the internal signal indicating that the 3rd harmonic differential stator
ground fault element picks up (the fault detector of fault detector DSP module).
64S2
64S2.U1P1_Hm 64S2.St
64S2.U1P2_Hm 64S2.Alm_U_Hm3_Ratio
Flg_52a 64S2.Op_U_Hm3_Ratio
64S2.En1 64S2.Alm_U_Hm3_Diff
64S2.En2
64S2.Blk
f
Figure 3.7-3 Function block diagram of generator 3rd harmonic stator ground fault protection
rd
Table 3.7-1 Input signals of generator 3 harmonic stator ground fault protection

Zero-sequence voltage input 1, generally it is generator terminal zero-sequence
1 64S2.U1P1_Hm
voltage.
Zero-sequence voltage input 2, generally it is generator neutral point
2 64S2.U1P2_Hm
zero-sequence voltage.
3 Flg_52a The signal indicating that the generator is connected with the system.
4 f The frequency input.
5 G_Term.VT1.VTS_Pri.Blk generator terminal VT1 primary circuit failure blocking input
6 64S2.En1 Protection function enabling input1 and input 2, it can be binary inputs or
7 64S2.En2 settings, such as function enabling binary inputs, logic links, etc.
8 64S2.Blk Protection function blocking input, such as function blocking binary input.
Date: 2016-08-16
3 Operation Theory
rd
Table 3.7-2 Output signals of generator 3 harmonic stator ground fault protection

rd
1 64S2.St Generator 3 harmonic stator ground fault protection starts.
rd
2 64S2.Op_U_Hm3_Ratio 3 harmonic ratio stator ground fault element operates to trip.
3 64S2.Alm_U_Hm3_Ratio 3rd harmonic ratio stator ground fault element operates to issue alarm signal.
3rd harmonic differential stator ground fault element operates to issue alarm
4 64S2.Alm_U_Hm3_Diff
signal.
Table 3.7-3 Output signals of generator 3rd harmonic stator ground fault protection (event recorder)
Tripping reports
1 64S2.Op_U_Hm3_Ratio 3rd harmonic ratio stator ground fault element operates to trip.
Start signals
2 64S2.St Generator 3rd harmonic stator ground fault protection starts.
Alarm signals
rd
3 harmonic ratio stator ground fault element operates to issue alarm
3 64S2.Alm_U_Hm3_Ratio
signal.
3rd harmonic differential stator ground fault element operates to issue alarm
signal.
Waveform recording
Generator 3rd harmonic stator ground fault protection operates to trigger

5 64S2.TrigDFR
waveform recording.
Table 3.7-4 Output signals of generator 3rd harmonic stator ground fault protection (measurements)
1 64S2.K_U_Hm3_Ratio 3rd harmonic voltage ratio value
rd
2 64S2.Ud_Hm3_Diff 3 harmonic differential voltage V
Access path:
Main menu -> Measurements -> Measurements1-> Gen Values-> Gen Volt Values
rd
The enabled status of 3 harmonic differential stator ground
3 Flg_On_U_Hm3_Diff
fault element of 3rd harmonic stator ground fault protection
Access path:
Main menu -> Measurements -> Measurements2-> Prot Values-> Misc Prot Values
The 3rd harmonic residual voltage amplitude of VT1 of generator

terminal
Date: 2016-08-16
3 Operation Theory

rd
The 3 harmonic residual voltage amplitude of VT1 of generator
5 G_NP.3U0_Hm3 V
neutral point
The phase angle between the 3rd harmonic residual voltage of

6 Ang(3U0_Hm3_Term&NP_Gen) deg
generator terminal and neutral point
7 64S2.K_U_Hm3_Ratio 3rd harmonic voltage ratio value
8 64S2.Re_K_Hm3_Diff The real part of 3rd harmonic differential balance coefficient

rd
The imaginary part of 3 harmonic differential balance
9 64S2.Im_K_Hm3_Diff
coefficient
rd
10 64S2.Ud_Hm3_Diff 3 harmonic differential voltage V
11 64S2.Ur_Hm3_Diff 3rd harmonic restraint voltage V

rd
The internal signal indicating that 3 harmonic ratio stator
12 64S2.Flg_U_Hm3_Ratio
ground fault element is released
rd
The internal signal indicating that 3 harmonic differential stator
13 64S2.Flg_U_Hm3_Diff
ground fault element is released
Access Path:
Main menu -> Measurements -> Measurements2-> Prot Values-> Gen StaEF Prot Values
3.7.6 Settings
Table 3.7-5 Settings list of generator 3rd harmonic stator ground fault protection

0: disable
1 64S2.En 1 generator 3rd harmonic stator
1: enable
3rd harmonic voltage ratio setting
2 64S2.K_Pre_U_Hm3_Ratio 0.50~10 0.01 pu before the unit is connected with the
power grid.
rd
3 harmonic voltage ratio setting
3 64S2.K_Post_U_Hm3_Ratio 0.50~10 0.01 pu after the unit is connected with the
power grid.
The ratio setting for 3rd harmonic
4 64S2.K_U_Hm3_Diff 0.05~2 0.01 pu differential stator ground fault
element.
rd
Time delay setting of generator 3
5 64S2.t_Op 0.00~30 0.01 s harmonic stator ground fault
protection.
rd
6 64S2.OutMap 0~3FFFFFFF 3 harmonic stator ground fault
protection.
7 64S2.En_Alm_U_Hm3_Ratio 0: disable 1 Logic setting of enabling/disabling
Date: 2016-08-16
3 Operation Theory
rd
1: enable 3 harmonic ratio stator ground fault
element operates to alarm.
0: disable 3
rd
harmonic differential stator
8 64S2.En_Alm_U_Hm3_Diff 1
1: enable ground fault element operates to
alarm.

9 64S2.En_Trp_U_Hm3_Ratio 1 3rd harmonic ratio stator ground fault
1: enable
element operates to trip.
Access path: Settings-> Prot Settings -> Gen Hm3StaEF Settings
3.8 Generator Ping-Pang Type Rotor Ground Fault Protection (64R)
3.8.1 Application
Rotor ground fault protection is used to detect the ground fault of generator excitation circuit. If
generator rotor winding one-point ground fault happens, the rotor will not be damaged immediately,
the generator can continue to run. Then if another-point ground fault happens, a closed electrical
circuit will be generated between the two grounded points, which will lead to winding overheating
and unit vibration, it will be a serious threat to the security of the generator.
 Rotor one-point ground fault element for alarm.
 Rotor one-point ground fault element for trip.
 Rotor two-point ground fault element for trip.

3.8.3.1 Overview
Generator Ping-Pang type rotor ground fault protection includes three operation elements:
sensitive stage of rotor one-point ground fault element for alarm, insensitive stage of rotor
one-point ground fault element for tripping or alarm, and rotor two-point ground fault element for
tripping.
Rotor one-point ground fault element reflects the decline of the insulation resistance between rotor
winding and the shaft, two stages are equipped, the sensitive stage for alarm and the insensitive
stage for alarm or trip. Rotor two-point ground fault element reflects the change of rotor ground
position, it can operate to trip.
3.8.3.2 Calculation Process of Ping-Pang Type Rotor Ground Fault Protection
Generator Ping-Pang type rotor ground fault protection adopts switch-over sampling principle
(ping-pang type), the working circuit is shown as below.
Date: 2016-08-16
3 Operation Theory
Generator rotor
U
+ αU -
rotor
R Rg R
R S1 S2 R
Figure 3.8-1 Schematic diagram of Ping-Pang type rotor ground fault protection
Where:
R is resistance of the circuit;
U is rotor voltage;
α is the grounded position percentage of rotor winding;
Rg is the resistance value of generator rotor grounded resistance.
Corresponding equations can be got by switching over the two electronic switches S1 and S2
alternately, then the rotor grounded resistance Rg and the grounded position percentage “α” (it is
0% for negative terminal and 100% for positive terminal) can be calculated.
3.8.3.3 Rotor One-point Ground Fault Element
Two stages are equipped for rotor one-point ground fault element, the sensitive stage for alarm
and the insensitive stage for alarm or trip. The time delay setting for the two stages can be set
respectively. When the measured generator rotor grounded resistance value is lower than the
resistance setting of sensitive stage, the sensitive stage will operate to alarm with a settable time
delay. When the measured generator rotor grounded resistance value is lower than the resistance
setting of insensitive stage, the insensitive stage will operate to alarm or trip with a settable time
delay.
3.8.3.4 Rotor Two-point Ground Fault Element
If rotor one-point ground fault element is used for alarm only, when rotor grounded resistance Rg is
lower than the resistance setting of insensitive stage of rotor one-point ground fault element, rotor
two-point ground fault element will be enabled with a time delay automatically after the operation
of rotor one-point ground fault element. If the grounded position percentage α varies and the
variation reaches its setting value, two-point ground fault element will operate to trip.
3.8.4 Logic
For generator Ping-Pang type rotor ground fault protection, if following three conditions are met,
the protection will be enabled.
Date: 2016-08-16
3 Operation Theory
(1) Logic setting [64R.En] is set as “1”.
(2) Protection function enabling inputs [64R.En1], [64R.En2] are “1”.
(3) Protection function blocking input [64R.Blk] is “0”.
If generator Ping-Pang type rotor ground fault protection is disabled, all the related output signals
will be reset. If no external input is configured to [64R.En1] ([64R.En2]), the default initial value of
[64R.En1] ([64R.En2]) is “1”; if no external input is configured to [64R.Blk], the default initial value
of [64R.Blk] is “0”.
SIG [64R.En1] &

SIG [64R.En2]
SIG [64R.Blk]
&
EN [64R.1PEF.En_Trp_Insens] &
[64R.St]
SIG Rg<[64R.1PEF.Rg_Insens] ≥1
EN [64R.2PEF.En]
&
SIG 64R.2PEF.On
SIG Δα>3%
En [64R.1PEF.En_Alm_Sens] &
[64R.1PEF.t_Alm] 0
SIG Rg<[64R.1PEF.Rg_Sens] [64R.1PEF.Alm_Sens]
EN [64R.En] &
SIG [64R.Blk]
&
En [64R.1PEF.En_Alm_Insens] [64R.1PEF.t_Alm] 0 [64R.1PEF.Alm_Insens]
SIG Rg<[64R.1PEF.Rg_Insens]
EN [64R.En]
SIG [64R.En1] &
SIG [64R.En2] &
[64R.1PEF.t_Op_Insens] 0 [64R.1PEF.Op_Insens]
SIG [64R.Blk]
EN [64R.1PEF.En_Trp_Insens]
SIG Rg<[64R.1PEF.Rg_Insens]
0ms 500ms
SIG 64R.1PEF.FD
EN [64R.En]
&
SIG [64R.En1]
SIG [64R.En2] & [64R.2PEF.t_Op] 0
[64R.2PEF.Op]
SIG [64R.Blk]
EN [64R.2PEF.En]
SIG 64R.2PEF.On
SIG Δα>3%
0ms 500ms
SIG 64R.2PEF.FD
Figure 3.8-2 Logic diagram of generator Ping-Pang type rotor ground fault protection
Where:
64R.1PEF.FD is the internal signal indicating that rotor one-point ground fault element picks up
64R.2PEF.FD is the internal signal indicating that rotor two-point ground fault element picks up
Date: 2016-08-16
3 Operation Theory
64R.2PEF.On is the internal signal indicating that the enabled status of Ping-Pang type rotor
two-point ground fault element.
64R
64R.ur+ 64R.St
64R.ur- 64R.1PEF.Alm_Sens
64R.En1 64R.1PEF.Alm_Insens
64R.En2 64R.1PEF.Op_Insens
64R.2PEF.Op
64R.Blk
Figure 3.8-3 Function block diagram of generator Ping-Pang type rotor ground fault protection
Table 3.8-1 Input signals of generator Ping-Pang type rotor ground fault protection

The voltage input between rotor positive pole and ground that used for generator
1 64R.ur+
Ping-Pang type rotor ground fault protection.
The voltage input between rotor negative pole and ground that used for generator
2 64R.ur-
3 64R.En1 Protection function enabling input1 and input 2, it can be binary inputs or settings, such
4 64R.En2 as function enabling binary inputs, logic links, etc.
5 64R.Blk Protection function blocking input, such as function blocking binary input.
Table 3.8-2 Output signals of generator Ping-Pang type rotor ground fault protection

1 64R.St Generator Ping-Pang type rotor ground fault protection starts.
Generator Ping-Pang type rotor one-point ground fault element operates to
2 64R.1PEF.Op_Insens
trip.
Generator Ping-Pang type rotor two-point ground fault element operates to
3 64R.2PEF.Op
trip.
The sensitive stage of Ping-Pang type rotor one-point ground fault element
4 64R.1PEF.Alm_Sens
The insensitive stage of Ping-Pang type rotor one-point ground fault
5 64R.1PEF.Alm_Insens
element operates to issue alarm signal.
Date: 2016-08-16
3 Operation Theory
Table 3.8-3 Output signals of generator Ping-Pang type rotor ground fault protection (event recorder)
Tripping reports
1 64R.1PEF.Op_Insens Generator Ping-Pang type rotor one-point ground fault element operates to trip.
2 64R.2PEF.Op Generator Ping-Pang type rotor two-point ground fault element operates to trip.
Start signals
3 64R.St Generator Ping-Pang type rotor ground fault protection starts.
Alarm signals
The sensitive stage of Ping-Pang type rotor one-point ground fault element
4 64R.1PEF.Alm_Sens
operates to issue alarm signal
The insensitive stage of Ping-Pang type rotor one-point ground fault element
Waveform recording
Generator Ping-Pang type rotor ground fault protection operates to trigger

6 64R.TrigDFR
waveform recording.
7 64R.1PEF.St Generator Ping-Pang type rotor one-point ground fault element starts.
8 64R.2PEF.St Generator Ping-Pang type rotor two-point ground fault element starts.
Table 3.8-4 Output signals of generator Ping-Pang type rotor ground fault protection (measurements)
The voltage between rotor positive pole and ground that used for
1 64R.U+_Rot V
generator Ping-Pang type rotor ground fault protection.
The voltage between rotor negative pole and ground that used for
2 64R.U-_Rot V
3 64R.Rg Rotor grounded resistance kΩ
4 64R.Location_EF The grounded position percentage of the rotor %
Access path:
The enabled status of Ping-Pang type rotor two-point ground fault

5 64R.2PEF.On
element
The voltage between rotor positive pole and ground that used for
6 64R.U+_Rot V
The voltage between rotor negative pole and ground that used for
7 64R.U-_Rot V
8 64R.Rg Rotor grounded resistance kΩ
Date: 2016-08-16
3 Operation Theory
The grounded position percentage of the rotor (it is “0” for rotor
9 64R.Location_EF winding negative pole ground fault and “100%” for rotor winding %
positive pole ground fault).
Access Path:
Main menu -> Measurements -> Measurements2-> Prot Values-> Gen SwitchRotEF Prot Values
3.8.6 Settings
Table 3.8-5 Settings list of generator Ping-Pang type rotor ground fault protection

1 64R.En 1
1: enable Ping-Pang type rotor ground fault protection.
Resistance setting of sensitive stage of
2 64R.1PEF.Rg_Sens 0.10~100 0.01 kΩ generator Ping-Pang type rotor one-point
ground fault element.
Resistance setting of insensitive stage of
3 64R.1PEF.Rg_Insens 0.10~100 0.01 kΩ generator Ping-Pang type rotor one-point
ground fault element.
Time delay setting for generator Ping-Pang
4 64R.1PEF.t_Alm 0.00~30 0.01 s type rotor one-point ground fault element
operates to alarm.
Time delay setting for insensitive stage of
5 64R.1PEF.t_Op_Insens 0.00~30 0.01 s generator Ping-Pang type rotor one-point
ground fault element operates to trip.
Time delay setting of generator Ping-Pang
6 64R.2PEF.t_Op 0.00~30 0.01 s
type rotor two-point ground fault element.
Switching sampling cycle setting of generator
7 64R.t_Switch 0.50~10 0.01 s
Tripping logic setting of generator Ping-Pang
8 64R.OutMap 0~3FFFFFFF
type rotor ground fault protection.
Logic setting of enabling/disabling sensitive
0: disable
9 64R.1PEF.En_Alm_Sens 1 stage of generator Ping-Pang type rotor
1: enable
one-point ground fault element.
Logic setting of enabling/disabling insensitive
0: disable stage of generator Ping-Pang type rotor
10 64R.1PEF.En_Alm_Insens 1
1: enable one-point ground fault element operates to
alarm.
Logic setting of enabling/disabling insensitive
0: disable
11 64R.1PEF.En_Trp_Insens 1 stage of generator Ping-Pang type rotor
1: enable
one-point ground fault element operates to trip.
12 64R.2PEF.En 1
1: enable Ping-Pang type rotor two-point ground fault
Date: 2016-08-16
3 Operation Theory
element.
Access path: Settings-> Prot Settings -> Gen SwitchRotEF Settings
3.9 Generator Rotor Ground Fault Protection with Low-frequency
Square-wave Voltage Injection (64RInj)
3.9.1 Application
The low-frequency square-wave voltage is injected between the generator rotor winding
positive/negative pole leading-out terminal and the shaft, via measuring the leakage current, the
rotor one-point ground resistance is calculated, it can reflect the decline of insulation resistance
that between the rotor winding (includes the directly connected excitation circuit) and the rotor
shaft.

Detect rotor winding (includes the directly connected excitation circuit) one-point ground fault.
If double-ends injecting wiring is adopted, it can detect the location of rotor winding ground fault.
When the calculated rotor ground fault location changes, it will be considered that a two-point
ground fault happens.

3.9.3.1 Overview
The external low-frequency square-wave voltage is injected to generator rotor winding circuit, if no
rotor one-point ground fault happens, the leakage current generated by the injected signal is small,
capacitive current exists only when the square-wave is switching, the leakage current is zero
during the steady-state of the square-wave. If rotor one-point ground fault happens, the leakage
current will increase and the calculated ground transition resistance value will decrease, the
protection will operate with a time delay. Two stages of rotor one-point ground fault protection are
equipped, the sensitive stage is for alarm and the insensitive stage is for alarm or trip.
If double-end injecting wiring is adopted, the device can calculate the location of rotor ground fault.
After the rotor one-point ground fault happens and the device is steady again, two-point ground
fault element can be enabled according to user’s requirement. When the calculated rotor ground
fault location changes, it will be considered that a two-point ground fault happens, the protection
will operate to trip with a time delay.
3.9.3.2 Calculation Process of Rotor Ground Fault Protection
The calculation process of generator rotor ground fault protection with low-frequency square-wave
voltage injection is shown as below. In the figure generator rotor winding positive/negative pole
and the rotor shaft is leading out via slip-ring carbon brush. The device detects the injected voltage
and leakage current and other signals, calculates the ground transition resistance value and the
ground fault location.
Date: 2016-08-16
3 Operation Theory
Ry +
Generator
Ry Field
Generator
_ Rotor
Us Ur
Square-wave voltage PCS-985
Filtering us, ix, ur, iDC, Rg
(a) double-ends injecting type
Generator
Ry Field
Generator
_ Rotor
Us Ur
Square-wave voltage PCS-985
Filtering us, ix, ur, iDC, Rg
(b) Single-end injecting type
Figure 3.9-1 Schematic diagram of rotor ground fault protection with low-frequency square-wave voltage
injection
Where:
Ry is the big-power resistor of the injected circuit;
Us is the injected square-wave voltage;
Ur is the rotor winding voltage.
3.9.3.3 Rotor One-point Ground Fault Element with Low-frequency Square-wave Voltage
Injection
Rotor one-point ground fault element with low-frequency square-wave voltage injection adopts the
ground transition resistance to judge. Two stages are equipped, the sensitive stage is for alarm
and the insensitive stage is for alarm or trip. The criterion is:
Rg < RSens1PEF Equation 3.9-1
Date: 2016-08-16
3 Operation Theory
Rg < R1PEF Equation 3.9-2
Where:
Rg is the resistance value of the ground transition resistance;
RSens1PEF is the alarm resistance setting of sensitive stage;
R1PEF is the alarm or trip resistance setting of insensitive stage.
3.9.3.4 Rotor two-point Ground Fault Element with Low-frequency Square-wave Voltage
Injection
For the unit that users can simultaneously lead-out the positive and negative pole of rotor winding,
double-ends injecting wiring can be adopted. The device can calculate the location of rotor
one-point ground fault, so it can realize the two-point ground fault protection via the change of the
rotor ground fault location. If above Equation 3.9-2 is met, and rotor one-point ground fault element
operates for alarm, two-point ground fault element is enabled automatically with a time delay.
3.9.4 Logic
For generator rotor ground fault protection (with low-frequency square-wave voltage injection), if
following three conditions are met, the protection will be enabled.
(1) Logic setting [64RInj.En] is set as “1”.
(2) Protection function enabling inputs [64RInj.En1], [64RInj.En2] are “1”
(3) Protection function blocking input [64RInj.Blk] is “0”.
If generator rotor ground fault protection (with low-frequency square-wave voltage injection) is
disabled, all the related output signals will be reset. If no external input is configured to
[64RInj.En1] ([64RInj.En2]), the default initial value of [64RInj.En1] ([64RInj.En2]) is “1”; if no
external input is configured to [64RInj.Blk], the default initial value of [64RInj.Blk] is “0”.
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3 Operation Theory
SIG [64RInj.En1] &

SIG [64RInj.En2]
SIG [64RInj.Blk]
&
EN [64RInj.1PEF.En_Trp_Insens] &
[64RInj.St]
SIG Rg<[64RInj.1PEF.Rg_Insens] ≥1
EN [64RInj.2PEF.En]
&
SIG 64RInj.2PEF.On
SIG |ΔLocation_EF| >3%
EN [64RInj.1PEF.En_Alm_Sens] &
[64RInj.1PEF.t_Alm] 0s
SIG Rg < [64RInj.1PEF.Rg_Sens] [64RInj.1PEF.Alm_Sens]
EN [64RInj.En] &
SIG [64RInj.Blk]
&
EN [64RInj.1PEF.En_Alm_Insens] [64RInj.1PEF.t_Alm] 0s
[64RInj.1PEF.Alm_Insens]
SIG Rg < [64RInj.1PEF.Rg_Insens]
EN [64RInj.1PEF.En_Trp_Insens]
&
SIG Rg < [64RInj.1PEF.Rg_Insens] [64RInj.1PEF.t_Op_Insens] 0s
[64RInj.1PEF.Op_Insens]
SIG 64RInj.1PEF.FD 0ms 500ms
EN [64RInj.En]
&
SIG [64RInj.En1]
SIG [64RInj.En2]
SIG [64RInj.Blk]
SIG 64RInj.2PEF.On & &

[64RInj.2PEF.t_Op] 0s
EN [64RInj.2PEF.En] [64RInj.2PEF.Op]
SIG |ΔLocation_EF| >3%
SIG 64RInj.2PEF.FD 0ms 500ms
Figure 3.9-2 Logic diagram of generator rotor ground fault protection (with low-frequency square-wave
voltage injection)
Where:
64RInj.1PEF.FD is the internal signal indicating that the generator rotor one-point ground fault
protection (with low-frequency square-wave voltage injection) picks up (the fault detector of fault
detector DSP module).
64RInj.2PEF.On is the internal signal indicating that generator rotor two-point ground fault
protection (with low-frequency square-wave voltage injection) is enabled.
|ΔLocation_EF| is rotor ground fault location variation.
64RInj.2PEF.FD is the internal signal indicating that the generator rotor two-point ground fault
protection (with low-frequency square-wave voltage injection) picks up (the fault detector of fault
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64RInj
64RInj.us 64RInj.St
64RInj.ix 64RInj.1PEF.Op_Insens
64RInj.ur 64RInj.2PEF.Op
64RInj.iDC 64RInj.1PEF.Alm_Sens
64RInj.En1 64RInj.1PEF.Alm_Insens
64RInj.En2
64RInj.Blk
Figure 3.9-3 Function block diagram of generator rotor ground fault protection (with low-frequency
square-wave voltage injection)
Table 3.9-1 Input signals of generator rotor ground fault protection (with low-frequency square-wave
voltage injection)

1 64RInj.us The injected low-frequency voltage.
2 64RInj.ix The leakage current.
3 64RInj.ur The rotor voltage.
4 64RInj.iDC The rotor voltage measured via transmitter (input 4~20mA current signal)
5 64RInj.En1 Protection function enabling input1 and input 2, it can be binary inputs or
6 64RInj.En2 settings, such as function enabling binary inputs, logic links, etc.
7 64RInj.Blk Protection function blocking input, such as function blocking binary input.
Table 3.9-2 Output signals of generator rotor ground fault protection (with low-frequency square-wave
voltage injection)

Generator rotor ground fault protection (with low-frequency square-wave
1 64RInj.St
voltage injection) starts.
Generator rotor one-point ground fault element (with low-frequency
2 64RInj.1PEF.Op_Insens
square-wave voltage injection) operates to trip.
Generator rotor two-point ground fault element (with low-frequency
3 64RInj.2PEF.Op
Sensitive stage of rotor one-point ground fault element (with low-frequency
4 64RInj.1PEF.Alm_Sens
square-wave voltage injection) operates to issue alarm signal.
Insensitive stage of rotor one-point ground fault element (with low-frequency
5 64RInj.1PEF.Alm_Insens
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3 Operation Theory
voltage injection) (event recorder)
Tripping reports
Generator rotor one-point ground fault element (with low-frequency

1 64RInj.1PEF.Op_Insens
Generator rotor two-point ground fault element (with low-frequency

2 64RInj.2PEF.Op
Start signals

3 64RInj.St
voltage injection) starts.
Alarm signals
The external injected power supply of generator rotor ground fault protection
4 64RInj.Alm_Pwr_Inj
(with low-frequency square-wave voltage injection) is abnormal.
Sensitive stage of rotor one-point ground fault element (with low-frequency

Insensitive stage of rotor one-point ground fault element (with low-frequency

Waveform recording

7 64RInj.TrigDFR
voltage injection) operates to trigger waveform recording.
Generator rotor one-point ground fault protection (with low-frequency

8 64RInj.1PEF.St
square-wave voltage injection) starts.
Generator rotor two-point ground fault protection (with low-frequency

9 64RInj.2PEF.St
square-wave voltage injection) starts.
voltage injection) (measurements)
1 64RInj.I_Leak1 Leakage current 1 mA
3 64RInj.U_Inj The injected square-wave voltage V
4 64RInj.Rg Rotor ground resistance. kΩ
Rotor ground fault location (it is “0” for rotor winding negative pole
5 64RInj.Location_EF %
ground fault and “100%” for rotor winding positive pole ground fault).
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3 Operation Theory
Access path:
The internal signal indicating that generator rotor two-point ground

6 64RInj.2PEF.On fault protection (with low-frequency square-wave voltage injection) is
enabled.
7 U_Rot Rotor voltage. V
8 I_Transducer Current of the current transducer (4~20mA). mA
11 64RInj.U_Inj The injected square-wave voltage V
12 64RInj.Rg Rotor ground resistance. kΩ
Rotor ground fault location (it is “0” for rotor winding negative pole
13 64RInj.Location_EF %
ground fault and “100%” for rotor winding positive pole ground fault).
Access Path:
Main menu -> Measurements -> Measurements2-> Prot Values-> Gen InjRotEF Prot Values
3.9.6 Settings
Table 3.9-5 Settings list of generator rotor ground fault protection (with low-frequency square-wave
voltage injection)

0: disable generator rotor ground fault protection
1 64RInj.En 1
1: enable (with low-frequency square-wave voltage
injection).
The resistance setting of sensitive stage of
rotor one-point ground fault element (with
2 64RInj.1PEF.Rg_Sens 0.10~100.00 0.01 kΩ
low-frequency square-wave voltage
injection).
The resistance setting of insensitive stage
of rotor one-point ground fault element
3 64RInj.1PEF.Rg_Insens 0.10~100.00 0.01 kΩ
(with low-frequency square-wave voltage
injection).
Time delay setting for rotor one-point
ground fault element (with low-frequency
4 64RInj.1PEF.t_Alm 0.00~30.00 0.01 s
square-wave voltage injection) operates to
alarm.
Time delay setting for rotor one-point
5 64RInj.1PEF.t_Op_Insens 0.00~30.00 0.01 s ground fault element (with low-frequency
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3 Operation Theory
trip.
Time delay setting of rotor two-point
6 64RInj.2PEF.t_Op 0.00~30.00 0.01 s ground fault element (with low-frequency
square-wave voltage injection).
The switching cycle of the injected
7 64RInj.t_Switch 0.50~10.00 0.01 s
square-wave voltage.
The resistance value of the big-power
8 64RInj.R_Injected 0.10~100.00 0.01 kΩ
resistor of the injected circuit.
Tripping logic setting of generator rotor
9 64RInj.OutMap 0~3FFFFFFF ground fault protection (with low-frequency
square-wave voltage injection).
0: disable stage of rotor one-point ground fault
10 64RInj.1PEF.En_Alm_Sens 1
1: enable element (with low-frequency square-wave
voltage injection) operates to alarm.
insensitive stage of rotor one-point ground
0: disable
11 64RInj.1PEF.En_Alm_Insens 1 fault element (with low-frequency
1: enable
alarm.
insensitive stage of rotor one-point ground
0: disable
12 64RInj.1PEF.En_Trp_Insens 1 fault element (with low-frequency
1: enable
trip.
Logic setting of enabling/disabling rotor
0: disable two-point ground fault element (with
13 64RInj.2PEF.En 1
1: enable low-frequency square-wave voltage
injection).
Rotor voltage input mode.
14 64RInj.Opt_U_Rot 0, 1 1 0: the measured result of rotor voltage
1: the measured result of 20mA transmitter
0: The injected mode selection.
15 64RInj.Opt_Mode_Inj Double-ends 0: Double-ends injecting type
1: Single-end 1: Single-end injecting type
Access path: Settings-> Prot Settings -> Gen InjRotEF Settings
3.10 Generator Rotor Winding Overload Protection (49E)
3.10.1 Application
Generator rotor winding overload protection is equipped to reflect the average heating condition of
rotor winding.
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3 Operation Theory

 Rotor winding definite-time overload protection.
 Rotor winding inverse-time overload protection.
Generator rotor winding overload protection comprises definite-time overload protection and
inverse-time overload protection. The low-setting stage of definite-time overload protection is used
for alarm and the high-setting stage of definite-time overload protection is used for tripping.
Inverse-time overload protection can simulate the heat accumulation process of the rotor winding.
3.10.3.1 Rotor Winding Overload Protection Calculation Process
Only considering the temperature change that caused by copper loss of rotor winding. The copper
loss is proportional to the square of current, so there is a certain proportional relationship between
the temperature change of rotor winding and the square of excitation circuit current. Via checking
the change of excitation circuit current can reflect the temperature change of rotor winding
indirectly. For a given temperature increase (Δθ), the corresponding expression between
permissive time (t) and current can be got:
A
t=
(I )
∗ 2
−1
Equation 3.10-1
Where:
A is the heat capacity for the generator rotor winding.
I ∗ is the per-unit value of excitation circuit current (when the excitation current is the rated
current, the checked rotor circuit current is taken as the referenced value).
3.10.3.2 Rotor Winding Definite-time Overload Protection
There are two stages of rotor winding definite-time overload protection. The low-setting stage of
definite-time overload protection is used for alarm, and the settings should be set to make the
protection can drop off reliably for long-term permissive load current. The high-setting stage of
definite-time overload protection is used for tripping, and the settings should be set according to
the permissive time for more serious overload condition.
3.10.3.3 Rotor winding Inverse-time Overload Protection
Inverse-time rotor winding overload protection consists of three parts: lower-limit initiation part,
inverse-time part and upper limit definite-time part. Minimum operation time delay setting
[49E.IDMT.tmin] is provided for upper limit definite-time part.
When the current in excitation circuit is over the low setting [49E.IDMT.I_Set], the heat
accumulation starts. When the heat accumulation reaches its setting [49E.IDMT.A_Therm],
inverse-time rotor winding overload protection can operate to trip. The inverse time protection can
simulate the heat accumulation and dissipation process of the excitation circuit. If the current in
excitation circuit is over the low setting [49E.IDMT.I_Set], the heat accumulation starts; if the
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3 Operation Theory
current in excitation circuit is lower than the low setting [49E.IDMT.I_Set], the heat dissipation
starts.
The operation characteristic of inverse-time rotor winding overload protection is as follows:
IE
IUpper −lim it
I Pickup
t min tmax t
Figure 3.10-1 Operation characteristic of inverse-time rotor winding overload protection
Where:
t min is the minimum time delay for upper limit definite-time part, i.e. the setting [49E.IDMT.tmin].
t max is maximum time delay for lower-limit initiation part.
I Pickup is the pickup current setting of inverse-time rotor winding overload protection, i.e. the
setting [49E.IDMT.I_Set].
part.
[( I E I b） − 1] × t ≥ ATherm
2
Equation 3.10-2
Where:
I E is the current in excitation circuit.
I b is inverse-time reference current of excitation circuit.
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3 Operation Theory
ATherm is the heat capacity of rotor winding, i.e. the setting [49E.IDMT.A_Therm].
3.10.4 Logic
For rotor winding overload protection, if following three conditions are met, the protection will be
enabled.
(1) Logic setting [49E.En] is set as “1”.
(2) Protection function enabling inputs [49E.En1], [49E.En2] are “1”
(3) Protection function blocking input [49E.Blk] is “0”.
If rotor winding overload protection is disabled, all the related output signals will be reset. If no
external input is configured to [49E.En1] ([49E.En2]), the default initial value of [49E.En1]
([49E.En2]) is “1”; if no external input is configured to [49E.Blk], the default initial value of [49E.Blk]
is “0”.
SIG [49E.En1] &

SIG [49E.En2]
SIG [49E.Blk]
En [49E.DT.OutMap].bit0 & &

[49E.St]
SIG I>[49E.DT.I_Set]
En [49E.IDMT.OutMap].bit0 ≥1
&
SIG I>[49E.IDMT.I_Set]
SIG I>[49E.I_Alm] &

[49E.t_Alm] 0
& [49E.Alm]
EN [49E.En]
SIG [49E.Blk]
EN [49E.En]
SIG [49E.En1] &
& [49E.DT.t_Op] 0
SIG [49E.En2] [49E.DT.Op]
SIG [49E.Blk]
SIG I>[49E.DT.I_Set]
0ms 500ms
SIG 49E.DT.FD
EN [49E.En]
SIG [49E.En1] &
SIG [49E.En2] &

IDMT
[49E.IDMT.Op]
SIG [49E.Blk]
SIG I>[49E.IDMT.I_Set]
0ms 500ms
SIG 49E.IDMT.FD
Figure 3.10-2 Logic diagram of rotor winding overload protection
Where:
49E.DT.FD is the internal signal indicating that the rotor winding definite-time overload protection
picks up (the fault detector of fault detector DSP module).
49E.IDMT.FD is the internal signal indicating that the rotor winding inverse-time overload
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3 Operation Theory
protection picks up (the fault detector of fault detector DSP module).
49E
49E.I3P 49E.St
49E.En1 49E.IDMT.Op
49E.En2 49E.DT.Op
49E.Blk 49E.Alm
Figure 3.10-3 Function block diagram of rotor winding overload protection
Table 3.10-1 Input signals of rotor winding overload protection

1 49E.I3P Three-phase current input.
2 49E.En1 Protection function enabling input1 and input 2, it can be binary inputs or settings, such
3 49E.En2 as function enabling binary inputs, logic links, etc.
4 49E.Blk Protection function blocking input, such as function blocking binary input.
Table 3.10-2 Output signals of rotor winding overload protection

1 49E.St Tripping stage of rotor winding overload protection starts.
2 49E.DT.Op Definite-time rotor winding overload protection operates to trip.
3 49E.IDMT.Op Inverse-time rotor winding overload protection operates to trip.
4 49E.Alm The alarm stage of rotor winding overload protection operates to issue alarm signal
Table 3.10-3 Output signals of rotor winding overload protection (event recorder)
Tripping reports
1 49E.DT.Op Definite-time rotor winding overload protection operates to trip.
2 49E.IDMT.Op Inverse-time rotor winding overload protection operates to trip.
Start signals
3 49E.St Tripping stage of rotor winding overload protection starts.
Alarm signals
The alarm stage of rotor winding overload protection operates to issue alarm
4 49E.Alm
signal
Waveform recording
Tripping stage of rotor winding overload protection operates to trigger

5 49E.TrigDFR
waveform recording.
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3 Operation Theory
6 49E.DT.St Definite-time rotor winding overload protection starts.
7 49E.IDMT.St Inverse-time rotor winding overload protection starts.
Table 3.10-4 Output signals of rotor winding overload protection (measurements)
1 49E.IDMT.ThermAccu Overload heat accumulation of rotor winding %
Access path:
3.10.6 Settings
Table 3.10-5 Settings list of rotor winding overload protection

0: disable Logic setting of enabling/disabling rotor winding
1 49E.En
1: enable overload protection.

2 49E.DT.I_Set 0.10~20In 0.01 A
definite-time rotor winding overload protection.
3 49E.DT.t_Op 0.00~30.00 0.01 s
Tripping logic setting of definite-time rotor
4 49E.DT.OutMap 0~3FFFFFFF
winding overload protection.
5 49E.I_Alm 0.10~20In 0.01 A
6 49E.t_Alm 0.00~30.00 0.01 s
Pickup current setting of inverse-time rotor
7 49E.IDMT.I_Set 0.10~20In 0.01 A
8 49E.IDMT.tmin 0.10~10.00 0.01 s definite-time part of inverse-time rotor winding
The heat capacity of rotor winding for
9 49E.IDMT.A_Therm 1.00~320.00 0.01 s
inverse-time rotor winding overload protection.
The inverse-time reference current of excitation
10 49E.IDMT.Ib_Set 0.10~10In 0.01 A circuit for inverse-time rotor winding overload
protection.
Tripping logic setting of inverse-time rotor
11 49E.IDMT.OutMap 0~3FFFFFFF
Access path: Settings-> Prot Settings -> Exc OvLd Settings
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3 Operation Theory
3.11 Generator Inadvertent Energization Protection (50/27)
3.11.1 Application
For a generator have not been connected to the power grid, if the circuit breaker is closed wrongly,
voltage will be injected to the generator stator winding suddenly, which may lead to severe current
impact. Generator inadvertent energization protection is used to detect the fault, once the
protection operates, circuit breaker can be tripped quickly.

Generator inadvertent energization protection can reflect the condition that the generator is closed
suddenly by mistake.

3.11.3.1 Overview
During resting, hand turning and startup-and-shutdown process, the generator has not been
excited or the excitation current is small, generator terminal voltage and the frequency is low, then
if the generator is closed inadvertently, the generator voltage will be pulled high, the frequency will
be pulled into synchronism, and significant impulse current will be generated. If generator voltage
is larger enough and the frequency is close to the rated value, then if the generator is closed
inadvertently, larger impulse current due to asynchronous closing may be generated.
The protection device according to the characteristics of voltage, frequency, circuit breaker state
and current before and after the generator is closed inadvertently to detect inadvertent
energization condition.
3.11.3.2 Protection Calculation Process
1) Detect the three-phase voltage of generator terminal, calculate the value of voltage to judge
the low-voltage condition;
2) Judge the low-frequency condition via the frequency element;
3) Detect the three-phase current of generator terminal and generator neutral point, calculate
the value of current to judge the overcurrent condition;
4) Detect the auxiliary contact of the circuit breaker to judge the circuit breaker state before and
after the generator is closed inadvertently.
3.11.3.3 Protection Criteria
Following three types of inadvertent energization conditions are taken into account:
1. In the course of generator’s hand turning (low frequency condition), if it has not been excited,
inadvertent closure of the circuit breaker may lead to asynchronous starting of the generator.
Under this condition, before the generator is closed inadvertently, generator voltage is low,
low-voltage element will be enabled with a time delay of t1; after the generator is closed
inadvertently, generator voltage will rise, low-voltage element will quit with a time delay of t2
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3 Operation Theory
(designed to coordinate with low-frequency element).
2. In the case that generator circuit breaker is closed inadvertently in excited condition but the
frequency is lower than the setting which occurs during startup-and-shutdown process. Under
this condition, before the generator is closed inadvertently, generator frequency is low,
low-frequency element will be enabled with a time delay of t3; after the generator is closed
inadvertently, generator frequency will be pulled into synchronism, low- frequency element will
quit with a time delay of t4 (the time delay should make sure the completion of the tripping
course of inadvertent energization protection).
3. In the case that generator circuit breaker is closed inadvertently or asynchronously in excited
condition but the frequency is larger than the setting which occurs during
startup-and-shutdown process. Under this condition, circuit breaker position is adopted to
judge, circuit breaker position element is enabled with a time delay of t5 (the opening time of
the circuit breaker is taken into account) and quit with a time delay of t6.
After the generator is closed inadvertently, the current will increase suddenly, take the overcurrent
element of generator terminal current and generator neutral point current to reflect the fault
characteristic of current increase.
Inadvertent energization protection contains several elements.
 The criterion of low-frequency element is:
f < f UF
Where:
f is the calculated frequency;
fUF is the frequency setting of low-frequency element of inadvertent energization protection.
 The criterion of low-voltage element is:
U _ Gen < UUV
Where:
U _ Gen is the average value of generator three-phase voltage;
U UV is the voltage setting of low-voltage element of inadvertent energization protection.
 The criterion of overcurrent element is:
I max > I OC
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3 Operation Theory
Where:
I OC is the current setting of overcurrent element of inadvertent energization protection.
If the current source selection setting for inadvertent energization protection [50/27.Opt_Source_I]
is set as “0”, I max takes the maximum phase current value of three-phase current input 1
(three-phase current input 1 can be configured as generator terminal current or neutral point side
current). If the current source selection setting for inadvertent energization protection
[50/27.Opt_Source_I] is set as “1”, I max takes the smaller value of three-phase current input 1
maximum phase current and three-phase current input 2 maximum phase current (three-phase
current input 1 and three-phase current input 2 can be configured as generator terminal current
and neutral point side current).
If the logic selection setting for inadvertent energization protection [50/27.Opt_Mode] is set as “0”,
the internal logic between low-frequency/voltage element and circuit breaker position element is
“Or”; if the logic selection setting for inadvertent energization protection [50/27.Opt_Mode] is set
as “1”, the internal logic between low-frequency/voltage element and circuit breaker position
element is “And”.
3.11.4 Logic
For inadvertent energization protection, if following three conditions are met, the protection will be
enabled.
(1) Logic setting [50/27.En] is set as “1”.
(2) Protection function enabling inputs [50/27.En1], [50/27.En2] are “1”
(3) Protection function blocking input [50/27.Blk] is “0”.
If inadvertent energization protection is disabled, all the related output signals will be reset. If no
external input is configured to [50/27.En1] ([50/27.En2]), the default initial value of [50/27.En1]
([50/27.En2]) is “1”; if no external input is configured to [50/27.Blk], the default initial value of
[50/27.Blk] is “0”.
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SIG f < [50/27.f_Blk] & t3 0s t4 ≥1 ≥1 & ≥1

SIG U_Gen < [50/27.U_Blk]
t1 0s t2
EN [50/27.En_CB_Ctrl] & & &

t5 0s t6
SIG Flg_52a
SIG No current for CB
EN [50/27.Opt_Mode]
EN [50/27.Opt_Source_I] & ≥1
SIG Imax1 > [50/27.I_Set] &
&
&
[50/27.St]
SIG Imax2 > [50/27.I_Set]
EN [50/27.En] & [50/27.t_Op] 0s

[50/27.Op]
SIG [50/27.En1]
SIG [50/27.En2]
SIG [50/27.Blk]
0 500ms
SIG 50/27.FD
Figure 3.11-1 Logic diagram of inadvertent energization protection
Where:
50/27.FD is the internal signal indicating that the inadvertent energization protection picks up (the
fault detector of fault detector DSP module).
Imax1 is the maximum current value of three-phase current input 1.
Imax2 is the maximum current value of three-phase current input 2.
50/27
50/27.I3P1 50/27.St
50/27.I3P2 50/27.Op
50/27.U3P
50/27.En1
50/27.En2
50/27.Blk
Flg_52a
Figure 3.11-2 Function block diagram of inadvertent energization protection
Table 3.11-1 Input signals of inadvertent energization protection

Three-phase current input 1, generally it is configured as generator terminal
1 50/27.I3P1
three-phase current, and it can be changed by PCS-Explorer2.
2 50/27.I3P2 Three-phase current input 2, generally it is configured as generator neutral point side
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3 Operation Theory

three-phase current, and it can be changed by PCS-Explorer2.
Three-phase voltage input, generally it is configured as generator terminal three-phase
3 50/27.U3P
voltage, and it can be changed by PCS-Explorer2.
4 f Generator frequency.
5 50/27.En1 Protection function enabling input1 and input 2, it can be binary inputs or settings, such
6 50/27.En2 as function enabling binary inputs, logic links, etc.
7 50/27.Blk Protection function blocking input, such as function blocking binary input.
Table 3.11-2 Output signals of inadvertent energization protection

1 50/27.St Inadvertent energization protection starts.
2 50/27.Op Inadvertent energization protection operates to trip.
Table 3.11-3 Output signals of inadvertent energization protection (event recorder)
Tripping reports
1 50/27.Op Inadvertent energization protection operates to trip.
Start signals
2 50/27.St Inadvertent energization protection starts.
Waveform recording
3 50/27.TrigDFR Inadvertent energization protection operates to trigger waveform recording.
able 3.11-4 Output signals of inadvertent energization protection (measurements)
1 50/27.On The working status of inadvertent energization protection
2 I_Gen The generator current A
3 U_Gen The generator voltage V
Access Path:
Main menu -> Measurements -> Measurements2-> Prot Values-> Gen AccEnerg Prot Values
3.11.6 Settings
Table 3.11-5 Settings list of inadvertent energization protection

0: disable Logic setting of enabling/disabling inadvertent
1 50/27.En 1
1: enable energization protection.
2 50/27.f_Blk 40.00~60.00 0.01 Hz The frequency setting of low-frequency
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3 Operation Theory
element of inadvertent energization protection.

The current setting of overcurrent element of
3 50/27.I_Set 0.10~10In.00 0.01 A
inadvertent energization protection
The voltage setting of low-voltage element of
4 50/27.U_Blk 6.00~100.00 0.01 V
inadvertent energization protection.
Time delay setting of inadvertent energization
5 50/27.t_Op 0.01~1.00 0.01 s
protection.
Tripping logic setting of inadvertent
6 50/27.OutMap 0~3FFFFFFF
energization protection.
Logic setting of enabling/disabling inadvertent
0: disable
7 50/27.En_CB_Ctrl 1 energization protection being controlled by the
1: enable
circuit breaker position element.
The setting to select the internal logic between
0: Or
8 50/27.Opt_Mode 1 low-frequency/voltage element and circuit
1: And
breaker position element.
The setting to select the current source for
inadvertent energization protection.
9 50/27.Opt_Source_I 0, 1 0: three-phase current input 1 is adopted
1: generator terminal current and neutral point
side current are adopted.
Access path: Settings-> Prot Settings -> Gen AccEnerg Settings
3.12 Generator Out-of-Step Protection (78)
3.12.1 Application
Generator out-of-step protection is used to detect the asynchronous operation due to generator
out-of-step.

Out-of-step protection judge whether out-of-step swing occurs via the locus of calculated
impedance, and judge whether the out-of-step swing center is within the generator. Out-of-step
protection can operate to trip or alarm.

Out-of-step protection detects out-of-step swing according to the locus of calculated impedance.
The protection device will measure the three-phase current and voltage of generator terminal, and
then the positive-sequence impedance can be calculated according to following equation:
U 1
Z1 = Equation 3.12-1
I
1
Where:
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3 Operation Theory
U 1 is the secondary positive-sequence voltage of generator terminal.
I1 is the secondary positive-sequence current of generator terminal.
Following figure shows operation characteristic of out-of-step protection that comprises three parts:
①lens, ②boundary and ③reactance line.
jX
Left Right
2
Za
Up Out
In
Down
Zc
3
α
OL
IL
1 IR
OR
ϕ
O R
Zb
Figure 3.12-1 Operation characteristic of out-of-step protection
1. ①lens divides the impedance plane into lens inside part (In) and lens outside part (Out).
2. ②boundary divides the impedance plane into left half part (Left) and right half part (Right).
3. ③reactance line divides the impedance plane into upper half part (Up) and lower half part
(Down).
α is the interior angle of ①lens, it takes 120deg by default. φ is the sensitive angle of ②boundary,
it takes 85deg by default.
The impedance plane is divided into four areas by ①lens and ②boundary: OL, IL, IR and OR. If
the impedance locus passes through these four areas in sequence from right to left or vice versa
(OLILIROR or ORIRILOL), and staying in each area for a duration longer than a
certain time delay, this case is considered as out-of-step swing. The times of the impedance locus
passing through the four areas in sequence is considered as the pole sliding times. Per time the
impedance locus passes through the four areas in sequence, the pole sliding times will plus 1. If
the sequence for impedance locus passing through these four areas is OLILIROR, it is
called decelerate out-of-step; if the sequence for impedance locus passing through these four
areas is ORIRILOL, it is called accelerate out-of-step. Once the pole sliding times is over
the corresponding setting, out-of-step protection can operate to alarm or trip.
As to ③reactance line, if the impedance locus falls into the lower half part (Down), the swing
center is considered within the generator. If the impedance locus falls into the upper half part (Up),
the swing center is considered outside the generator. Pole sliding times setting for these two cases
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3 Operation Theory
can be configured separately.
The minimum swing period that can be identified by out-of-step protection is 120ms.
The tripping permissive current setting is an auxiliary criterion for out-of-step protection, it should
be set according to the circuit breaker permissive breaking capacity. The device can automatically
select to trip when the current is small, so that the damage to the circuit breaker due to too larger
tripping current can be prevented.
3.12.4 Logic
For generator out-of-step protection, if following three conditions are met, the protection will be
enabled.
(1) Logic setting [78.En] is set as “1”.
(2) Protection function enabling inputs [78.En1], [78.En2] are “1”
(3) Protection function blocking input [78.Blk] is “0”.
(4) The input signal for loss-of-excitation protection operation to block out-of-step protection
[78.ExcLoss_Blk] is “0”
If generator out-of-step protection is disabled, all the related output signals will be reset. If no
external input is configured to [78.En1] ([78.En2]), the default initial value of [78.En1] ([78.En2]) is
“1”; if no external input is configured to [78.Blk] and [78.ExcLoss_Blk], the default initial value of
[78.Blk] and [78.ExcLoss_Blk] is “0”.
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EN [78.En_Alm_Ext] &
SIG 78.N_Slip_Ext≥[78.Num_Slip_Ext] [78.Alm_Ext]
EN [78.En] &
SIG [78.Blk]
&
EN [78.En_Alm_Int] [78.Alm_Int]
SIG 78.N_Slip_Int≥[78.Num_Slip_Int]
EN [78.En]
SIG [78.En1] &
SIG [78.En2]
[78.St]
SIG [78.Blk] &
&
EN [78.En_Trp_Ext] & [78.Op_Ext]
SIG 78.N_Slip_Ext≥[78.Num_Slip_Ext]
SIG Ibrk_max<[78.Ibrk_Perm_CB] &
SIG [78.ExcLoss_Blk]
0 500ms
SIG 78.FD
EN [78.En]
SIG [78.En1] &
SIG [78.En2]
[78.St]
SIG [78.Blk] &
&
EN [78.En_Trp_Int] & [78.Op_Int]
SIG 78.N_Slip_Int≥[78.Num_Slip_Int]
SIG Ibrk_max<[78.Ibrk_Perm_CB] &
SIG [78.ExcLoss_Blk]
0 500ms
SIG 78.FD
Figure 3.12-2 Logic diagram of generator out-of-step protection
Where:
78.FD is the internal signal indicating that the out-of-step protection picks up (the fault detector of
fault detector DSP module).
78.N_Slip_Ext is the pole sliding times for external power swing.
78.N_Slip_Int is the pole sliding times for internal power swing.
Ibrk_max is the maximum value of the three phase currents that flows through the circuit breaker.
78.ExcLoss_Blk is the input signal for loss-of-excitation protection operation to block out-of-step
protection.
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3 Operation Theory
78
78.U3P 78.St
78.I3P1 78.Op_Ext
78.I3P2 78.Op_Int
78.En1 78.Alm_Ext
78.En2 78.Alm_Int
78.Blk 78.Alm_Accel
78.ExcLoss_Blk 78.Alm_Decel
Figure 3.12-3 Function block diagram of generator out-of-step protection
Table 3.12-1 Input signals of generator out-of-step protection

1 78.U3P Generator terminal three-phase voltage input.
Three-phase current input 1, it is configured as generator terminal current by default,
2 78.I3P1
Three-phase current input 2, it can be three-phase current of generator terminal circuit
3 78.I3P2 breaker or main transformer HV side circuit breaker. It corresponds to the tripping
permissive current setting [78.Ibrk_Perm_CB].
4 78.En1 Protection function enabling input1 and input 2, it can be binary inputs or settings, such
5 78.En2 as function enabling binary inputs, logic links, etc.
6 78.Blk Protection function blocking input, such as function blocking binary input.
The input signal for loss-of-excitation protection operation to block out-of-step
7 78.ExcLoss_Blk
protection.
Table 3.12-2 Output signals of generator out-of-step protection

1 78.St Out-of-step protection starts.
2 78.Op_Ext Out-of-step protection for external power swing operates to trip.
3 78.Op_Int Out-of-step protection for internal power swing operates to trip.
4 78.Alm_Ext Out-of-step protection for external power swing operates to issue alarm signal.
5 78.Alm_Int Out-of-step protection for internal power swing operates to issue alarm signal.
6 78.Alm_Accel Alarm signal indicating that accelerate out-of-step occurs.
7 78.Alm_Decel Alarm signal indicating that decelerate out-of-step occurs.
Table 3.12-3 Output signals of generator out-of-step protection (event recorder)
Tripping reports
1 78.Op_Ext Out-of-step protection for external power swing operates to trip.
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2 78.Op_Int Out-of-step protection for internal power swing operates to trip.
Start signals
3 78.St Out-of-step protection starts.
Alarm signals
Out-of-step protection for external power swing operates to issue alarm

4 78.Alm_Ext
signal.
Out-of-step protection for internal power swing operates to issue alarm

5 78.Alm_Int
signal.
6 78.Alm_Accel Alarm signal indicating that accelerate out-of-step occurs.
7 78.Alm_Decel Alarm signal indicating that decelerate out-of-step occurs.
Waveform recording
Tripping stage of out-of-step protection operates to trigger waveform

8 78.TrigDFR
recording.
9 78.St_Ext Out-of-step protection for external power swing starts.
10 78.St_Int Out-of-step protection for internal power swing starts.
Table 3.12-4 Output signals of generator out-of-step protection (measurements)
1 78.Z1_Sec Positive-sequence impedance. Ω
2 78.N_Slip_Ext Pole sliding times for external power swing
3 78.N_Slip_Int Pole sliding times for internal power swing
Access Path:
Main menu -> Measurements -> Measurements2-> Prot Values-> Gen OOS Prot Values
3.12.6 Settings
Table 3.12-5 Settings list of generator out-of-step protection

0: disable Logic setting of enabling/disabling out-of-step
1 78.En 1
1: enable protection.
2 78.Za 0.00~200.00 0.01 Ω Impedance setting Za of out-of-step protection.
3 78.Zb 0.00~200.00 0.01 Ω Impedance setting Zb of out-of-step protection.
4 78.Zc 0.00~200.00 0.01 Ω Impedance setting Zc of out-of-step protection.
Sensitive angle setting of operation
5 78.phi_Reach 0.00~90.00 0.01 deg
characteristic of out-of-step protection.
The lens interior angle of operation
6 78.phi_Inner 0.00~150.00 0.01 deg
characteristic of out-of-step protection.
7 78.Num_Slip_Ext 1~1000 1 Pole sliding times setting for external power
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3 Operation Theory
swing.
Pole sliding times setting for internal power
8 78.Num_Slip_Int 1~1000 1
swing.
Tripping permissive current setting for
9 78.Ibrk_Perm_CB 0.10~20In 0.01 A
out-of-step protection.
Tripping logic setting of definite-time out-of-step
10 78.OutMap 0~3FFFFFFF
protection
Logic setting of enabling/disabling out-of-step
0: disable
11 78.En_Alm_Ext 1 protection for external power swing operates to
1: enable
alarm.
0: disable
12 78.En_Trp_Ext 1 protection for external power swing operates to
1: enable
trip.
0: disable
13 78.En_Alm_Int 1 protection for internal power swing operates to
1: enable
alarm.
0: disable
14 78.En_Trp_Int 1 protection for internal power swing operates to
1: enable
trip.
Access path: Settings-> Prot Settings -> Gen OOS Settings
3.13 Generator Startup and Shutdown protection (StShut)
3.13.1 Application
Generator startup and shutdown protection can reflect single-phase ground fault or
phase-to-phase short-circuit fault during startup and shutdown process of generator.

Generator startup and shutdown protection includes low-frequency zero-sequence overvoltage
element and low-frequency overcurrent element.
Low-frequency zero-sequence overvoltage element is used to reflect single-phase ground fault

during startup and shutdown process of generator.
Low-frequency overcurrent element is used to reflect phase-to-phase short-circuit fault during

startup and shutdown process of generator.

3.13.3.1 Overview
During startup and shutdown process of generator, frequency is usually very low, if single-phase
ground fault happens, the residual voltage will increase; if phase-to-phase short-circuit fault
happens, the current of generator neutral point side will increase. According to these two fault
features, the device adopts a frequency-independent calculation method to calculate the
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3 Operation Theory
generator neutral point-to-earth residual voltage and generator neutral point side current.
3.13.3.2 Protection Calculation Process
Detect the generator neutral point-to-earth residual voltage, detect generator neutral point side
current and takes the maximum value.
3.13.3.3 Protection Criteria
 Criterion of low-frequency zero-sequence overvoltage element
 f < fUF
 Equation 3.13-1
3U 0 > 3U0 Set
Where:
f is the calculated frequency;
fUF is the frequency setting for generator startup and shutdown protection;
3U0 is the generator neutral point-to-earth residual voltage;
3U0Set is the residual voltage setting for generator startup and shutdown protection.
If the two equations are met simultaneously, low-frequency zero-sequence overvoltage element
will operate with a time delay.
 Criterion of low-frequency overcurrent element
 f < fUF
 Equation 3.13-2
 I max > I OC
Where:
Imax is the maximum value of generator neutral point side three-phase current;
IOC is the current setting for generator startup and shutdown protection.
If the two equations are met simultaneously, low-frequency overcurrent element will operate with a
time delay.
3.13.4 Logic
For generator startup and shutdown protection, if following three conditions are met, the protection
will be enabled.
(1) Logic setting [StShut.En] is set as “1”.
(2) Protection function enabling inputs [StShut.En1], [StShut.En2] are “1”
(3) Protection function blocking input [StShut.Blk] is “0”.
If generator startup and shutdown protection is disabled, all the related output signals will be reset.
If no external input is configured to [StShut.En1] ([StShut.En2]), the default initial value of
[StShut.En1] ([StShut.En2]) is “1”; if no external input is configured to [StShut.Blk], the default
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3 Operation Theory
initial value of [StShut.Blk] is “0”.
EN [StShut.En]
&
SIG [StShut.En1]
SIG [StShut.En2]
SIG [StShut.Blk]
[StShut.St]
&
EN [StShut.En_StaROV] &
& [StShut.t_StaROV] 0s
SIG U0P > [StShut.3U0_StaROV] [StShut.Op_StaROV]
SIG Flg_52a &
SIG f > [StShut.f_UF]
0 500ms
SIG StShut.FD_StaROV
EN [StShut.En]
&
SIG [StShut.En1]
SIG [StShut.En2]
SIG [StShut.Blk]
[StShut.St]
&
EN [StShut.En_OC] &
& [StShut.t_OC] 0s
SIG Imax > [StShut.I_OC] [StShut.Op_OC]
SIG Flg_52a &
SIG f > [StShut.f_UF]
0 500ms
SIG StShut.FD_OC
Figure 3.13-1 Logic diagram of generator startup and shutdown protection
Where:
StShut.FD_StaROV is the internal signal indicating that the low-frequency zero-sequence

overvoltage element of generator startup and shutdown protection picks up (the fault detector of
StShut.FD_OC is the internal signal indicating that the low-frequency overcurrent element of
generator startup and shutdown protection picks up (the fault detector of fault detector DSP
module).
StShut
StShut.U1P_Hm StShut.St
StShut.I3P StShut.Op_StaROV
f StShut.Op_OC
StShut.En1
StShut.En2
StShut.Blk
Flg_52a
Figure 3.13-2 Function block diagram of generator startup and shutdown protection
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3 Operation Theory
Table 3.13-1 Input signals of generator startup and shutdown protection

1 StShut.U1P_Hm Generator neutral point-to-earth residual voltage.
2 StShut.I3P Generator neutral point side three-phase current.
3 f Calculated frequency of the generator.
4 StShut.En1 Protection function enabling input1 and input 2, it can be binary inputs or settings,
5 StShut.En2 such as function enabling binary inputs, logic links, etc.
6 StShut.Blk Protection function blocking input, such as function blocking binary input.
Table 3.13-2 Output signals of generator startup and shutdown protection

1 StShut.St Generator startup and shutdown protection starts.
Low-frequency zero-sequence overvoltage element of generator startup and
2 StShut.Op_StaROV
shutdown protection operates to trip.
Low-frequency overcurrent element of generator startup and shutdown protection
3 StShut.Op_OC
operates to trip.
Table 3.13-3 Output signals of generator startup and shutdown protection (event recorder)
Tripping reports

1 StShut.Op_StaROV
shutdown protection operates to trip.
Low-frequency overcurrent element of generator startup and shutdown

2 StShut.Op_OC
Start signals
3 StShut.St Generator startup and shutdown protection starts.
Waveform recording
Generator startup and shutdown protection operates to trigger waveform

4 StShut.TrigDFR
recording.

5 StShut.St_StaROV
shutdown protection starts.
Low-frequency overcurrent element of generator startup and shutdown

6 StShut.St_OC
protection starts
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3 Operation Theory
Table 3.13-4 Output signals of generator startup and shutdown protection (measurements)
1 StShut.On The working status of generator startup and shutdown protection
2 StShut.Imax The maximum value of startup and shutdown current A
3 StShut.3U0 Startup and shutdown residual voltage V
Access Path:
Main menu -> Measurements -> Measurements2-> Prot Values-> Gen StShut Prot Values
3.13.6 Settings
Table 3.13-5 Settings list of generator startup and shutdown protection

1 StShut.En 1
1: enable generator startup and shutdown protection.
Frequency blocking setting for generator

2 StShut.f_UF 40.00~60.00 0.01 Hz
startup and shutdown protection.
Residual voltage setting for generator
3 StShut.3U0_StaROV 5.00~25.00 0.01 V
startup and shutdown protection.
Time delay setting for low-frequency
4 StShut.t_StaROV 0.10~30.00 0.01 s overcurrent element of generator startup
and shutdown protection.
Tripping logic setting of low-frequency
5 StShut.OutMap_StaROV 0~3FFFFFFF zero-sequence overvoltage element of
generator startup and shutdown protection.
Current setting for generator startup and
6 StShut.I_OC 0.10~20In 0.01 A
shutdown protection.
Time delay setting for low-frequency
7 StShut.t_OC 0.00~30.00 0.01 s zero-sequence overvoltage element of
Tripping logic setting of low-frequency
8 StShut.OutMap_OC 0~3FFFFFFF overcurrent element of generator startup
and shutdown protection.
0: disable low-frequency zero-sequence overvoltage
9 StShut.En_StaROV 1
1: enable element of generator startup and shutdown
protection.

10 StShut.En_OC 1 low-frequency overcurrent element of
1: enable
Access path: Settings-> Prot Settings -> Gen StShut Settings
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3 Operation Theory
3.14 Generator Shaft Overcurrent Protection (51GS)
3.14.1 Application
Generator shaft overcurrent protection detects the shaft current of generator rotor shaft, it can
prevent the bearing from damage. The function is mainly used for hydropower unit.

 Sensitive stage of shaft overcurrent protection for alarm
 Sensitive stage of shaft overcurrent protection for trip
 Insensitive stage of shaft overcurrent protection for trip

3.14.3.1 Overview
If generator shaft current density exceeds the allowed value, the journal sliding surface and the
axle bush of generator shaft will be damaged. Generally the shaft overcurrent protection that
reflect the fundamental component is selected, users can also select the shaft overcurrent
protection that reflect the 3rd harmonic component by corresponding logic setting. Shaft
overcurrent protection includes two operation stages: sensitive stage and insensitive stage.
Sensitive stage of shaft overcurrent protection can operate to alarm or trip, and insensitive stage of
shaft overcurrent protection can operate to trip.
Generally generator shaft overcurrent protection is used for alarm purpose.
3.14.3.2 Calculation Process of Generator Shaft Overcurrent Protection
The device detects the generator shaft current (via shaft current CT or transmitter), than the
fundamental and 3rd harmonic component of the shaft current is calculated, then the device can
select the fundamental component or 3rd harmonic component (according to corresponding logic
setting) to conduct the logic judgment.
3.14.3.3 Sensitive Stage
I > I Sens Equation 3.14-1
Where:
I is the fundamental component or 3rd harmonic component (controlled by the two logic settings
[51GS.En_Hm1] and [51GS.En_Hm3]) of the shaft current;
I Sens is the current setting of sensitive stage of shaft overcurrent protection.
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3 Operation Theory
3.14.3.4 Insensitive Stage
I > I Insens Equation 3.14-2
Where:
I is the fundamental component or 3rd harmonic component (controlled by the two logic settings
[51GS.En_Hm1] and [51GS.En_Hm3]) of the shaft current;
I Insens is the current setting of insensitive stage of shaft overcurrent protection.
3.14.4 Logic
For generator shaft overcurrent protection, if following three conditions are met, the protection will
be enabled.
(1) Logic setting [51GS.En] is set as “1”.
(2) Protection function enabling inputs [51GS.En1], [51GS.En2] are “1”
(3) Protection function blocking input [51GS.Blk] is “0”.
If generator shaft overcurrent protection is disabled, all the related output signals will be reset. If no
external input is configured to [51GS.En1] ([51GS.En2]), the default initial value of [51GS.En1]
([51GS.En2]) is “1”; if no external input is configured to [51GS.Blk], the default initial value of
[51GS.Blk] is “0”.
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3 Operation Theory
EN [51GS.En_Alm_L]
EN [51GS.En_Hm1] & ≥1 &
SIG I1st > [51GS.I_L]

[51GS.t_L] 0s
EN [51GS.En_Hm3] & [51GS.Alm]
SIG I3rd > [51GS.I_L]
EN [51GS.En] &
SIG [51GS.Blk]
EN [51GS.En] &
SIG [51GS.En1]
SIG [51GS.En2]
SIG [51GS.Blk]
&
EN [51GS.En_Trp_L] [51GS.t_L] 0s
[51GS.Op_L]
EN [51GS.OutMap_L].bit0
0 500ms
SIG 51GS.FD
≥1
[51GS.St]
EN [51GS.En_Hm1] & ≥1 &

SIG I1st > [51GS.I_H]
[51GS.t_Op_H] 0s
EN [51GS.En_Hm3] & [51GS.Op_H]
SIG I3rd > [51GS.I_H]
EN [51GS.En_Trp_H]
EN [51GS.OutMap_H].bit0
Figure 3.14-1 Logic diagram of generator shaft overcurrent protection
Where:
51GS.FD is the internal signal indicating that the generator shaft overcurrent protection picks up
51GS
51GS.I1P_Hm 51GS.St
51GS.En1 51GS.Op_L
51GS.En2 51GS.Op_H
51GS.Blk 51GS.Alm
Figure 3.14-2 Function block diagram of generator shaft overcurrent protection
Table 3.14-1 Input signals of generator shaft overcurrent protection

1 51GS.I1P_Hm Current input for generator shaft overcurrent protection.
2 51GS.En1 Protection function enabling input1 and input 2, it can be binary inputs or settings, such
3 51GS.En2 as function enabling binary inputs, logic links, etc.
4 51GS.Blk Protection function blocking input, such as function blocking binary input.
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3 Operation Theory
Table 3.14-2 Output signals of generator shaft overcurrent protection

1 51GS.St Generator shaft overcurrent protection starts.
Sensitive stage of generator shaft overcurrent protection operates to issue alarm
2 51GS.Alm
signal
3 51GS.Op_L Sensitive stage of generator shaft overcurrent protection operates to trip.
4 51GS.Op_H Insensitive stage of generator shaft overcurrent protection operates to trip.
Table 3.14-3 Output signals of generator shaft overcurrent protection (event recorder)
Tripping reports
1 51GS.Op_L Sensitive stage of generator shaft overcurrent protection operates to trip.
2 51GS.Op_H Insensitive stage of generator shaft overcurrent protection operates to trip.
Start signals
3 51GS.St Generator shaft overcurrent protection starts.
Alarm signals
Sensitive stage of generator shaft overcurrent protection operates to issue

4 51GS.Alm
alarm signal
Waveform recording
Generator shaft overcurrent protection operates to trigger waveform

5 51GS.TrigDFR
recording.
6 51GS.St_L Sensitive stage of generator shaft overcurrent protection starts.
7 51GS.St_H Insensitive stage of generator shaft overcurrent protection starts.
Table 3.14-4 Output signals of generator shaft overcurrent protection (measurements)
1 51GS.I_Hm1 The fundamental amplitude of the shaft current mA
2 51GS.I_Hm3 The 3rd harmonic amplitude of the shaft current mA
Access path:
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3 Operation Theory
3.14.6 Settings
Table 3.14-5 Settings list of generator shaft overcurrent protection

1 51GS.En 1
1: enable generator shaft overcurrent protection.
The current setting of sensitive stage of
2 51GS.I_L 0.10~100.00 0.01 mA
shaft overcurrent protection.
Time delay setting of sensitive stage of
3 51GS.t_L 0.00~30.00 0.01 s
Tripping logic setting of sensitive stage of
4 51GS.OutMap_L 0~3FFFFFFF
generator shaft overcurrent protection.
The current setting of insensitive stage of
5 51GS.I_H 0.10~100.00 0.01 mA
Time delay setting of insensitive stage of
6 51GS.t_Op_H 0.00~30.00 0.01 s
Tripping logic setting of insensitive stage of
7 51GS.OutMap_H 0~3FFFFFFF
generator shaft overcurrent protection.
0: disable
8 51GS.En_Hm1 1 fundamental component generator shaft
1: enable
overcurrent protection.
rd
Logic setting of enabling/disabling 3
0: disable
9 51GS.En_Hm3 1 harmonic component generator shaft
1: enable
0: disable
10 51GS.En_Alm_L 1 stage of shaft overcurrent protection
1: enable
operates to alarm.
0: disable
11 51GS.En_Trp_L 1 stage of shaft overcurrent protection
1: enable
operates to trip.
0: disable
12 51GS.En_Trp_H 1 insensitive stage of shaft overcurrent
1: enable
Access path: Settings-> Prot Settings -> Gen Shaft OC Settings
3.15 Generator Negative-sequence Overload Protection (46G)
3.15.1 Application
Negative-sequence current protection detects the unbalanced load of three-phase induction motor,
negative-sequence current will generate a magnetic field rotating in reverse direction, the
frequency of the magnetic field is twice relative to the frequency of the rotor. The double-frequency
magnetic field will generate eddy current on the surface of the rotor, which will lead to the
over-heating of the surface of the rotor. Generator negative-sequence overload protection can
Date: 2016-08-16
3 Operation Theory
reflect the over-heating condition of generator rotor surface, it can also reflect the other
abnormalities that caused by negative-sequence current.
 Definite-time negative-sequence overload protection.
 Inverse-time negative-sequence overload protection.

3.15.3.1 Overview
Generator negative-sequence overload protection comprises definite-time negative-sequence

overload protection and inverse-time negative-sequence overload protection. The low-setting
stage of definite-time negative-sequence overload protection is used for alarm and the high-setting
stage of definite-time negative-sequence overload protection is used for tripping. Inverse-time
negative-sequence overload protection can simulate the heat accumulation and dissipation
process of the rotor, and it can operate to trip.
3.15.3.2 Negative-sequence Overload Protection Calculation Process
Negative-sequence current can be calculated after filtering the three-phase current, if the negative
sequence current is larger than the threshold value, the protection starts, once the starting time is
longer than the time delay setting, the protection will operate to issue alarm signal or trip.
Generally the generator manufacturer will provide the long-term permissive negative-sequence
current I2∞ (per-unit value) and the rotor negative-sequence heating time constant A. for example,
a rotor-directly-cooled turbo-generator, the long-term permissive negative-sequence current is 8%
(per-unit value), the rotor negative-sequence heating time constant is 8, then the permissive
operation duration corresponds to a given negative-sequence current can be calculated according
to following equation.
A
t=
(I )
2
∗ 2
Equation 3.15-1
Where:
A is the rotor negative-sequence heating time constant.
∗
I 2 is the per-unit value of rotor negative-sequence current.
3.15.3.3 Generator Definite-time Negative-sequence Overload Protection
There are two stages of definite-time negative-sequence overload protection. The low-setting
stage of definite-time negative-sequence overload protection is used for alarm, and the settings
should be set to make the protection can drop off reliably for long-term permissive
negative-sequence current. The high-setting stage of definite-time negative-sequence overload
protection is used for tripping, and the settings should be set larger than the maximum
negative-sequence current that flowing through the generator for an external asymmetric
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short-circuit fault.
3.15.3.4 Generator Inverse-time Negative-sequence Overload Protection
Inverse-time negative-sequence overload protection consists of three parts: lower-limit initiation

part, inverse-time part and upper limit definite-time part. Minimum operation time delay setting
[46G.IDMT.tmin] is provided for upper limit definite-time part.
When the negative-sequence current is over the pickup current setting for negative-sequence
overload protection [46G.IDMT.I_Set], the heat accumulation starts. When the heat accumulation
reaches its setting [46G.IDMT.A_Therm], inverse-time negative-sequence overload protection can
operate to trip. The inverse-time negative-sequence overload protection can simulate the heat
accumulation and dissipation process of the rotor. Since the heat accumulation starts, if the
negative-sequence current is lower than the pickup current setting [46G.IDMT.I_Set], the heat
dissipation starts; then if the negative-sequence current increases to over the pickup current
setting [46G.IDMT.I_Set], the heat accumulation will starts again from the current heat
accumulation value.
The operation characteristic of inverse-time negative-sequence overload protection is as follows:
I2
IU pper−limit
I P ickup
t min tmax t
Figure 3.15-1 Operation characteristic of inverse-time negative-sequence overload protection
Where:
t min is the minimum time delay for upper limit definite-time part, i.e. the setting [46G.IDMT.tmin].
t max is the maximum time delay for lower-limit initiation part.
I Pickup is the pickup current setting of inverse-time negative-sequence overload protection, i.e. the
setting [46G.IDMT.I_Set]
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part.
[(I 2 I b） − (I 2 ∞ I b） ] × t ≥ A
2 2
Equation 3.15-2
Where:
I 2 is the negative-sequence current.
I 2 ∞ is the long-term operation permissive negative-sequence current of the generator.
A is the rotor negative-sequence heating constant.
I b is the secondary rated current of generator.
The maximum time delay for lower-limit initiation part should be smaller than the calculated
operating time corresponds to the lower-limit pickup current setting according to Equation 3.15-2.
3.15.4 Logic
For generator negative-sequence overload protection, if following three conditions are met, the
(1) Logic setting [46G.En] is set as “1”.
(2) Protection function enabling inputs [46G.En1], [46G.En2] are “1”
(3) Protection function blocking input [46G.Blk] is “0”.
If generator negative-sequence overload protection is disabled, all the related output signals will
be reset. If no external input is configured to [46G.En1] ([46G.En2]), the default initial value of
[46G.En1] ([46G.En2]) is “1”; if no external input is configured to [46G.Blk], the default initial value
of [46G.Blk] is “0”.
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SIG [46G.En1] &

SIG [46G.En2]
SIG [46G.Blk]
En [46G.DT.OutMap].bit0 & &

[46G.St]
SIG I2>[46G.DT.I_Set]
En [46G.IDMT.OutMap].bit0 ≥1
&
SIG I2>[46G.IDMT.I_Set]
SIG I2>[46G.I_Alm] &

[46G.t_Alm] 0ms
EN [46G.En] [46G.Alm]
SIG [46G.Blk]
EN [46G.En]
SIG [46G.En1] &
& [46G.DT.t_Op] 0ms
SIG [46G.En2] [46G.DT.Op]
SIG [46G.Blk]
SIG I2>[46G.DT.I_Set]
0ms 500ms
SIG 46G.DT.FD
EN [46G.En]
SIG [46G.En1] &
& IDMT ≥1
SIG [46G.En2]
SIG [46G.Blk] t ≥ t max &
[46G.IDMT.Op]
SIG I2>[IDMT.I_Set]
0ms 500ms
SIG 46G.IDMT.FD
Figure 3.15-2 Logic diagram of generator negative-sequence overload protection
Where:
46G.DT.FD is the internal signal indicating that the definite-time generator negative-sequence
overload protection picks up (the fault detector of fault detector DSP module).
46G.IDMT.FD is the internal signal indicating that the inverse-time generator negative-sequence
overload protection picks up (the fault detector of fault detector DSP module).
46G
46G.I3P1 46G.St
46G.I3P2 46G.DT.Op
46G.En1 46G.IDMT.Op
46G.En2 46G.Alm
46G.Blk
Figure 3.15-3 Function block diagram of generator negative-sequence overload protection
Table 3.15-1 Input signals of generator negative-sequence overload protection

1 46G.I3P1 Three-phase current input 1, it is configured as generator terminal current by default,
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Three-phase current input 2, it is configured as generator neutral point side current by
2 46G.I3P2
3 46G.En1 Protection function enabling input1 and input 2, it can be binary inputs or settings, such
4 46G.En2 as function enabling binary inputs, logic links, etc.
5 46G.Blk Protection function blocking input, such as function blocking binary input.
Table 3.15-2 Output signals of generator stator overload protection

1 46G.St Tripping stage of generator negative-sequence overload protection starts.
2 46G.DT.Op Definite-time generator negative-sequence overload protection operates to trip.
3 46G.IDMT.Op Inverse-time generator negative-sequence overload protection operates to trip.
The alarm stage of generator negative-sequence overload protection operates to issue
4 46G.Alm
alarm signal.
Table 3.15-3 Output signals of generator negative-sequence overload protection (event recorder)
Tripping reports
1 46G.DT.Op Definite-time generator negative-sequence overload protection operates to trip.
2 46G.IDMT.Op Inverse-time generator negative-sequence overload protection operates to trip.
Start signals
3 46G.St Tripping stage of generator negative-sequence overload protection starts.
Alarm signals
The alarm stage of generator negative-sequence overload protection operates to

4 46G.Alm
issue alarm signal
Waveform recording
Tripping stage of generator negative-sequence overload protection operates to

5 46G.TrigDFR
trigger waveform recording.
1 46G.DT.St Definite-time generator negative-sequence overload protection starts.
2 46G.IDMT.St Inverse-time generator negative-sequence overload protection starts.
Table 3.15-4 Output signals of generator negative-sequence overload protection (measurements)
1 46G.IDMT.ThermAccu Negative-sequence overload heat accumulation %
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Access path:
3.15.6 Settings
Table 3.15-5 Settings list of generator negative-sequence overload protection

1 46G.En
1: enable negative-sequence overload protection.

2 46G.DT.I_Set 0.10~4In 0.01 A definite-time generator negative-sequence
3 46G.DT.t_Op 0.00~30.00 0.01 s definite-time generator negative-sequence
Tripping logic setting of definite-time generator
4 46G.DT.OutMap 0~3FFFFFFF
negative-sequence overload protection.
5 46G.I_Alm 0.05~4In 0.01 A definite-time generator negative-sequence
6 46G.t_Alm 0.00~30.00 0.01 s definite-time generator negative-sequence
Pickup current setting of inverse-time generator
7 46G.IDMT.I_Set 0.05~In 0.01 A
The long-term permissive negative-sequence
8 46G.I2_Perm 0.05~In
current
9 46G.IDMT.tmin 0.10~10.00 0.01 s definite-time part of inverse-time generator
The maximum time delay for lower-limit initiation
10 46G.IDMT.tmax 0.1~5000 0.1 s part of inverse-time generator
The heat capacity of stator for inverse-time
11 46G.IDMT.A_Therm 1.00~320.00 0.01 s generator negative-sequence overload
protection.
Tripping logic setting of inverse-time generator
12 46G.IDMT.OutMap 0~3FFFFFFF
The setting to select the current for generator
13 46G.Opt_Source_I 0, 1 negative-sequence overload protection.
0: three-phase current input 1 is adopted
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3 Operation Theory
1: generator terminal current and neutral point

side current are adopted.
Access path: Settings-> Prot Settings -> Gen NegOC Settings
3.16 Generator Reverse Power Protection (32R)
3.16.1 Application
For some reasons the generator will change into motor operating mode due to loss of its motive
power, then the generator will absorb energy from the power grid to driven the turbine (gas turbine)
to run. In order to prevent the turbine blades or gas turbine gears from damage, generator reverse
power protection should be configured.
 Conventional reverse power element.
 Sequence tripping reverse power element.

3.16.3.1 Overview
Generator reverse power protection includes two operation elements: conventional reverse power
element and sequence tripping reverse power element.
If conventional reverse power element is enabled, when the detected reverse power value
exceeds the conventional reverse power setting, conventional reverse power element can operate
to alarm or trip with a time delay.
After the operation of some abnormal protections (such as overload protection, overexcitation
protection, loss-of-excitation protection and etc.) and sequence tripping is needed, the device will
turn off the main valve first, then sequence tripping reverse power element (controlled by main
valve contact and interconnection status between the generator and the power grid) operates to
trip with a short time delay.
3.16.3.2 Calculation Process of Generator Reverse Power Protection
Generator power is calculated according to generator terminal three-phase voltage and

three-phase current. The device can calculate the positive-sequence component of active power
according to the fundamental of the voltage and current, so the generator reverse power
protection is independent of the asymmetric component, and then it can truly reflect the load
conditions of the power system of the prime mover. Reactive power may vary over a wide range
for reverse power conditions, in order to make sure the calculation accuracy of active power, the
phase angle difference of CT and VT is compensated in the device.
The active power absorption level of a generator depends on the friction loss that needs to
overcome, the reverse power setting will be different for different type of units. When testing on the
primary side of the unit, the absorbed active power of the generator can be measured by the
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device. Users should set the reverse power setting as 50% of the measured reverse power value.
3.16.3.3 Conventional Reverse Power Element
Two time delays are configured for conventional reverse power element, time delay 1 is for alarm
and time delay 2 is for shutdown.
The operation criterion of conventional reverse power element is:
P < − RPSet Equation 3.16-1
Where:
RPSet is the conventional reverse power setting.
The setting range of conventional reverse power setting is (0.5%~50%)Pn, Pn is the rated active
power of the generator.
3.16.3.4 Sequence Tripping Reverse Power Element
One time delay is configured for sequence tripping reverse power element, if the main valve is
closed and the reverse power value exceeds the sequence tripping reverse power setting, the
sequence tripping reverse power will operate to trip with a short time delay.
The operation criterion of sequence tripping reverse power element is:
P < − STRPSet Equation 3.16-2
Where:
STRPSet is the sequence tripping reverse power setting.
The setting range of sequence tripping reverse power setting is (0.5%~10%)Pn, Pn is the rated
active power of the generator.
3.16.4 Logic
For generator reverse power protection, if following three conditions are met, the protection will be
enabled.
(1) Logic setting [32R.En] is set as “1”.
(2) Protection function enabling inputs [32R.En1], [32R.En2] are “1”
(3) Protection function blocking input [32R.Blk] is “0”.
If generator reverse power protection is disabled, all the related output signals will be reset. If no
external input is configured to [32R.En1] ([32R.En2]), the default initial value of [32R.En1]
([32R.En2]) is “1”; if no external input is configured to [32R.Blk], the default initial value of [32R.Blk]
is “0”.
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EN P<-[32R.CONV.P_Set] &
[32R.CONV.t_Alm] 0ms
SIG [32R.En] [32R.CONV.Alm]
SIG [32R.Blk]
SIG [32R.En]
& [32R.CONV.St]
SIG [32R.En1]
& [32R.CONV.t_Op] 0ms
SIG [32R.En2] [32R.CONV.Op]
SIG [32R.Blk]
SIG P<-[32R.CONV.P_Set]
0ms 500ms
SIG 32R.CONV.FD
SIG [32R.En]
&
SIG [32R.En1] [32R.SEQ.St]
SIG [32R.En2] &
[32R.SEQ.t_Op] 0ms
[32R.SEQ.Op]
SIG [32R.Blk]
SIG P<-[32R.SEQ.P_Set]
SIG [BI_Valve]
0ms 500ms
SIG 32R.SEQ.FD
Figure 3.16-1 Logic diagram of generator reverse power protection
Where:
32R.CONV.FD is the internal signal indicating that the conventional reverse power element picks
32R.SEQ.FD is the internal signal indicating that the sequence tripping reverse power element
32R
32R.POWER 32R.St
32R.En1 32R.CONV.Op
32R.En2 32R.SEQ.Op
32R.Blk 32R.CONV.Alm
BI_Valve
Figure 3.16-2 Function block diagram of generator reverse power protection
Table 3.16-1 Input signals of generator reverse power protection

1 32R.POWER The calculated generator power.
2 32R.En1 Protection function enabling input1 and input 2, it can be binary inputs or settings, such
3 32R.En2 as function enabling binary inputs, logic links, etc.
4 32R.Blk Protection function blocking input, such as function blocking binary input.
The main valve closed position input signal, it is used for sequence tripping reverse
5 BI_Valve
power element
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Table 3.16-2 Output signals of overexcitation protection

1 32R.St Generator reverse power protection starts.
2 32R.CONV.Alm The conventional reverse power element operates to alarm.
3 32R.CONV.Op The conventional reverse power element operates to trip.
4 32R.SEQ.Op The sequence tripping reverse power element operates to trip.
Table 3.16-3 Output signals of generator reverse power protection (event recorder)
Tripping reports
1 32R.CONV.Op The conventional reverse power element operates to trip.
2 32R.SEQ.Op The sequence tripping reverse power element operates to trip.
Start signals
3 32R.St Generator reverse power protection starts.
Alarm signals
4 32R.CONV.Alm The conventional reverse power element operates to alarm.
Waveform recording
5 32R.TrigDFR Generator reverse power protection operates to trigger waveform recording.
6 32R.CONV.St The conventional reverse power element operates starts.
7 32R.SEQ.St The sequence tripping reverse power element starts.
Table 3.16-4 Output signals of generator reverse power protection (measurements)
1 PowerCal.Ia The phase-A current for power calculation A
2 PowerCal.Ib The phase-B current for power calculation A
3 PowerCal.Ic The phase-C current for power calculation A
4 PowerCal.I1 Positive-sequence current for power calculation A
5 PowerCal.I2 Negative-sequence current for power calculation A
6 PowerCal.3I0_Cal The calculated residual current for power calculation A
Access path:
Main menu -> Measurements -> Measurements1-> Gen Values-> Gen Curr Values
Main menu -> Measurements -> Measurements2-> Gen Values-> Gen Curr Values
7 PowerCal.Ia The phase-A current for power calculation A
8 PowerCal.Ib The phase-B current for power calculation A
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3 Operation Theory
9 PowerCal.Ic The phase-C current for power calculation A
10 P The active power %
11 Q The reactive power %
Access Path:
Main menu -> Measurements -> Measurements2-> Prot Values-> Gen Power Prot Values
3.16.6 Settings
Table 3.16-5 Settings list of generator reverse power protection

1 32R.En 1
1: enable generator reverse power protection.
The power setting of conventional reverse
2 32R.CONV.P_Set 0.50~50 0.01 %
power element.
Time delay setting for conventional
3 32R.CONV.t_Alm 0.10~3000 0.01 s
reverse power element operating to alarm.
Time delay setting for conventional
4 32R.CONV.t_Op 0.10~3000 0.01 s
reverse power element operating to trip.
Tripping logic setting for conventional
5 32R.CONV.OutMap 0~3FFFFFFF
reverse power element.
The power setting of sequence tripping
6 32R.SEQ.P_Set 0.50~10 0.01 %
Time delay setting for sequence tripping
7 32R.SEQ.t_Op 0.01~30 0.01 s
reverse power element operating to trip.
Tripping logic setting for sequence tripping
8 32R.SEQ.OutMap 0~3FFFFFFF
Access path: Settings-> Prot Settings -> Gen RevPower Settings
3.17 Generator Low Forward Power Protection (32F)
3.17.1 Application
For some reasons the generator will change into motor operating mode due to loss of its motive
power, the generator power is gradually reduced to zero and then is reversed. When the generator
power is lower than a set low forward power threshold, generator low forward power protection will
operate to alarm and output a contact or shutdown.

3.17.2.1 Overview
In case generator low forward power protection is enabled, if the detected forward active power
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3 Operation Theory
reduces and when it is lower than the low forward power setting, low forward power protection can
operate to alarm and output a contact or shutdown with a time delay. Usually generator low
forward power protection can be blocked by emergency shutdown binary input or main valve open
contact.
3.17.2.2 Calculation Process of Generator Low Forward Power Protection
Generator power is calculated according to generator terminal three-phase voltage and

three-phase current. The device can calculate the positive-sequence component of active power
according to the fundamental of the voltage and current, so the generator low forward power
protection is independent of the asymmetric component, and then it can truly reflect the load
conditions of the power system of the prime mover. Reactive power may vary over a wide range
for low forward power conditions, in order to make sure the calculation accuracy of active power,
the phase angle difference of CT and VT is compensated in the device.
3.17.2.3 Protection Criterion
One time delay is configured for generator low forward power protection, it can operate to alarm
and output a contact or trip. The criterion of generator low forward power protection is:
P < PSet Equation 3.17-1
Where:
PSet is the low forward power setting.
The setting range of low forward power setting is (0.5%~100%)Pn, Pn is the rated active power of
the generator.
3.17.3 Logic
For generator low forward power protection, if following three conditions are met, the protection
will be enabled.
(1) Logic setting [32F.En] is set as “1”.
(2) Protection function enabling inputs [32F.En1], [32F.En2] are “1”
(3) Protection function blocking input [32F.Blk] is “0”.
If generator low forward power protection is disabled, all the related output signals will be reset. If
no external input is configured to [32F.En1] ([32F.En2]), the default initial value of [32F.En1]
([32F.En2]) is “1”; if no external input is configured to [32F.Blk], the default initial value of [32F.Blk]
is “0”.
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SIG P<[32F.P_Set]
&
EN [32.En_Alm] [32F.t_Op] 0ms [32F.Alm]
SIG [BI_UnderPower_Blk]
SIG [32F.En] &
SIG [32F.Blk]
SIG [32F.En]
&
SIG [32F.En1] [32F.St]
SIG [32F.En2] &
[32F.t_Op] 0ms
SIG [32F.Op]
[32F.Blk]
SIG P<[32F.P_Set]
SIG [BI_UnderPower_Blk]
0ms 500ms
SIG 32F.FD
Figure 3.17-1 Logic diagram of generator low forward power protection
Where:
32F.FD is the internal signal indicating that generator low forward power protection picks up (the
32F
32F.POWER 32F.St
32F.En1 32F.Op
32F.En2 32F.Alm
32F.Blk
BI_UnderPower_Blk
Figure 3.17-2 Function block diagram of generator low forward power protection
Table 3.17-1 Input signals of generator low forward power protection

1 32F.POWER The calculated generator power.
2 32F.En1 Protection function enabling input1 and input 2, it can be binary inputs or settings,
3 32F.En2 such as function enabling binary inputs, logic links, etc.
4 32F.Blk Protection function blocking input, such as function blocking binary input.
Protection function blocking binary input, emergency shutdown binary input or main
5 BI_UnderPower_Blk
valve open contact can be configured to this signal.
Table 3.17-2 Output signals of generator low forward power protection

1 32F.St Generator low forward power protection starts.
2 32F.Alm Generator low forward power protection operates to alarm.
3 32F.Op Generator low forward power protection operates to trip.
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Table 3.17-3 Output signals of generator low forward power protection (event recorder)
Tripping reports
1 32F.Op Generator low forward power protection operates to trip.
Start signals
2 32F.St Generator low forward power protection starts.
Alarm signals
Generator low forward power protection operates to alarm and output a

3 32F.Alm
contact.
Waveform recording
Generator low forward power protection operates to trigger waveform

4 32F.TrigDFR
recording.
3.17.5 Settings
Table 3.17-4 Settings list of generator low forward power protection

1 32F.En 1
1: enable low forward power protection.
The power setting of generator low forward
2 32F.P_Set 0.50~100.00 0.01 %
power protection.
Time delay setting of generator low forward
3 32F.t_Op 0.01~30.00 0.01 s
power protection.
Tripping logic setting for generator low forward
4 32F.OutMap 0~3FFFFFFF
power protection.
0: disable Logic setting of enabling/disabling the alarm

5 32F.En_Alm 1 function of generator low forward power
1: enable
protection.
Access path: Settings-> Prot Settings -> Gen FwdPower Settings
3.18 Generator Overexcitation Protection (Gen.24)
3.18.1 Application
Overexcitation protection is used to check the over-flux phenomenon during operation of the
generator and transformer. Abnormal voltage increase and abnormal frequency decline will lead to
the increase of flux density. When the flux density increase quickly over the rated flux density, it will
cause core saturation and resulting in great vortex, then it will lead to severe heating, the
insulation of the equipment will be damaged.
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3 Operation Theory

Overexcitation protection has following functions:
 The ratio of voltage and frequency is adopted to check overexcitation, for the ratio is
proportional to the flux density (B) of the protected object
 RMS of three phase-to-phase voltages is used to calculate the overexcitation multiple, which
is not affected by frequency fluctuation.
 One stage definite-time overexcitation protection for tripping and one stage definite-time
overexcitation protection for alarm are equipped (with respective overexcitation multiple
setting and time delay).
 One-stage inverse-time overexcitation protection for tripping is equipped. The overexcitation

protection inverse-time stage is determined by eight groups of the per-unit value of
overexcitation multiple (U/f) and the tripping time (t), users can configure it flexibly according
to the required over-excitation time characteristics.

3.18.3.1 Calculation of Overexcitation Multiple
Overexcitation multiples can be expressed by following equation:
n = U* / f* Equation 3.18-1
Where:
U * and f * are per unit value of voltage and frequency respectively.
The reference value for calculating per unit value of voltage is generator secondary voltage, and
the reference value for calculating per unit value of frequency is rated frequency. During normal
operation, n = 1.
For example, if generator primary voltage is 20kV (i.e. [Gen.U1n_Plate]=20kV) and voltage
transformer ratio is 20kV/100V (i.e. [G_Term.VT1.U1n] =20kV, [G_Term.VT1.U2n]=100V). The
reference value for calculating per unit value of voltage is:
[Gen.U1n_Plate] × [G_Term.VT1.U2n] 20 ×100

= = 57.74V
3 × [G_Term.VT1.U1n] 3 × 20
The device will calculate the voltage reference value automatically according to the above settings,
so the primary voltage of the protected equipment, the primary and secondary voltage of the
voltage transformer should be set correctly.
3.18.3.2 Definite-time Overexcitation Protection
 Tripping stage
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3 Operation Theory
For Definite-time overexcitation protection tripping stage, the operation equation is:
U * / f * >[Gen.24.DT.K] Equation 3.18-2
Where:
U * / f * is the overexcitation multiples.
[Gen.24.DT.K] is overexcitation multiple setting of definite-time overexcitation protection tripping

stage.
 Alarm stage
For Definite-time overexcitation protection alarm stage, the operation equation is:
U * / f * >[Gen.24.K_Alm] Equation 3.18-3
Where:
U * / f * is the overexcitation multiple.
[Gen.24.K_Alm] is overexcitation multiple setting of definite-time overexcitation protection alarm

stage.
3.18.3.3 Inverse-time Overexcitation Protection
Inverse-time overexcitation protection realizes inverse-time characteristic by linear processing on

given inverse-time operation characteristic, after calculating the overexcitation multiple, by using
the method of piece-wise linear interpolation to get the corresponding operation time, then the
inverse-time characteristic can be realized. The heat accumulation and dissipation function is
equipped for inverse-time overexcitation protection.
Users can set eight groups of overexcitation multiple and tripping time to simulate the inverse-time
operation characteristics curve and it can satisfy the overexcitation requirement of various
generator. For the overexcitation multiple between two overexcitation multiple settings, the
corresponding tripping time can be calculated via the internal piece-wise linear interpolation
method.
Following figure shows inverse-time characteristic curve of overexcitation protection.
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3 Operation Theory
U*/f*
K0
K1
K2
K3
K4
K5
K6
K7
t0 t1 t2 t3 t4 t5 t6 t7 t(s)
Figure 3.18-1 Inverse-time overexcitation characteristic curve
The main harm of generator overexcitation is overheat, inverse-time characteristic curve can
roughly simulate the heat accumulation and dissipation process for generator overexcitation. Once
the generator overexcitation multiple over the lower limit of inverse-time overexcitation multiple
[Gen.24.IDMT.K7], the time will be accumulated. When accumulated time delay is larger than the
tripping time of overexcitation protection, a tripping command will be issued by the device. Once
the generator overexcitation multiple is less than the lower limit of inverse-time overexcitation
multiple [Gen.24.IDMT.K7], the inverse-time dissipation process starts. If the generator
overexcitation multiple is always less than the lower limit of inverse-time overexcitation multiple,,
the accumulated value will decrease to “0” gradually.
The eight groups of settings of inverse-time characteristic curve must meet following conditions:
K0≥K1 ≥ K2 ≥ K3 ≥ K4 ≥ K5 ≥ K6 ≥ K7
t0 ≤t1 ≤ t2 ≤ t3 ≤ t4 ≤ t5 ≤ t6 ≤ t7
3.18.4 Logic
For overexcitation protection, if following three conditions are met, the protection will be enabled.
(1) Logic setting [Gen.24.En] is set as “1”.
(2) Protection function enabling inputs [Gen.24.En1], [Gen.24.En2] are “1”
(3) Protection function blocking input [Gen.24.Blk] is “0”.
If overexcitation protection is disabled, all the related output signals will be reset. If no external
input is configured to [Gen.24.En1] ([Gen.24.En2]), the default initial value of [Gen.24.En1]
([Gen.24.En2]) is “1”; if no external input is configured to [Gen.24.Blk], the default initial value of
[Gen.24.Blk] is “0”.
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SIG U*/f*>[Gen.24.K_Alm] &

[Gen.24.t_Alm] 0ms
EN [Gen.24.En] [Gen.24.Alm]
SIG [Gen.24.Blk]
EN [Gen.24.En]
SIG [Gen.24.En1] &
SIG [Gen.24.En2] &

[Gen.24.DT.t_Op] 0ms
[Gen.24.DT.Op]
SIG [Gen.24.Blk]
SIG U*/f*>[Gen.24.DT.K]
>=1
≥1
0ms 500ms
SIG Gen.24.DT.FD
[Gen.24.St]
EN [Gen.24.En]
SIG [Gen.24.En1] &
SIG [Gen.24.En2] &

IDMT
[Gen.24.IDMT.Op]
SIG [Gen.24.Blk]
SIG U*/f*>[Gen.24.IDMT.K7]
0ms 500ms
SIG Gen.24.IDMT.FD
Figure 3.18-2 Logic diagram of overexcitation protection
Where:
U * / f * is the overexcitation multiple.
Gen.24.DT.FD is the internal signal indicating that the definite-time overexcitation protection picks
Gen.24.IDMT.FD is the internal signal indicating that the inverse-time overexcitation protection
24
Gen.24.U3P Gen.24.St
f Gen.24.DT.Op
Gen.24.En1 Gen.24.IDMT.Op
Gen.24.En2 Gen.24.Alm
Gen.24.Blk
Figure 3.18-3 Function block diagram of overexcitation protection
Table 3.18-1 Input signals of overexcitation protection

1 Gen.24.U3P Three-phase voltage input.
2 f Frequency input for the protection.
3 Gen.24.En1 Protection function enabling input1 and input 2, it can be binary inputs or settings, such
4 Gen.24.En2 as function enabling binary inputs, logic links, etc.
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5 Gen.24.Blk Protection function blocking input, such as function blocking binary input.
Table 3.18-2 Output signals of overexcitation protection

1 Gen.24.St Tripping stage of overexcitation protection starts.
2 Gen.24.DT.Op Definite-time overexcitation protection operates to trip.
3 Gen.24.IDMT.Op Inverse-time overexcitation protection operates to trip.
4 Gen.24.Alm The alarm stage of overexcitation protection operates to issue alarm signal
Table 3.18-3 Output signals of overexcitation protection (event recorder)
Tripping reports
1 Gen.24.DT.Op Definite-time overexcitation protection operates to trip.
2 Gen.24.IDMT.Op Inverse-time overexcitation protection operates to trip.
Start signals
3 Gen.24.St Tripping stage of overexcitation protection starts.
Alarm signals
4 Gen.24.Alm The alarm stage of overexcitation protection operates to issue alarm signal
Waveform recording
Tripping stage of overexcitation protection operates to trigger waveform

5 Gen.24.TrigDFR
recording.
6 Gen.24.DT.St Tripping stage of definite-time overexcitation protection starts.
7 Gen.24.IDMT.St Tripping stage of inverse-time overexcitation protection starts.
Table 3.18-4 Output signals of overexcitation protection (measurements)
1 Gen.24.U/f Overexcitation multiple of overexcitation protection.
2 Gen.24.IDMT.ThermAccu Inverse-time accumulate value of overexcitation protection. %
Access path:
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3 Operation Theory
3.18.6 Settings
Table 3.18-5 Settings list of overexcitation protection

1 Gen.24.En 1
1: enable overexcitation protection.
Overexcitation multiple setting of alarm stage
2 Gen.24.K_Alm 1.00~2.00 0.01
of definite-time overexcitation protection.
Time delay setting of alarm stage of
3 Gen.24.t_Alm 0.1~30 0.1 s
definite-time overexcitation protection.
Overexcitation multiple setting of tripping stage
4 Gen.24.DT.K 1.00~2.00 0.01
of definite-time overexcitation protection.
Time delay setting of tripping stage of
5 Gen.24.DT.t_Op 0.1~3000 0.1 s
definite-time overexcitation protection.
Tripping logic setting of definite-time
6 Gen.24.DT.OutMap 0~3FFFFFFF
Upper-limit overexcitation multiple setting of
7 Gen.24.IDMT.K0 1.00~2.00 0.01
inverse-time overexcitation protection
Time delay setting corresponds to upper-limit
8 Gen.24.IDMT.t0_Op 1~3000 0.1 s
overexcitation multiple setting
Overexcitation multiple setting 1 of
9 Gen.24.IDMT.K1 1.00~2.00 0.01
Time delay setting corresponds to
10 Gen.24.IDMT.t1_Op 1~3000 0.1 s
overexcitation multiple setting 1
11 Gen.24.IDMT.K2 1.00~2.00 0.01
12 Gen.24.IDMT.t2_Op 1~3000 0.1 s
13 Gen.24.IDMT.K3 1.00~2.00 0.01
14 Gen.24.IDMT.t3_Op 1~3000 0.1 s
15 Gen.24.IDMT.K4 1.00~2.00 0.01
16 Gen.24.IDMT.t4_Op 1~3000 0.1 s
17 Gen.24.IDMT.K5 1.00~2.00 0.01
18 Gen.24.IDMT.t5_Op 1~3000 0.1 s
19 Gen.24.IDMT.K6 1.00~2.00 0.01
20 Gen.24.IDMT.t6_Op 1~3000 0.1 s Time delay setting corresponds to
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3 Operation Theory

21 Gen.24.IDMT.K7 1.00~2.00 0.01
22 Gen.24.IDMT.t7_Op 1~3000 0.1 s
Tripping logic setting of inverse-time
23 Gen.24.IDMT.OutMap 0~3FFFFFFF
Access path: Settings-> Prot Settings -> Gen OvExc Settings
3.19 Loss of Excitation Protection (40G)
3.19.1 Application
Loss of excitation protection can reflects the generator abnormal operation condition due to failure
of generator excitation circuit. If a fault happens in excitation system or the excitation adjusting
device is abnormal, loss of excitation protection can prevent the generator running in
asynchronous state, and it can also prevent the stator and rotor from overheating. In addition, loss
of excitation protection can ensure the stability of the power grid is not endangered due to
underexcitation of large synchronous generators.
3.19.2 Function
Loss of excitation protection has following functions:
 Three stages of loss of excitation protection with respective impedance setting and time delay
are available.
 The offset characteristics of impedance circle of each stage of loss of excitation protection
can be configured as forward offset or reverse offset.
 Each stage of loss of excitation protection can be controlled by reverse reactive power
element (reverse reactive power element can be enabled or disabled by corresponding logic
setting).
 Each stage of loss of excitation protection can be controlled by stator side busbar low voltage
element (stator side busbar low voltage element can be enabled or disabled by corresponding
logic setting).
 Each stage of loss of excitation protection can be controlled by rotor low voltage element
(rotor low voltage element can be enabled or disabled by corresponding logic setting).
 Each stage of loss of excitation protection can be configured to trip or alarm.
Loss of excitation protection is composed by following fours elements:
 Loss of excitation impedance element, one loss of excitation impedance element is

configured for per stage of loss of excitation protection.
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3 Operation Theory
 Reverse reactive power element, it provides reverse reactive power auxiliary releasing
function.
 Stator side busbar low voltage element, it provides stator side busbar low voltage controlling
function.
 Rotor low voltage element, it provides rotor low voltage controlling function.
Reverse Flag_RevQ
Power Stage1
reactive power 40G.St
element
Impedance 40G.Op
element
Rotor low Flag_RotUV

Ur Stage2
voltage
40G.St
element
Impedance 40G.Op
I3P element
Stator side Stage3

U3P 40G.St
busbar low
voltage Impedance 40G.Op
Alm_VTS Flag_StaUV
element element
Figure 3.19-1 Function diagram of loss of excitation protection
3.19.3.1 Loss of Excitation Impedance Element
The voltage and current used in loss of excitation protection is the positive-sequence voltage and
voltage of generator terminal. The operation equation is
Z + jX B
270° ≥ Arg ≥ 90° Equation 3.19-1
Z − jX A
Where:
XA: it is the upper boundary setting of the impedance circle, it corresponds to the setting [40Gn.Za],
i.e. the impedance setting ZA of stage n of loss of excitation protection (n=1, 2 or 3).
XB: it is the lower boundary setting of the impedance circle, it corresponds to the setting [40Gn.Zb],
i.e. the impedance setting ZB of stage n of loss of excitation protection (n=1, 2 or 3).
Via the setting [40Gx.Opt_Offset_Z], users can select the offset characteristic (forward offset or
reverse offset) of the upper boundary of the impedance circle. If forward offset characteristic is
selected, the impedance circle is a static stabilization boundary impedance circle. If reverse offset
characteristic is selected, the impedance circle is an asynchronous impedance circle or a standard
impedance circle.
 Static stabilization boundary impedance circle:
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3 Operation Theory
2
U gn × na
X= Xs × Equation 3.19-2
S gn × nv
A
2
U gn × na
XB =
−( X d ) × non-salient pole generator
S gn × nv
X d +X q U gn2
× na
XB =
−( )× salient pole generator
2 S gn × nv
Where:
X s is per unit value (takes generator apparent power as the referenced capacity) of the maximum
tie reactance between the generator and system (including the impedance of step-up transformer).
X d ' and X d are per unit value of transient reactance and direct-axis synchronous reactance of
generator respectively.
X q is per unit value of generator cross-axis synchronous reactance.
U gn and S gn are rated voltage and rated apparent power of generator respectively.
na is CT ratio of generator terminal or neutral point.
nv is VT ratio of generator terminal.
 Asynchronous impedance circle:
X d' U gn × na
2
XA =
− × Equation 3.19-3
2 S gn × nv
2
U gn × na
XB =
−( X d ) × non-salient pole generator
S gn × nv
X d +X q U gn2
× na
XB =
−( )× salient pole generator
2 S gn × nv
 Standard impedance circle:
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3 Operation Theory
X ' U gn × na
2
XA =
− d ×
2 S gn × nv
Equation 3.19-4
X U × na
' 2
X B =−(1 + d gn
)
2 S gn × nv
Where:
The diameter of the standard impedance circle is 1.0p.u (per unit value is 1, takes generator
apparent power as the referenced capacity).
The impedance characteristic of loss of excitation protection is shown as follows:
jx
R
Static stabilization boundary
impedance circle
Standard impedance circle
Asynchronous impedance circle
Figure 3.19-2 Impedance circle of loss of excitation protection
Following auxiliary criteria are used for the impedance element loss of excitation protection.
 The positive-sequence voltage U1≥6V
 The negative-sequence voltage U2<0.1Un (Un is the rated voltage of the generator)
 The generator current Ig≥0.1In (In is the rated current of CT of the generator)
3.19.3.2 Reverse Reactive Power Element
The criterion of reverse reactive power element is:
Q < −QSet Equation 3.19-5
Where:
Q is the reactive power of the generator;
QSet is the reverse reactive power setting [40G.Q_Rev]
3.19.3.3 Stator Side Busbar Low Voltage Element
 System low voltage criterion
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3 Operation Theory
This criterion is mainly used to prevent the system voltage collapse and widespread power cut due
to inadequate reactive power reserve which caused by generator loss of excitation or
underexcitation fault. The voltage used for system low voltage criterion is derived from the HV side
VT of the main transformer, if main transformer HV side VT circuit failure happens, system low
voltage criterion will be blocked.
System three-phase low voltage criterion is as follows:
U ppH < U L _ Set1 Equation 3.19-6
Where:
U ppH is phase-to-phase voltage of HV side of the main transformer;
U L _ Set1 is the system low voltage setting [Tr_HVS.Upp_VCE], generally it takes 90%~95% of the
minimum system normal operating voltage.
 Generator terminal low voltage criterion
The voltage setting of generator terminal low voltage criterion should be set to not destroy the
safety of auxiliary power and it should be lower than the forced excitation pick up voltage. The
voltage used for generator terminal low voltage criterion is derived from the generator terminal VT,
if generator terminal VT circuit failure happens, generator terminal low voltage criterion will be
blocked.
Generator terminal three-phase low voltage criterion is as follows:
U ppG < U L _ Set 2 Equation 3.19-7
Where:
U ppG is phase-to-phase voltage of generator terminal;
U L _ Set 2 is the generator terminal low voltage setting [G_Term.Upp_VCE], generally it takes
85%~90% of the generator rated voltage.
Generally, stage 1 of loss of excitation protection adopts system low voltage criterion and stage 2
of loss of excitation protection adopts generator terminal low voltage criterion.
3.19.3.4 Rotor Voltage Element
If the rotor voltage input mode setting [40G.Opt_U_Rot] is set as “0”, means rotor voltage directly
input mode is adopted. If the rotor voltage input mode setting [40G.Opt_U_Rot] is set as “1”,
means 4~20mA transducer input mode is adopted, i.e. the rotor voltage is converted as 4~20mA
signal via the transducer, then the 4~20mA signal is input to the device. The setting transducer
input voltage upper limit value [Umax_Rot_Transducer] should be set according to the rotor
voltage that corresponds to 20mA signal. The 4~20mA signal will be converted into rotor voltage
according to the setting [Umax_Rot_Transducer], then the converted rotor voltage will be
displayed.
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3 Operation Theory
The rotor voltage described below is the directly input rotor voltage or the rotor voltage converted
from 4~20mA signal.
 Rotor low voltage criterion
Ur < Ur1set Equation 3.19-8
Where:
Ur is the generator rotor voltage;
Ur1set is the rotor low voltage setting [40G.U_UV_Rot], generally it takes 60%~80% of the
generator no-load rated excitation voltage.
 Variable excitation voltage criterion
Ur < Kxs*(P-Pt)*Uf0
Equation 3.19-9
Kxs =Krel*(Xd+Xs)
Where:
Kxs is the coefficient setting of rotor low voltage criterion [40G.K_UV_Rot]
P is the per unit value of the generator output power;
Pt is the per unit value of generator salient pole power, for hydro-generator, Pt= 0.5* (1/Xq∑－
1/Xd∑); for turbo-generator, Pt=0;
Uf0 is generator no-load rated excitation voltage setting [40G.U_NoLoad_Rot];
Krel is reliability coefficient, it takes 0.7~0.85.
Xd is the per unit value of generator direct-axis synchronous reactance, and Xs is the per unit
value of system tie reactance.
If the rotor voltage Ur drops to zero or minus value suddenly during loss of excitation, the rotor low
voltage criterion will be met quickly (before the static stability limit of the generator reaches). If Ur
drops to zero or reduces to a value gradually during underexcitation or loss of excitation fault, the
variable excitation voltage criterion will be met. Underexcitation or loss of excitation fault will cause
out-of-step, and then the rotor voltage Ur and the output power of the generator will swing
seriously. In this case, the rotor low voltage criterion and the variable excitation voltage criterion
will be met and reset periodically in general. So the rotor voltage element will reset with a time
delay after out-of-step happens (the measured impedance fall into the static stabilization boundary
impedance circle).
3.19.4 Logic
For each stage of loss of excitation protection, if following three conditions are met, the protection
will be enabled.
(1) Logic setting [40Gn.En] is set as “1”.
(2) Protection function enabling inputs [40Gn.En1], [40Gn.En2] are “1”
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3 Operation Theory
(3) Protection function blocking input [40Gn.Blk] is “0”.
If loss of excitation protection is disabled, all the related output signals will be reset. If no external
input is configured to [40Gn.En1] ([40Gn.En2]), the default initial value of [40Gn.En1] ([40Gn.En2])
is “1”; if no external input is configured to [40Gn.Blk], the default initial value of [40Gn.Blk] is “0”
(n=1, 2 or 3).
SET [40Gn.En_Alm]
&
EN [40Gn.En] [40Gn.t_Op] 0ms
[40Gn.Alm]
SIG [40Gn.Blk]
SIG Op_Zn &
SIG Op_RevQ >=1

&
SET [40Gn.En_RevQ] [40Gn.St]
SIG Op_StaUV >=1
[40Gn.t_Op] 0ms
[40Gn.Op]
SET [40Gn.En_BusUV]
SIG Op_RotUV >=1
SET [40Gn.En_RotUV]
EN [40Gn.En]
SIG [40Gn.En1] &
SIG [40Gn.En2]
SIG [40Gn.Blk]
0ms 500ms
SIG 40Gn.FD
Figure 3.19-3 Logic diagram of loss of excitation protection
Where:
Op_Zn is the internal signal indicating that Equation 3.19-1 is met;
Op_RevQ is the internal signal indicating that Equation 3.19-5 is met;
Op_StaUV is the internal signal indicating that Equation 3.19-6 or Equation 3.19-7 is met;
Op_RotUV is the internal signal indicating that Equation 3.19-8 or Equation 3.19-9 is met;
40Gn.FD is the internal signal indicating that stage n of loss of excitation protection picks up (the
40G
40Gn.U3P 40Gn.St
40Gn.I3P 40Gn.Op
40Gn.POWER 40Gn.Alm
40Gn.En1
40Gn.En2
40Gn.Blk
40Gn.RotVolt_Ctrl
40Gn.StaVolt_Ctrl
Figure 3.19-4 Function block diagram of loss of excitation protection
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3 Operation Theory
Table 3.19-1 Input signals of loss of excitation protection

1 40Gn.U3P Three-phase voltage input.
2 40Gn.I3P Three-phase current input.
3 40Gn.POWER Generator power data input.
4 40Gn.En1 Protection function enabling input1 and input 2, it can be binary inputs or settings,
5 40Gn.En2 such as function enabling binary inputs, logic links, etc.
6 40Gn.Blk Protection function blocking input, such as function blocking binary input.
7 40Gn.RotVolt_Ctrl Rotor voltage element input
8 40Gn.StaVolt_Ctrl Stator voltage element input
Table 3.19-2 Output signals of loss of excitation protection

1 40Gn.St Stage n of loss of excitation protection starts.
2 40Gn.Op Stage n of loss of excitation protection operates to trip.
3 40Gn.Alm Stage n of loss of excitation protection operates to issue alarm signal.
Table 3.19-3 Output signals of loss of excitation protection (event recorder)
Tripping reports
1 40Gn.Op Stage n of loss of excitation protection operates to trip.
Start signals
2 40Gn.St Stage n of loss of excitation protection starts.
Alarm signals
3 40Gn.Alm Stage n of loss of excitation protection operates to issue alarm signal.
4 40Gn.Alm_RotVoltCircuit Rotor voltage circuit failure alarm for stage n of loss of excitation protection.
Waveform recording
Stage n of loss of excitation protection operates to trigger waveform

5 40Gn.TrigDFR
recording.
Table 3.19-4 Output signals of loss of excitation protection (measurements)
Access path:
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3 Operation Theory
The enabled status of rotor voltage element of loss of

3 Flg_On_RotUV_ExcLoss
excitation protection.
Access Path:
The voltage controlled element of generator terminal

4 G_Term.VCE.Op
operates
The voltage controlled element of HV side of main

5 Tr_HVS.VCE.Op
transformer operates
6 P The active power. %
7 Q The reactive power. %
8 U_Exc_Rot_P The excitation voltage corresponds to current power. V
Positive-sequence impedance for stage 1 of loss of

11 40G1.Z1_Sec Ohm

12 40G2.Z1_Sec Ohm

13 40G3.Z1_Sec Ohm
Access Path:
Main menu -> Measurements -> Measurements2-> Prot Values-> Gen ExcLoss Prot Values
3.19.6 Settings
Table 3.19-5 Settings list of loss of excitation protection

Generator terminal phase-to-phase low voltage
1 G_Term.Upp_VCE 2~120 0.01 V
setting.
Main transformer HV side phase-to-phase low
2 Tr_HVS.Upp_VCE 2~120 0.01 V
voltage setting.
Rotor low voltage setting for loss of excitation
3 40G.U_UV_Rot 0.10~500 0.01 V
protection.
Generator no-load rated excitation voltage
4 40G.U_NoLoad_Rot 0.10~500 0.01 V
setting for loss of excitation protection.
The coefficient setting of rotor low voltage
5 40G.K_UV_Rot 0-10 0.01
criterion for loss of excitation protection.
Generator salient pole power setting for loss of
6 40G.P_SalientPole 0-100 0.01 %
Rotor voltage input mode for loss of excitation
7 40G.Opt_U_Rot 0~1 1
protection.
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3 Operation Theory
0: rotor voltage input

1: 4~20mA transducer input
The reverse reactive power setting of loss of
8 40G.Q_Rev 0~50 0.01 %
0: disable Logic setting of enabling/disabling stage 1 of
9 40G1.En 1
1: enable loss of excitation protection.
Impedance setting ZA of stage 1 of loss of
10 40G1.Za 0~200 0.01 ohm
Impedance setting ZB of stage 1 of loss of
11 40G1.Zb 0~200 0.01 ohm
Time delay setting of stage 1 of loss of excitation
12 40G1.t_Op 0~3000 0.01 s
protection.
Tripping logic setting of stage 1 of loss of
13 40G1.OutMap 0~3FFFFFFF
Logic setting of enabling/disabling busbar low
14 40G1.En_BusUV 0~1 1 voltage element for stage 1 of loss of excitation
protection.
Logic setting of enabling/disabling rotor voltage
15 40G1.En_RotUV 0~1 1 element for stage 1 of loss of excitation
protection.
Logic setting of enabling/disabling reverse
16 40G1.En_RevQ 0~1 1 reactive power element for stage 1 of loss of
Logic setting of enabling/disabling stage 1 of
17 40G1.En_Alm 0~1 1
loss of excitation protection operates to alarm.
Logic setting to select the offset characteristic of
the impedance circle of stage 1 of loss of
18 40G1.Opt_Offset_Z 0~1 1 excitation protection.
0: forward offset
1: reverse offset
19 40G2.En 1
20 40G2.Za 0~200 0.01 ohm
21 40G2.Zb 0~200 0.01 ohm
22 40G2.t_Op 0~3000 0.01 s
protection.
excitation protection
protection.
25 40G2.En_RotUV 0~1 1 Logic setting of enabling/disabling rotor voltage
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3 Operation Theory
element for stage 2 of loss of excitation

protection.
27 40G2.En_Alm 0~1 1
0: forward offset
1: reverse offset
29 40G3.En 1
30 40G3.Za 0~200 0.01 ohm
31 40G3.Zb 0~200 0.01 ohm
32 40G3.t_Op 0~3000 0.01 s
protection.
excitation protection
protection.
Logic setting of enabling/disabling rotor voltage
35 40G3.En_RotUV 0~1 1 element for stage 3 of loss of excitation
protection.
37 40G3.En_Alm 0~1 1
0: forward offset
1: reverse offset
Access path: Settings-> Prot Settings -> Gen ExcLoss Settings
39 Umax_Rot_Transducer 0~4000 1 V The upper limit of input voltage of the transducer
Access path: Settings-> Config Settings
Date: 2016-08-16
3 Operation Theory
3.20 Generator Phase Overcurrent Protection (Gen.50/51P)
3.20.1 Application
When a fault occurs in power system, the current increases and generator phase overcurrent
protection operates to avoid damages to protected equipment. Voltage controlled element can be
selected to improve the sensitivity of generator phase overcurrent protection and direction element
can be selected to improve the selectivity of the protection. For self and parallel-excited generator,
current will decrease so quick during fault that it may be lower than overcurrent setting before
tripping. So memorizing function for fault current can be enabled for this phase overcurrent
protection.
An external fault will result in generator overload, it will lead to damage of generator if the fault can
not be cut off quickly, in this case generator phase overcurrent protection can operate to trip
generator circuit breaker to avoid physical damage. For small-scale generator, generator phase
overcurrent protection can protect generator from internal fault, for large-scale generator,
generator phase overcurrent protection is applied as the backup protection of generator differential
protection.
Generator phase overcurrent protection has following functions:
 Three-stage generator phase overcurrent protection with independent logic, current and time
delay settings.
 Stage 1 and stage 2 are definite-time characteristic, stage 3 can be selected as definite-time
or inverse-time characteristic. The inverse-time characteristic is selectable among IEC and
ANSI/IEEE standard inverse-time characteristics and a user-defined inverse-time curve.
 Voltage controlled element can be selected to control each stage of generator phase
 Direction element can be selected to control each stage of generator phase overcurrent
protection with three options: no direction, forward direction and reverse direction.
 Memorizing function for fault current can be enabled or disabled for each stage of generator
phase overcurrent protection.

3.20.3.1 Overview
Generator phase overcurrent protection consists of following elements:
 Phase overcurrent element: each stage is equipped with one independent overcurrent
element.
 Voltage controlled element: one voltage controlled element shared by all phase overcurrent
elements.
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3 Operation Theory
 Direction element: one direction element shared by all phase overcurrent elements.
U3P
Stage 1
[Alm_VTS] Direction Direction signal St
Element
Overcurrent Op
Element
voltage signal
Voltage Stage 2
Control St
Element Overcurrent Op
Element
I3P
Stage 3
St
Overcurrent Op
Element
Figure 3.20-1 Function diagram of generator phase overcurrent protection
3.20.3.2 Current Element
The operation criterion of each stage of generator phase overcurrent protection is:
I p > [Gen.50/51Pn.I_Set] Equation 3.20-1
Where:
I p is measured phase current.
[Gen.50/51Pn.I_Set] is the current setting of stage n (n=1, 2, or 3) of generator phase overcurrent

protection. For inverse-time overcurrent protection, it can be set as 1.1 times of base current of
inverse-time overcurrent protection.
If any phase current is larger than the current setting of any enabled stage of generator phase
overcurrent protection, voltage controlled element operates (or voltage controlled element is
disabled), and direction element operates (or direction element is disabled), the stage of generator
phase overcurrent protection will operate after a settable time delay. The stage generator phase
overcurrent protection will drop off instantaneously or with a memorizing time delay (if the fault
current memorizing function is enabled) after fault current disappears.
3.20.3.3 Time Curve
Generator phase overcurrent protection stage 1 and stage 2 are definite-time characteristic and
each stage can perform instantaneous operation if the corresponding time delay setting is set as
“0”. Stage 3 can be selected as definite-time or inverse-time characteristic, and inverse-time
operating time curve is as follows.
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3 Operation Theory
 
 

t(I) = 
K
+ C  × TP Equation 3.20-2
I α
 ( ) −1 
 I set 
Where:
I set is the base current setting, corresponds to the setting [Gen.50/51P3.Ib_Set]. The maximum
operating current of the circuit should be taken into account, it should not pick up for overload.
T p is inverse-time time factor, corresponds to the setting [Gen.50/51P3.TMS]. It should
coordinate to the time differential of the of the power grid.
K , α ,C are inverse-time constants of inverse-time curve.
The user can select the operating characteristic from various inverse-time characteristic curves by
the setting [Gen.50/51P3.Opt_Curve], and parameters of available characteristics for selection are
shown in the following table.
Table 3.20-1 Inverse-time curve parameters of stage 3 of generator phase overcurrent protection
Gen.50/51P3.Opt_Curve Time Characteristic K α C
0 Definite time
1 IEC Normal inverse 0.14 0.02 0
2 IEC Very inverse 13.5 1.0 0
3 IEC Extremely inverse 80.0 2.0 0
4 IEC Short-time inverse 0.05 0.04 0
5 IEC Long-time inverse 120.0 1.0 0
6 ANSI Extremely inverse 28.2 2.0 0.1217
7 ANSI Very inverse 19.61 2.0 0.491
8 ANSI Inverse 0.0086 0.02 0.0185
9 ANSI Moderately inverse 0.0515 0.02 0.114
10 ANSI Long-time extremely inverse 64.07 2.0 0.25
11 ANSI Long-time very inverse 28.55 2.0 0.712
12 ANSI Long-time inverse 0.086 0.02 0.185
13 Programmable user-defined
If all available curves do not comply with user application, user can configure
[Gen.50/51P3.Opt_Curve] as “13” to customize the inverse-time curve characteristic (by
Date: 2016-08-16
3 Operation Theory
configuring the three inverse-time curve constants K , α and C ).
If fault current memorizing function is disabled, define-time or inverse-time generator phase

overcurrent protection drops off instantaneously. If fault current memorizing function is enabled,
define-time or inverse-time generator phase overcurrent protection will drop off with a settable
memorizing time delay.
3.20.3.4 Voltage Controlled Element
Generator phase overcurrent protection is equipped as the backup protection of generator and
adjacent power equipment, and voltage element is usually used to control generator phase
overcurrent protection to improve sensitivity of the protection. Unsymmetrical fault will result in
unsymmetrical sequence voltages and symmetrical fault will lead to low three phase voltages at
relay location. If voltage element is enabled, generator phase overcurrent protection can operate if
the sequence voltage is larger than a setting or phase-to-phase voltage is lower than a setting, so
current settings of generator phase overcurrent protection can be set lower with high sensitivity.
 Operation criterion of voltage controlled element
The voltage controlled element picks up if phase-to-phase voltage is lower than its setting or
negative-sequence voltage is larger than its setting.
Criteria:
U ΦΦ < [Gen.50/51P.Upp_VCE] or U 2 > [Gen.50/51P.U2_VCE] Equation 3.2-3
Where:
U ΦΦ is the phase-to-phase voltage.
U 2 is the negative-sequence voltage.
[Gen.50/51P.Upp_VCE] is the phase-to-phase undervoltage setting.
[Gen.50/51P.U2_VCE] is the negative-sequence overvoltage setting.
Voltage of any side can be used as the input of voltage controlled element through PCS-Explorer2.
 Effect of VT Circuit
The logic setting [Gen.50/51P.En_VTS_Blk] is used to control the voltage controlled element of
generator phase overcurrent protection during VT circuit failure. When VT circuit fails, if setting
[Gen.50/51P.En_VTS_Blk] is set as “1”, the voltage controlled element will not pick up when VT
circuit fails; if the setting is set as “0”, and voltage controlled element meet the criterion, voltage
controlled element will pick up.
3.20.3.5 Fault Current Memorizing Function
For self and parallel-excited generator, current will decrease so quick during fault that it may be
lower than overcurrent setting before tripping. So memorizing function for fault current is equipped
with this protection. Once the generator phase overcurrent protection picks up and the voltage
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3 Operation Theory
controlled element operates, memorizing function is equipped to make the protection operates to
trip reliably. The logic setting [Gen.50/51Pn.En_CurrMem] should be set as “1” for self and
parallel-excited generator. Meanwhile, the voltage controlled element for generator phase
overcurrent protection should be enabled. If voltage controlled element is disabled, fault current
memorizing function will quit automatically. If fault current is smaller than 10% of the setting
[Gen.50/51Pn.I_Set], the fault will be thought as cut off, then fault current memorizing function will
quit automatically.
3.20.3.6 Direction Element
Direction element can be selected to control generator phase overcurrent protection to coordinate
with other protections of power grid. If the element is selected for generator phase overcurrent
protection, then the protection becomes directional overcurrent protection.
Positive-sequence voltage (U1) is adopted as polarizing voltage, and pre-fault memory

positive-sequence voltage is used during three-phase close-up faults to ensure the direction
element working properly. Phase current (Ip) is adopted for calculation of direction element, and if
current is less than current threshold, both of forward direction and reverse direction are not met.

When a fault occurs at forward direction, the angle between polarizing voltage U ref and fault
current Idir is:
U
ϕ k = arg  ref Equation 3.20-3
I dir
When a fault occurs at reverse direction, the angle is:
U
ϕ ′k = arg  ref = 180° + ϕ k Equation 3.20-4
I dir
Assuming that relay characteristic angle is ϕ sen (corresponds to the setting [Gen.50/51P.RCA]),
i.e. the angle polarizing voltage leading fault current, in order to ensure the direction element can
operate reliably, the angle range of the forward direction is:
U ref <
ϕ sen − 90° < arg ϕ sen + 90° Equation 3.20-5
I dir
If VT and CT are connected as following figure, i.e. positive polarity of CT is at busbar side, points
to the protected object, then the operation zone of forward and reverse direction element are
shown in Figure 3.20-3 (Wherein the hatched portion is the operation zone of forward direction
element). Symbol” ” represents the positive polarity of current transformer.
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3 Operation Theory
Reverse Forward
CT
Protected
Object
VT
Direction
Element
Figure 3.20-2 Connection of VT and CT of direction element
Reverse
Uref(U1)
Φsen
Φsen+180°
Idir(Ip)
Forward
Figure 3.20-3 Direction characteristic of generator phase overcurrent protection
 Effect of VT Circuit
The logic setting [Gen.50/51P.En_VTS_Blk] is used to control the direction element of generator
phase overcurrent protection during VT circuit failure. When VT circuit fails, if setting
[Gen.50/51P.En_VTS_Blk] is set as “1”, the direction element will not pick up when VT circuit fails;
if the setting is set as “0”, and direction element meet the criterion, direction element will pick up.
3.20.4 Logic
Logic diagram of generator phase overcurrent is shown in the following figure, including phase
overcurrent element, voltage controlled element and direction element, fault current memorizing
function and enabling and blocking logic of the protection.
 Function Enable/Disable
For stage n of generator phase overcurrent protection, if following three conditions are met, stage
n of generator phase overcurrent protection is enabled.
(1) Logic setting [Gen.50/51Pn.En] is set as “1”.
(2) The protection function enabling inputs [Gen.50/51Pn.En1], [Gen.50/51Pn.En2] are “1”
(3) The protection function blocking input [Gen.50/51Pn.Blk] is “0”.
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3 Operation Theory
If generator phase overcurrent protection is disabled, all the related output signals will be reset. If
no external input is configured to [Gen.50/51Pn.En1] ([Gen.50/51Pn.En2]), the default initial value
of [Gen.50/51Pn.En1] ([Gen.50/51Pn.En2]) is “1”; if no external input is configured to
[Gen.50/51Pn.Blk], the default initial value of [Gen.50/51Pn.Blk] is “0”.
EN [Gen.50/51Pn.En]
SIG [Gen.50/51Pn.En1] &
SIG [Gen.50/51Pn.En2]
SIG [Gen.50/51Pn.Blk]
SIG [Gen.50/51P.VCE.Op] &
SET [Gen.50/51Pn.En_VCE] &

>=1
SET [Gen.50/51Pn.En_CurrMem]
SIG [Gen.50/51P.I3P]
& &
[Gen.50/51Pn.St]
SET [Gen.50/51Pn.I_Set]
SIG [Gen.50/51P.VCE.Op] >=1

Timer
t
SET [Gen.50/51Pn.En_VCE] [Gen.50/51Pn.Op]
t
SIG [Gen.50/51P.DIR.Op] >=1
Inverse-time only for
stage 3
SET [Gen.50/51Pn.En_Dir]
0ms 500ms
SIG Gen.50/51Pn.FD
Figure 3.20-4 Logic diagram of generator phase overcurrent protection (n=1,2,3)
Where:
[Gen.50/51Pn.VCE.Op] is the signal indicating that the voltage controlled element operates.
[Gen.50/51P.I3P] is the three-phase current input.
[Gen.50/51Pn.DIR.Op] is the signal indicating that the direction element operates.
50/51Pn.FD is the internal signal indicating that stage n of generator phase overcurrent protection
SIG [Gen.50/51P.En] &

&
SIG [Gen.50/51P.Blk] [Gen.50/51P.VCE.Op_Upp]
SET U ΦΦ <[Gen.50/51P.Upp_VCE] &

≥1
SIG VT circuit failure
&
EN [Gen.50/51P.En_VTS_Blk]
Figure 3.20-5 Logic diagram of phase-to-phase VCE of generator phase overcurrent protection
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3 Operation Theory
SIG [Gen.50/51Pn.En] &

&
SIG [Gen.50/51Pn.Blk] [Gen.50/51P.VCE.Op_U2]
SET U 2 >[Gen.50/51P.U2_VCE] &

≥1
SIG VT circuit failure
&
Figure 3.20-6 Logic diagram of negative-sequence VCE of generator phase overcurrent protection
Where:
U ΦΦ
is the phase-to-phase voltage.
U 2 is the negative-sequence voltage.
[Gen.50/51P.VCE.Op_Upp] is the internal operation signal of phase-to-phase undervoltage

element.
[Gen.50/51P.VCE.Op_U2] is the internal operation signal of negative-sequence voltage element.
EN [Gen.50/51P.En] &
SIG [Gen.50/51P.Blk] &

[Gen.50/51P.DIR.Op]
SIG [Gen.50/51P.I3P]
Direction
Check &
SIG [Gen.50/51P.U3P]
Fwd/Rev
SET [Gen.50/51P.Opt_Dir]
SIG VT circuit failure &
Figure 3.20-7 Logic diagram of direction element of generator phase overcurrent protection
Where:
[Gen.50/51P.I3P] is the three-phase current input.
[Gen.50/51P.U3P] is the three-phase voltage input.
[Gen.50/51P.DIR.Op] is the internal signal indicating that the direction element operates.
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3 Operation Theory
50/51P
Gen.50/51Pn.I3P Gen.50/51Pn.St
Gen.50/51Pn.U3P Gen.50/51Pn.Op
Gen.50/51Pn.En1
Gen.50/51Pn.En2
Gen.50/51Pn.Blk
Figure 3.20-8 Function block diagram of generator phase overcurrent protection
Table 3.20-2 Input signals of generator phase overcurrent protection

1 Gen.50/51Pn.I3P Three-phase current data
2 Gen.50/51Pn.U3P Three-phase voltage data
3 Gen.50/51Pn.En1 Protection function enabling input1 and input 2, it can be binary inputs or settings, such
4 Gen.50/51Pn.En2 as function enabling binary inputs, logic links, etc.
5 Gen.50/51Pn.Blk Protection function blocking input, such as function blocking binary input.
Table 3.20-3 Output signals of generator phase overcurrent protection

1 Gen.50/51P1.Op Stage 1 of generator phase overcurrent protection operates.
4 Gen.50/51P1.St Stage 1 of generator phase overcurrent protection starts.
Table 3.20-4 Output signals of generator phase overcurrent protection (event recorder)
Tripping reports
Start signals
Waveform recording
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3 Operation Theory
Stage 1 of generator phase overcurrent protection operates to trigger

7 Gen.50/51P1.TrigDFR
waveform recording.

waveform recording.

waveform recording.
Table 3.20-5 Output signals of generator phase overcurrent protection (measurements)
Inverse-time accumulate value of phase A of stage 3 of

1 Gen.50/51P3.Accu_A %
generator phase overcurrent protection.
Inverse-time accumulate value of phase B of stage 3 of

2 Gen.50/51P3.Accu_B %
Inverse-time accumulate value of phase C of stage 3 of

3 Gen.50/51P3.Accu_C %
The internal signal indicating that the direction element

4 Gen.50/51P.DIR.Op
operates.
The signal indicating that the voltage controlled element

5 Gen.50/51Pn.VCE.Op
operates.
Access Path:
Main menu -> Measurements -> Measurements2-> Prot Values->Gen PPF Prot Values
3.20.6 Settings
Table 3.20-6 Settings list of generator phase overcurrent protection

Phase-to-phase undervoltage setting of
1 Gen.50/51P.Upp_VCE 2.00~120.00 0.01 V voltage controlled element of generator
Negative-sequence overvoltage setting of
2 Gen.50/51P.U2_VCE 1.00~120.00 0.01 V voltage controlled element of generator
Relay characteristic angle of direction
3 Gen.50/51P.RCA -90~90 0.01 deg element of generator phase overcurrent
protection.
Logic setting of selecting the pointing
direction of direction element of generator
0 Forward
4 Gen.50/51P.Opt_Dir 1 phase overcurrent protection.
1: Reverse
0: Forward direction
1: Reverse direction
5 Gen.50/51P.En_VTS_Blk 0: disable 1 Logic setting of enabling/disabling voltage
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3 Operation Theory

1: enable controlled element or direction element
being blocked during VT circuit failure.
0: disable Logic setting of enabling/disabling stage 1
6 Gen.50/51P1.En 1
1: enable of generator phase overcurrent protection.
Current setting of stage 1 of generator
7 Gen.50/51P1.I_Set 0.05~20.00In 0.01 A
Time delay of stage 1 of generator phase
8 Gen.50/51P1.t_Op 0~3000 0.01 s
Memorizing time delay of stage 1 of
9 Gen.50/51P1.t_CurrMem 1~30 0.01 s
Tripping logic setting of stage 1 of
10 Gen.50/51P1.OutMap 0~3FFFFFFF
Logic setting of enabling/disabling voltage
0: disable
11 Gen.50/51P1.En_VCE 1 controlled element of generator phase
1: enable
Logic setting of enabling/disabling direction
0: disable
12 Gen.50/51P1.En_Dir 1 element of generator phase overcurrent
1: enable
protection.
Logic setting of enabling/disabling fault
0: disable
13 Gen.50/51P1.En_CurrMem 1 current memorizing function of stage 1 of
1: enable
14 Gen.50/51P2.En 1
1: enable of phase overcurrent protection.
Current setting of stage 2 of generator
15 Gen.50/51P2.I_Set 0.05~20.00In 0.01 A
16 Gen.50/51P2.t_Op 0~3000 0.01 s
Memorizing time delay of stage 2 of
17 Gen.50/51P2.t_CurrMem 1~30 0.01 s
0: disable
1: enable
0: disable
1: enable
protection.
Logic setting of enabling/disabling fault
0: disable
21 Gen.50/51P2.En_CurrMem 1 current memorizing function of stage 2 of
1: enable
22 Gen.50/51P3.En 1
1: enable of generator phase overcurrent protection.
23 Gen.50/51P3.I_Set 0.05~20.00In 0.01 A Current setting of stage 3 of generator
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3 Operation Theory

24 Gen.50/51P3.t_Op 0~3000 0.01 s
Multiple of the maximum operating current
25 Gen.50/51P3.K_I_Max 10~40 0.01 to the pickup setting of stage 3 of generator
The base current of generator inverse-time
26 Gen.50/51P3.Ib_Set 0.10~4.00In 0.01 A
Time factor setting of stage 3 of generator
27 Gen.50/51P3.TMS 0.05~10.00 0.01
Minimum time delay of stage 3 of generator
28 Gen.50/51P3.tmin 0~10 0.01 s
The constant K of stage 3 of generator
29 Gen.50/51P3.K 0~120 0.01
The constant C of stage 3 of generator
30 Gen.50/51P3.C 0~20 0.01 s
The exponent alpha of stage 3 of generator
31 Gen.50/51P3.Alpha 0.02~5 0.01
Logic setting for selecting operating
32 Gen.50/51P3.Opt_Curve 0~13 1 characteristic curve of stage 3 of generator
0: disable
1: enable
0: disable
1: enable
protection.
Access path: Settings-> Prot Settings -> Gen OC Settings
3.21 Generator Phase Overvoltage Protection (Gen.59P)
3.21.1 Application
In the power system, there many causes will lead to overvoltage, such as mal-operation of the
excitation system, fault of voltage automatic adjustment device, load shedding due to full load of
generator, disconnection between generator and the system or isolated operation of the generator.
Overvoltage protection is provided to protect the operating equipment against the risk due to
abnormal rise of voltage.
Phase overvoltage protection has following functions:
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3 Operation Theory
 Two-stage phase overvoltage protection for tripping and one-stage phase overvoltage
protection for alarm are available (with respective voltage setting, time delay and logic
setting).
 Stage 1 of phase overvoltage protection for tripping and the phase overvoltage protection for
alarm are definite-time overvoltage protection fixedly, stage 2 of phase overvoltage
protection for tripping can be configured as inverse-time overvoltage protection (IDMT) or
definite-time overvoltage protection by the setting [Gen.59P2.Opt_Curve] (0: definite-time
characteristic, 1: inverse-time characteristic).
 Phase-to-phase voltage instead of phase-to-earth voltage is selected for overvoltage

protection calculation, it can prevent the overvoltage protection from mal-operation due to
single phase earthing for ungrounded system.

3.21.3.1 Fault Detector
When phase-to-phase voltage is larger than corresponding voltage setting, corresponding stage of
overvoltage protection will pick up and operate with a settable time delay.
 Phase-to-phase voltage criterion
For each stage of overvoltage protection, the operation criterion is:
U ϕϕ _ RMS > [Gen.59Pn.Upp_Set]

Equation 3.21-1
and U ϕϕ _ min >0.95* [Gen.59Pn.Upp_Set]
Where:
U ϕϕ _ min is the minimum value of amplitude of three phase-to-phase voltages.
U ϕϕ _ RMS is the RMS value of amplitude of three phase-to-phase voltages.
[Gen.59Pn.Upp_Set] is the phase-to-phase voltage setting of stage n (n=1 or 2 or Alm) of

overvoltage protection.
3.21.3.2 Time Curve
Stage 1 of phase overvoltage protection for tripping and the phase overvoltage protection for alarm
are definite-time overvoltage protection fixedly.
Stage 2 of phase overvoltage protection for tripping can be configured as inverse-time overvoltage
protection (IDMT) or definite-time overvoltage protection by the setting [Gen.59P2.Opt_Curve] (0:
definite-time characteristic, 1: inverse-time characteristic), the equation of inverse-time
characteristic is:
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3 Operation Theory
TP
t=
U Equation 3.21-2
−1
U set
Where:
U set is inverse-time overvoltage pick-up setting, corresponds to the setting [Gen.59P2.Upp_Set].
T p is inverse-time time factor, corresponds to the setting [Gen.59P2.TMS].
3.21.4 Logic
For each stage of phase overvoltage protection, if following three conditions are met,
corresponding stage of phase overvoltage protection will be enabled.
(1) Logic setting [Gen.59Pn.En] is set as “1”.
(2) The protection function enabling inputs [Gen.59Pn.En1], [Gen.59Pn.En2] are “1”
(3) The protection function blocking input [Gen.59Pn.Blk] is “0”.
If overvoltage protection is disabled, all the related output signals will be reset. If no external input
is configured to [Gen.59Pn.En1] ([Gen.59Pn.En2]), the default initial value of [Gen.59Pn.En1]
([Gen.59Pn.En2]) is “1”; if no external input is configured to [Gen.59Pn.Blk], the default initial value
of [Gen.59Pn.Blk] is “0”.
SIG [Gen.59PAlm.U3P]
&
SET [Gen.59PAlm.Upp_Set] [Gen.59PAlm.St]
EN [Gen.59Pn.En] &
SIG [Gen.59Pn.Blk]
Timer
Gen.59PAlm.t_Op
[Gen.59PAlm.Alm]
EN [Gen.59Pn.En]
SIG [Gen.59Pn.En1] &
SIG [Gen.59Pn.En2]
SIG [Gen.59Pn.Blk]
SIG [Gen.59Pn.U3P] &

[Gen.59Pn.St]
SET [Gen.59Pn.Upp_Set] Timer
t
0ms 500ms
[Gen.59Pn.Op]
SIG 59Pn.FD t
Inverse-time for stage 2 only
Figure 3.21-1 Logic diagram of phase overvoltage protection
Where:
[Gen.59Pn.U3P] is the three-phase voltage input for alarm or tripping stage of phase overvoltage
protection.
59Pn.FD is the signal to indicate that the fault detector of overvoltage protection picks up (the fault
detector of fault detector DSP module).
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3 Operation Theory
59Pn (n=1 or 2) 59PAlm
Gen.59Pn.U3P Gen.59Pn.St Gen.59PAlm.U3P Gen.59PAlm.St
Gen.59Pn.En1 Gen.59Pn.Op Gen.59PAlm.En1 Gen.59PAlm.Alm
Gen.59Pn.En2 Gen.59PAlm.En2
Gen.59Pn.Blk Gen.59PAlm.Blk
Figure 3.21-2 Function block diagram of phase overvoltage protection
Table 3.21-1 Input signals of phase overvoltage protection

1 Gen.59Pn.U3P Three-phase voltage data. (n=1 or 2 or Alm)
2 Gen.59Pn.En1 Protection function enabling input1 and input 2, it can be binary inputs or settings,
3 Gen.59Pn.En2 such as function enabling binary inputs, logic links, etc. (n=1 or 2 or Alm)
Protection function blocking input, such as function blocking binary input. (n=1 or 2 or
4 Gen.59Pn.Blk
Alm)
Table 3.21-2 Output signals of phase overvoltage protection

1 Gen.59P1.St Phase overvoltage protection tripping stage 1 starts.
3 Gen.59PAlm.St Phase overvoltage protection alarm stage starts.
4 Gen.59P1.Op Phase overvoltage protection tripping stage 1 operates.
6 Gen.59PAlm.Alm Phase overvoltage protection alarm stage operates to issue alarm signal.
Table 3.21-3 Output signals of phase overvoltage protection (event recorder)
Tripping reports
3 Gen.59PAlm.Alm Phase overvoltage protection alarm stage operates to issue alarm signal.
Start signals
6 Gen.59PAlm.St Phase overvoltage protection alarm stage starts.
Waveform recording
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3 Operation Theory
Phase overvoltage protection tripping stage 1 operates to trigger waveform

7 Gen.59P1.TrigDFR
recording.
Phase overvoltage protection tripping stage 2 operates to trigger waveform

8 Gen.59P2.TrigDFR
recording.
Table 3.21-4 Output signals of phase overvoltage protection (measurements)
4 Upp_Min The minimum value of three phase-to-phase voltages V
5 Upp_RMS The RMS value of three phase-to-phase voltages V
6 Upp_Peak The peak value of three phase-to-phase voltages V
Inverse-time accumulate value of stage 2 of phase overvoltage

7 Gen.59P2.Accu %
protection.
Access Path:
Main menu -> Measurements -> Measurements2-> Prot Values-> Gen Volt Prot Values
3.21.6 Settings
Table 3.21-5 Settings list of phase overvoltage protection

1 Gen.59P1.En 1
1: enable phase overvoltage protection.
Voltage setting of stage 1 of phase overvoltage
2 Gen.59P1.Upp_Set 0.10~200 0.01 V
protection.
Time delay of stage 1 of phase overvoltage
3 Gen.59P1.t_Op 0~30 0.01 s
protection.
Tripping logic setting of stage 1 of phase
4 Gen.59P1.OutMap 0~3FFFFFFF
0: disable
5 Gen.59P2.En 1 phase overvoltage protection.
1: enable
0: disable; 1: enable
Voltage setting of stage 2 of phase overvoltage
6 Gen.59P2.Upp_Set 0.10~200.00 0.01 V
protection.
Time delay of stage 2 of phase overvoltage
7 Gen.59P2.t_Op 0~30 0.01 s
protection.
Time factor setting of stage 2 of inverse-time
8 Gen.59P2.TMS 0.05~10.00 0.01 phase overvoltage protection. It is invalid if the
logic setting [59P2.Opt_Curve] is set as “0”.
Minimum time delay of stage 2 of inverse-time
9 Gen.59P2.tmin 0~10 0.01 s phase overvoltage protection. It is invalid if the
10 Gen.59P2.Opt_Curve 0~1 1 Logic setting for selecting operating
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3 Operation Theory

characteristic curve of stage 2 of phase
0: define-time
1: inverse-time
0: disable Logic setting of enabling/disabling phase
12 Gen.59PAlm.En 1
1: enable overvoltage protection alarm stage.
Voltage setting of phase overvoltage protection
13 Gen.59PAlm.Upp_Set 0.10~200.00 0.01 V
alarm stage.
Time delay of phase overvoltage protection alarm
14 Gen.59PAlm.t_Op 0~30 0.01 s
stage.
Access path: Settings-> Prot Settings -> Gen OV Settings
3.22 Phase Undervoltage Protection (27P)
3.22.1 Application
Undervoltage protection is used to detect the voltage decline of the operating motor, so to avoid
the impermissible operating conditions and the possible loss of stability. When the system voltage
decline to a certain degree so that the system stability will be affected, undervoltage protection can
be used as the operation criterion of load shedding.
Undervoltage protection has following functions:
 Two-stage phase undervoltage protection for tripping and one-stage phase undervoltage
protection for alarm are available (with respective voltage setting, time delay and logic
setting).
 Stage 1 of phase undervoltage protection for tripping and the phase undervoltage protection
for alarm are definite-time undervoltage protection fixedly, stage 2 of phase undervoltage
protection for tripping can be configured as inverse-time undervoltage protection (IDMT) or
definite-time undervoltage protection by the setting [Gen.27P2.Opt_Curve] (0: definite-time
characteristic, 1: inverse-time characteristic).
 Phase-to-phase voltage instead of phase-to-earth voltage is selected for undervoltage

protection calculation, it is insensitive to asymmetric voltage decline, but it is sensitive to
system stability problem.
3.22.3 Operation Principle

When phase-to-phase voltage is lower than corresponding voltage setting and the auxiliary
criterion is also met, corresponding stage of undervoltage protection will pick up and operate with
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3 Operation Theory
a settable time delay.
 Phase-to-phase voltage criterion
For each stage of undervoltage protection, the operation criterion is:
U φφ _ max > [Gen.27Px.Upp_Set] Equation 3.22-1
Where:
U φφ _ max is the maximum value of amplitude of three phase-to-phase voltages.
[Gen.27Px.Upp_Set] is the phase-to-phase voltage setting of stage x (x=1 or 2 or Alm) of

undervoltage protection.
3.22.3.2 Time Curve
Stage 1 of phase undervoltage protection for tripping and the phase undervoltage protection for
alarm are definite-time undervoltage protection fixedly.
Stage 2 of phase undervoltage protection for tripping can be configured as inverse-time

undervoltage protection (IDMT) or definite-time undervoltage protection by the setting
[Gen.27P2.Opt_Curve] (0: definite-time characteristic, 1: inverse-time characteristic), the equation
of inverse-time characteristic is:
TP
t=
U Equation 3.22-2
1−
U set
Where:
U set is inverse-time undervoltage pick-up setting, corresponds to the setting [Gen.27P2.Upp_Set].
T p is inverse-time time factor, corresponds to the setting [Gen.27P2.TMS].
3.22.3.3 Auxiliary Criterion
Undervoltage protection can be blocked by the normally open auxiliary contact of the circuit
breaker [Flg_52a]. If [Flg_52a] is “0”, undervoltage protection is blocked. Besides, the normally
open auxiliary contact of the circuit breaker can be replaced by the internal signal that indicating
the generator is connected with the system.
The undervoltage protection is also controlled by the load current, only if any phase current is
larger than 0.04In (the signal [Gen.27Px.Flg_OnLoad]=1), the undervoltage protection can be
enabled.
When a fault happens at the secondary circuit of VT, the undervoltage protection tripping stage
can be blocked by a binary input signal (such as VT MCB auxiliary contact and etc.). The output
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3 Operation Theory
signal of VT circuit supervision function can also be adopted to block the undervoltage protection.
[Flg_52a], [Gen.27Px.Flg_OnLoad] and the VT abnormal binary input (or signal) can be configured
by the software PCS-Explorer2.
3.22.4 Logic
For each stage of phase undervoltage protection, if following three conditions are met,
corresponding stage of phase undervoltage protection will be enabled.
(1) Logic setting [Gen.27Pn.En] is set as “1”.
(2) The protection function enabling inputs [Gen.27Pn.En1], [Gen.27Pn.En2] are “1”
(3) The protection function blocking input [Gen.27Pn.Blk] is “0”.
If undervoltage protection is disabled, all the related output signals will be reset. If no external input
is configured to [Gen.27Pn.En1] ([Gen.27Pn.En2]), the default initial value of [Gen.27Pn.En1]
([Gen.27Pn.En2]) is “1”; if no external input is configured to [Gen.27Pn.Blk], the default initial value
of [Gen.27Pn.Blk] is “0”.
Logic diagram of undervoltage protection is shown in the following figure.
SET UΦΦ_max<[Gen.27PAlm.Upp_Set] &

EN [Gen.27Pn.En] [Gen.27PAlm.St]
SIG [Gen.27Pn.Blk]
Timer
EN [Gen.27Pn.En] Gen.27PAlm.t_Op
& [Gen.27PAlm.Alm]
SIG [Gen.27Pn.En1]
SIG [Gen.27Pn.En2]
SIG [Gen.27Pn.Blk]
&
SET UΦΦ_max<[Gen.27Pn.Upp_Set] [Gen.27Pn.St]
0ms 500ms
SIG Gen.27Pn.FD
Timer
t
[Gen.27Pn.Op]
t
Inverse-time for stage 2 only
Figure 3.22-1 Logic diagram of undervoltage protection
Where:
n=1 or 2 or Alm;
Gen.27Pn.FD is the internal signal to indicate that stage n of undervoltage protection picks up (the
Date: 2016-08-16
3 Operation Theory
27Pn (n=1 or 2) 27PAlm
Gen.27Pn.U3P Gen.27Pn.St Gen.27PAlm.U3P Gen.27PAlm.St
Gen.27Pn.En1 Gen.27Pn.Op Gen.27PAlm.En1 Gen.27PAlm.Alm
Gen.27Pn.En2 Gen.27PAlm.En2
Gen.27Pn.Blk Gen.27PAlm.Blk
Flg_52a Flg_52a
Gen.27Pn.Flg_Onload Gen.27PAlm.Flg_Onload
Figure 3.22-2 Function block diagram of undervoltage protection
Table 3.22-1 Input signals of undervoltage protection

1 Gen.27Pn.U3P Three-phase voltage data. (n=1 or 2 or Alm)
3 Gen.27Pn.Flg_Onload The signal indicating that the load current is detected. (n=1 or 2 or Alm)
4 Gen.27Pn.En1 Protection function enabling input1 and input 2, it can be binary inputs or settings,
5 Gen.27Pn.En2 such as function enabling binary inputs, logic links, etc. (n=1 or 2 or Alm)
Protection function blocking input, such as function blocking binary input. (n=1 or 2
6 Gen.27Pn.Blk
or Alm)
Table 3.22-2 Output signals of undervoltage protection

1 Gen.27P1.St Phase undervoltage protection tripping stage 1 starts.
3 Gen.27PAlm.St Phase undervoltage protection alarm stage starts.
4 Gen.27P1.Op Phase undervoltage protection tripping stage 1 operates.
6 Gen.27PAlm.Alm Phase undervoltage protection alarm stage operates to issue alarm signal.
Table 3.22-3 Output signals of phase undervoltage protection (event recorder)
Tripping reports
3 Gen.27PAlm.Alm Phase undervoltage protection alarm stage operates to issue alarm signal.
Start signals
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6 Gen.27PAlm.St Phase undervoltage protection alarm stage starts.
Waveform recording
Phase undervoltage protection tripping stage 1 operates to trigger waveform

7 Gen.27P1.TrigDFR
recording.
Phase undervoltage protection tripping stage 2 operates to trigger waveform

8 Gen.27P2.TrigDFR
recording.
Table 3.22-4 Output signals of phase undervoltage protection (measurements)
1 Upp_Max The maximum value of three phase-to-phase voltages V
Inverse-time accumulate value of stage 2 of phase undervoltage

2 Gen.27P2.Accu %
protection.
Access Path:
Main menu -> Measurements -> Measurements2-> Prot Values-> Gen Volt Prot Values
3.22.6 Settings
Table 3.22-5 Settings list of undervoltage protection

1 Gen.27P1.En 1
1: enable phase undervoltage protection.
Voltage setting of stage 1 of phase undervoltage
2 Gen.27P1.Upp_Set 0.10~120 0.01 V
protection.
Time delay of stage 1 of phase undervoltage
3 Gen.27P1.t_Op 0~30 0.01 s
protection.
0: disable
5 Gen.27P2.En 1 phase undervoltage protection.
1: enable
0: disable; 1: enable
Voltage setting of stage 2 of phase undervoltage
6 Gen.27P2.Upp_Set 0.10~120.00 0.01 V
protection.
Time delay of stage 2 of phase undervoltage
7 Gen.27P2.t_Op 0~30 0.01 s
protection.
Time factor setting of stage 2 of inverse-time
8 Gen.27P2.TMS 0.05~10.00 0.01 phase undervoltage protection. It is invalid if the
Minimum time delay of stage 2 of inverse-time
9 Gen.27P2.tmin 0~10 0.01 s phase undervoltage protection. It is invalid if the
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3 Operation Theory

Logic setting for selecting operating
characteristic curve of stage 2 of phase
10 Gen.27P2.Opt_Curve 0~1 1 undervoltage protection.
0: define-time
1: inverse-time
0: disable Logic setting of enabling/disabling phase
12 Gen.27PAlm.En 1
1: enable undervoltage protection alarm stage.
Voltage setting of phase undervoltage protection
13 Gen.27PAlm.Upp_Set 0.10~120.00 0.01 V
alarm stage.
Time delay of phase undervoltage protection
14 Gen.27PAlm.t_Op 0~30 0.01 s
alarm stage.
Access path: Settings-> Prot Settings -> Gen UV Settings
3.23 Overfrequency Protection (81O)
3.23.1 Application
When active power surplus happens to the power system or the speed regulating system of
generator is in abnormal operation, the frequency of the power system will rise, so overfrequency
protection can be used to detect the above abnormal over-frequency conditions. If the frequency is
larger than the overfrequency protection setting, overfrequency protection will operate to issue
alarm signal or trip with a time delay.
Steam-turbine generator is able to withstand the frequency shifting, but this will leads to the
vibration of the turbine blade which will eventually cause the metal fatigue damage of the blade.
This kind of damage is a process of accumulation and it is irreversible, therefore, when the
frequency protection is applied for steam-turbine generator, a feature of frequency accumulation is
required.
Overfrequency protection has following functions:
 Four stages of overfrequency protection (with respective frequency setting, time delay and
logic setting) are available. Each stage can be configured to issue alarm signal or trip.
 Four stages of overfrequency band accumulate protection are available and each stage has
respective frequency upper limit setting, lower limit frequency setting, accumulated time
setting and logic setting. Each stage can be configured to issue alarm signal or trip.

3.23.3.1 Overview
When the system frequency is larger than the overfrequency setting, the protection picks up, after
Date: 2016-08-16
3 Operation Theory
a time delay determined by the time delay setting, the overfrequency protection will operate to
issue alarm signal or trip. If the frequency accumulation function is enabled, i.e. the logic setting
[81O.OFx.En_Alm_Accu] or [81O.OFx.En_Trp_Accu] (x=1~4) is set as “1”, the relay will
accumulate the time that the system frequency falling into the corresponding overfrequency band,
if the accumulated time is larger than the corresponding time delay setting, the overfrequency
band accumulate protection will operate to issue alarm signal or trip.
The positive voltage is used to calculate the system frequency, after a filtering process, the
measurement of system frequency will not be affected by the harmonic component.
 Operation criterion of overfrequency protection
f >[81O.OFx.f_Set] Equation 3.23-1
Where:
f is system frequency.
[81O.OFx.f_Set] is the frequency setting of stage x (x=1~4) of overfrequency protection.
 Operation criterion of overfrequency band accumulate protection
[81O.OFx’.f_Set] > f >[81O.OFx.f_Set] Equation 3.23-2
Where:
[81O.OFx.f_Set] is the lower limit frequency setting of stage x (x=1~4) of overfrequency band
accumulate protection.
[81U.UFx’.f_Set] is the upper limit frequency setting of stage x (x=1~4) of overfrequency band
If x=1~3, x’=x+1.
If x=4, the operation criterion of overfrequency band accumulation protection is:
f >[81O.OF4.f_Set] Equation 3.23-3
If the setting [81O.En_NVM_Accu] is set as “0”, the accumulation value will be cleared
automatically when this protection is reverted. If the setting [81O.En_NVM_Accu] is set as “1”, the
accumulation value will be kept even this protection is reverted or this device is re-energized,
when this protection is picked up again, the accumulation value will be accumulated continuously
on the base of present accumulation value. The accumulation value can be cleared by energizing
the binary input [81O.Clear].
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3.23.4 Logic
For overfrequency protection, when following three conditions are met, the protection is enabled.
(1) Logic setting [81O.En] is set as “1”.
(2) The protection function enabling binary inputs [81O.En1] and [81O.En2] are “1”
(3) The protection function blocking input [81O.Blk] is “0”.
If overfrequency protection is disabled, all the related output signals will be reset. If no external
input is configured to [81O.En1] ([81O.En2]), the default initial value of [81O.En1] ([81O.En2]) is
“1”; if no external input is configured to [81O.Blk], the default initial value of [81O.Blk] is “0”.
EN [81O.En] &
SIG [81O.Blk] &
[81O.OFx.t_Op] 0s
[81O.OFx.Alm]
EN [81O.OFx.En_Alm] &
SIG f > [81O.OFx.f_Set]
& [81O.St]
EN [81O.En]
& [81O.OFx.t_Op] 0s
EN [81O.OFx.En_Trp] &
[81O.OFx.Op]
SIG f > [81O.OFx.f_Set]
SIG [81O.En1] &

SIG [81O.En2]
SIG [81O.Blk]
0 500ms
SIG 81O.FD
Figure 3.23-1 Logic diagram of stage x of overfrequency protection
EN [81O.En] &
SIG [81O.Blk]
SIG [Flg_52a] &
SIG [81O.Flg_OnLoad]
&
[81O.OF1.t_Accu] 0s
[81O.OF1.Alm_Accu]
EN [81O.OF1.En_Alm_Accu] &
SIG [81O.OF2.f_Set]>f>[81O.OF1.f_Set]
& [81O.St]
EN [81O.En]
& [81O.OF1.t_Accu] 0s
EN [81O.OF1.En_Trp_Accu] &
[81O.OF1.Op_Accu]
SIG [81O.OF2.f_Set]>f>[81O.OF1.f_Set]
SIG [81O.En1] &

SIG [81O.En2]
SIG [81O.Blk]
0 500ms
SIG 81O.FD
Figure 3.23-2 Logic diagram of stage 1 of overfrequency band accumulate protection
The stage 2 and stage 3 of overfrequency band accumulate protection are similar to stage 1 of
overfrequency band accumulate protection.
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3 Operation Theory
EN [81O.En] &
SIG [81O.Blk]
SIG [Flg_52a] &
SIG [81O.Flg_OnLoad]
&
[81O.OF4.t_Accu] 0s
[81O.OF4.Alm_Accu]
EN [81O.OF4.En_Alm_Accu] &
SIG f>[81O.OF4.f_Set]
& [81O.St]
EN [81O.En]
& [81O.OF4.t_Accu] 0s
EN [81O.OF4.En_Trp_Accu] &
[81O.OF4.Op_Accu]
SIG f>[81O.OF4.f_Set]
SIG [81O.En1] &

SIG [81O.En2]
SIG [81O.Blk]
0 500ms
SIG 81O.FD
Figure 3.23-3 Logic diagram of stage 4 of overfrequency band accumulate protection
Where:
81O.FD is the internal signal to indicate that overfrequency protection picks up (the fault detector
of fault detector DSP module).
81O
f 81O.St
81O.En1 81O.OF1.Op
81O.En2 81O.OF2.Op
81O.Blk 81O.OF3.Op
81O.Flg_OnLoad 81O.OF4.Op
Flg_52a 81O.OF1.Op_Accu
Clear 81O.OF2.Op_Accu
81O.OF3.Op_Accu
81O.OF4.Op_Accu
81O.OF1.Alm
81O.OF2.Alm
81O.OF3.Alm
81O.OF4.Alm
81O.OF1.Alm_Accu
81O.OF2.Alm_Accu
81O.OF3.Alm_Accu
81O.OF4.Alm_Accu
Figure 3.23-4 Function block diagram of overfrequenncy protection
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3 Operation Theory
Table 3.23-1 Input signals of overfrequenncy protection

2 81O.Flg_Onload The signal indicating that current is detected.
3 f Measured frequency data input.
4 81O.En1 Protection function enabling input1 and input 2, it can be binary inputs or settings, such
5 81O.En2 as function enabling binary inputs, logic links, etc.
6 81O.Blk Protection function blocking input, such as function blocking binary input.
Overfrequency accumulation value clearing input, it can be configured through
7 81O.Clear
PCS-Explorer2
Table 3.23-2 Output signals of overfrequenncy protection

1 81O.St Overfrequency protection starts.
2 81O.OF1.Op Stage 1 of overfrequency protection operates to trip.
6 81O.OF1.Op_Accu Stage 1 of overfrequency band accumulate protection operates to trip.
10 81O.OF1.Alm Stage 1 of overfrequency protection operates to issue alarm signal.
14 81O.OF1.Alm_Accu Stage 1 of overfrequency band accumulate protection operates to issue alarm signal.
Table 3.23-3 Output signals of overfrequency protection (event recorder)
Tripping reports
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3 Operation Theory
Start signals
9 81O.St Overfrequency protection starts.
Alarm signals
Stage 1 of overfrequency band accumulate protection operates to issue alarm

14 81O.OF1.Alm_Accu
signal.

15 81O.OF2.Alm_Accu
signal.

16 81O.OF3.Alm_Accu
signal.

17 81O.OF4.Alm_Accu
signal.
Waveform recording
18 81O.TrigDFR Underfrequency protection operates to trigger waveform recording.
IO events
19 81O.OF1.St Stage 1 of overfrequency protection starts.
23 81O.OF1.St_Accu Stage 1 of overfrequency band accumulate protection starts.
Table 3.23-4 Output signals of overfrequency protection (measurements)
1 81O.OF1.Dur_Accu The accumulate duration of stage 1 of overfrequency protection min
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3 Operation Theory
Access Path:
Main menu -> Measurements -> Measurements2-> Prot Values-> Freq Prot Values
3.23.6 Settings
Table 3.23-5 Settings list of overfrequency protection

1 81O.En 1
1: enable overfrequency protection.
Frequency setting of stage 1 of overfrequency

2 81O.OF1.f_Set 50.00~70.00 0.01 Hz
protection.
Time delay of stage 1 of overfrequency band

3 81O.OF1.t_Accu 0.10~300.00 0.01 min
Time delay of stage 1 of overfrequency

4 81O.OF1.t_Op 0.10~300.00 0.01 s
protection.

5 81O.OF1.OutMap 0~3FFFFFFF
overfrequency protection.

6 81O.OF2.f_Set 50.00~70.00 0.01 Hz
protection.

7 81O.OF2.t_Accu 0.10~300.00 0.01 min

8 81O.OF2.t_Op 0.10~300.00 0.01 s
protection.


10 81O.OF3.f_Set 50.00~70.00 0.01 Hz
protection.

11 81O.OF3.t_Accu 0.10~300.00 0.01 min

12 81O.OF3.t_Op 0.10~300.00 0.01 s
protection.


14 81O.OF4.f_Set 50.00~70.00 0.01 Hz
protection.

15 81O.OF4.t_Accu 0.10~300.00 0.01 min

16 81O.OF4.t_Op 0.10~300.00 0.01 s
protection.
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3 Operation Theory


0: disable
18 81O.OF1.En_Alm 1 overfrequency protection operates to issue
1: enable
alarm signal.

19 81O.OF1.En_Trp 1
1: enable overfrequency protection operates to trip.

0: disable
20 81O.OF1.En_Alm_Accu 1 overfrequency band accumulate protection
1: enable

0: disable
21 81O.OF1.En_Trp_Accu 1 overfrequency band accumulate protection
1: enable
operates to trip.

0: disable
1: enable
alarm signal.

23 81O.OF2.En_Trp 1

0: disable
1: enable

0: disable
1: enable
operates to trip.

0: disable
1: enable
alarm signal.

27 81O.OF3.En_Trp 1

0: disable
1: enable

0: disable
1: enable
operates to trip.

0: disable
1: enable
alarm signal.

31 81O.OF4.En_Trp 1
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3 Operation Theory

0: disable
1: enable

0: disable
1: enable
operates to trip.
Access path: Settings-> Prot Settings -> OverFreq Settings
Logic setting of enabling non-volatile memory

for accumulation duration of overfrequency
0: disable
34 81O.En_NVM_Accu 1 protection. When it is set as “1”, the accumulate
1: enable
duration of overfrequency protection will not be
cleared even when the device is not powered.
3.24 Underfrequency Protection (81U)
3.24.1 Application
When the power system requires more active power or the speed regulating system of generator
is in abnormal operation, the frequency of the power system will decline, so underfrequency
protection can be used to detect the above abnormal low-frequency conditions. If the frequency is
lower than the underfrequency protection setting, underfrequency protection will operate to issue
alarm signal or trip with a time delay.
Steam-turbine generator is able to withstand the frequency shifting, but this will leads to the
vibration of the turbine blade which will eventually cause the metal fatigue damage of the blade.
This kind of damage is a process of accumulation and it is irreversible, therefore, when the
frequency protection is applied for steam-turbine generator, a feature of frequency accumulation is
required.
Underfrequency protection has following functions:
 Four stages of underfrequency protection (with respective frequency setting, time delay and
logic setting) are available. Each stage can be configured to issue alarm signal or trip.
 Four stages of underfrequency band accumulate protection are available and each stage has
respective frequency upper limit setting, lower limit frequency setting, accumulated time
setting and logic setting. Each stage can be configured to issue alarm signal or trip.

3.24.3.1 Overview
When the system frequency is smaller than the underfrequency setting, the protection picks up,
Date: 2016-08-16
3 Operation Theory
after a time delay determined by the time delay setting, the underfrequency protection will operate
to issue alarm signal or trip. If the frequency accumulation function is enabled, i.e. the logic setting
[81U.UFx.En_Alm_Accu] or [81U.UFx.En_Trp_Accu] (x=1~4) is set as “1”, the relay will
accumulate the time that the system frequency falling into the corresponding underfrequency band,
if the accumulated time is larger than the corresponding time delay setting, the underfrequency
band accumulate protection will operate to issue alarm signal or trip.
The positive voltage is used to calculate the system frequency, after a filtering process, the
measurement of system frequency will not be affected by the harmonic component.
 Operation criterion of underfrequency protection
f <[81U.UFx.f_Set] Equation 3.24-1
Where:
[81U.UFx.f_Set] is the frequency setting of stage x (x=1~4) of underfrequency protection.
 Operation criterion of underfrequency band accumulate protection
[81U.UFx’.f_Set] < f <[81U.UFx.f_Set] Equation 3.24-2
Where:
[81U.UFx.f_Set] is the upper limit frequency setting of stage x (x=1~4) of underfrequency band
[81U.UFx’.f_Set] is the lower limit frequency setting of stage x (x=1~4) of underfrequency band
If x=4, [81U.UFx’.f_Set]=0; if x=1~3, x’=x+1.
If the setting [81U.En_NVM_Accu] is set as “0”, the accumulation value will be cleared
automatically when this protection is reverted. If the setting [81U.En_NVM_Accu] is set as “1”, the
accumulation value will be kept even this protection is reverted or this device is re-energized,
when this protection is picked up again, the accumulation value will be accumulated continuously
on the base of present accumulation value. The accumulation value can be cleared by energizing
the binary input [81U.Clear].
3.24.4 Logic
For underfrequency protection, when following three conditions are met, the protection is enabled.
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3 Operation Theory
(1) Logic setting [81U.En] is set as “1”.
(2) The protection function enabling binary inputs [81U.En1] and [81U.En2] are “1”
(3) The protection function blocking input [81U.Blk] is “0”.
If underfrequency protection is disabled, all the related output signals will be reset. If no external
input is configured to [81U.En1] ([81U.En2]), the default initial value of [81U.En1] ([81U.En2]) is “1”;
if no external input is configured to [81U.Blk], the default initial value of [81U.Blk] is “0”.
EN [81U.En] &
SIG [81U.Blk]
SIG [Flg_52a] &
SIG [81U.Flg_OnLoad]
&
[81U.UFx.t_Op] 0s
[81U.UFx.Alm]
EN [81U.UFx.En_Alm] &
SIG f < [81U.UFx.f_Set]
& [81U.St]
EN [81U.En]
& [81U.UFx.t_Op] 0s
EN [81U.UFx.En_Trp] &
[81U.UFx.Op]
SIG f < [81U.UFx.f_Set]
SIG [81U.En1] &

SIG [81U.En2]
SIG [81U.Blk]
0 500ms
SIG 81U.FD
Figure 3.24-1 Logic diagram of stage x of underfrequency protection (x=1~4)
EN [81U.En] &
SIG [81U.Blk]
SIG [Flg_52a] &
&
[81U.UF1.t_Accu] 0s
[81U.UF1.Alm_Accu]
EN [81U.UF1.En_Alm_Accu] &
SIG [81U.UF2.f_Set]<f< [81U.UF1.f_Set]
& [81U.St]
EN [81U.En]
& [81U.UF1.t_Accu] 0s
EN [81U.UF1.En_Trp_Accu] &
[81U.UF1.Op_Accu]
SIG [81U.UF2.f_Set]<f< [81U.UF1.f_Set]
SIG [81U.En1] &

SIG [81U.En2]
SIG [81U.Blk]
0 500ms
SIG 81U.FD
The stage 2 and stage 3 of underfrequency band accumulate protection are similar to stage 1 of
underfrequency band accumulate protection.
Date: 2016-08-16
3 Operation Theory
EN [81U.En] &
SIG [81U.Blk]
SIG [Flg_52a] &
&
[81U.UF4.t_Accu] 0s
[81U.UF4.Alm_Accu]
EN [81U.UF4.En_Alm_Accu] &
SIG 0<f< [81U.UF4.f_Set]
& [81U.St]
EN [81U.En]
& [81U.UF4.t_Accu] 0s
EN [81U.UF4.En_Trp_Accu] &
[81U.UF4.Op_Accu]
SIG 0<f< [81U.UF4.f_Set]
SIG [81U.En1] &

SIG [81U.En2]
SIG [81U.Blk]
0 500ms
SIG 81U.FD
Where:
81U.FD is the internal signal to indicate that underfrequency protection picks up (the fault detector
of fault detector DSP module).
81U
f 81U.St
81U.En1 81U.UF1.Op
81U.En2 81U.UF2.Op
81U.Blk 81U.UF3.Op
81U.Flg_OnLoad 81U.UF4.Op
Flg_52a 81U.UF1.Op_Accu
Clear 81U.UF2.Op_Accu
81U.UF3.Op_Accu
81U.UF4.Op_Accu
81U.UF1.Alm
81U.UF2.Alm
81U.UF3.Alm
81U.UF4.Alm
81U.UF1.Alm_Accu
81U.UF2.Alm_Accu
81U.UF3.Alm_Accu
81U.UF4.Alm_Accu
Figure 3.24-4 Function block diagram of underfrequency protection
Date: 2016-08-16
3 Operation Theory
Table 3.24-1 Input signals of underfrequency protection

2 81U.Flg_Onload The signal indicating that current is detected.
3 f Measured frequency data input.
4 81U.En1 Protection function enabling input1 and input 2, it can be binary inputs or settings, such
5 81U.En2 as function enabling binary inputs, logic links, etc.
6 81U.Blk Protection function blocking input, such as function blocking binary input.
Underfrequency accumulation value clearing input, it can be configured through
7 81U.Clear
PCS-Explorer2
Table 3.24-2 Output signals of underfrequency protection

1 81U.St Underfrequency protection starts.
2 81U.UF1.Op Stage 1 of underfrequency protection operates to trip.
6 81U.UF1.Op_Accu Stage 1 of underfrequency band accumulate protection operates to trip.
10 81U.UF1.Alm Stage 1 of underfrequency protection operates to issue alarm signal.
Stage 1 of underfrequency band accumulate protection operates to issue alarm
14 81U.UF1.Alm_Accu
signal.
15 81U.UF2.Alm_Accu
signal.
16 81U.UF3.Alm_Accu
signal.
17 81U.UF4.Alm_Accu
signal.
Table 3.24-3 Output signals of underfrequency protection (event recorder)
Tripping reports
Date: 2016-08-16
3 Operation Theory
Start signals
9 81U.St Underfrequency protection starts.
Alarm signals

14 81U.UF1.Alm_Accu
signal.

15 81U.UF2.Alm_Accu
signal.

16 81U.UF3.Alm_Accu
signal.

17 81U.UF4.Alm_Accu
signal.
Waveform recording
18 81U.TrigDFR Underfrequency protection operates to trigger waveform recording.
IO events
19 81U.UF1.St Stage 1 of underfrequency protection starts.
23 81U.UF1.St_Accu Stage 1 of underfrequency band accumulate protection starts.
Date: 2016-08-16
3 Operation Theory
Table 3.24-4 Output signals of underfrequency protection (measurements)
1 81U.UF1.Dur_Accu The accumulate duration of stage 1 of underfrequency protection min
Access Path:
Main menu -> Measurements -> Measurements2-> Prot Values-> Freq Prot Values
3.24.6 Settings
Table 3.24-5 Settings list of underfrequency protection

1 81U.En 1
1: enable underfrequency protection.
Frequency setting of stage 1 of underfrequency

2 81U.UF1.f_Set 45.00~61.00 0.01 Hz
protection.
Time delay of stage 1 of underfrequency band

3 81U.UF1.t_Accu 0.10~300.00 0.01 min
Time delay of stage 1 of underfrequency

4 81U.UF1.t_Op 0.10~300.00 0.01 s
protection.

5 81U.UF1.OutMap 0~3FFFFFFF
underfrequency protection.

6 81U.UF2.f_Set 45.00~61.00 0.01 Hz
protection.

7 81U.UF2.t_Accu 0.10~300.00 0.01 min

8 81U.UF2.t_Op 0.10~300.00 0.01 s
protection.


10 81U.UF3.f_Set 45.00~61.00 0.01 Hz
protection.

11 81U.UF3.t_Accu 0.10~300.00 0.01 min

12 81U.UF3.t_Op 0.10~300.00 0.01 s
protection.

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14 81U.UF4.f_Set 45.00~61.00 0.01 Hz
protection.

15 81U.UF4.t_Accu 0.10~300.00 0.01 min

16 81U.UF4.t_Op 0.10~300.00 0.01 s
protection.


0: disable
18 81U.UF1.En_Alm 1 underfrequency protection operates to issue
1: enable
alarm signal.

19 81U.UF1.En_Trp 1
1: enable underfrequency protection operates to trip.

0: disable
20 81U.UF1.En_Alm_Accu 1 underfrequency band accumulate protection
1: enable

0: disable
21 81U.UF1.En_Trp_Accu 1 underfrequency band accumulate protection
1: enable
operates to trip.

0: disable
1: enable
alarm signal.

23 81U.UF2.En_Trp 1

0: disable
1: enable

0: disable
1: enable
operates to trip.

0: disable
1: enable
alarm signal.

27 81U.UF3.En_Trp 1

0: disable
1: enable
29 81U.UF3.En_Trp_Accu 0: disable 1 Logic setting of enabling/disabling stage 3 of
Date: 2016-08-16
3 Operation Theory
1: enable underfrequency band accumulate protection

operates to trip.

0: disable
1: enable
alarm signal.

31 81U.UF4.En_Trp 1

0: disable
1: enable

0: disable
1: enable
operates to trip.
Access path: Settings-> Prot Settings -> UnderFreq Settings
Logic setting of enabling non-volatile memory

for accumulate duration of underfrequency
0: disable protection. When it is set as “1”, the accumulate
34 81U.En_NVM_Accu 1
1: enable duration of underfrequency protection will not
be cleared even when the device is not
powered.
3.25 Impedance Protection (21)
3.25.1 Application
When generator phase overcurrent protection cannot meet the sensitivity requirement of
generator and transformer backup protection, generator impedance protection can be configured.
The operation mode of power system has little effect on impedance protection, so impedance
protection can coordinate with protections of adjacent equipment easily.
 Two stage phase-to-phase impedance protection elements with respective impedance setting,
time delay setting and logic setting.
 Two stage phase-to-earth impedance protection elements with respective impedance setting,
time delay setting and logic setting.
 Power swing blocking releasing function.
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3.25.3.1 Overview
Impedance protection includes phase-to-phase impedance protection and phase-to-earth

protection. Positive polarity of CT is at generator neutral point side, and direction settings should
be set according to the principle.
The fault detector of impedance protection includes the DPFC phase-to-phase current fault
detector and the negative-sequence current fault detector. The fault detector output signal will last
for 500ms after the corresponding fault detector picks up, if phase-to-phase or phase-to-earth
impedance relay operates within 500ms, the fault detector output signal will be kept.
 DPFC phase-to-phase current fault detector
Criteria of this fault detector:
∆I > 1.25∆I t + I th Equation 3.25-1
Where:
∆I t is the floating threshold value which will arise automatically and gradually according to
increasing of the current changing. The coefficient takes 1.25 in order to ensure the threshold
current is always slightly larger than the unbalance output, so the protection will not mal-operate
under power swing and frequency shifting condition.
∆I is the deviation value of phase-to-phase current.
I th is the fixed threshold 0.2In and it does not need to be set.
 Negative-sequence current fault detector
Criteria of this fault detector:
I 2> 0.2In Equation 3.25-2
Where:
I 2 is the negative-sequence current of one side.
In is the secondary rated current of CT.
3.25.3.3 Direction Element
If VT and CT are connected as following figure, i.e. the positive polarity of CT is at busbar side,
points to the protected object, then the setting [Y.21Mx.ZP.Opt_Dir] and [Y.21Mx.ZG.Opt_Dir]
should be set as “1”. Otherwise [Y.21Mx.ZP.Opt_Dir] and [Y.21Mx.ZG.Opt_Dir] should be set as “0”.
Date: 2016-08-16
3 Operation Theory
Symbol “ ” represents the positive polarity of current transformer.
Reverse Forward
CT
Protected
Object
VT
Direction
Element
Figure 3.25-1 Connection of VT and CT of direction element
3.25.3.4 Phase-to-Phase Impedance Protection
Following figure shows operating characteristic of phase-to-phase impedance relay, the setting
[Y.21Mx.RCA] (x=1 or 2) is impedance characteristic angle (i.e. ϕ m shown in the following figure,
it is also called reach angle). In the figure, if the setting [Y.21Mx.ZP.Opt_Dir] is “1”, Zn is the
reverse impedance setting [Y.21Mx.ZP.Z_Rev] and Zp is the forward impedance setting
[Y.21Mx.ZP.Z_Fwd]. If the setting [Y.21Mx.ZP.Opt_Dir] is “0”, Zn is the forward impedance setting
[Y.21Mx.ZP.Z_Fwd] and Zp is the reverse impedance setting [Y.21Mx.ZP.Z_Rev].
jx

IZ p
U − IZ

p
U
ϕm
R
 U + IZ

− IZ n
n
Figure 3.25-2 Operating characteristic of phase-to-phase impedance relay
The operation criterion of phase-to-phase impedance relay is as follows.

• •
(U − I Z P )
90 < Arg

• •
< 270 Equation 3.25-3
(U + I Z n )
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3 Operation Theory
Where:
U is phase-to-phase voltage vector.
I is phase-to-phase current vector.
NOTICE!
When [Gen.21Mx.En_VTS_Blk] is “1”, if VT circuit failure signal [G_Term.VT1.Alm_VTS]

or [G_Term.VT2.Alm_VTS] is issued, phase-to-phase impedance protection will be
BLOCKED.
3.25.3.5 Phase-to-Earth Impedance Protection
Following figure shows operating characteristic of phase-to-earth impedance relay, the setting
[Y.21Mx.RCA] (x=1 or 2) is impedance characteristic angle (i.e. ϕ m shown in the following figure,
it is also called reach angle). In the figure, If the setting [Y.21Mx.ZG.Opt_Dir] is “1”, Zn is the
reverse impedance setting [Y.21Mx.ZG.Z_Rev] and ZG is the forward impedance setting
[Y.21Mx.ZG.Z_Fwd]. If the setting [Y.21Mx.ZG.Opt_Dir] is “0”, Zn is the forward impedance setting
[Y.21Mx.ZG.Z_Fwd] and ZG is the reverse impedance setting [Y.21Mx.ZG.Z_Rev].
jx •
I ϕ ZG
• •
Uϕ − I ϕ ZG
U φ
ϕm
R
• •
•
Uϕ + I ϕ Z n
- I ϕ Zn
Figure 3.25-3 Operating characteristic of phase-to-earth impedance relay
The operation criterion of phase-to-earth impedance relay is as follows.
• •
Uϕ − I ϕ ZG
90 < Arg • •
< 270 Equation 3.25-4
Uϕ + I ϕ Z n
Where:
U φ is phase-to-earth voltage vector.
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3 Operation Theory
Iφ is phase-to-earth current vector.
NOTICE!
When [Gen.21Mx.En_VTS_Blk] is “1”, if VT circuit failure signal [G_Term.VT1.Alm_VTS]

or [G_Term.VT2.Alm_VTS] is issued, phase-to-earth impedance protection will be
BLOCKED.
3.25.3.6 Power Swing Blocking Releasing (PSBR)
The device adopts power swing blocking releasing to avoid mal-operation of impedance protection
due to power swing. The protection is blocked all along under the normal condition and power
swing. Only if fault (internal fault or power swing with internal fault) is detected, power swing
blocking for impedance protection is released by PSBR element.
The logic setting [Gen.21Mx.En_PSBR] is used to enable or disable PSBR function. If it is set as
“1”, the PSBR function is enabled. Otherwise, it is disabled.
If the time delay of impedance protection is more than 1.5s, PSBR function is not needed for the
impedance protection.
Power swing blocking for impedance relay will be released if any of the following PSBR elements
operate.
 Fault detector PSBR element (FD PSBR)
 Unsymmetrical fault PSBR element (UF PSBR)
 Symmetrical fault PSBR element (SF PSBR)
1. Fault detector PSBR element
At the moment that any impedance protection fault detector picks up, if positive-sequence
overcurrent element does not operate or the operating duration is less then 10ms, FD PSBR will
operate for 160ms.
Positive-sequence overcurrent element:
I1<[Gen.21Mx.I_PSBR] Equation 3.25-5
I1 is positive-sequence current.
[Gen.21Mx.I_PSBR] (x=1 or 2) is the current setting of FD PSBR, which is set larger than the
maximum load current of generator.
10ms 0
SIG I1>[Gen.21Mx.I_PSBR] >=1
&
0 160ms
SIG I1≤[Gen.21Mx.I_PSBR] Flg_Pkp_FDPSBR
SIG FD_Gen.21M
Figure 3.25-4 Logic diagram of FD PSBR
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3 Operation Theory
2. Unsymmetrical fault PSBR element
When an internal unsymmetrical fault happens, power swing blocking for impedance relay can be
released by following element:
I 0 + I 2 > m × I1 Equation 3.25-6
Where:
“m” is an internal fixed coefficient with a certain margin which can ensure UF PSBR operate during
power swing with internal unsymmetrical fault, while not operate during power swing or power
swing with external fault.
I1，I 2，I 0 are positive-sequence current, negative-sequence current and zero-sequence current
respectively.
3. Symmetrical fault PSBR element
When fault detector operates and after 160ms, or during the power swing, if a three-phase fault
occurs, both of FD PSBR and UF PSBR can not operate to release the impedance protection.
Thus, SF PSBR is provided for this case specially. This detection is based on measuring the
voltage of power swing center:
U OS = U 1 × cos Φ Equation 3.25-7
Where:
Φ : the angle between positive-sequence voltage and positive-sequence current.
U 1 : the positive-sequence voltage.
The criterion of SF PSBR element comprises the following two parts:
1) When − 0.03U N < U OS < 0.08U N , the SF PSBR element will operate with a time delay
150ms.
2) When − 0.1U N < U OS < 0.25U N , the SF PSBR element will operate with a time delay
500ms.
3.25.4 Logic
The logic of phase-to-earth impedance protection is same to that of phase-to phase impedance
protection, and stage 1 of phase-to-phase impendence protection is taken as an example as
shown below.
For each stage of impedance protection, if following three conditions are met, the corresponding
stage of impedance protection is enabled.
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3 Operation Theory
(1) The logic setting [Gen.21Mx.ZP.En] is set as “1”.
(2) The protection function enabling inputs [Gen.21Mx.En1], [Gen.21Mx.En2] are “1”.
(3) The protection function blocking input [Gen.21Mx.Blk] is “0”.
If impedance protection is disabled, all the related output signals will be reset. If no external input
is configured to [Gen.21Mx.En1] ([Gen.21Mx.En2]), the default initial value of [Gen.21Mx.En1]
([Gen.21Mx.En2]) is “1”; if no external input is configured to [Gen.21Mx.Blk], the default initial
value of [Gen.21Mx.Blk] is “0”.
EN Flg_Pkp_UFPSBR
≥1
EN Flg_Pkp_SFPSBR Flg_Pkp_PSBR
SIG Flg_Pkp_FDPSBR
SIG Flg_Pkp_PSBR ≥1
SIG [Gen.21M1.En_PSBR]
SIG Flg_Op_ZP1
&
SET [Gen.21M1.En]
&
SIG [Gen.21M1.En1] &
[Gen.21M1.ZP.St]
SIG [Gen.21M1.En2]
[Gen.21M1.ZP.t_Op] 0s
SIG [Gen.21M1.Blk] [Gen.21M1.ZP.Op]
SIG VT circuit failure &
SIG [Gen.21M1.En_VTS_Blk]
0ms 500ms
SIG 21M1.FD
Figure 3.25-5 Logic diagram of stage 1 of phase-to-phase impedance protection
Where:
Flg_Pkp_UFPSBR is the internal flag indicating that unsymmetrical fault PSBR element picks up.
Flg_Pkp_SFPSBR is the internal flag indicating that symmetrical fault PSBR element picks up.
Flg_Pkp_FDPSBR is the internal flag indicating that fault detector PSBR element picks up.
21M1.FD is the operation flag of the fault detector of DPFC phase-to-phase current or that of
negative-sequence current (the fault detector of fault detector DSP module).
Flg_Pkp_PSBR is the internal flag indicating that power swing blocking releasing element picks
up.
Flg_Op_ZP1 is the internal flag indicating that the operation criterion of stage 1 of phase-to-phase
impedance relay (i.e. Equation 3.25-3) is met.
[Gen.21M1.En_VTS_Blk] is the setting to enable the impedance protection being blocked by VT

circuit failure.
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3 Operation Theory
21
Gen.21Mx.U3P Gen.21Mx.St
Gen.21Mx.I3P Gen.21Mx.ZP.Op
Gen.21Mx.En1 Gen.21Mx.ZG.Op
Gen.21Mx.En2
Gen.21Mx.Blk
Figure 3.25-6 Function block diagram of impedance protection
x=1 and 2.
Table 3.25-1 Input signals of impedance protection

1 Gen.21Mx.I3P Three-phase current input.
2 Gen.21Mx.U3P Three-phase voltage data.
3 Gen.21Mx.En1 Protection function enabling input1 and input 2, it can be binary inputs or settings, such
4 Gen.21Mx.En2 as function enabling binary inputs, logic links, etc.
5 Gen.21Mx.Blk Protection function blocking input, such as function blocking binary input.
Table 3.25-2 Output signals of impedance protection

1 Gen.21Mx.St Stage x of impedance protection starts (x=1 or 2).
2 Gen.21Mx.ZP.Op Stage x of phase-to-phase impedance protection operates (x=1 or 2).
3 Gen.21Mx.ZG.Op Stage x of phase-to-earth impedance protection operates (x=1 or 2).
Table 3.25-3 Output signals of impedance protection (event recorder)
Tripping reports
1 Gen.21M1.ZP.Op Stage 1 of phase-to-phase impedance protection operates.
2 Gen.21M2.ZP.Op Stage 2 of phase-to-phase impedance protection operates.
3 Gen.21M1.ZG.Op Stage 1 of phase-to-earth impedance protection operates.
4 Gen.21M2.ZG.Op Stage 2 of phase-to-earth impedance protection operates.
Start signals
5 Gen.21M1.St Stage 1 of Impedance protection starts.
6 Gen.21M2.St Stage 2 of Impedance protection starts.
Waveform recording
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3 Operation Theory
7 Gen.21M1.TrigDFR Stage 1 of impedance protection operates to trigger waveform recording.
8 Gen.21M2.TrigDFR Stage 2 of impedance protection operates to trigger waveform recording.
Table 3.25-4 Output signals of impedance protection (measurements)
1 Gen.21Mx.Uab Phase-to-phase voltage of phase AB. V
2 Gen.21Mx.Ubc Phase-to-phase voltage of phase BC. V
3 Gen.21Mx.Uca Phase-to-phase voltage of phase CA. V
4 Gen.21Mx.Iab Phase-to-phase current of phase AB. A
5 Gen.21Mx.Ibc Phase-to-phase current of phase BC. A
6 Gen.21Mx.Ica Phase-to-phase current of phase CA. A
7 Gen.21Mx.Zab Phase-to-phase impedance of phase AB. Ohm
8 Gen.21Mx.Zbc Phase-to-phase impedance of phase BC. Ohm
9 Gen.21Mx.Zca Phase-to-phase impedance of phase CA. Ohm
10 Gen.21Mx.Ua Phase-to-earth voltage of phase A. V
11 Gen.21Mx.Ub Phase-to-earth voltage of phase B. V
12 Gen.21Mx.Uc Phase-to-earth voltage of phase C. V
13 Gen.21Mx.Ia Current of phase A. A
14 Gen.21Mx.Ib Current of phase B. A
15 Gen.21Mx.Ic Current of phase C. A
16 Gen.21Mx.Za Phase-to-earth impedance of phase A. Ohm
17 Gen.21Mx.Zb Phase-to-earth impedance of phase B. Ohm
18 Gen.21Mx.Zc Phase-to-earth impedance of phase C. Ohm
19 Gen.21Mx.Ang(Uab-Iab) Phase angle between phase-AB voltage and phase-AB current deg
20 Gen.21Mx.Ang(Ubc-Ibc) Phase angle between phase-BC voltage and phase-BC current deg
21 Gen.21Mx.Ang(Uca-Ica) Phase angle between phase-CA voltage and phase-CA current deg
22 Gen.21Mx.Ang(Ua-Ia) Phase angle between phase-A voltage and phase-A current deg
23 Gen.21Mx.Ang(Ub-Ib) Phase angle between phase-B voltage and phase-B current deg
24 Gen.21Mx.Ang(Uc-Ic) Phase angle between phase-C voltage and phase-C current deg
Access path:
Main menu -> Measurements -> Measurements2-> Prot Values->Gen PPF Prot Values
Date: 2016-08-16
3 Operation Theory
3.25.6 Settings
Table 3.25-5 Settings list of impedance protection
x=1 or 2

0: disable Logic setting of enabling/disabling stage x of
1 Gen.21Mx.En 1
1: enable impedance protection.
Impedance characteristic angle (also called
2 Gen.21Mx.RCA 0~90 0.01 deg reach angle) of stage x of impedance
protection.
Current setting of PSBR element of stage x of
3 Gen.21Mx.I_PSBR 0.05~20In 0.01 A
impedance protection
The direction that the stage x of
phase-to-phase impedance point to.
4 Gen.21Mx.ZP.Opt_Dir 0,1 1
0: generator
1: system
Forward impedance setting of stage x of
5 Gen.21Mx.ZP.Z_Fwd 0.05~200 0.01 ohm
phase-to-phase impedance protection.
Reverse impedance setting of stage x of
6 Gen.21Mx.ZP.Z_Rev 0.05~200 0.01 ohm
Time delay of stage x of phase-to-phase
7 Gen.21Mx.ZP.t_Op 0.05~30 0.01 s
Tripping logic setting of stage x of
8 Gen.21Mx.ZP.OutMap 0~3FFFFFFF
9 Gen.21Mx.ZP.En 1
1: enable phase-to-phase impedance protection
The direction that the stage x of
phase-to-earth impedance point to.
10 Gen.21Mx.ZG.Opt_Dir 0,1 1
0: generator
1: system
Forward impedance setting of stage x of
11 Gen.21Mx.ZG.Z_Fwd 0.05~200 0.01 ohm
phase-to-earth impedance protection.
Reverse impedance setting of stage x of
12 Gen.21Mx.ZG.Z_Rev 0.05~200 0.01 ohm
Time delay of stage x of phase-to-earth
13 Gen.21Mx.ZG.t_Op 0.05~30 0.01 s
Tripping logic setting of stage x of
14 Gen.21Mx.ZG.OutMap 0~3FFFFFFF
15 Gen.21Mx.ZG.En 1
1: enable phase-to-earth impedance protection.
Logic setting of enabling/disabling VT circuit
0: disable
16 Gen.21Mx.En_VTS_Blk 1 failure block element of stage x of impedance
1: enable
protection.
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3 Operation Theory
0: disable Logic setting of enabling/disabling the PSBR

17 Gen.21Mx.En_PSBR 1
1: enable element of stage x of impedance protection.
Access path: Settings-> Prot Settings -> Gen Impedance Settings
3.26 Breaker Failure Protection (50BF)
3.26.1 Application
Breaker failure protection is applied to monitor the circuit breaker state to ensure that the circuit
breaker is correctly opened. When a tripping command is issued from the protection device, but
the circuit breaker have not been tripped within a certain time delay, so that the fault can not be cut
off, then the circuit breaker of upper stream will be initiated to trip.
Breaker failure protection has following two criteria:
 After the tripping command been issued, the device will check whether the phase current and
negative-sequence current are larger than corresponding setting.
 The protection will use the auxiliary contact of the circuit breaker to judge whether the circuit
breaker is correctly tripped. As under certain circumstances, the criteria of current are not
applicable, like frequency protection, voltage protection and overexcitation protection etc.
The internal logic between above two criteria can be “And” or “Or”. If the setting
[Gen.50BF.Opt_Mode] is set as “0”, the internal logic between current criterion and circuit breaker
auxiliary contact criterion is “Or”; if the setting [Gen.50BF.Opt_Mode] is set as “1”, the internal logic
between current criterion and circuit breaker auxiliary contact criterion is “And”. Current criterion
and circuit breaker auxiliary contact criterion can be enabled or disabled separately, so that there
are four possible combinational logics for breaker failure protection:
1) Current criterion “And” circuit breaker auxiliary contact criterion;
2) Current criterion “or” circuit breaker auxiliary contact criterion;
3) Current criterion (circuit breaker auxiliary contact criterion is disabled);
4) Circuit breaker auxiliary contact criterion (current criterion is disabled);

3.26.3.1 Overview
The breaker failure protection has two independent tripping stages and is controlled by the input
signal [Gen.50BF.Init], which can be an internal protection tripping signal or an external protection
operating binary input.
Date: 2016-08-16
3 Operation Theory
3.26.3.2 Current Criteria
Current criteria include phase current criterion and negative-sequence current criterion. If any
current criterion is satisfied, current element of breaker failure protection picks up.
1) Phase current criterion:
I Φ _ max >[Gen.50BF.Ip_Set] Equation 3.26-1
Where:
I Φ _ max is the maximum value of three-phase current.

[Gen.50BF.Ip_Set] is the phase current setting of breaker failure protection.
2) Negative-sequence current criterion:
I2> [Gen.50BF.I2_Set] Equation 3.26-2
Where:
I2 is the calculated negative-sequence current.
[Gen.50BF.I2_Set] is negative-sequence current setting of breaker failure protection.
3.26.4 Logic
For breaker failure protection, when following three conditions are met, the breaker failure
protection is enabled.
(1) Logic setting [Gen.50BF.En] is set as “1”.
(2) The protection function enabling inputs [Gen.50BF.En1], [Gen.50BF.En2] are “1”.
(3) The protection function blocking input [Gen.50BF.Blk] is “0”.
If breaker failure protection is disabled, all the related output signals will be reset. If no external
input is configured to [Gen.50BF.En1] ([Gen.50BF.En2]), the default initial value of [Gen.50BF.En1]
([Gen.50BF.En2]) is “1”; if no external input is configured to [Gen.50BF.Blk], the default initial value
of [Gen.50BF.Blk] is “0”.
Logics of breaker failure protection (with two time delays) is shown in following figure.
Date: 2016-08-16
3 Operation Theory
Set [Gen.50BF.En_Ip] &

0 A OR B
Sig IΦ_max>[Gen.50BF.Ip_set] A
Set [Gen.50BF.En_I2] & 1 A AND B

B
Sig I2>[Gen.50BF.I2_Set]
Sig [BI_52b]
OR/AND
&
Set [Gen.50BF.Opt_Mode] [Gen.50BF.St]
[Gen.50BF.t1_Op] 0ms
En [Gen.50BF.En] [Gen.50BF.Op_t1]
&
SIG [Gen.50BF.En1] [Gen.50BF.t2_Op] 0ms
[Gen.50BF.Op_t2]
SIG [Gen.50BF.En2]
SIG [Gen.50BF.Blk]
Sig [50BF.Init]
0ms 500ms
Sig 50BF.FD
Figure 3.26-1 Logic diagram of breaker failure protection
Where:
[BI_52b] is the normally closed auxiliary contact of the circuit breaker.
I2 is the negative-sequence current.
50BF.FD is the operation flag of the fault detector of breaker failure protection (the fault detector of
3.26.5 Input and Output
50BF
Gen.50BF.I3P Gen.50BF.St
Gen.50BF.Init Gen.50BF.Op_t1
Gen.50BF.En1 Gen.50BF.Op_t2
Gen.50BF.En2
Gen.50BF.Blk
BI_52b
Figure 3.26-2 Function block diagram of breaker failure protection
Table 3.26-1 Input signals of breaker failure protection

1 Gen.50BF.I3P Three-phase current input.
2 Gen.50BF.Init Input signal of initiating breaker failure protection.
3 Gen.50BF.En1 Protection function enabling input1 and input 2, it can be binary inputs or settings, such
4 Gen.50BF.En2 as function enabling binary inputs, logic links, etc.
5 Gen.50BF.Blk Protection function blocking input, such as function blocking binary input.
6 BI_52b The normally closed auxiliary contact of the circuit breaker.
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3 Operation Theory
Table 3.26-2 Output signals of breaker failure protection

1 Gen.50BF.St Breaker failure protection starts.
2 Gen.50BF.Op_t1 Breaker failure protection with time delay 1 operates.
Table 3.26-3 Output signals of breaker failure protection (event recorder)
Tripping reports
Start signals
3 Gen.50BF.St Breaker failure protection starts.
Waveform recording
4 Gen.50BF.TrigDFR Breaker failure protection operates to trigger waveform recording.
Table 3.26-4 Output signals of breaker failure protection (measurements)
1 Gen.50BF.Ia The phase-A current for breaker failure protection A
2 Gen.50BF.Ib The phase-B current for breaker failure protection A
3 Gen.50BF.Ic The phase-C current for breaker failure protection A
4 Gen.50BF.I1 Positive-sequence current for breaker failure protection A
5 Gen.50BF.I2 Negative-sequence current for breaker failure protection A
6 Gen.50BF.3I0_Cal The calculated residual current for breaker failure protection A
Access path:
Main menu -> Measurements -> Measurements1-> Prot Values->Gen Curr Values
Main menu -> Measurements -> Measurements2-> Prot Values->Gen Curr Values
3.26.6 Settings
Table 3.26-5 Settings list of breaker failure protection

0: disable Logic setting of enabling/disabling breaker failure
1 Gen.50BF.En 1
1: enable protection.
Current setting of phase current criterion of breaker
2 Gen.50BF.Ip_Set 0.05~10.00In 0.01 A
failure protection.
3 Gen.50BF.I2_Set 0.05~4.00In 0.01 A Current setting of negative-sequence current
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criterion of breaker failure protection.
4 Gen.50BF.t1_Op 0~10 0.01 s Time delay 1 of breaker failure protection.
Tripping logic setting of breaker failure protection
5 Gen.50BF.OutMap_t1 0~3FFFFFFF
with time delay 1.
6 Gen.50BF.t2_Op 0~10 0.01 s Time delay 2 of breaker failure protection.
Tripping logic setting of breaker failure protection
7 Gen.50BF.OutMap_t2 0~3FFFFFFF 0.01
with time delay 2.
0: disable
8 Gen.50BF.En_I2 negative-sequence current criterion of breaker
1: enable
failure protection.
0: disable Logic setting of enabling/disabling phase current
9 Gen.50BF.En_Ip
1: enable criterion of breaker failure protection.
Logic setting of enabling/disabling circuit breaker
0: disable
10 Gen.50BF.En_CB_Ctrl auxiliary contact criterion of breaker failure
1: enable
protection.
The setting to select the internal logic between
0: Or
11 Gen.50BF.Opt_Mode current criterion and circuit breaker auxiliary
1: And
contact criterion.
Access path: Settings-> Prot Settings -> Gen BFP Settings
3.27 Mechanical Protection (MR)
3.27.1 Application
Any operation signal from the generator body protection or other external device can be coupled to
the microprocessor-based protection device via the binary input signal. Generator mechanical
protection can repeat these binary input signals to send alarm signals, tripping directly or tripping
with a time delay. By this way the output signal of some mechanical protection (such as gas
protection and etc.) can be coupled to the microprocessor-based protection device, then these
signals can be repeated through high-power relays to improve the anti-inference ability of the
protection.

Mechanical protection has following functions:
 High-power relays are adopted to improve the anti-interference ability of mechanical

protection.
 Each module provides 4 mechanical signal input channels for trip or alarm.

Generator relay repeats external binary input signal through high-power relays and send them to
CPU through opto-coupler circuits. After CPU receiving those signals, the device will record them
as events, issue alarm signal and send tripping command with settable time delays. Because the
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3 Operation Theory
drop off time of mechanical input signals is usually too long, an internal time delay setting
[MR1(2).t_PW_n] (n=1, 2, 3, and 4) is used to control the drop off time (the default value is 9s), it
can prevent the relay from sending long-time tripping command.
3.27.4 Logic
For mechanical protection, if following three conditions are met, the protection will be enabled.
(1) Logic setting [MRx.En] (x=1, 2) is set as “1”.
(2) The protection function enabling inputs [MRx.En1], [MRx.En2] are “1”
(3) The protection function blocking input [MRx.Blk] is “0”.
If mechanical protection is disabled, all the related output signals will be reset. If no external input
is configured to [MRx.En1] ([MRx.En2]), the default initial value of [MRx.En1] ([MRx.En2]) is “1”; if
no external input is configured to [MRx.Blk], the default initial value of [MRx.Blk] is “0”.
Here takes channel 1 of mechanical protection 1 as an example. The logics of channel 2, 3 and 4
are similar with that of channel 1.
EN [MR1.En] &
EN [MR1.En_1] [MR1.Sig1]
SIG [MR1.Input1]
EN [MR1.En] & &

SIG [MR1.En1]
SIG [MR1.En2]
[MR1.t_DPU_1] [MR1.t_PW_1]
SIG [MR1.Blk] [MR1.Op1]
EN [MR1.En_1] &
SIG [MR1.Input1]
SET [MR1.OutMap_1] (bit0=1)
Figure 3.27-1 Logic diagram of channel 1 of mechanical protection 1
MRx
MRx.Input1 MRx.St
MRx.Input2 MRx.Op1
MRx.Input3 MRx.Op2
MRx.Input4 MRx.Op3
MRx.En1 MRx.Op4
MRx.En2 MRx.Sig1
MRx.Blk MRx.Sig2
MRx.Sig3
MRx.Sig4
Figure 3.27-2 Function block diagram of mechanical protection (x=1, 2)
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3 Operation Theory
Table 3.27-1 Input signals of mechanical protection (x=1, 2)

1 MRx.Input1 Input signal of channel 1 of mechanical protection x.
5 MRx.En1 Protection function enabling input1 and input 2, it can be binary inputs or settings, such
6 MRx.En2 as function enabling binary inputs, logic links, etc.
7 MRx.Blk Protection function blocking input, such as function blocking binary input.
Table 3.27-2 Output signals of mechanical protection (x=1, 2)

1 MRx.St Mechanical protection x starts
2 MRx.Sig1 Output alarm signal of channel 1 of mechanical protection x.
6 MRx.Op1 Output tripping signal of channel 1 of mechanical protection x.
Table 3.27-3 Output signals of mechanical protection (event recorder) (x=1, 2)
Tripping reports
Start signals
5 MRx.St Mechanical protection x starts.
Waveform recording
6 MRx.TrigDFR Mechanical protection x operates to trigger waveform recording.
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3 Operation Theory
IO events
11 MRx.St1 Channel 1 of mechanical protection x starts.
3.27.6 Settings
Table 3.27-4 Settings list of mechanical protection

0: disable Logic setting of enabling/disabling mechanical
1 MR1.En
1: enable protection 1.
Delay pickup time of tripping command of channel
2 MR1.t_DPU_1 0.00~6000.00 0.01 s
1 of mechanical protection 1.
Tripping logic setting of channel 1 of mechanical
3 MR1.OutMap_1 0~3FFFFFFF
protection 1.
0: disable Logic setting of enabling/disabling channel 1 of
4 MR1.En_1
1: enable mechanical protection 1.
5 MR1.t_DPU_2 0.00~6000.00 0.01 s
protection 1.
7 MR1.En_2
8 MR1.t_DPU_3 0.00~6000.00 0.01 s
protection 1.
10 MR1.En_3
11 MR1.t_DPU_4 0.00~6000.00 0.01 s
protection 1.
13 MR1.En_4
0: disable Logic setting of enabling/disabling mechanical
14 MR2.En
1: enable protection 2.
15 MR2.t_DPU_1 0.00~6000.00 0.01 s
protection 2.
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3 Operation Theory

17 MR2.En_1
18 MR2.t_DPU_2 0.00~6000.00 0.01 s
protection 2.
20 MR2.En_2
21 MR2.t_DPU_3 0.00~6000.00 0.01 s
protection 2.
23 MR2.En_3
24 MR2.t_DPU_4 0.00~6000.00 0.01 s
protection 2.
26 MR2.En_4
Access path: Settings-> Prot Settings -> MechRly Settings
3.28 Excitation Transformer Current Differential Protection (87ET)
3.28.1 Application
Excitation transformer current differential protection is the main protection for the internal
short-circuit fault of excitation transformer winding. Current differential protection can operate
quickly to clear the internal fault to avoid the excitation transformer from damages or reduce the
maintenance cost as low as possible.
 It is suitable for two-winding excitation transformer.
 For Y-Y, △→△, △→Y and Y→△ connection, all possible vector combinations have been taken
into account, so it is very flexible.
 Optional inrush current distinguished principles and inrush current blocking method, which
can avoid the inrush current reliably, and it can also ensure the operation speed when a fault
happens during normal operation.
 Fifth harmonic blocking criterion applied continuously to detect overexcitation condition.
 Reliable biased differential element
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3 Operation Theory
Biased current differential element with initial restraint slope is adopted, it consists of sensitive and
conventional biased differential elements as well as independent CT saturation criterion.
 Unrestrained instantaneous differential element is equipped.
For internal serious fault, once the differential current is larger than the current setting of
instantaneous differential element, the current differential protection will operate to cut off the fault
quickly.
 Reliable differential CT circuit abnormality detection
Voltage is also used to judge the abnormality of differential CT circuit, multi-phase CT circuit failure,
multi-side CT circuit failure and short-circuit condition can be detected.

3.28.3.1 Overview
Current differential protection includes two operation elements: biased differential element, and
unrestrained differential element. When the differential current is larger than the corresponding
current threshold and no larger harmonic is detected, current differential protection will operate,
and it will drop off if the fault current disappears.
Sensitive biased differential element is variable slope differential element with initial restraint slope.
Conventional biased differential element is differential element with two broken lines. Unrestrained
differential element is used to cut off the serious fault quickly and there is no any blocking element
for it.
3.28.3.2 Amplitude Compensation
Generally, the magnitudes of secondary current of each side of excitation transformer are different
due to the difference of voltage level and CT ratio. The current value difference between each side
shall be eliminated before calculation for current differential protection by amplitude
compensation.
The nameplate parameters of the excitation transformer (includes the rated apparent power and
the rated voltage of each side) and the primary and secondary data of CT of each side of the
excitation transformer should be input to the device. The device will calculate the rated current of
each side and the differential adjust coefficient automatically according to the parameters.
 Calculate rated primary current of each side
Sn
I1bBrm = Equation 3.28-1
3U1nBrm
Where:
Brm=Branch (side) “m”.
S n is the maximum rated capacity.
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3 Operation Theory
U 1nBrm is rated primary voltage of branch m.
I1bBrm is rated primary current of branch m.
 Calculate rated secondary current of each side
I
I 2bBrm = 1bBrm Equation 3.28-2
CTBrm
Where:
I 2bBrm is rated secondary current of side m.
CTBrm is the CT ratio of side m.
 Calculate differential adjust coefficient
k Base = 1
I 2bBase
k Brm =
I 2bBrm Equation 3.28-3
( I 2bBase / I 2 nBase )
≤ 32
( I 2bBrm / I 2 nBrm )
Where:
Brm=Branch (side) “m”.
I 2bBrm , I 2bBase are rated secondary current of calculated side and referenced side of excitation
transformer.
I 2nBrm , I 2nBase are rated secondary current of CT of calculated side and referenced side of
excitation transformer (1A or 5A).
k Base is adjust coefficient of referenced side of excitation transformer.
k Brm is adjust coefficient of calculated side of excitation transformer.
Excitation transformer HV side is the referenced side. If Equation 3.28-3 is not met, the setting
error alarm signals [87ET.Fail_Settings] will be issued and displayed on LCD and the protective
device will be blocked.
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3 Operation Theory
3.28.3.3 Phase Compensation
 Phase Compensation Principle
For the connection mode of excitation transformer each side winding is different, different vector
group will be generated, the vector group will lead the phase shift of secondary currents of each
side, which should be adjusted via the phase compensation of the software.
The preconditions for current phase compensation calculation are:
1) Each side three-phase CT of excitation transformer shall be connected in star type.
2) The secondary current channel of CT will be connected to the protection device directly.
3) The positive polarity of each side three-phase CT shall be at busbar side.
Phase compensation is carried out from LV side to HV side. The HV side (the referenced side) is 0
or 12 o’clock. LV side is n o’clock (n=0~11) relative to HV side. If the HV side is △ connection, then
it does not need to be compensated, LV side needs to shift for n o’clock. If the HV side is Y
connection, then HV side is 1 o’clock to eliminate the effects of zero-sequence current, LV side
needs to shift for n+1 o’clock.
For example:
The vector group of a excitation transformer is Y0/Δ11, the setting [ET_S1.WdgConn] should be
set as “Wye”, the setting [ET_S2.WdgConn] should be set as “Delta”, and the setting
[ET_S2.Clk_WRT_S1] should be set as “11”. The HV side is Y connection, so the phase shift
matrix corresponds to 1 o’clock is adopted to compensate HV side current. It is 11 o'clock for LV
side relative to HV side, so the phase shift matrix corresponds to 12 (or 0, 11+1=12) o’clock is
adopted to compensate LV side current.
Table 3.28-1 Phase shift matrix for phase compensation
Relative o’clock Matrix
1 0 0
0  
(No phase shit) 0 1 0 
0 0 1
 1 −1 0 
1 1  
(Shift 30° leading)  0 1 − 1
3
− 1 0 1 
 0 − 1 0
2  0 0 −1 
(shift 60° leading)  
− 1 0 0
 0 −1 1 
3 1  
(Shit 90° leading)  1 0 − 1
3
− 1 1 0 
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3 Operation Theory
Relative o’clock Matrix
0 0 1 
4  
(Shit 120° leading) 1 0 0
0 1 0
−1 0 1 
5 1  
(Shift 150° leading)  1 −1 0 
3
 0 1 − 1
− 1 0 0
6  0 − 1 0
(Shift 180° leading)  
 0 0 − 1
− 1 1 0 
1 
0 − 1 1 
7
(Shift 150° lagging) 3 
 1 0 − 1
0 1 0 
8  
(Shift 120° lagging) 0 0 1 
1 0 0
 0 1 −1
S9 1  
(Shift 90° lagging) − 1 0 1 
3
 1 − 1 0 
 0 0 −1
10  
 0 − 1 0 
 1 0 −1
11 1  
3
 0 − 1 1 
NOTICE!
For Y-y and D-d connection the vector group can ONLY BE even number, (i.e. Y-y4,
D-d8), for Y-d and D-y connection the vector group can ONLY BE odd number, (i.e.
Y-d11, D-y5), if the two conditions can not be met, the setting error alarm signal
[87ET.Fail_Settings] will be issued and displayed on LCD and the protective device will
be blocked.
3.28.3.4 Calculations of Differential Current and Restraint Current
The calculation equation of differential current is:
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3 Operation Theory
 I dA   I A1  I A2 
I  = ×   /I + × /I
 dB  M 1  I B1 2 bBr1 M 2  I B 2  2 bBr 2 Equation 3.28-4
 I dC   I C1  I C 2 
    
1 2
The above equation can be simplified to the following:
 I dA = I ′ A1 + I ′ A2

 I dB = I ′B1 + I ′B 2 Equation 3.28-5
I = I ′ + I ′
 dC C1 C2
Where:
I Am , I Bm , I Cm in the equation are the secondary current vectors of side m (m=1, 2).
I ′ Am , I ′Bm , I ′Cm are corrected secondary current vectors of side m (m=1, 2).
I dA , I dB , I dC are differential currents.
M 1 , M 2 are phase shift matrixes of each side of excitation transformer respectively. Its value is
decided according to the vector group of excitation transformer and please refers to Section
3.28.3.3 for details.
I 2bBr1 , I 2bBr 2 are rated secondary values of each side of excitation transformer respectively.
The calculation equation of restraint current is:

 I rA =
1
( I ′A1 + I ′A2 )
2


 I rB = ( I ′B1 + I ′B 2 )
1
Equation 3.28-6
 2

 I rC = 2 ( I ′C1 + I ′C 2 )
1

Where:
I rA , I rB , I rC are restraint currents.
Current compensation process is shown in the flowing figure. The symbol “*” represents the
polarity of CT. If current flowing into the polarity side of CT, the current direction is defined as
positive direction. In an ideal situation, the differential current （i.e. I d = I ′ _ H + I ′ _ L ）should be
zero during the normal operation of the excitation transformer or an external fault occurring.
Date: 2016-08-16
3 Operation Theory
Ip_H Ip_L
* * *
* * *
HV side LV side
I_H I_L
PCS-985GE
Phase shift/zero sequence Phase shift/zero sequence
current elimination (*M1) current elimination (*M2)
Magnitude compensation Magnitude compensation

(/I2bBr1) (/I2bBr2)
I'_H I'_L
Calculate differential current and restraint current
Figure 3.28-1 Excitation transformer current compensation calculation process
In above figure:
Ip_H, Ip_L are primary current vectors of HV and LV side respectively.
I_H, I_L are secondary current vectors of HV and LV side respectively.
I’_H, I’_L are secondary corrected current vectors of HV and LV side respectively.
M1, M2 are phase shift matrixes of HV and LV side respectively.
I 2bBr1 , I 2bBr 2 are rated secondary currents of HV and LV side respectively.
To clarify the principle, in an ideal situation, three important operation conditions are considered.
1. Through-flowing current under undisturbed conditions or external fault:
The direction of I’_H is reverse to that of I’_L, but the amplitude of I’_H is equal to that of I’_L,
i.e. I’_H=–I’_L, |I’_H|=|I’_L|.
Id=|I’_H+I’_L|=|I’_H–I’_H|=0;
Ir=(|I’_H|+|I’_L|)/2=(|I’_H|+|I’_H|)/2=|I’_H|
No differential current (Id=0), restraint current (Ir) is one time of the through-flowing current,
and current differential protection will not operate.
2. Internal short-circuit fault, e.g. the fed currents of two sides are equal:
I’_L=I’_H, moreover |I’_L|=|I’_H|
Id=|I’_H+I’_L|=|I’_H+I’_H|=2|I’_H|;
Ir=(|I’_H|+|I’_L|)/2=(|I’_H|+|I’_H|)/2=|I’_H|
Differential current (Id) is two times of restraint current (Ir) and it corresponds to the total fault
Date: 2016-08-16
3 Operation Theory
current, current differential protection operates sensitively.
The above results show that Id = 2Ir during an internal fault. I.e. the operation characteristic of
current differential protection for internal fault is a straight line with a slope of 2.
3. Internal short-circuit fault, current is only fed from one side:
Assuming I’_L=0
Id=|I’_H+I’_L|=|I’_H+0|=|I’_H|;
Ir=(|I’_H|+|I’_L|)/2=(|I’_H|+|0|)/2=|I’_H|/2
Differential current (Id) is two times of restraint current (Ir) and it corresponds to fault current of
single side, current differential protection operates sensitively.
The above results show that Id = 2Ir during an internal fault. I.e. the operation characteristic of
current differential protection for internal fault is a straight line with a slope of 2.
3.28.3.5 Sensitive Biased Differential Element
The operation equation of sensitive biased differential element is:
 I d > K bl × I r + I Diff . Pickup ( I r < nI e )


 K bl = K bl1 + K blr × ( I r / I e )

 I d > K bl 2 × ( I r − nI e ) + b + I Diff . Pckup ( I r ≥ nI e )

 K blr = ( K bl 2 − K bl1 ) /(2 × n)
b = ( K bl1 + K blr × n) × nI e Equation 3.28-7
 1 • •
 I r = ( I 1 + I 2 )
 2
 • •
I = I 1 + I 2
 d
Where:
Ii (i = 1, 2) are the corrected secondary currents of HV and LV side of excitation transformer
respectively.
I Diff .Pickup is the pickup current setting of biased differential element [87ET.I_Biased].
I e is the rated current of excitation transformer.
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3 Operation Theory
K b1 is the restraint coefficient of biased differential element.
K b1r is the restraint coefficient increment of biased differential element.
K bl1 is the initial slope setting of biased differential element, it takes 0.10 generally [87ET.Slope1].
K bl 2 is the maximum slope setting of biased differential element, it takes 0.70 generally
[87ET.Slope2].
n is the restraint current multiple when the restraint coefficient reach to the maximum value. This
internal value is set as 6 fixedly.
3.28.3.6 Conventional Biased Differential Element
Conventional biased differential element with higher pickup current and higher restraint coefficient
comparing with sensitive biased differential element is equipped. Its biased restraint characteristic
can make the differential element not operate due to CT transient and steady-state saturation
during external fault, and it can operate reliably even the CT is seriously saturated during internal
fault. Operation criterion of conventional biased differential element is:
 I d > 1.2 × I e

I d > I r Equation 3.28-8
Where:
I d and I r have the same definitions as mentioned above.
NOTICE!
The related parameters of conventional biased differential element are set FIXEDLY in
the device. Therefore, the slope and the knee point with constant values do not need to
be set by user.
3.28.3.7 Unrestrained Instantaneous Differential Element
Unrestrained instantaneous differential element of excitation transformer is used to accelerate the

operation speed for serious internal fault. The element has no blocking element and the current
setting is very high. If differential current of any phase is larger than the current setting of
unrestrained instantaneous differential element, the protection will operate to trip the circuit
breaker of each side instantaneously. Its operation criterion is:
I dφ max > [87ET.I_Inst] Equation 3.28-9
Where:
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3 Operation Theory
I dφ max is the maximum value of three phase differential currents.
[87ET.I_Inst] is the current setting of the unrestrained instantaneous differential element.
3.28.3.8 Operation Characteristic of Differential Protection
Id (Ie)
differential Tripping area of
current instantaneous diff.
2
K=
[87ET.I_Inst]
ff.
di
.0 ed f
K bia a o
l re
=1 s
na a
tio ing of f.
a dif
en pp
e
ar d
nv Tri
n g ase
2]
pi e bi
pe
p
co
lo
i
Tr itiv
.S
ET
ns
7
se
[8
1.2Ie
pe1]
T.Slo
[87E
[87ET.I_Biased]
restraint current
0 1Ie 1.2Ie nIe Ir (Ie)
Figure 3.28-2 Operation characteristic curve of differential protection of excitation transformer
Current differential protection carries out the fault discrimination according to the current of each
phase. If the current criteria are met and no related blocking element(s) operate, differential
protection will operate to trip.
1) Sensitive biased differential element will send tripping signal monitored by CT saturation,
overexcitation, inrush current and CT circuit failure (optional). It can ensure the sensitivity of
differential protection and avoid the unwanted operation when CT is saturated during an
external fault. Its operation area is the tint shadow area in the figure above.
2) Conventional biased differential element will send tripping signal monitored by inrush current
and CT circuit failure (optional). It eliminates the influence of transient and steady-state
saturations of CT during an external fault and ensures differential protection can operate
reliably even if CT is saturated during an internal fault by means of its biased characteristic. Its
operation area is the deeper shadow area in the figure above.
3) Unrestrained instantaneous differential element will send tripping signal without any blocking
element if differential current of any phase is larger than corresponding current setting.
Unrestrained instantaneous differential element is used to cut off the internal serious fault
quickly. Its operation area is over the above two areas with the deepest dark shadow.
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3 Operation Theory
3.28.3.9 Inrush Current Detection
The logic setting [87ET.Opt_Inrush_Ident] is provided for users to select the inrush current
detection principle. If the logic setting is set as “Waveform”, discrimination by waveform distortion
is enabled, and if it is set as “Hm2”, discrimination by second harmonics is enabled.
The logic setting [87ET.Opt_BlkMode_Inrush] is provided for users to select the inrush current
blocking mode, synthetic blocking mode, cross blocking mode and phase blocking mode can be
selected.
3.28.3.9.1 Distinguishing by Harmonics
The ratio between second harmonic and fundamental component of three-phase differential
current is used to distinguish inrush current. Its criteria are:
I 2 nd > K 2 xb * I1st Equation 3.28-10
Where:
I 2nd is the second harmonic of per-phase differential current.
I1st is the fundamental component of the differential current of the corresponding phase.
K 2 xb is the restraint coefficient of second harmonics [87ET.K_Hm2_Inrush],
[87ET.K_Hm2_Inrush]=0.15 is recommended.
Users can select the second harmonic criterion or wave distortion criterion (see following section)
to distinguish inrush current.
3.28.3.9.2 Distinguishing by Wave Distortion
After the transmission of current transformer, the differential current is basically the fundamental
sinusoidal wave during an internal fault. When the excitation transformer is energized, plentiful
harmonics will appear, the waveform will be distorted, the waveform is interrupted and
unsymmetrical.
When an internal fault happens, the following expression is established:
S > K b * S +
 Equation 3.28-11
S > S t
Where:
S is the full-cycle integral value of differential current;
S + is the full-cycle integral value of (differential current instantaneous value + differential current
instantaneous value a half cycle ago);
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3 Operation Theory
K b is a fixed coefficient.
St is the threshold setting. The expression of St is:
St > α * I d + 0.1I e Equation 3.28-12
Where:
I d is the full-cycle integral value of differential current;
α is a ratio coefficient.
When inrush current appears, the above waveform distinguish expression is not met, current
differential protection will not mal-operate.
3.28.3.9.3 Inrush Current Blocking Mode
Users can select the inrush current blocking mode by the logic setting
[87ET.Opt_BlkMode_Inrush].
 Synthetic Blocking Mode
If the following criterion is met, the three-phase differential protection will be blocked.
Max{Ia 2 nd ,Ib 2 nd , Ic 2 nd } > [87 ET .K _ Hm2 _ Inrush] × Max( Ia1nd ,Ib1nd , Ic1nd ) Equation 3.28-13
 Cross Blocking Mode
If the following criterion is met, the three-phase differential protection will be blocked.
 Ia 2 nd > [87 ET .K _ Hm2 _ Inrush] × Ia1nd

 or
 Ib 2 nd > [87 ET .K _ Hm2 _ Inrush] × Ib1nd
 or Equation 3.28-14
 Ic 2 nd > [87 ET .K _ Hm2 _ Inrush] × Ic1nd
 Ic 2 nd > [87 ET .K _ Hm2 _ Inrush] × Ic1nd

 Ib 2 nd > [87 ET .K _ Hm2 _ Inrush] × Ib1nd
 Phase Blocking Mode
If one of the following criteria is met, only the corresponding phase differential protection will be
blocked.


 Ib 2 nd > [87 ET .K _ Hm2 _ Inrush] × Ib1nd Equation 3.28-15
 Ic > [87 ET .K _ Hm2 _ Inrush] × Ic
 2 nd 1nd
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3 Operation Theory
The synthetic blocking mode is strongly recommended to be selected in the actual application.
Operating experience indicating that the synthetic blocking mode can guarantee the differential
protection not operate under most inrush current situation, and ensure the differential protection
can operate sensitively when the excitation is no-load energized on to a fault.
3.28.3.10 CT Saturation Detection
When an excitation transformer external fault happens, great through-fault current will flowing
through the CT, if the saturation degree of LV side CT is inconsistent with that of HV side CT, great
unbalance differential current will generate in the differential circuit, which will lead to the
mal-operation of differential protection. So the CT saturation detection function is required for
excitation transformer differential protection.
There is a certain time before the CT falling into saturated state, so the changing characteristic of
differential current and restraint current within the initial time of the fault can be used to judge
whether it is an external fault. For an external fault, the deviation of power frequency component
(DPFC) of restraint current appears before the appearance of DPFC of differential current; for an
internal fault, DPFC of restraint current and differential current appear almost simultaneously. If
external fault is detected, CT saturation blocking criterion is enabled.
In order to prevent an unwanted operation of sensitive biased differential element caused by

transient state saturation of CT during an external fault, the second and third harmonics of current
are used for the protection device to discriminate saturation of three-phase CT.
 I Φ _ 2 nd > K Φsat _ 2 xb × I Φ _ 1st

 I Φ _ 3rd > K Φsat _ 3 xb × I Φ _ 1st
Where:
I Φ _ 1st is the fundamental component of one phase differential current.
I Φ _ 2nd is the secondary harmonic of the corresponding phase differential current.
I Φ _ 3rd is the third harmonic of the corresponding phase differential current.
K Φsat _ 2 xb and K Φsat _ 3 xb are fixed coefficients.
If any harmonic of one phase differential current meets the above equation, it will be considered
that it is CT saturation to cause this phase differential current and sensitive biased differential
element will be blocked. The criterion is only enabled when the excitation transformer is in service.
3.28.3.11 Overexcitation Detection
When a excitation transformer is overexcited, the exciting current will increase sharply which may
result in unwanted operation of differential protection. Therefore the overexcitation shall be
discriminated to block differential protection. If overexcitation is detected, then sensitive biased
Date: 2016-08-16
3 Operation Theory
differential element will be blocked.
I 5th > k 5 xb * I 1st Equation 3.28-17
Where:
I1st is the fundamental component of differential current.
I 5th is the fifth harmonic of differential current.
k5 xb is the coefficient of fifth harmonic overexcitation detection [87ET.K_Hm5_OvExc]
3.28.3.12 Differential Circuit CT Supervision
3.28.3.12.1 Differential Circuit CT Abnormality Alarm
If the excitation transformer differential current of any phase meets the following criteria and
corresponding differential element is enabled, the excitation transformer differential current
abnormality alarm [87ET.Alm_Diff] with a time delay of 300ms, this alarm signal will not block the
differential element. The signal will reset if the differential current disappears with a time delay of
10s.
 I d > [87 ET .I _ Alm]

I d > k * I r
k is the restraint coefficient of differential current abnormality alarm.
[87ET.I_Alm] is the current setting of differential current abnormality alarm.
3.28.3.12.2 Differential Circuit CT Circuit Failure Alarm
 Criteria
If any one of following four conditions is satisfied after the fault detector of biased differential
current picks up, it will be determined as fault and differential protection is released, otherwise it
will be determined that the fault detector of biased differential current picks up due to differential
CT circuit failure or short-circuit.
 Negative-sequence voltage of any side is larger than 1V.
 Any phase current of any side increases after the fault detector picks up.
 The maximum phase current is larger than 1.2Ie after the fault detector picks up.
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3 Operation Theory
 Among all the current channels, any three phases of the current decrease after fault
detector picks up.
If none of above four conditions is satisfied within 40ms after the fault detector of biased
differential current picks up, it will be determined as differential CT circuit failure and CT circuit
failure alarm will be issued. Then if the logic setting [87ET.En_CTS_Blk] is set as “1”, sensitive and
conventional biased differential element will be blocked, if the logic setting [87ET.En_CTS_Blk] is
set as “0”, sensitive and conventional biased differential element will not be blocked. Excitation
transformer unrestrained instantaneous differential element will not be blocked during CT circuit
failure.
The above conditions contain the voltage criteria and current criteria, which realizes the high
accuracy and sensitivity of the CT circuit failure detection.
The CT circuit failure alarm is latched once issued, it can be reset only after the failure is cleared
and the device is reset (i.e. the binary input [BI_RstTarg] is energized).
No matter whether the abnormality alarm signal makes the differential protection picks up, there
must be some problems in the differential circuit. For example, when the differential circuit fails,
the differential protection will not pick up for light-loaded condition, but the differential current
abnormality alarm signal will be issued. If the abnormality is treated in time, the mal-operation of
differential protection due to increase of load or external fault can be avoided (if the logic setting
[87ET.En_CTS_Blk] is set as “0”).
Once the differential CT circuit failure alarm is issued, the CT circuit should be check carefully, only
if the fault is cleared, the reset operation can be conducted.
3.28.4 Logic
For excitation transformer current differential protection, if following three conditions are met, the
(1) Logic setting [87ET.En] is set as “1”.
(2) The protection function enabling inputs [87ET.En1], [87ET.En2] are “1”
(3) The protection function blocking input [87ET.Blk] is “0”.
If excitation transformer differential protection is disabled, all the related output signals will be reset.
If no external input is configured to [87ET.En1] ([87ET.En2]), the default initial value of [87ET.En1]
([87ET.En2]) is “1”; if no external input is configured to [87ET.Blk], the default initial value of
[87ET.Blk] is “0”.
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3 Operation Theory
SIG [87ET.En1] &

SIG [87ET.En2]
SIG [87ET.Blk]
En 87ET.En_Inst & &

[87ET.St]
SIG Idmax>[87ET.I_Inst]
En 87ET.En_Biased ≥1
&
SIG Idmax>[87ET.I_Biased]
Figure 3.28-3 Logic diagram of startup of excitation transformer current differential protection
Where:
EN [87ET.En_Inst]
SIG [87ET.En1] &
&
SIG [87ET.En2]
[87ET.Op_Inst]
SIG [87ET.Blk]
SIG Idmax>[87ET.I_Inst]
0ms 500ms
SIG 87ET.FD_Inst
EN [87ET.En_Biased]
SIG [87ET.En1] &
SIG &
[87ET.En2]
SIG [87ET.Blk]
SIG Flg_ConvBiasDiff &
SIG Flg_Inrush_ConvBiasDiff
SIG Flg_CTS &
SET [87ET.En_CTS_Blk] ≥1
[87ET.Op_Biased]
SIG 87ET.FD_Biased 0ms 500ms
EN [87ET.En_Biased]
SIG [87ET.En1] &
SIG [87ET.En2]
SIG [87ET.Blk]
&
SIG Flg_SensBiasDiff
SIG Flg_CTSaturation
SIG Flg_Inrush_SensBiasDiff &
SIG Flg_CTS &
SET [87ET.En_CTS_Blk]
SIG Flg_OvExc_Hm5 &
SET [87ET.En_OvExc_Blk]
0ms 500ms
SIG 87ET.FD_Biased
Figure 3.28-4 Logic diagram of excitation transformer current differential protection
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3 Operation Theory
Where:
Flg_ConvBiasDiff is the internal flag indicating that the operation criteria of conventional biased
differential element are satisfied.
Flg_SensBiasDiff is the internal flag indicating that operation criteria of sensitive biased differential
element are satisfied.
Flg_Inrush_ConvBiasDiff is the internal flag indicating that inrush current is detected for
conventional biased differential element.
Flg_Inrush_SensBiasDiff is the internal flag indicating inrush current is detected for sensitive
biased differential element.
Flg_OvExc_Hm5 is the internal flag indicating that overexcitation of excitation transformer is

distinguished by fifth harmonic criterion.
87ET.FD_Inst is the signal indicating that the fault detector of unrestrained instantaneous
87ET.FD_Biased is the signal indicating that the fault detector of biased differential element picks
87ET
87ET.I3P1 87ET.St
87ET.I3P2 87ET.Op_Biased
87ET.En1 87ET.Op_Inst
87ET.En2 87ET.Alm_Diff
87ET.Blk 87ET.Alm_CTS
Figure 3.28-5 Function block diagram of excitation transformer current differential protection
Table 3.28-2 Input signals of excitation transformer current differential protection

1 87ET.I3P1 Three-phase current data input 1
2 87ET.I3P2 Three-phase current data input 2
3 87ET.En1 Protection function enabling input1 and input 2, it can be binary inputs or settings,
4 87ET.En2 such as function enabling binary inputs, logic links, etc.
5 87ET.Blk Protection function blocking input, such as function blocking binary input.
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Table 3.28-3 Output signals of excitation transformer current differential protection

1 87ET.St Excitation transformer current differential protection starts.
2 87ET.Op_Inst Instantaneous differential element of excitation transformer operates.
3 87ET.Op_Biased Biased differential element of excitation transformer operates.
Alarm message indicating CT secondary circuit of excitation transformer differential
4 87ET.Alm_Diff
protection is abnormal.
Alarm message indicating that CT secondary circuit of excitation transformer
5 87ET.Alm_CTS
differential protection fails.
Table 3.28-4 Output signals of excitation transformer current differential protection (event recorder)
Tripping reports
6 87ET.Op_Inst Instantaneous differential element of excitation transformer operates.
7 87ET.Op_Biased Biased differential element of excitation transformer operates.
Start signals
8 87ET.St Excitation transformer current differential protection starts.
Alarm signals
Alarm message indicating CT secondary circuit of excitation transformer

9 87ET.Alm_Diff
differential protection is abnormal.
Alarm message indicating that CT secondary circuit of excitation transformer

10 87ET.Alm_CTS
differential protection fails.
Waveform recording
Excitation transformer differential protection operates to trigger waveform

11 87ET.TrigDFR
recording.
12 87ET.St_Biased Excitation transformer biased differential element starts.
Table 3.28-5 Output signals of excitation transformer current differential protection
87ET.Ida
Three-phase differential current amplitude of excitation
1 87ET.Idb pu
transformer.
87ET.Idc
87ET.Ira
Three-phase restraint current amplitude of excitation
2 87ET.Irb pu
transformer.
87ET.Irc
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Access path:
Main menu -> Measurements -> Measurements1-> Exc Values-> Exc AC Values
Main menu -> Measurements -> Measurements2-> Exc Values-> Exc AC Values
87ET.Ang(Ia_Br1-Br2)
Phase angle between HV side corrected current and LV side
3 87ET.Ang(Ib_Br1-Br2) deg
corrected current of the same phase.
87ET.Ang(Ic_Br1-Br2)
Access path:
Main menu -> Measurements -> Measurements2-> Phase Angle-> Exc PhaseAngle Values
The secondary rated current of HV side of excitation

4 87ET.I2b_Br1 A
transformer.
The secondary rated current of LV side of excitation

5 87ET.I2b_Br2 A
transformer.
Access path:
Main menu -> Measurements -> Measurements2-> Cal Param Display-> Sec Rated Curr Values
Adjust coefficient of HV side for excitation transformer

6 87ET.K_Br1
Adjust coefficient of LV side for excitation transformer

7 87ET.K_Br2
Access path:
Main menu -> Measurements -> Measurements2-> Cal Param Display-> Diff Corr Coef Values
87ET.Ida
Three-phase differential current amplitude of excitation
8 87ET.Idb pu
transformer.
87ET.Idc
87ET.Ira
Three-phase restraint current amplitude of excitation
9 87ET.Irb pu
transformer.
87ET.Irc
87ET.Ia_Cr_Br1
Three-phase corrected current of HV side that used for
10 87ET.Ib_Cr_Br1 pu
87ET.Ic_Cr_Br1
87ET.Ia_Cr_Br2
Three-phase corrected current of LV side that used for
11 87ET.Ib_Cr_Br2 pu
87ET.Ic_Cr_Br2
87ET.Ia_Th_Biased_L
Three-phase current threshold of excitation transformer
12 87ET.Ib_Th_Biased_L pu
sensitive biased differential current protection.
87ET.Ic_Th_Biased_L
87ET.Ia_Th_Biased_H
Three-phase current threshold of excitation transformer
13 87ET.Ib_Th_Biased_H pu
conventional biased differential current protection.
87ET.Ic_Th_Biased_H
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3 Operation Theory
87ET.Ida_Hm2
Second harmonic amplitude of three-phase differential
14 87ET.Idb_Hm2 pu
current of excitation transformer.
87ET.Idc_Hm2
87ET.Ida_Hm3
Third harmonic amplitude of three-phase differential current
15 87ET.Idb_Hm3 pu
of excitation transformer.
87ET.Idc_Hm3
87ET.Ida_Hm5
Fifth harmonic amplitude of three-phase differential current
16 87ET.Idb_Hm5 pu
of excitation transformer.
87ET.Idc_Hm5
Access path:
Main menu -> Measurements -> Measurements2-> Prot Values-> Exc Diff Prot Values
3.28.6 Settings
Table 3.28-6 Settings list of excitation transformer current differential protection
0: disable The logic setting of enabling/disabling

1 87ET.En 1
1: enable excitation transformer differential protection.
Pickup current setting of excitation

2 87ET.I_Biased 0.10~1.5 0.01 pu
transformer biased differential element.
Current setting of excitation transformer

3 87ET.I_Inst 2~14 0.01 pu unrestrained instantaneous differential
element
Differential current alarm setting of excitation

4 87ET.I_Alm 0.05~1.0 0.01 pu
transformer.

5 87ET.Slope1 0.01~0.5 0.01
excitation transformer.

6 87ET.Slope2 0.5~0.8 0.01
nd
Coefficient of 2 harmonic for excitation
7 87ET.K_Hm2_Inrush 0.05~0.5 0.01
transformer inrush current detection.
th
Coefficient of 5 harmonic for excitation
8 87ET.K_Hm5_OvExc 0.05~0.5 0.01
transformer overexcitation detection
Tripping logic setting of excitation

9 87ET.OutMap 0~3FFFFFFF
transformer current differential protection.

0: disable
10 87ET.En_Inst 1 excitation transformer unrestrained
1: enable
instantaneous differential element.

11 87ET.En_Biased 1
1: enable excitation transformer biased differential
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3 Operation Theory
element.

0: disable
12 87ET.En_OvExc_Blk 1 overexcitation blocking element of
1: enable

0: disable
13 87ET.En_CTS_Blk 1 excitation transformer biased differential
1: enable
element being blocked by CT circuit failure.
Logic setting of selecting the inrush current

distinguishing method of excitation
Hm2
14 87ET.Opt_Inrush_Ident 1 transformer biased differential element:
Waveform
0: Hm2
1: Waveform
Logic setting of selecting inrush current

blocking mode for excitation transformer
SyntheticBlk
biased differential element:
15 87ET.Opt_BlkMode_Inrush CrossBlk 1
0: SyntheticBlk
PhaseBlk
1: CrossBlk
2: PhaseBlk
Access path: Settings-> Prot Settings -> Exc Diff Settings
NOTICE!
The logic setting [87ET.OutMap] is SHARED by the unrestrained instantaneous

differential element and biased differential element of excitation transformer.
3.29 Excitation Transformer Overcurrent Protection (Exc.50/51P)
3.29.1 Application
When a fault occurs in power system, the current increases and phase overcurrent protection
operates to avoid damages to protected equipment.
An external fault will result in excitation transformer overload, it will lead to damage of excitation
transformer if the fault can not be cut off quickly, in this case phase overcurrent protection can
operate to trip circuit breaker to avoid physical damage. For small-scale excitation transformer,
phase overcurrent protection can protect excitation transformer from internal fault, for large-scale
excitation transformer, phase overcurrent protection is applied as the backup protection of

Two-stage phase overcurrent protection with independent logic, current and time delay settings
are available for the device. If stage x of excitation transformer overcurrent protection is enabled,
once the phase current is over than the current setting of stage x of excitation transformer
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3 Operation Theory
overcurrent protection, stage x of excitation transformer overcurrent protection will operate with a
settable time delay.
3.29.3 Logic
For stage n of excitation transformer phase overcurrent protection, if following three conditions are
met, stage n of excitation transformer phase overcurrent protection is enabled.
(1) Logic setting [Exc.50/51Pn.En] is set as “1”.
(2) The protection function enabling inputs [Exc.50/51Pn.En1], [Exc.50/51Pn.En2] are “1”.
(3) The protection function blocking input [Exc.50/51Pn.Blk] is “0”.
If excitation transformer phase overcurrent protection is disabled, all the related output signals will
be reset. If no external input is configured to [Exc.50/51Pn.En1] ([Exc.50/51Pn.En2]), the default
initial value of [Exc.50/51Pn.En1] ([Exc.50/51Pn.En2]) is “1”; if no external input is configured to
[Exc.50/51Pn.Blk], the default initial value of [Exc.50/51Pn.Blk] is “0”.
EN [Exc.50/51Pn.En]
SIG [Exc.50/51Pn.En1] &
SIG [Exc.50/51Pn.En2]
SIG [Exc.50/51Pn.Blk]
SIG [Exc.50/51P.I3P] &

[Exc.50/51Pn.St]
SET [Exc.50/51Pn.I_Set]
[Exc.50/51Pn.t_Op] 0ms
[Exc.50/51Pn.Op]
0ms 500ms
SIG Exc.50/51Pn.FD
Figure 3.29-1 Logic diagram of excitation transformer phase overcurrent protection (n=1,2)
Where:
[Exc.50/51P.I3P] is the three-phase current input.
Exc.50/51Pn.FD is the internal signal indicating that stage n of excitation transformer phase
overcurrent protection picks up (the fault detector of fault detector DSP module).
Exc.50/51P
Exc.50/51Pn.I3P Exc.50/51Pn.St
Exc.50/51Pn.En1 Exc.50/51Pn.Op
Exc.50/51Pn.En2
Exc.50/51Pn.Blk
Figure 3.29-2 Function block diagram of excitation transformer phase overcurrent protection
Table 3.29-1 Input signals of excitation transformer phase overcurrent protection

1 Exc.50/51Pn.I3P Three-phase current data.
2 Exc.50/51Pn.En1 Protection function enabling input1 and input 2, it can be binary inputs or settings, such
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3 Operation Theory

3 Exc.50/51Pn.En2 as function enabling binary inputs, logic links, etc.
4 Exc.50/51Pn.Blk Protection function blocking input, such as function blocking binary input.
Table 3.29-2 Output signals of excitation transformer phase overcurrent protection

1 Exc.50/51P1.Op Stage 1 of excitation transformer phase overcurrent protection operates.
3 Exc.50/51P1.St Stage 1 of excitation transformer phase overcurrent protection starts.
Table 3.29-3 Output signals of excitation transformer phase overcurrent protection (event recorder)
Tripping reports
2 Exc.50 /51P2.Op Stage 2 of excitation transformer phase overcurrent protection operates.
Start signals
Waveform recording
Stage 1 of excitation transformer phase overcurrent protection operates to

5 Exc.50/51P1.TrigDFR
Stage 2 of excitation transformer phase overcurrent protection operates to

6 Exc.50/51P2.TrigDFR
3.29.5 Settings
Table 3.29-4 Settings list of excitation transformer phase overcurrent protection

Logic setting of enabling/disabling stage 1
0: disable
1 Exc.50/51P1.En 1 of excitation transformer phase overcurrent
1: enable
protection.
Current setting of stage 1 of excitation
2 Exc.50/51P1.I_Set 0.05~20.00In 0.01 A
transformer phase overcurrent protection.
Time delay of stage 1 of excitation
3 Exc.50/51P1.t_Op 0~3000 0.01 s
4 Exc.50/51P1.OutMap 0~3FFFFFFF excitation transformer phase overcurrent
protection.
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3 Operation Theory

Logic setting of enabling/disabling stage 2
0: disable
5 Exc.50/51P2.En 1 of excitation transformer phase overcurrent
1: enable
protection.
Current setting of stage 2 of excitation
6 Exc.50/51P2.I_Set 0.05~20.00In 0.01 A
Time delay of stage 2 of excitation
7 Exc.50/51P2.t_Op 0~3000 0.01 s
8 Exc.50/51P2.OutMap 0~3FFFFFFF excitation transformer phase overcurrent
protection.
Access path: Settings-> Prot Settings -> Exc OC Settings
3.30 Interconnection Status Element (CBStatus)
3.30.1 Application
If a generator or a generator-transformer unit is connecting with the power network, it is called
“interconnection status”. Some protections (such as startup and shutdown protection) should be
enabled before the interconnection status and disabled after the interconnection status, while
some protections should be enabled after the interconnection status. The device will detect the
position of generator terminal circuit breaker or main transformer HV side circuit breaker and the
current of the CT at the outlet of the circuit breaker, then comprehensively judge whether the
generator or the generator-transformer unit is during interconnection status, the interconnection
status flag can be output for the user to implement logic programming.

Interconnection status element has following functions:
 Two circuit breaker auxiliary contact inputs, the auxiliary contact of generator terminal circuit
breaker or main transformer HV side circuit breaker can be connected to the device.
 Two groups of current inputs respectively correspond to the CT at the outlet of generator
terminal circuit breaker and main transformer HV side circuit breaker.

If the setting [En_GCB] is set as “1”, it means there is a circuit breaker on generator terminal, then
only the auxiliary contact of generator terminal circuit breaker and the current of the CT at the
outlet of generator terminal circuit breaker should be input. If the setting[En_GCB] is set as “0”, it
means there is no circuit breaker on generator terminal, then the position of main transformer HV
side circuit breaker should be judged. When the setting [Opt_Conn_Tr] is set as “0”, it means only
one circuit breaker is equipped for main transformer HV side (it is also called double-busbars
wiring), then the auxiliary contact of main transformer HV side circuit breaker and the current of the
CT at the outlet of main transformer HV side circuit breaker should be input. When the setting
[Opt_Conn_Tr] is set as “1”, it means two circuit breakers are equipped for main transformer HV
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3 Operation Theory
side (it is also called 3/2 breakers wiring), then the auxiliary contact of the two circuit breakers of
main transformer HV side and the current of the two CTs at the outlet of the two circuit breakers
should be input.
3.30.4 Logic
Logic of interconnection status element is shown in following two figures.
EN [En_GCB] &
[Flg_52a]
SIG BI_52b_CB1
SIG Imax1>0.04In [CBStatus.Flg_OnLoad]
Figure 3.30-1 Logic diagram of interconnection status element ([En_GCB]=1)
EN [Opt_Conn_Tr] &
EN [En_GCB] &
SIG BI_52b_CB1
≥1
&
[Flg_52a]
&
SIG BI_52b_CB2
EN [Opt_Conn_Tr] &
EN [En_GCB]
SIG Imax1>0.04In ≥1
[CBStatus.Flg_OnLoad]
SIG Imax2>0.04In
Figure 3.30-2 Logic diagram of interconnection status element ([En_GCB]=0)
Where:
Imax1 is the maximum phase current value of three-phase current 1.
Imax2 is the maximum phase current value of three-phase current 2.
CBStatus
CBStatus.I3P1 Flg_52a
CBStatus.I3P2 CBStatus.Flg_OnLoad
BI_52b_CB1
BI_52b_CB2
Figure 3.30-3 Function block diagram of interconnection status element
Table 3.30-1 Input signals of interconnection status element

1 CBStatus.I3P1 Three-phase current input 1.
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3 Operation Theory

2 CBStatus.I3P2 Three-phase current input 2.
3 BI_52b_CB1 The normally closed auxiliary contact of circuit breaker 1.
4 BI_52b_CB2 The normally closed auxiliary contact of circuit breaker 2.
Table 3.30-2 Output signals of interconnection status element

The signal indicating that current of the CT at the outlet of the circuit breaker
2 CBStatus.Flg_OnLoad
is detected.
Table 3.30-3 Output signals of interconnection status element (measurements)
The signal indicating that the generator is connected with the

1 Flg_52a
system.
The signal indicating that current of the CT at the outlet of the circuit
2 CBStatus.Flg_OnLoad
breaker is detected.
Access path:
3.30.6 Settings
Table 3.30-4 Settings list of interconnection status element

Logic setting indicating whether a circuit breaker is
1 En_GCB 0/1 1
equipped at generator terminal.
0: DblBus Wiring mode selection of HV side of main
1: 3/2 transformer:
2 Opt_Conn_Tr 1
breakers 0: double-busbars wiring
wiring 1: 3/2 breakers wiring
Access path: Settings->Gen Sys Settings
3.31 Voltage Balance Protection (60)
3.31.1 Application
If abnormality happens to voltage transformer, the performance of the voltage related generator
protection (such as impedance protection, loss of excitation protection, out-of-step protection etc.)
will be affected, sometimes these protections even should be blocked during VT circuit failure in
order to prevent mal-operation.
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3 Operation Theory
For some generator, two groups of VT are equipped, the two groups of VT can be connected into
the generator protection device simultaneously, via comparing, the VT of which abnormality is
detected can be identified, if abnormality happens to one VT, all the protections that use the VT will
be switched to another normal VT automatically, so the performance of the voltage related
protections will not be affected.
Voltage balance protection has following functions:
 Automatic switching function of two groups of VT during VT circuit failure, when VT circuit
failure is detected for one VT, the related protections can be switched to another normal VT
automatically.
 Two groups of VT primary circuit failure discriminate function.

3.31.3.1 VT Circuit Failure Initiating Switching Criterion
Two groups of VT are connected into the generator protection device simultaneously, VT circuit
failure can be detected via comparing the phase-to-phase voltage, positive-sequence voltage and
negative-sequence voltage of the two groups of VT.
VT1 circuit failure initiating switching criterion:
U ab − U AB > 5V or U bc − U BC > 5V or U ca − U CA > 5V or U1′ − U1 > 3V , and U 2′ < 1V
VT2 circuit failure initiating switching criterion:
U AB − U ab > 5V or U BC − U bc > 5V or U CA − U ca > 5V or U1 − U1′ > 3V , and U 2 < 1V
Where:
U AB , U BC , U CA are three phase-to-phase voltages of VT1;
U1 is positive-sequence voltage of VT1;
U 2 is negative-sequence voltage of VT1;
U ab , U bc , U ca are three phase-to-phase voltages of VT2;
U1′ is positive-sequence voltage of VT2;
U 2′ is negative-sequence voltage of VT2;
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3 Operation Theory
If above criterion is met, VT circuit failure alarm signal will be issued with a time delay of 0.42s,
and VT switching will be initiated. When VT circuit failure happens to one VT, impedance
protection, loss of excitation protection, out-of-step protection, overvoltage protection,
overexcitation protection, reverse power protection and frequency protection etc. voltage related
protection will not be affected.
If only one group of VT is equipped at generator terminal, voltage balance protection can be
disabled.
3.31.3.2 VT1 Primary Circuit Failure 1 Criteria
in service.
The criteria of VT1 primary circuit failure 1 are:
The negative-sequence voltage of VT2 3U 2′ < 3V ;
The negative-sequence voltage of VT1 3U 2 > 8V ;
The calculated residual voltage 3U 0 zc > 8V ;
The broken-delta residual voltage 3U 0 > 8V .
If above conditions are all met, VT1 primary circuit failure 1 alarm signal will be issued with a short
time delay, generator 3rd harmonic stator ground fault protection (including 3rd harmonic ratio stator
ground fault element and 3rd harmonic differential stator ground fault element) will be blocked
during VT1 primary circuit failure, please refer to Section 3.7.3.5.
not in service.
Neutral point zero-sequence voltage 3U 0′ < 4V
Negative-sequence voltage of VT1 3U 2 > 8V
The calculated zero-sequence voltage of VT1 3U 0 zc > 8V
The broken-delta zero-sequence voltage of VT1 3U 0 > 8V
If above conditions are all met, VT1 primary circuit failure 1 alarm signal will be issued with a short
time delay, generator 3rd harmonic stator ground fault protection (including 3rd harmonic ratio stator
Date: 2016-08-16
3 Operation Theory
ground fault element and 3rd harmonic differential stator ground fault element) will be blocked
during VT1 primary circuit failure, please refer to Section 3.7.3.5.
3.31.3.3 VT1 Primary Circuit Failure 2 Criteria
If the zero sequence voltage is only from the zero sequence voltage input of generator terminal,
the VT circuit failure of generator terminal may cause the mal-operation of the zero sequence
voltage protection of stator. So, it is necessary to block the zero sequence voltage protection of
stator when the VT circuit failure of generator terminal is occurred.

If above two conditions are satisfied, the VT1 circuit failure alarm signal 2 is issued with a short
time delay, and the sensitive and insensitive stages of fundamental zero sequence voltage
protection will be blocked, please refer to Section 3.4.3.3.
3.31.3.4 VT2 Primary Circuit Failure Criteria
Criteria 1:
3U 2 < U 2 _ set1 or 3U 2′ < U 2 _ set 2 , and 3U 0′ > U 0 _ set
Criteria 2:
U AB − U ab > 5V or U BC − U bc > 5V or U CA − U ca > 5V , and 3U 0′ > U 0 _ set
Where:
U 2 is negative-sequence voltage of VT1;
U 2′ is negative-sequence voltage of VT2;
U 2 _ set1 and U 2 _ set 2 are two internal settings which are related to U 0 _ set ;
3U 0′ is the broken-delta residual voltage of VT2;
U 0 _ set is the longitudinal residual voltage setting of inter-turn protection.
U AB , U BC , U CA are three phase-to-phase voltages of VT1;
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U ab , U bc , U ca are three phase-to-phase voltages of VT2;
If any of above two criteria is met, VT2 primary circuit failure alarm signal will be issued with a time
delay of 40ms, longitudinal zero-sequence voltage inter-turn protection can be blocked by VT2
primary circuit failure alarm signal, please refer to Section 3.4.3.3.

When the criterion operates, VT2 primary circuit failure alarm will be issued with a time delay of
40ms, longitudinal zero-sequence voltage inter-turn protection can be blocked by VT2 primary
circuit failure alarm signal, please refer to Section 3.4.3.3.
3.31.3.5 Generator Neutral Point VT Circuit Failure and Generator Terminal Broken-delta VT
Circuit Failure
VT circuit failure criteria: the positive-sequence voltage of generator terminal secondary circuit is
larger than 0.9Un, the 3rd harmonic of residual voltage is small than 0.1V, then VT circuit failure
alarm signal will be issued with a time delay of 10s, the alarm signal will reset automatically with a
time delay of 10s once the abnormality disappears.
If calculated generator terminal zero-sequence voltage is adopted, generator terminal VT circuit

failure is not judged.
Generator neutral point VT circuit failure and generator terminal broken-delta VT circuit failure
alarm function can be enabled or disabled by respective logic setting, please refer to Section 3.6
and Section 3.4 related contents for details.
3.31.4 Logic
Logic of voltage balance protection is shown in following figure.
EN [60.En] &
t [60.VT1.Alm_SwitchVTS]
SIG Flg_VTS1_Init_Switch
EN [60.En] &
t [60.VT2.Alm_SwitchVTS]
SIG Flg_VTS2_Init_Switch
Figure 3.31-1 Logic diagram of voltage balance protection
Where:
Flg_VTS1_Init_Switch is the internal signal indicating that the VT1 circuit failure initiating switching
criterion is met.
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3 Operation Theory
Flg_VTS2_Init_Switch is the internal signal indicating that the VT2 circuit failure initiating switching
criterion is met.
60
60.U3P1 60.U3P
60.U3P2 60.VT1.Alm_SwitchVTS
60.U1P1_Hm 60.VT2.Alm_SwitchVTS
60.U1P2_Hm G_Term.VT1.Alm_VTS_Pri_1
60.U1P3_Hm G_Term.VT1.Alm_VTS_Pri_2
60.Flg_OnLOad G_Term.VT2.Alm_VTS_Pri
Figure 3.31-2 Function block diagram of voltage balance protection
Table 3.31-1 Input signals of voltage balance protection

1 60.U3P1 Three-phase voltage input of VT1.
2 60.U3P2 Three-phase voltage input of VT2.
3 60.U1P1_Hm Zero-sequence voltage data of VT1.
4 60.U1P2_Hm Zero-sequence voltage data of VT2.
5 60.U1P3_Hm Zero-sequence voltage data of generator neutral point.
6 60.Flg_OnLoad The signal indicating that current is detected.
Table 3.31-2 Output signals of voltage balance protection

1 60.VT1.Alm_SwitchVTS VT1 circuit failure initiating switching alarm.
3 G_Term.VT1.Alm_VTS_Pri_1 Generator terminal VT1 primary circuit failure 1 alarm
4 G_Term.VT1.Alm_VTS_Pri_2 Generator terminal VT1 primary circuit failure 2 alarm
5 G_Term.VT2.Alm_VTS_Pri Generator terminal VT2 primary circuit failure alarm
6 60.U3P Three-phase voltage data set (After switching)
7 60.Ua Phase-A voltage amplitude (After switching)
8 60.Ub Phase-B voltage amplitude (After switching)
9 60.Uc Phase-C voltage amplitude (After switching)
Table 3.31-3 Output signals of voltage balance protection (event recorder)
Alarm signals
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3 G_Term.VT1.Alm_VTS_Pri_1 Generator terminal VT1 primary circuit failure 1 alarm.
4 G_Term.VT1.Alm_VTS_Pri_2 Generator terminal VT1 primary circuit failure 2 alarm.
5 G_Term.VT2.Alm_VTS_Pri Generator terminal VT2 primary circuit failure alarm.
6 G_Term.VT1.Alm_VTS_Delt Generator terminal VT1 broken-delta circuit failure alarm.
7 G_Term.VT2.Alm_VTS_Delt Generator terminal VT2 broken-delta circuit failure alarm.
8 G_NP.Alm_VTS Generator neutral point VT circuit failure alarm.
Table 3.31-4 Output signals of voltage balance protection (measurements)
The phase angle between phase-A voltage of VT1 and VT2 of deg
1 Ang(Ua_VT1-2_G_Term)
generator terminal
The phase angle between phase-B voltage of VT1 and VT2 of deg
2 Ang(Ub_VT1-2_G_Term)
generator terminal
The phase angle between phase-C voltage of VT1 and VT2 of deg
3 Ang(Uc_VT1-2_G_Term)
generator terminal
Access path:
3.31.6 Settings
Table 3.31-5 Settings list of voltage balance protection

0: disable Logic setting of enabling/disabling voltage
1 60.En 1
1: enable balance protection.
3.32 Three-Phase Current Element (Curr3P)
NOTICE!
In Section 3.32, the prefix “Y” in settings (such as [Y.I1n]) and input/output signals (such
as [Y.Ia]) can be G_Term, G_NP, G_Bak, 32, ET_S1, ET_S2. Details of the prefix are
as:
G_Term corresponds to three-phase current of generator terminal CT
G_NP corresponds to three-phase current of generator neutral point CT
G_Bak corresponds to three-phase current of generator backup protection used CT
32 corresponds to three-phase current of power protection used CT
ET_S1 corresponds to three-phase current of the CT of side 1 of excitation transformer
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3 Operation Theory
ET_S2 corresponds to three-phase current of the CT of side 2 of excitation transformer
3.32.1 Application
Three-phase current element is responsible for pre-processing three phase currents and
calculating sequence components, amplitudes and phases of three phase currents, etc. All
calculated information of three-phase current element is for the protection logic calculation.
Three-phase current element has following functions:
 Pre-process three phase currents.
 Calculate information related to three-phase current.
 Monitor the secondary circuit of current including CT circuit abnormality.
3.32.3 Principle
 CT circuit abnormality supervision
If the calculated residual current is larger than 0.04In plus 25% of the maximum phase current, the
corresponding CT circuit abnormality alarm signal [Y.AlmL_CTS] will be issued with a time delay of
10s, and it will be reset with a time delay of 10s if the CT circuit returns to normal condition.
 Current detection
When any phase current is larger than 0.04In, it will be identified that current is detected for the
corresponding CT, CT having current signal can be used for programmable logic application.
3.32.4 Logic
10s 10s
SIG Y.3I0>0.04In+0.25Imax [Y.AlmL_CTS]
SIG Y.Ia>0.04In
≥1
SIG Y.Ib>0.04In [Y.Flg_OnLoad]
SIG Y.Ic>0.04In
Figure 3.32-1 Current pre-processing logic diagram
Where:
Y.Ia, Y.Ib, and Y.Ic are sampled three phase current values.
Y.3I0 is the calculated residual current.
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3 Operation Theory
Curr3P
Y.ia Y.I3P
Y.ib Y.Ia
Y.ic Y.Ib
Y.Ic
Y.I_Avg
Y.AlmL_CTS
Y.Flg_OnLoad
Figure 3.32-2 Function block diagram of three-phase current element
Table 3.32-1 Input signals of three-phase current element

1 Y.ia Sampled value of phase-A current
2 Y.ib Sampled value of phase-B current
3 Y.ic Sampled value of phase-C current
Table 3.32-2 Output signals of three-phase current element

1 Y.I3P Three-phase current data set.
2 Y.Ia Phase-A current.
3 Y.Ib Phase-B current.
4 Y.Ic Phase-C current.
5 Y.I_Avg The average amplitude of three-phase current.
6 Y.AlmL_CTS CT secondary circuit abnormality alarm.
7 Y.Flg_OnLoad A flag indicating that load current is detected
Above input signals and output signals can be used for programmable logic, and following output
signals are only for LCD display of equipment.
Table 3.32-3 Output signals of three-phase current element (event recorder)
Alarm signals
1 Y.AlmL_CTS CT secondary circuit abnormality alarm.
Table 3.32-4 Output signals of three-phase current element (measurements)
No. Output Signal Description
1 G_Term.Ia
2 G_Term.Ib Phase current amplitude of generator terminal CT

3 G_Term.Ic
4 G_Term.I1 Positive-sequence current amplitude of generator terminal CT
5 G_Term.I2 Negative-sequence current amplitude of generator terminal CT
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6 G_Term.3I0_Cal The calculated residual current amplitude of generator terminal CT
7 G_NP.Ia
8 G_NP.Ib Phase current amplitude of generator neutral point CT

9 G_NP.Ic
10 G_NP.I1 Positive-sequence current amplitude of generator neutral point CT
11 G_NP.I2 Negative-sequence current amplitude of generator neutral point CT
12 G_NP.3I0_Cal The calculated residual current amplitude of generator neutral point CT
13 G_Bak.Ia
14 G_Bak.Ib Phase current amplitude of generator backup protection used CT

15 G_Bak.Ic
Positive-sequence current amplitude of generator backup protection used

16 G_Bak.I1
CT
Negative-sequence current amplitude of generator backup protection used

17 G_Bak.I2
CT
The calculated residual current amplitude of generator backup protection

18 G_Bak.3I0_Cal
used CT
Access path:
Main menu -> Measurements -> Measurements1-> Gen Values1-> Gen Curr Values
Main menu -> Measurements -> Measurements2-> Gen Values2-> Gen Curr Values
19 ET_S1.Ia
20 ET_S1.Ib Phase current amplitude of the CT of side 1 of excitation transformer
21 ET_S1.Ic
Positive-sequence current amplitude of the CT of side 1 of excitation

22 ET_S1.I1
transformer
Negative-sequence current amplitude of the CT of side 1 of excitation

23 ET_S1.I2
transformer
The calculated residual current amplitude of the CT of side 1 of excitation

24 ET_S1.3I0_Cal
transformer
25 ET_S2.Ia
26 ET_S2.Ib Phase current amplitude of the CT of side 2 of excitation transformer

27 ET_S2.Ic
Positive-sequence current amplitude of the CT of side 2 of excitation

28 ET_S2.I1
transformer
Negative-sequence current amplitude of the CT of side 2 of excitation

29 ET_S2.I2
transformer
30 ET_S2.3I0_Cal The calculated residual current amplitude of the CT of side 2 of excitation
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3 Operation Theory
transformer
Access path:
Main menu -> Measurements -> Measurements1-> Exc Values1-> Exc AC Values
Main menu -> Measurements -> Measurements2-> Exc Values2-> Exc AC Values
Phase angle between phase-A current and phase-B current of generator

31 G_Term.Ang(Ia-Ib)
terminal
Phase angle between phase-B current and phase-C current of generator

32 G_Term.Ang(Ib-Ic)
terminal
Phase angle between phase-C current and phase-A current of generator

33 G_Term.Ang(Ic-Ia)
terminal
Phase angle between phase-A current and phase-B current of generator
34 G_NP.Ang(Ia-Ib)
neutral point
Phase angle between phase-B current and phase-C current of generator

35 G_NP.Ang(Ib-Ic)
neutral point
Phase angle between phase-C current and phase-A current of generator

36 G_NP.Ang(Ic-Ia)
neutral point
Access path:
Phase angle between phase-A current and phase-B current of side 1 of

37 ET_S1.Ang(Ia-Ib)
excitation transformer
Phase angle between phase-B current and phase-C current of side 1 of

38 ET_S1.Ang(Ib-Ic)
Phase angle between phase-C current and phase-A current of side 1 of

39 ET_S1.Ang(Ic-Ia)
Phase angle between phase-A current and phase-B current of side 2 of

40 ET_S2.Ang(Ia-Ib)
Phase angle between phase-B current and phase-C current of side 2 of

41 ET_S2.Ang(Ib-Ic)
Phase angle between phase-C current and phase-A current of side 2 of

42 ET_S2.Ang(Ic-Ia)
Access path:
Main menu -> Measurements -> Measurements2-> Phase Angle-> Exc PhaseAngleValues
3.32.6 Settings
Table 3.32-5 Settings list of three-phase current element

1 Y.I1n 0~60000 1 A Primary rated current of corresponding CT
2 Y.I2n 1 or 5 A Secondary rated current of corresponding CT
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3 Operation Theory

3.33 Three-Phase Voltage Element (Volt3P)
NOTICE!
In Section 3.33, the prefix “Y” in settings (such as [Y.U1n]) and input/output signals
(such as [Y.Ua]) can be G_Term.VT1, G_Term.VT2 and Tr_HVS. Details of the prefix
are as:
G_Term.VT1 corresponds to three-phase voltage of VT1 of generator terminal
G_Term.VT2 corresponds to three-phase voltage of VT2 of generator terminal
Tr_HVS corresponds to three-phase voltage of the VT of HV side of main transformer
3.33.1 Application
Three-phase voltage element is responsible for pre-processing three phase voltages and
calculating sequence components, amplitudes and phases of three phase voltages, etc. All
calculated information of three-phase voltage element is for the protection logic calculation.
 Pre-process three phase voltages.
 Calculate information related to three phase voltages.
 Monitor the secondary circuit of voltage including VT circuit abnormality.
 VT neutral line failure supervision.
3.33.3 Principle
 VT circuit abnormality supervision
If one of following two criteria is met and there is no operation of any fault detectors, VT circuit
failure alarm will be issued with a time delay of 10s. The abnormality alarm will be reset with a time
delay of 10s if the VT circuit returns to normal condition.
1) Positive sequence voltage is less than 18V and any phase current is larger than 0.04 In.
2) The three times of negative sequence voltage (3U2) is larger than 8V.
 VT neutral line failure supervision
If following two criteria are all met, VT neutral line failure alarm will be issued with a time delay of
20s. The abnormality alarm will be reset with a time delay of 20s if the VT neutral line returns to
normal condition. VT neutral line failure supervision function can be enabled or disabled
independently.
1) Positive sequence voltage is larger than 48V.
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3 Operation Theory
2) The third harmonic of calculated residual voltage (3U0_3ω) is larger than K*U1
K is the VT neutral line failure percentage restraint coefficient [Y.K_VTNS], it takes 0.2~0.5
generally.
3.33.4 Logic
SIG 3U2>8V
≥1
10s 10s
SIG U1<18V & [Y.Alm_VTS]
SIG [Y.Flg_OnLoad]
EN Y.En_VTNS
&
20s 20s
SIG U1>48V & [Y.Alm_VTNS]
SIG 3U0_3ω>[Y.K_VTNS]*U1
Figure 3.33-1 Voltage pre-processing logic diagram
Where:
U2 and U1 are negative sequence voltage value and positive sequence voltage value respectively.
3U0_3ω is the third harmonic of calculated residual voltage.
Volt3P
Y.ua Y.Alm_VTS
Y.ub Y.Alm_VTNS
Y.uc Y.U3P
Y.Flg_OnLoad Y.Ua
Y.Ub
Y.Uc
Y.U_Avg
Figure 3.33-2 Function block diagram of three-phase voltage element
Table 3.33-1 Input signals of three-phase voltage element

1 Y.ua Sampled value of phase A voltage
2 Y.ub Sampled value of phase B voltage
3 Y.uc Sampled value of Phase C voltage
4 Y.Flg_OnLoad A flag indicating that load current is detected
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Table 3.33-2 Output signals of three-phase voltage element

1 Y.U3P Three-phase voltage data set.
2 Y.Ua Phase-A voltage.
3 Y.Ub Phase-B voltage.
4 Y.Uc Phase-C voltage.
5 Y.U_Avg The average amplitude of three-phase voltage.
6 Y.Alm_VTS VT secondary circuit failure alarm.
7 Y.Alm_VTNS VT neutral line failure alarm.
Table 3.33-3 Output signals of three-phase voltage element (event recorder)
Alarm signals
1 Y.Alm_VTS VT secondary circuit failure alarm.
2 Y.Alm_VTNS VT neutral line failure alarm.
Table 3.33-4 Output signals of three-phase voltage element (measurements)
1 G_Term.VT1.Ua
2 G_Term.VT1.Ub Phase voltage amplitude of VT1 of generator terminal
3 G_Term.VT1.Uc
4 G_Term.VT1.U1 Positive-sequence voltage amplitude of VT1 of generator terminal
5 G_Term.VT1.U2 Negative-sequence voltage amplitude of VT1 of generator terminal
6 G_Term.VT1.3U0_Cal The calculated residual voltage amplitude of VT1 of generator terminal
7 G_Term.VT1.Uab
8 G_Term.VT1.Ubc Phase-to-phase voltage amplitude of VT1 of generator terminal
9 G_Term.VT1.Uca
10 G_Term.VT2.Ua
11 G_Term.VT2.Ub Phase voltage amplitude of VT2 of generator terminal
12 G_Term.VT2.Uc
13 G_Term.VT2.U1 Positive-sequence voltage amplitude of VT2 of generator terminal
14 G_Term.VT2.U2 Negative-sequence voltage amplitude of VT2 of generator terminal
15 G_Term.VT2.3U0_Cal The calculated residual voltage amplitude of VT2 of generator terminal
16 G_Term.VT2.Uab
17 G_Term.VT2.Ubc Phase-to-phase voltage amplitude of VT2 of generator terminal
18 G_Term.VT2.Uca
19 Tr_HVS.Ua Phase voltage amplitude of the VT of HV side of main transformer
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20 Tr_HVS.Ub
21 Tr_HVS.Uc
Positive-sequence voltage amplitude of the VT of HV side of main
22 Tr_HVS.U1
transformer
Negative-sequence voltage amplitude of the VT of HV side of main

23 Tr_HVS.U2
transformer
The calculated residual voltage amplitude of the VT of HV side of main

24 Tr_HVS.3U0_Cal
transformer
25 Tr_HVS.Uab
Phase-to-phase voltage amplitude of the VT of HV side of main
26 Tr_HVS.Ubc
transformer
27 Tr_HVS.Uca
Access path:
Phase angle between phase-A voltage and phase-B voltage of VT1 of

28 G_Term.VT1.Ang(Ua-Ub)
generator terminal
Phase angle between phase-B voltage and phase-C voltage of VT1 of

29 G_Term.VT1.Ang(Ub-Uc)
generator terminal
Phase angle between phase-C voltage and phase-A voltage of VT1 of

30 G_Term.VT1.Ang(Uc-Ua)
generator terminal
Phase angle between phase-A voltage and phase-B voltage of VT2 of

31 G_Term.VT2.Ang(Ua-Ub)
generator terminal
Phase angle between phase-B voltage and phase-C voltage of VT2 of

32 G_Term.VT2.Ang(Ub-Uc)
generator terminal
Phase angle between phase-C voltage and phase-A voltage of VT2 of

33 G_Term.VT2.Ang(Uc-Ua)
generator terminal
Access path:
3.33.6 Settings
Table 3.33-5 Settings list of three-phase voltage element

1 Y.U1n 1~2000 0.01 kV Primary rated voltage of corresponding VT
Secondary rated phase-to-phase voltage of
2 Y.U2n 1~300 0.01 V
corresponding VT
0: disable Logic setting of enabling/disabling VT neutral line
3 Y.En_VTNS
1: enable failure supervision function.
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3 Operation Theory

4 Y.K_VTNS 0.10~1.00 0.01 VT neutral line failure percentage restraint coefficient
Access path:
Settings->Config Settings
3.34 Single Current Element with Filter (CurrFilt1P)
NOTICE!
In Section 3.34, the prefix “Y” in input/output signals (such as [Y.I1P]) can be 87NTG
and 51GS. Details of the prefix are as:
87NTG corresponds to neutral point transverse differential current
51GS corresponds to the shaft current
3.34.1 Application
Single current element with filter is responsible for pre-processing measured single current and
calculating the fundamental component amplitude and 3rd harmonic amplitude of single current,
etc. All calculated information of single current element with filter is for the protection logic
calculation.
 Pre-process measured single current.
 Calculate information related to single current.
CurrFilt1P
Y.in Y.I1P_Hm
Y.I_Hm1
Y.I_Hm3
Figure 3.34-1 Function block diagram of single current element with filter
Table 3.34-1 Input signals of single current element with filter

1 Y.in Measured single current
Table 3.34-2 Output signals of single current element with filter

1 Y.I1P_Hm A current data set
2 Y.I_Hm1 The fundamental component current amplitude
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3 Operation Theory

rd
3 Y.I_Hm3 The 3 harmonic current amplitude
Table 3.34-3 Output signals of single current element with filter (measurements)

rd
2 87NTG.I_Hm3 The 3 harmonic of neutral point transverse differential current. A
Access path:
3 51GS.I_Hm1 The fundamental amplitude of the shaft current mA

rd
4 51GS.I_Hm3 The 3 harmonic amplitude of the shaft current mA
Access path:
3.34.4 Settings
Table 3.34-4 Settings list of single current element with filter

Primary current value of neutral point transverse
1 87NTG.I1n 0~60000 1 A
differential protection used CT,
Secondary current value of neutral point transverse
2 87NTG.I2n 1 or 5 A
differential protection used CT.
3.35 Residual Voltage Element with Filter (VoltFilt1P)
NOTICE!
In Section 3.35, the prefix “Y” in input/output signals (such as [Y.U1P]) can be
G_Term.VT1, G_Term.VT2, G_NP and Tr_HVS. Details of the prefix are as:
G_Term.VT1 corresponds to residual voltage of VT1 of generator terminal
G_Term.VT2 corresponds to residual voltage of VT2 of generator terminal
G_NP corresponds to residual voltage of VT of generator neutral point
Tr_HVS corresponds to residual voltage of VT of HV side of main transformer
3.35.1 Application
Residual voltage element is responsible for pre-processing residual voltage and calculating the
fundamental component amplitude and 3rd harmonic amplitude of residual voltage, etc. All
calculated information of residual voltage element is for the protection logic calculation
Date: 2016-08-16
3 Operation Theory

 Pre-process measured residual voltage.
 The residual voltage can select the calculated residual voltage or the broken-delta residual
voltage.
 Calculate information related to residual voltage.
VoltFilt1P
Y.ua Y.U1P_Hm
Y.ub Y.3U0_Hm1
Y.uc Y.3U0_Hm3
Y.3u0
Figure 3.35-1 Function block diagram of residual voltage element
Table 3.35-1 Input signals of residual voltage element

1 Y.ua Sampled value of phase-A voltage
2 Y.ub Sampled value of phase-B voltage
3 Y.uc Sampled value of phase-C voltage
4 Y.3u0 Measured residual voltage
Table 3.35-2 Output signals of residual voltage element

1 Y.U1P_Hm A voltage data set
2 Y.3U0_Hm1 The fundamental residual voltage amplitude
rd
3 Y.3U0_Hm3 The 3 harmonic residual voltage amplitude
Table 3.35-3 Output signals of residual voltage element (measurements)
1 G_Term.VT1.3U0_Hm1 The fundamental residual voltage amplitude of VT1 of generator terminal

rd
2 G_Term.VT1.3U0_Hm3 The 3 harmonic residual voltage amplitude of VT1 of generator terminal
The fundamental residual voltage amplitude of VT of generator neutral

3 G_NP.3U0_Hm1
point
rd
The 3 harmonic residual voltage amplitude of VT of generator neutral
4 G_NP.3U0_Hm3
point
5 G_Term.VT2.3U0_Hm1 The fundamental residual voltage amplitude of VT2 of generator terminal

rd
6 G_Term.VT2.3U0_Hm3 The 3 harmonic residual voltage amplitude of VT2 of generator terminal
The fundamental residual voltage amplitude of the VT of HV side of main

7 Tr_HVS.3U0_Hm1
transformer
Date: 2016-08-16
3 Operation Theory
Access path:
3.35.4 Settings
Table 3.35-4 Settings list of residual voltage element

1 G_Term.VT1.U1n 1~2000 0.01 kV Primary voltage value of VT1 of generator terminal
Secondary voltage value of VT1 of generator
2 G_Term.VT1.U2n 1~300 0.01 V
terminal
Secondary voltage value of broken-delta VT1 of
3 G_Term.VT1.U2n_Delt 1~300 0.01 V
generator terminal
4 G_Term.VT2.U1n 1~2000 0.01 kV Primary voltage value of VT2 of generator terminal
Secondary voltage value of VT2 of generator
5 G_Term.VT2.U2n 1~300 0.01 V
terminal
Secondary voltage value of broken-delta VT2 of
6 G_Term.VT2.U2n_Delt 1~300 0.01 V
generator terminal
Primary voltage value of VT of generator neutral
7 G_NP.U1n 1~2000 0.01 kV
point
Secondary voltage value of VT of generator neutral
8 G_NP.U2n_Delt 1~300 0.01 V
point
Date: 2016-08-16
3 Operation Theory
Date: 2016-08-16
4 Supervision
4 Supervision
Table of Contents
4 Supervision ........................................................................................ 4-a
4.1 Overview .......................................................................................................... 4-1
4.2 Failure and Abnormality Alarms .................................................................... 4-1
4.3 Relay Self-supervision.................................................................................. 4-12
4.3.1 Relay Hardware Monitoring ............................................................................................... 4-12
4.3.2 Fault Detector Monitoring .................................................................................................. 4-12
4.3.3 Setting Checking ................................................................................................................ 4-12
4.3.4 Memory Checking .............................................................................................................. 4-12
4.3.5 Opto-coupler Power Supervision ....................................................................................... 4-12
4.3.6 Output Tripping Circuit Supervision ................................................................................... 4-13
4.3.7 Test Mode Supervision ...................................................................................................... 4-13
4.3.8 Hardware Configuration Supervision ................................................................................. 4-13
List of Tables
Table 4.2-1 Alarm description..................................................................................................... 4-1
Table 4.2-2 Troubleshooting ....................................................................................................... 4-8

Date: 2016-08-16
4 Supervision
Date: 2016-08-16
4 Supervision
4.1 Overview
Protection system is in quiescent state under normal conditions, and it is required to respond
promptly for faults occurred on power system. When the device is in energizing process before the
LED “HEALTHY” is on, the device need to be checked to ensure no abnormality. Therefore, the
automatic supervision function, which checks the health of the protection system when startup and
during normal operation, plays an important role.
The numerical relay based on the microprocessor operations is suitable for implementing this
automatic supervision function of the protection system.
In case a defect is detected during initialization when DC power supply is provided to the device,
the device will be blocked with indication and alarm of relay out of service. It is suggested a trial
recovery of the device by re-energization. Please contact supplier if the device is still failure.
When a failure is detected by the automatic supervision, it is followed by a LCD message, LED
indication and alarm contact outputs. The failure alarm is also recorded in event recording report
and can be printed If required.
4.2 Failure and Abnormality Alarms

NOTICE!
If the protective device is blocked or alarm signal is sent during operation, please try to
find out its reason with the help of self-diagnostic record. If the failure reason can not be
found at site, please inform the manufacturer NR or the agent for maintenance. Please
DO NOT simply press button “TARGET RESET” on the protection panel or re-energize
on the device.
Hardware circuit and operation status of the device are self-supervised continuously. If any
abnormal condition is detected, information or report will be displayed and a corresponding alarm
will be issued.
A minor abnormality may block a certain number of protections functions while the other functions
can still work. However, if severe hardware failure or abnormality, such as PWR module failure,
DC converter failure and so on, are detected, all protection functions will be blocked and the LED
“HEALTHY” will be extinguished and blocking output contacts BO_FAIL will be given. The
protective device then can not work normally and maintenance is required to eliminate the failure.
All the alarm signals and the corresponding handling suggestions are listed below.
Table 4.2-1 Alarm description
Blocking
No. Item Description
Device
Fail Signals
The device fails.
1 Fail_Device This signal will be pick up if any fail signal picks up and it Blocked
will drop off when all fail signals drop off.

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4 Supervision
Blocking
Device
Set value of any setting is out of scope.
2 Fail_Setting_OvRange This signal will pick up instantaneously and will be latched Blocked
unless the recommended handling suggestion is adopted.
Mismatch between the configuration of plug-in modules and
3 Fail_BoardConfig Blocked
the designing drawing of an applied-specific project.
4 Fail_Config_Parsed The configuration file is wrong parsed. Blocked
5 Fail_Board_Regst Any board is failed to register. Blocked
6 Fail_Board_Inited Any board is failed to initialize. Blocked
After config file is updated, settings of the file and settings
saved on the device are not matched.
7 Fail_SettingItem_Chgd Blocked
This signal will pick up instantaneously and will be latched
Error is found during checking memory data (fault detector
DSP module).
8 FDBrd.Fail_Memory Blocked
Error is found during checking settings (fault detector DSP
module).
9 FDBrd.Fail_Settings Blocked
DSP chip is damaged (fault detector DSP module).
10 FDBrd.Fail_DSP This signal will pick up instantaneously and will be latched Blocked
AC current and voltage samplings are abnormal (fault
11 FDBrd.Fail_Sample This signal will pick up with a time delay of 50ms and will be Blocked
latched unless the recommended handling suggestion is
adopted.
Error is found during checking memory data (protection
DSP module).
12 ProtBrd.Fail_Memory Blocked
Error is found during checking settings (protection DSP
module).
13 ProtBrd.Fail_Settings Blocked
DSP chip is damaged (protection DSP module).
14 ProtBrd.Fail_DSP This signal will pick up instantaneously and will be latched Blocked
AC current and voltage samplings are abnormal (protection
15 ProtBrd.Fail_Sample DSP module). Blocked
This signal will pick up with a time delay of 50ms and will be
Date: 2016-08-16
4 Supervision
Blocking
Device
latched unless the recommended handling suggestion is
adopted.
The HTM bus for data exchange is abnormal (fault detector
16 FDBrd.Fail_HTM Blocked
DSP module).
The HTM bus for data exchange is blocked for a long time
17 ProtBrd.Fail_HTM Blocked
(protection DSP module).
The alarm indicating that the tripping output module located
18 Bn.Fail_Board Blocked
in slot No.n (n=11~14) is in abnormal status.
The alarm indicating that the output contactor of the tripping
19 Bn.Fail_Output output module located in slot No.n (n=11~14) is in abnormal Blocked
status.
Alarm Signals
The device is abnormal.
20 Alm_Device This signal will be pick up if any alarm signal picks up and it Unblocked
will drop off when all alarm signals drop off.
21 Alm_Insuf_Memory The memory of MON plug-in module is insufficient. Unblocked
The device is in the communication test mode.
22 Alm_CommTest This signal will pick up instantaneously and will drop off Unblocked
instantaneously.
23 Alm_Init The device is in initialization process. Unblocked
24 Board_Stall_Flag Any board is abnormal. Unblocked
The error is found during MON module checking settings of
device.
25 Alm_Settings_MON Unblocked
This signal will pick up with a time delay of 10s and will be
latched unless re-powering or rebooting the device.
The error is found during checking the version of software
downloaded to the device.
26 Alm_Version Unblocked
This signal will pick up instantaneously and will drop off
instantaneously.
The active group set by settings in device and that set by
binary input are not matched.
27 Alm_BI_SettingGrp Unblocked
This signal will pick up instantaneously and will drop off
instantaneously.
28 Alm_TimeSyn Time synchronization abnormality alarm. Unblocked
The alarm is to indicate that the IEC103 file in the device is
29 Alm_CfgFile_IEC103 Unblocked
invalid.
The alarm is to indicate that the device is in testing mode for
30 Alm_TestMode Unblocked
signal/trip output.
The alarm is to indicate that the board at slot n (n=6~10, 15)
31 Bn.Alm_Board Unblocked
is in abnormal status.
32 B09.Alm_OptoDC The power supply of BI plug-in module in slot 09 is Unblocked

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4 Supervision
Blocking
Device
abnormal.
This signal will pick up with a time delay of 10s and will drop
off with a time delay of 10s.
The power supply of BI plug-in module in slot 14 is
abnormal.
33 B14.Alm_OptoDC Unblocked
The device is in the GOOSE test mode.
34 Alm_GOOSETest This signal will pick up instantaneously and will drop off Unblocked
instantaneously.
The “master” process is alarm.
35 Alm_master This signal will pick up instantaneously and will drop off Unblocked
instantaneously.
Current fault detector element operates for longer than 10s
(fault detector DSP module).
36 FDBrd.Alm_Pkp Unblocked
Current fault detector element operates for longer than 10s
(protection DSP module).
37 ProtBrd.Alm_Pkp Unblocked
off with a time delay of 10s .
Protection Element Alarm Signals
38 G_Term.AlmL_CTS Generator terminal CT secondary circuit abnormality alarm. Unblocked
Generator neutral point CT secondary circuit abnormality
39 G_NP.AlmL_CTS Unblocked
alarm.
Generator backup protection used CT secondary circuit
40 G_Bak.AlmL_CTS Unblocked
abnormality alarm.
Power protection used CT secondary circuit abnormality
41 32.AlmL_CTS Unblocked
alarm.
Excitation transformer side 1 CT secondary circuit
42 ET_S1.AlmL_CTS Unblocked
abnormality alarm.
Excitation transformer side 2 CT secondary circuit
43 ET_S2.AlmL_CTS Unblocked
abnormality alarm.
44 G_Term.VT1.Alm_VTS Generator terminal VT1 secondary circuit failure alarm. Unblocked
45 G_Term.VT1.Alm_VTNS Generator terminal VT1 neutral line failure alarm. Unblocked
46 G_Term.VT2.Alm_VTS Generator terminal VT2 secondary circuit failure alarm. Unblocked
47 G_Term.VT2.Alm_VTNS Generator terminal VT2 neutral line failure alarm. Unblocked
Main transformer HV side VT secondary circuit failure
48 Tr_HVS.Alm_VTS Unblocked
alarm.
49 Tr_HVS.Alm_VTNS Main transformer HV side VT neutral line failure alarm. Unblocked
Generator terminal circuit breaker auxiliary contact
50 Alm_52_GCB Unblocked
abnormality alarm.
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Blocking
Device
51 60.VT1.Alm_SwitchVTS VT1 circuit failure initiating switching alarm. Unblocked
52 60.VT2.Alm_SwitchVTS VT2 circuit failure initiating switching alarm. Unblocked
53 G_Term.VT1.Alm_VTS_Pri_1 Generator terminal VT1 primary circuit failure 1 alarm. Unblocked
54 G_Term.VT1.Alm_VTS_Pri_2 Generator terminal VT1 primary circuit failure 2 alarm. Unblocked
55 G_Term.VT2.Alm_VTS_Pri Generator terminal VT2 primary circuit failure alarm. Unblocked
56 G_Term.VT1.Alm_VTS_Delt Generator terminal VT1 broken-delta circuit failure alarm. Unblocked
57 G_Term.VT2.Alm_VTS_Delt Generator terminal VT2 broken-delta circuit failure alarm. Unblocked
58 G_NP.Alm_VTS Generator neutral point VT circuit failure alarm. Unblocked
Alarm message indicating CT secondary circuit of generator
59 87G.Alm_Diff Unblocked
differential protection is abnormal.
Alarm message indicating that CT secondary circuit of
60 87G.Alm_CTS Unblocked
generator differential protection fails.
Negative-sequence DPFC direction inter-turn element to
61 59NIT.Alm_P2_DPFC Unblocked
issue alarm signal.
The sensitive stage of fundamental zero-sequence voltage
62 64S1.Alm_ROV_L stator ground fault protection operates to issue alarm Unblocked
signal.
The fundamental zero-sequence current stator ground fault
63 64S1.Alm_ROC Unblocked
3rd harmonic ratio stator ground fault element operates to
64 64S2.Alm_U_Hm3_Ratio Unblocked
issue alarm signal.
3rd harmonic differential stator ground fault element
65 64S2.Alm_U_Hm3_Diff Unblocked
The alarm stage of stator overload protection operates to
66 49S.Alm Unblocked
issue alarm signal
The alarm stage of generator negative-sequence overload
67 46G.Alm Unblocked
Stage 1 of loss of excitation protection operates to issue
68 40G1.Alm Unblocked
alarm signal.
Rotor voltage circuit failure alarm for stage 1 of loss of
69 40G1.Alm_RotVoltCircuit Unblocked
alarm signal.
alarm signal.
Out-of-step protection for external power swing operates to
74 78.Alm_Ext Unblocked
issue alarm signal.

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Blocking
Device
Out-of-step protection for internal power swing operates to
75 78.Alm_Int Unblocked
issue alarm signal.
76 78.Alm_Accel Alarm signal indicating that accelerate out-of-step occurs. Unblocked
77 78.Alm_Decel Alarm signal indicating that decelerate out-of-step occurs. Unblocked
Phase overvoltage protection alarm stage operates to issue
78 Gen.59PAlm.Alm Unblocked
alarm signal.
Phase undervoltage protection alarm stage operates to
79 Gen.27PAlm.Alm Unblocked
issue alarm signal.
The alarm stage of overexcitation protection operates to
80 Gen.24.Alm Unblocked
issue alarm signal
81 32R.CONV.Alm The conventional reverse power element operates to alarm. Unblocked
82 32F.Alm Generator low forward power protection operates to alarm. Unblocked
The sensitive stage of Ping-Pang type rotor one-point
83 64R.1PEF.Alm_Sens Unblocked
ground fault element operates to issue alarm signal.
The insensitive stage of Ping-Pang type rotor one-point
84 64R.1PEF.Alm_Insens Unblocked
ground fault element operates to issue alarm signal.
Rotor voltage circuit failure alarm for Ping-Pang type rotor
85 64R.Alm_RotVoltCircuit Unblocked
one-point ground fault protection.
Sensitive stage of rotor one-point ground fault element (with
86 64RInj.1PEF.Alm_Sens low-frequency square-wave voltage injection) operates to Unblocked
issue alarm signal.
Insensitive stage of rotor one-point ground fault element
87 64RInj.1PEF.Alm_Insens (with low-frequency square-wave voltage injection) Unblocked
The external injected power supply of generator rotor
88 64RInj.Alm_Pwr_Inj ground fault protection (with low-frequency square-wave Unblocked
voltage injection) is abnormal.
Stage 1 of underfrequency protection operates to issue
89 81U.UF1.Alm Unblocked
alarm signal.
alarm signal.
alarm signal.
alarm signal.
Stage 1 of underfrequency band accumulate protection
93 81U.UF1.Alm_Accu Unblocked
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Blocking
Device
Stage 1 of overfrequency protection operates to issue alarm
97 81O.OF1.Alm Unblocked
signal.
signal.
signal.
signal.
Stage 1 of overfrequency band accumulate protection
101 81O.OF1.Alm_Accu Unblocked
Alarm message indicating CT secondary circuit of excitation
105 87ET.Alm_Diff Unblocked
transformer differential protection is abnormal.
Alarm message indicating that CT secondary circuit of
106 87ET.Alm_CTS Unblocked
excitation transformer differential protection fails.
The alarm stage of rotor winding overload protection
107 49E.Alm Unblocked
Sensitive stage of generator shaft overcurrent protection
108 51GS.Alm Unblocked
Output alarm signal of channel 1 of mechanical protection
109 MR1.Sig1 Unblocked
1.
1.
1.
1.
113 MR1.Alm_PwrLoss Power supervision alarm signal of mechanical protection 1. Unblocked
2.
2.
2.

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4 Supervision
Blocking
Device
2.
118 MR2.Alm_PwrLoss Power supervision alarm signal of mechanical protection 2. Unblocked
Table 4.2-2 Troubleshooting
No. Item Handling suggestion

Fail Signals
The signal is issued with other specific fail signals, and please refer to the
1 Fail_Device
handling suggestion other specific alarm signals.
Please reset setting values according to the range described in the
2 Fail_Setting_OvRange instruction manual, then re-power or reboot the device and the device will
restore to normal operation state.
1. Go to the menu “Information→Borad Info”, check the abnormality
information.
3 Fail_BoardConfig 2. For the abnormality board, if the board is not used, then remove, and if
the board is used, then check whether the board is installed properly and
work normally.
Please check the settings mentioned in the the prompt message on the
LCD, and go to the menu “Settings” and select “Confirm_Settings” item
4 Fail_SettingItem_Chgd
to comfirm settings. Then, the device will restore to normal operation
stage.
5 FDBrd.Fail_Memory Please inform the manufacture or the agent for repair.
6 FDBrd.Fail_Settings Please inform the manufacture or the agent for repair.
Chips are damaged and please inform the manufacture or the agent
7 FDBrd.Fail_DSP
replacing the module.
1. Please make the device out of service.
2. Then check if the analog input modules and wiring connectors
8 FDBrd.Fail_Sample connected to those modules are installed at the position.
3. Re-power the device and the device will restore to normal operation
state.
9 ProtBrd.Fail_Memory Please inform the manufacture or the agent for repair.
10 ProtBrd.Fail_Settings Please inform the manufacture or the agent for repair.
Chips are damaged and please inform the manufacture or the agent
11 ProtBrd.Fail_DSP
replacing the module.
1. Please make the device out of service.
2. Then check if the analog input modules and wiring connectors
12 ProtBrd.Fail_Sample connected to those modules are installed at the position.
3. Re-power the device and the device will restore to normal operation
state.
13 FDBrd.Fail_HTM Please inform the manufacture or the agent for repair.
14 ProtBrd.Fail_HTM Please inform the manufacture or the agent for repair.
15 Bn.Fail_Board Please inform the manufacture or the agent for repair.
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4 Supervision

16 Bn.Fail_Output Please check the output contactor of the module located in slot No.n.
Alarm Signals
The signal is issued with other specific alarm signals, and please refer to
17 Alm_Device
the handling suggestion other specific alarm signals.
18 Alm_Insuf_Memory Please replace MON plug-in module.
No special treatment is needed, and disable the communication test
19 Alm_CommTest
function after the completion of the test.
20 Alm_Settings_MON Please inform the manufacture or the agent for repair.
Users may pay no attention to the alarm signal in the project
commissioning stage, but it is needed to download the latest package file
(including correct version checksum file) provided by R&D engineer to
21 Alm_Version make the alarm signal disappear. Then users get the correct software
version. It is not allowed that the alarm signal is issued on the device
already has been put into service. the devices having being put into
service so that the alarm signal disappears.
Please check the value of setting [Active_Grp] and binary input of
indiating active group, and make them matched. Then the “ALARM” LED
22 Alm_BI_SettingGrp
will be extinguished and the corresponding alarm message will disappear
and the device will restore to normal operation state.
1. check whether the selected clock synchronization mode matches the

clock synchronization source;
2. check whether the wiring connection between the device and the clock
synchronization source is correct
23 Alm_TimeSyn 3. check whether the setting for selecting clock synchronization (i.e.
[Opt_TimeSyn]) is set correctly. If there is no clock synchronization,
please set the setting [Opt_TimeSyn] as ”No TimeSync”.
4. After the abnormality is removed, the “ALARM” LED will be

extinguished and the corresponding alarm message will disappear and
the device will restore to normal operation state.
Please check IEC103 version of the device, or, redownload the new
24 Alm_CfgFile_IEC103
IEC103 configuration file.
Please wait. The alarm will automatically disappear after the event test is
25 Alm_TestMode
finished.
26 Bn.Alm_Board Please check the module located in slot No.n.
1. check whether the binary input module is connected to the power
27 B09.Alm_OptoDC supply.
2. check whether the voltage of power supply is in the required range.
3. After the voltage for binary input module restores to normal range, the
“ALARM” LED will be extinguished and the corresponding alarm
28 B14.Alm_OptoDC message will disappear and the device will restore to normal operation
state.

Date: 2016-08-16
4 Supervision

Please wait. The alarm will automatically disappear after the GOOSE
29 Alm_GOOSETest
communication test is finished.
30 Alm_master Please inform the manufacture or the agent for repair.
31 FDBrd.Alm_Pkp Please check secondary values and protection settings. If settings are not
set reasonable to make fault detectors pick up, please reset settings, and
32 ProtBrd.Alm_Pkp then the alarm message will disappear and the device will restore to
normal operation state.
Protection Element Alarm Signals
33 G_Term.AlmL_CTS
34 G_NP.AlmL_CTS
35 G_Bak.AlmL_CTS Please check the corresponding CT secondary circuit. After the
36 32.AlmL_CTS abnormality is eliminated, the device returns to normal operation state.
37 ET_S1.AlmL_CTS
38 ET_S2.AlmL_CTS
39 G_Term.VT1.Alm_VTS
Please check the corresponding VT secondary circuit. After the
40 G_Term.VT2.Alm_VTS
abnormality is eliminated, the device returns to normal operation state.
41 Tr_HVS.Alm_VTS
42 G_Term.VT1.Alm_VTNS Please check the corresponding VT secondary circuit of neutral line. After
43 G_Term.VT2.Alm_VTNS the abnormality is eliminated, the device returns to normal operation
44 Tr_HVS.Alm_VTNS state.
Please check the auxiliary contact of the generator terminal circuit
45 Alm_52_GCB breaker. After the abnormality is eliminated, the device returns to normal
operation state.
46 60.VT1.Alm_SwitchVTS Please check the corresponding VT primary and secondary circuit. After
the abnormality is eliminated, the device returns to normal operation
47 60.VT2.Alm_SwitchVTS
state.
48 G_Term.VT1.Alm_VTS_Pri_1
Please check the corresponding VT primary circuit. After the abnormality
49 G_Term.VT1.Alm_VTS_Pri_2
is eliminated, the device returns to normal operation state.
50 G_Term.VT2.Alm_VTS_Pri
51 G_Term.VT1.Alm_VTS_Delt Please check the corresponding VT broken-delta secondary circuit. After
the abnormality is eliminated, the device returns to normal operation
52 G_Term.VT2.Alm_VTS_Delt
state.
Please check the corresponding VT secondary circuit. After the
53 G_NP.Alm_VTS
abnormality is eliminated, the device returns to normal operation state.
54 87G.Alm_Diff
55 87G.Alm_CTS
56 59NIT.Alm_P2_DPFC
57 64S1.Alm_ROV_L
Please check the logic of corresponding protection element in Chapter 3.
58 64S1.Alm_ROC
59 64S2.Alm_U_Hm3_Ratio
61 49S.Alm
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4 Supervision

62 46G.Alm
63 40G1.Alm
64 40G1.Alm_RotVoltCircuit
65 40G2.Alm
67 40G3.Alm
69 78.Alm_Ext
70 78.Alm_Int
71 78.Alm_Accel
72 78.Alm_Decel
73 Gen.59PAlm.Alm
74 Gen.27PAlm.Alm
75 Gen.24.Alm
76 32R.CONV.Alm
77 32F.Alm
78 64R.1PEF.Alm_Sens
80 64R.Alm_RotVoltCircuit
83 64RInj.Alm_Pwr_Inj
84 81U.UF1.Alm
85 81U.UF2.Alm
86 81U.UF3.Alm
87 81U.UF4.Alm
88 81U.UF1.Alm_Accu
89 81U.UF2.Alm_Accu
90 81U.UF3.Alm_Accu
91 81U.UF4.Alm_Accu
92 81O.OF1.Alm
93 81O.OF2.Alm
94 81O.OF3.Alm
95 81O.OF4.Alm
96 81O.OF1.Alm_Accu
97 81O.OF2.Alm_Accu
98 81O.OF3.Alm_Accu
99 81O.OF4.Alm_Accu
100 87ET.Alm_Diff
101 87ET.Alm_CTS
102 49E.Alm
103 51GS.Alm

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4 Supervision

104 MR1.Sig1
105 MR1.Sig2
106 MR1.Sig3
107 MR1.Sig4
108 MR2.Sig1
109 MR2.Sig2
110 MR2.Sig3
111 MR2.Sig4
112 MR1.Alm_PwrLoss
Check the power supply of mechanical relays.
113 MR2.Alm_PwrLoss
4.3 Relay Self-supervision
4.3.1 Relay Hardware Monitoring

All chips on DSP module are monitored to ensure whether they are damaged or having errors. If
any one of them is detected damaged or having error, the alarm signal [ProtBrd.Fail_DSP] or
[FDBrd.Fail_DSP] is issued with the device being blocked.
4.3.2 Fault Detector Monitoring

If any fault detector picks up to trigger oscillography function, the corresponding binary input
changing report will be recorded in “IO_Events” menu with tripping report [TrigDFR] being issued.
If a fault detector on protection or fault detector DSP module keeps picking up for 10s, the
corresponding alarm signal [ProtBrd.Alm_Pkp] or [FDBrd.Alm_Pkp] will be issued without the
device being blocked.
4.3.3 Setting Checking

This relay has 10 setting groups, only one setting group could be activiated (is active) at a time.
The settings of active setting group are checked to ensure they are reasonable. If settings are
checked to be unreasonable or out of setting scopes, a corresponding alarm signal will be issued,
and the device is also blocked.
4.3.4 Memory Checking

Data in non-volatile memory, which are not changed after device energized, are always checked
during device normal operation, such as settings, pointers, etc. If these data changed abnormally,
the corresponding alarm [ProtBrd.Fail_Memory] or [FDBrd.Fail_Memory] will be issued.
4.3.5 Opto-coupler Power Supervision

Positive power supply of opto-coupler on each BI module at slot x (Bx is the slot number) is
continuously monitored, and if a failure or damage on the module is detected, then the alarm
signal [Bx.Alm_OptoDC] will be issued.
Date: 2016-08-16
4 Supervision
4.3.6 Output Tripping Circuit Supervision

State of binary outputs on each BO module at slot Bx (Bx is the slot number) is continuously
monitored. If any abnormality is detected on the module, the corresponding alarm signal
[Bx.Alm_Output] will be issued with equipment being blocked.
4.3.7 Test Mode Supervision

When protection equipment is in communication test mode the alarm signal [Alm_CommTest] is
issued without blocking equipment.
4.3.8 Hardware Configuration Supervision

Module configuration is checked automatically during equipment initialization, if plug-in module
configuration is not consistent to the design drawing of an applied-specific, the alarm signal
[Fail_BoardConfig] is issued with the equipment being blocked.

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5 Management
5 Management
Table of Contents
5.1 Overview ........................................................................................................... 5-1

5.2 Measurement ................................................................................................... 5-1
5.3 Event & Fault Records .................................................................................... 5-1
5.3.1 Introduction ........................................................................................................................... 5-1
5.3.2 Event Recording ................................................................................................................... 5-2
5.3.3 Disturbance and Fault Recording......................................................................................... 5-2
5.3.4 Present Recording ................................................................................................................ 5-3
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5 Management
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5 Management
5.1 Overview
The relay also provides some auxiliary functions, such as on-line data metering, binary input
status, event and disturbance recording. All these functions make the relay meet the demands of
the modern power grid requirements.
5.2 Measurement
The device can continuously display the measured analogue input quantities, some internal flags
and calculated value based on the analogue input quantities can also be displayed. The
measurement data are displayed on the LCD of the relay front panel or by the software interface
on the local or remote PC. The analog quantities will be displayed as RMS values of the
secondary side of CT and VT.
The device samples 24 points per cycle. The RMS value is calculated in each interval and the LCD
display will be updated in every 0.5 second.
Users can view the measured data on LCD by navigating the menu “Measurements”, or by
PCS-Explorer2 software or substation automatic system (SAS) software.
The device has two DSP modules that are protection DSP module and fault detector DSP module,
the displayed values of the menu “Measurements->Measurement1” corresponds to the
measurement data of protection DSP module, and the displayed values of the menu
“Measurements->Measurement2” corresponds to the measurement data of fault detector DSP
module.
Please refer to the output signal list (for measurements) of Section “Inputs and Outputs” of each
protection element in Chapter 3 for detailed description and the concrete access path of each
measurement data. For a certain application, some measurement data listed in Chapter 3 may be
eliminated due to the scheme user required, so please look up the device on site for actual
displayed measurement data.
5.3 Event & Fault Records
5.3.1 Introduction
The device provides the following recording functions:
 Event recording
 Fault and disturbance recording
 Present recording
All the recorded information except for waveform can be viewed on local LCD or by printing.
Waveform must be printed or be extracted using PCS-Explorer2 software and a waveform
software.
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5 Management
5.3.2 Event Recording

The device can store up to 1024 abnormality alarm reports and 1024 binary input status changing
reports respectively. All the records are stored in non-volatile memory, and when the available
space is fully occupied, the oldest report is automatically overwritten by the latest one.
 Abnormality alarm reports
Abnormality detected during relay self-supervision, secondary circuit abnormality or protection

alarm element will be logged as individual events.
 Binary input status changing reports
When binary input status changes, the changed information will be displayed on LCD and logged
as binary input change report at the same time.
5.3.3 Disturbance and Fault Recording

5.3.3.1 Application
Users can use the disturbance recorder to achieve a better understanding of the behavior of the
power network and related primary and secondary device during and after a disturbance.
Analyzing on the recorded data can help to resolve practical problem.
5.3.3.2 Design
Disturbance recorder is consisted of tripping report and fault waveform and it is triggered by fault
detector. The device can store 64 pieces of trip reports and waveforms in non-volatile memory.
When protection operates, the operating information will be displayed on LCD and logged as trip
record at same time, which can be viewed in trip report. Here fault recording includes two kinds of
cases:
1) Only the fault detector element operates.
2) The fault detector element operates along with the operation of protective elements.
1. Trip record capacity and information
The device can store 64 pieces of trip reports in non-volatile memory. If a new fault occurs when
the spaces are fully occupied, the oldest will be overwritten by the latest one.
A complete trip record includes the following items:
1) Sequence number
Each operation will be recorded with a sequence number in the report and displayed on LCD
screen.
2) Date and time of fault occurrence
The time resolution is 1 ms using the relay internal clock. Initiating date and time is when a fault
detector picks up. The relative time is the time when protection element operates to send tripping
signal after fault detector picks up.
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5 Management
3) Operating time
It is the relative time when protection element operates to send tripping signal relative to fault
detector element operating, the operating time of output relay is not included.
4) Protection element
The protection element that issues the tripping command will be shown. If no protection element
operates to trip but only fault detector element operates, the fault report will record the title of fault
detector element.
2. Fault waveform record capacity and information
MON module of the relay can store 64 pieces of fault waveform in non-volatile memory. If a new
fault occurs when 64 fault waveform recorders have been stored, the oldest will be overwritten by
the latest one.
Each fault record consists of all analog and digital quantities related to protection, such as original
current and voltage, differential current, alarm elements, and binary inputs and etc.
1) Only the fault detector element operates.
Each time recording includes several-cycle pre-disturbance waveform (the waveform cycle
number before triggering is configured via the communication setting
[Num_Cyc_PreTrigDFR], the default value is 3-cycle) and 8-cycle after-disturbance
waveform.
2) The fault detector element operates along with the operation of protective element.
Each time recording includes several-cycle pre-fault waveform (the waveform cycle number
is configured via the communication setting [Num_Cyc_PreTrigDFR], the default value is
3-cycle), 8-cycle after-fault waveform, several-cycle pre-tripping waveform (the waveform
cycle number is configured via the communication setting [Num_Cyc_PreTrigDFR], the
default value is 3-cycle), 8-cycle after-tripping waveform and all the current and voltage
waveform with disturbance between the fault detector element and the protective element.
5.3.4 Present Recording
Present recording is used to record the waveform of present operating device which can be
triggered manually on LCD of device or remotely through PCS-Explorer2 software. Recording
content of present recording is same to that of disturbance recording. Each time recording
includes several-cycle pre-disturbance waveform (the waveform cycle number is configured via
the communication setting [Num_Cyc_PreTrigDFR], the default value is 3-cycle) and 8-cycle
after-disturbance waveform.
Date: 2016-08-16
5 Management
Date: 2016-08-16
6 Hardware
6 Hardware
Table of Contents
6.1 Overview ........................................................................................................... 6-1

6.2 Typical Wiring .................................................................................................. 6-4
6.3 CT Requirement ............................................................................................... 6-5
6.4 Plug-in Module Terminal Definition ................................................................ 6-6
6.4.1 Plug-in Module Arrangement................................................................................................ 6-6
6.4.2 PWR Module (Power Supply) .............................................................................................. 6-7
6.4.3 MON Plug-in Module (Monitor) ............................................................................................ 6-8
6.4.4 DSP Module 1 (Protection Calculation).............................................................................. 6-11
6.4.5 DSP Module 2 (Fault Detector Calculation) ....................................................................... 6-11
6.4.6 BI Module (Binary Input)..................................................................................................... 6-11
6.4.7 BO Module (Binary Output) ................................................................................................ 6-15
6.4.8 Mechanical Signal Input and Output Module (MR module) ............................................... 6-21
6.4.9 AI Module (Analog Input) .................................................................................................... 6-23
6.4.10 Rotor Ground Fault Protection Input Module ................................................................... 6-27
6.4.11 HMI Module ...................................................................................................................... 6-28
List of Figures
Figure 6.1-1 Hardware diagram .................................................................................................. 6-1
Figure 6.1-2 Front view of the device ........................................................................................ 6-3
Figure 6.1-3 Typical rear view of the device ............................................................................. 6-3
Figure 6.2-1 Typical wiring of PCS-985GE ................................................................................ 6-4
Figure 6.4-1 The module arrangement of PCS-985GE from rear view................................... 6-6
Figure 6.4-2 View of PWR plug-in module ................................................................................ 6-7
Figure 6.4-3 View of MON plug-in module ................................................................................ 6-9
Figure 6.4-4 Wiring of communication interface.................................................................... 6-10
Figure 6.4-5 Rear view of DSP module.................................................................................... 6-11
Date: 2019-02-21
6 Hardware
Figure 6.4-6 Debouncing technique ........................................................................................ 6-12
Figure 6.4-7 View of BI plug-in module (NR1503) .................................................................. 6-12
Figure 6.4-8 View of BI plug-in module (NR1504) .........................................错误！未定义书签。
Figure 6.4-9 View of BO plug-in module (NR1521A) .............................................................. 6-16
Figure 6.4-10 View of BO plug-in module (NR1521H) ............................................................ 6-17
Figure 6.4-11 Pin definition of signal output module NR1523A ........................................... 6-18
Figure 6.4-12 Pin definition of signal output module NR1523B ........................................... 6-19
Figure 6.4-13 Pin definition of signal output module NR1523C ........................................... 6-20
Figure 6.4-14 Pin definition of signal output module NR1523D ........................................... 6-21
Figure 6.4-15 Pin definition of mechanical relay IO module (x=1, 2) ................................... 6-22
Figure 6.4-16 Schematic diagram of CT circuit automatically closed ..................................... 6-24
Figure 6.4-17 Pin definition of AC analog output module..................................................... 6-25
Figure 6.4-18 Default terminal definition 1 of two NR1401 modules ................................... 6-26
Figure 6.4-19 Default terminal definition 2 of two NR1401 modules ................................... 6-27
Figure 6.4-20 Rotor ground fault protection input module................................................... 6-28
List of Tables
Table 6.1-1 Module configuration of PCS-985GE..................................................................... 6-2
Table 6.4-1 Terminal definition and description of PWR plug-in module ............................. 6-8
Date: 2019-02-21
6 Hardware
6.1 Overview
Output Relay
Binary Input
External
Protection
CT/VT A/D Calculation
DSP
Fault
A/D Detector Pickup
DSP Relay
N
R
H
E
E
T
T
LCD +E
Clock SYN
Power
Uaux LED CPU
Supply
R
5
4
J
Keypad
IN
R
P
T
Figure 6.1-1 Hardware diagram
The device adopts 32-bit microchip processor CPU as control core for management and
monitoring function, meanwhile, adopts high-speed digital signal processor DSP to be in charge of
all the protection calculation. 24 points are sampled in every cycle and parallel processing of
sampled data can be realized in each sampling interval to ensure ultra-high reliability and safety of
protection equipment.
The working process of the device is as follows: firstly, the current and voltage is converted into
small voltage signal and sent to DSP module after being filtered and converted by AD for
protection calculation and fault detector respectively. When DSP module completes all the
protection calculation, the result will be sent to 32-bit CPU on MON module to be recorded.
Protection DSP module carries out protection logic calculation, tripping output, and MON module
completes SOE (sequence of event) record, waveform recording, printing, communication
between protection and SAS and communication between HMI and CPU. The work process of
fault detector DSP module is similar to that of protection DSP module, and the only difference is,
when fault detector DSP module decides a fault detector picks up, only positive power supply of
output relay will be switched on.
The device is comprised of intelligent modules, except that few particular modules’ position cannot
be changed in the whole device (please refer to Figure 6.4-1 for details), the others like AI (analog
input) module such as AC current, AC voltage, DC current, and etc., and IO (input and output)
module such as binary input, tripping output, signal output, and etc can be flexibly configured
according to the remained slot positions.
Date: 2019-02-21
6 Hardware
Table 6.1-1 Module configuration of PCS-985GE
No. ID Module description Remark

1 NR1101/NR1102 Management and monitor module (MON module) Standard
2 NR1156 Protection calculation and fault detector module (DSP module) Standard
3 NR1503/NR1504 Binary input module (BI module) Standard
4 NR1536 Mechanical signal input module (MR module) Optional
5 NR1521/NR1523 Binary output module (BO module) Standard
6 NR1401 Analog input module (AI module) Standard
7 NR1417/1418 Rotor ground fault protection input module Optional
8 NR1301 Power supply module (PWR module) Standard
9 Human machine interface module (HMI module) Standard
 MON module provides functions like management function, completed event record, setting
management, and etc.
 DSP modules can carry out filtering, sampling, protection calculation and fault detector
calculation.
 AI module converts AC current and voltage to low voltage signals with current transformers
and voltage transformers respectively.
 BI module provides binary inputs via opto-couplers with rating voltage among
110V/125V/220V/250V (configurable)
 BO module provides all kinds of binary output contacts, including signal output contacts and
tripping output contacts.
 PWR module converts DC 250/220/125/110V into different DC voltage levels for various
modules of the device.
 HMI module is comprised of LCD, keypad, LED indicator and multiplex RJ45 ports for user as
human-machine interface.
Following figures show front and rear views of the device respectively. Programmable LED
indicators (No.4-No.20) can be defined by user through PCS-Explore2 software.
Date: 2019-02-21
6 Hardware
1 11
HEALTHY
2 12 PCS-985GE
ALARM
3
TRIP
13
GENERATOR RELAY
4 14
5 15
C GRP
6 16
7 17 ENT
ES
8 18
9 19
10 20
Figure 6.1-2 Front view of the device
Slot No. 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 P1
NR1101F NR1156D NR1156D NR1401 NR1401 NR1418C NR1504A NR1536A NR1521A NR1523A NR1523A NR1301T
5V BJ
1 2 3 1 2 3
4 5 6 4 5 6 BJJ BSJ
ON
OFF
DANGER DANGER 1 BO_COM1
2 BO_FAIL
3 BO_ALM
4 BO_COM2
5 BO_FAIL
6 BO_ALM
7 OPTO+
8 OPTO-
10 PWR+
11 PWR-
12 GND
Figure 6.1-3 Typical rear view of the device
Date: 2019-02-21
6 Hardware
6.2 Typical Wiring
AI module 1 (NR1401) AI module 2 (1401T-6I6U-G)

Opto+
0901 + 0601
0401 Ia
Three-phase current
Ia
Three-phase current
PCS-985GE
input channel 5
BI_TimeSyn 0602
input channel 1
0902 + 0402 Ian Ian
0403 0603
Ib Ib
0903 + BI_Print
0404 0604
Ibn Ibn
BI_Maintenance 0405 0605
0904 + Ic Ic
0406 0606
Icn Icn
0905 + BI_RstTarg
0407
current
Three-phase current
BI_06 Ia 0607
Shaft
0906 + I Rotor ground fault protection input
input channel 2
0408 0608 module
Ian In
0907 + BI_07 0409
Ib B08 NR1418
0410 IR+ 01
Reserved
Ibn
sensitive
Current
0908 Not used 0609
0411 I DC Transducer 02
Ic
0412 0610 In input IR- 03
0909 + BI_08 Icn
04
BI module 1 (NR1504)
Transverse
BI_09 Loss of UR2+ 05
differential
0910 + 0413
current
Ia 0611
Three-phase current
I excitation
06
input channel 3
BI_10 0414 Ian 0612 protection used

0911 + In rotor voltage UR2- 07
0415 Ib 08
0912 + BI_11
0416 Ibn 0613 Ua 09
Three-phase voltage
0417 UR1+ 10
input channel 1
0913 + BI_12 Ic 0614 Uan
0418 11
Icn 0615 Ub
0914 + BI_13 12
0616 Ubn 13
(measurement level CT)
0915 + Not used 0419 0617 14

Three-phase current
Ia Uc Ping-Pang type
input channel 4
0916 + BI_14 0420 Ian 0618 Ucn rotor ground RGND 15

fault protection 16
0421 Ib
residual VT residual VT residual VT

BI_15 TEST 17
Generator Generator
0917 + 0422 terminal 0619
Ibn 3U0
VT1 18
BI_16 0423 Ic 0620 3U0n
0918 + 19
0424 Icn UR1- 20
0919 + BI_17
21
neutral
0621
point
3U0
BI_18 22
0920 + Opto+ 0622
3U0n
1401 +
0921 + BI_19
BI_02
Generator
terminal
1402 + 0623 3U0

VT2
0922 - COM- 0624

BI_03 3U0n
1403 +
BI_04
1404 +
1405 + BI_05 MR IO Module 1 (NR1536A)
1406 + BI_06 1001 Reset Signal ResetInput
1101 BI_07 1002 MR1.Input1

BO_Trip_1-1 1407 +
High Voltage
1102 1003 MR1.Input2

Binary Input Signals of
P110 PWR+
1103 1408 Not used Mechanical protection
1004 MR1.Input3 Power External DC power
1104 BO_Trip_1-2
Supply P111 supply
1409 + BI_08 1005 MR1.Input4 PWR-
1105 P107
BI module 2 (NR1504)
BO_Trip_1-3 1006 BO_MR1.Sig1_1

OPTO+
1106 BI_09 Power supply for
1410 +
1007 BO_MR1.Sig2_1 P108 opto-coupler (24V)
1107 OPTO-
BI_10
PWR module
1108 BO_Trip_1-4 1411 + 1008 BO_MR1.Sig3_1

P102
BO module 1 for tripping (NR1521A)
BO_FAIL
1109 BI_11 1009 BO_MR1.Sig4_1
P103
1412 + BO_ALM
1110 BO_Trip_2-1
BI_12 1010 Common1
COM P101
1413 +
1111 P105
1011 BO_MR1.Sig1_2 BO_FAIL
1112 BO_Trip_2-2 BI_13
1414 + BO_ALM P106
1012 BO_MR1.Sig2_2
1113 P104
1415 + COM
1114 BO_Trip_2-3 Not used 1013 BO_MR1.Sig3_2
P112
1115 1416 + BI_14 1014 BO_MR1.Sig4_2 Grounding
BO_Trip_2-4 Screw
1116 1015 Common2
1417 + BI_15
1117 1016 BO_MR1.Sig1_3
Grounding
1118 BO_Trip_3-1 BI_16 Bus
1418 + 1017 BO_MR1.Sig2_3
1119
1419 + BI_17 1018 BO_MR1.Sig3_3
1120 BO_Trip_3-2
1019 BO_MR1.Sig4_3 Multiplex
1121 1420 + BI_18
RJ45 (Front)
1122 BO_Trip_3-3 1020 Common3
1421 + BI_19
1021 Pwr+
Module Power Input
1422 - COM- 1022 Pwr -
1201 1301 1501 Ethernet A

1202 BO_Signal_1-1 1302 BO_Signal_9-1 BO_Signal_17-1
1502 Ethernet B
1203 1303 1503 Electrical
BO_Signal_1-2 BO_Signal_9-2 Ethernet to
BO_Signal_17-2
Optional
1204 1304 1504 Ethernet C SCADA

1205 1305 1505 Ethernet D
1506
1207 1307 1507 Optical
Optional
BO module 3 for signal (NR1523C)
BO module 1 for signal (NR1523A)
BO module 2 for signal (NR1523A)
Ethernet C
BO_Signal_2-2 BO_Signal_10-2 BO_Signal_18-2 Ethernet to
1208 1308 1508
MON module (NR1101)
SCADA
Ethernet D
1209 1309 1509
BO_Signal_3-1 BO_Signal_11-1 BO_Signal_19-1
COM(optional)
1210 1310 1510 0101 485-1A

cable with single point earthing
To the screen of other coaxial
1211 1311 1511 0102 485-1B

1512 0103 SGND
1213 1313 1513 0104
1214 BO_Signal_4 1314 BO_Signal_12 BO_Signal_20
1514
0101 SYN+
1215 1315
Clock SYN
1515
BO_Signal_5 BO_Signal_13 BO_Signal_21 0102 SYN-
1216 1316 1516
0103 SGND
1217 1317 1517
BO_Signal_6 BO_Signal_14 BO_Signal_22 0104
1218 1318 1518
1219 1319 1519 0105 RTS
PRINT

1520 0106 TXD
1221 1321 1521 0107 SGND
1522
Figure 6.2-1 Typical wiring of PCS-985GE
Date: 2019-02-21
6 Hardware
6.3 CT Requirement
-Rated primary current Ipn:
According to the rated current or maximum load current of primary apparatus.
-Rated continuous thermal current Icth:
According to the maximum load current.
-Rated short-time thermal current Ith and rated dynamic current Idyn:
According to the maximum fault current.
-Rated secondary current Isn
-Accuracy limit factor Kalf:
Ipn Rated primary current (amps)

Icth Rated continuous thermal current (amps)
Ith Rated short-time thermal current (amps)
Idyn Rated dynamic current (amps)
Isn Rated secondary current (amps)
Kalf Accuracy limit factor (Kalf=Ipal/Ipn)
IPal Rated accuracy limit primary current (amps)
Performance verification
Esl > Esl′
Rated secondary limiting e.m.f (volts)

Esl
Esl = kalf×Isn×(Rct+Rbn)
Kalf Accuracy limit factor (Kalf=Ipal/Ipn)
IPal Rated accuracy limit primary current (amps)
Rct Current transformer secondary winding resistance (ohms)
Rated resistance burden (ohms)
Rbn 2
Rbn=Sbn/Isn
Sbn Rated burden (VAs)
Required secondary limiting e.m.f (volts)

Esl′
Esl′ = k×Ipcf ×Isn×(Rct+Rb)/Ipn
k stability factor = 2
Protective checking factor current (amps)
Ipcf
Same as the maximum prospective fault current
Rct Current transformer secondary winding resistance (ohms)
Date: 2019-02-21
6 Hardware
Real resistance burden (ohms)

Rb
Rb=Rr+2×RL+Rc
Rc Contact resistance, 0.05-0.1 ohm (ohms)
RL Resistance of a single lead from relay to current transformer (ohms)
Rr Impedance of relay phase current input (ohms)
For example:
1. Kalf=30, Isn=5A, Rct=1ohm, Sbn=60VA
Esl = kalf×Isn×(Rct+Rbn) = kalf×Isn×(Rct+ Sbn/ Isn2)
= 30×5×(1+60/25)=510V
2. Ipcf=40000A, RL=0.5ohm, Rr=0.1ohm, Rc=0.1ohm, Ipn=2000A
Esl′ = 2×Ipcf×Isn×(Rct+Rb)/Ipn
= 2×Ipcf ×Isn×(Rct+(Rr+2×RL+Rc))/Ipn
= 2×40000×5×(1+(0.1+2×0.5+0.1))/2000=440V
Thus, Esl > Esl′
6.4 Plug-in Module Terminal Definition
The device consists of PWR plug-in module, MON plug-in module, DSP plug-in module, AI plug-in
module, BI plug-in module, BO plug-in module etc. Terminal definitions and application of each
plug-in module are introduced as follows. Terminal definitions are represents with its slot position
and pin number. For example, contact 1301-1302 means terminal 01-02 of the module located in
slot 13, i.e. 13 represents the slot position, 01(02) represents the pin number on the module.
6.4.1 Plug-in Module Arrangement
The module arrangement of the device from rear view is shown in the following figure. The
irremovable modules are power supply module, MON module, DSP module and Rotor ground
fault protection input module.
NR1101F NR1156D NR1156D NR1401 NR1401 NR1418 NR1504A NR1536A NR1521A NR1523A NR1523A NR1504A NR1523C NR1301
protection input module
BO module 3 for signal

BO module 1 for trip
Rotor ground fault
DSP module 2
DSP module 1
PWR module
MON module
MR module 1
BI module 2
AI module 1
BI module 1
AI module 2
Slot No.
01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 P1
Figure 6.4-1 The module arrangement of PCS-985GE from rear view
Date: 2019-02-21
6 Hardware
Besides the fixed five modules are shown in above figure, there are eleven slots can be flexibly
configured.
 AI module can be configured at position between slot 04 to slot 07. The AC AI module can be
configured up to 2 pieces, and each AC AI module occupying 2 slots can provide 12 analog
inputs.
 BI module and BO module can be configured at position between slot 09 to slot 15.
6.4.2 PWR Module (Power Supply)

PWR module is a DC/DC converter with electrical insulation between input and output. It has an
input voltage range as described in Chapter 2. The standardized output voltages are +5V and
+24V DC. The tolerances of the output voltages are continuously monitored.
The +5V DC output provides power supply for all the electrical elements that need +5V DC power
supply in this device. The +24V DC output provides power supply for the static relays of this
device.
The use of an external miniature circuit breaker is recommended. The miniature circuit breaker
must be in the on position when the device is in operation and in the off position when the device is
in cold reserve.
A 12-pin connector is fixed on PWR module. The terminal definition of the connector is described
as below.
NR1301
5V OK ALM
BO_ALM BO_FAIL
1 BO_COM1 P101
BO_FAIL
2 BO_FAIL P102
BO_ALM
3 BO_ALM P103
4 BO_COM2 P104
BO_FAIL
5 BO_FAIL P105
BO_ALM
6 BO_ALM P106
7 OPTO+
8 OPTO-
9
10 PWR+
11 PWR-
12 GND
Figure 6.4-2 View of PWR plug-in module
Terminal definition and description is shown as follows:
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6 Hardware
Table 6.4-1 Terminal definition and description of PWR plug-in module
Terminal No. Symbol Description
01 BO_COM1 Common terminal 1
02 BO_FAIL Device failure output 1 (01-02, NC)
03 BO_ALM Device abnormality alarm output 1 (01-03, NO)
04 BO_COM2 Common terminal 2
05 BO_FAIL Device failure output 2 (04-05, NC)
06 BO_ALM Device abnormality alarm output 2 (04-06, NO)
07 OPTO+ Positive power supply for BI module (24V)
08 OPTO- Negative power supply for BI module (24V)
09 Blank Not used
10 PWR+ Positive input of power supply for the device (250V/220V/125V/110V)
11 PWR- Negative input of power supply for the device (250V/220V/125V/110V)
12 GND Grounded connection of the power supply
The standard rated voltage of PWR module is self-adaptive to 88~300Vdc. If the input voltage is
out of the range, an alarm signal (Fail_Device) will be issued. For non-standard rated voltage
power supply module please specify when place order, and check whether the rated voltage of
power supply module is the same as the voltage of power source before the device being put into
service.
PWR module provides terminal 12 and grounding screw for device grounding. Terminal 12 shall be
connected to grounding screw and then connected to the earth copper bar of panel via dedicated
grounding wire.
Effective grounding is the most important measure for a device to prevent EMI, so effective
grounding must be ensured before the device is put into service.
Like almost all electronic relays, PCS-985GE contains electrolytic capacitors. These capacitors
are well known to be subject to deterioration over time if voltage is not applied periodically.
Deterioration can be avoided by powering the relays up once a year.
6.4.3 MON Plug-in Module (Monitor)

MON module consists of high-performance built-in processor, FLASH, SRAM, SDRAM, Ethernet
controller and other peripherals. Its functions include management of the complete device, human
machine interface, communication and waveform recording etc.
MON module uses the internal bus to receive the data from other modules of the device. It
communicates with the LCD module by RS-485 bus. This module comprises 100BaseT Ethernet
interfaces, RS-485 communication interfaces, PPS/IRIG-B differential time synchronization
interface and RS-232 printing interface.
Modules with various combinations of memory and interface are available as shown in the table
Date: 2019-02-21
6 Hardware
below.
NR1102G NR1102M NR1102N NR1101F
TX TX ETHERNET
ETHERNET
RX RX
TX TX
RX RX
ETHERNET
TX
RX
Figure 6.4-3 View of MON plug-in module
Module ID Memory Interface Terminal No. Usage Physical Layer

3 FO Ethernet To SCADA Optical fiber ST
01 SYN+
02 SYN- To clock
RS-485 Twisted pair wire
03 SGND synchronization
NR1102G 256M DDR
04
05 RTS
RS-232 06 TXD To printer Cable
07 SGND
4 RJ45 Ethernet To SCADA
01 SYN+
02 SYN- To clock Twisted pair wire
RS-485
NR1102M 256M DDR
04
05 RTS
07 SGND
2 FO Ethernet To SCADA Optical fiber ST
NR1102N 256M DDR
01 SYN+ To clock
RS-485 Twisted pair wire
02 SYN- synchronization
Date: 2019-02-21
6 Hardware
03 SGND
04
05 RTS
07 SGND
01 A
02 B
RS-485 To SCADA
03 SGND
04
05 A
06 B Twisted pair wire
RS-485 To SCADA
07 SGND
NR1101F 256M DDR 08
09 SYN+
10 SYN- To clock
RS-485
12
13 RTS
15 SGND
16
The correct method of connection is shown in Figure 6.4-4. Generally, the shielded cables with two
pairs of twisted pairs inside shall be applied. One pair of the twisted pairs is used to connect the “+”
and “–” terminals of difference signal; the other is used to connect the signal ground of the
interface, i.e. connect the signal groundings of all the devices to a bus through the twisted pair.
The module reserves a free terminal for all the communication ports; the free terminal does not
need to be connected.
Twisted pair wire

A 01
B 02
COM
cable with single point earthing
To the screen of other coaxial
SGND 03
04
Twisted pair wire

SYN+ 01
CLOCK SYN
SYN- 02
SGND 03
04
Twisted pair wire

RTS 05
PRINT
TXD 06
SGND 07
Figure 6.4-4 Wiring of communication interface
Date: 2019-02-21
6 Hardware
CAUTION!
Do NOT look into the end of an optical fiber connected to an optical port.
Do NOT look into an optical port/connector.
A direct sight to laser light may cause temporary or permanent blindness.
6.4.4 DSP Module 1 (Protection Calculation)

The DSP Module 1 consists of high-performance digital signal processor and other peripherals.
The functions of this module include analog data acquisition, calculation of protection logic and
tripping output etc.
6.4.5 DSP Module 2 (Fault Detector Calculation)

The DSP Module 2 consists of high-performance digital signal processor and other peripherals.
The functions of this module include analog data acquisition, calculation of fault detector elements
and providing positive power supply to output relay.
DSP module 1 and DSP module 2 have the same hardware configuration and are located in slot
02 and slot 03 respectively. The following figure shows rear view and terminal definition for the
DSP module.
NR1156D
1 2 3
4 5 6
Figure 6.4-5 Rear view of DSP module
6.4.6 BI Module (Binary Input)

There are two kinds of BI modules available, NR1503 and NR1504. Up to 2 BI modules can be
Date: 2019-02-21
6 Hardware
equipped with one device. The rated voltage can be selected to be 110V, 125V, 220V and 250V.
The well-designed debouncing technique is adopted in this device, and the state change of binary
input within “Debouncing time” will be ignored. As shown in Figure 6.4-6.
Figure 6.4-6 Debouncing technique
Each BI module is with a 22-pin connector for 11 binary inputs (NR1503) or 18 binary inputs
(NR1504).
For NR1503, each binary input has independent negative power input of opto-coupler, and can be
configurable. The terminal definition of the connector of BI plug-in module is described as below.
[BI_n] (n=01, 02,…,11 can be configured as a specified binary input by PCS-Explorer2 software.)
BI_01 01
NR1503 Opto01- 02
BI_02 03
Opto02- 04
BI_03 05
Opto03- 06
BI_04 07
Opto04- 08
BI_05 09
Opto05- 10
BI_06 11
Opto06- 12
BI_07 13
Opto07- 14
BI_08 15
Opto08- 16
BI_09 17
Opto09- 18
BI_10 19
Opto10- 20
BI_11 21
Opto11- 22
Figure 6.4-7 View of BI plug-in module (NR1503)
Terminal description for NR 1503 is shown as follows.
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01 BI_01 Configurable binary input 1
02 Opto01- Negative supply of configurable binary input 1
For NR1504, all binary inputs share one common negative power input, and is configurable. The
terminal definition of the connector of BI plug-in module is described as below. [BI_n] (n=01,
02,…,19 can be configured as a specified binary input by PCS-Explorer2 software.)
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BI_01 01
NR1504 BI_02 02
BI_03 03
BI_04 04
BI_05 05
BI_06 06
BI_07 07
08
BI_08 09
BI_09 10
BI_10 11
BI_11 12
BI_12 13
BI_13 14
15
BI_14 16
BI_15 17
BI_16 18
BI_17 19
BI_18 20
BI_19 21
COM- 22
Figure 6.4-8 View of BI plug-in module (NR1504)
Terminal description for NR1504 is shown as follows.

01 BI_01 Positive supply of power supply of the module
08 Blank Not used
15 Blank Not used
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6 Hardware

22 COM- Common terminal of negative supply of binary inputs
A default configuration is given for first four binary signals (BI_02, BI_03, BI_04, BI_05) of the first
BI plug-in module (located in slot No.09), and they are, [BI_TimeSyn], [BI_Print], [BI_Maintenance]
and [BI_RstTarg] respectively. They can also be configured as other signals. Because the first
binary signal [BI_02] is set as [BI_TimeSyn] by default (the state change information of binary
signal [BI_TimeSyn] does not need be displayed), new binary signal should be added to state
change message if it is set as other signal.
1. Binary input: [BI_TimeSyn]
It is used to receive clock synchronization signal from clock synchronization device, the binary
input [BI_TimeSyn] will change from “0” to “1” once pulse signal is received. When the device
adopts “Conventional” mode as clock synchronization mode (refer to section “Communication
Settings”), the device can receives PPM (pulse per minute) and PPS (pulse per second). If the
setting [Opt_TimeSyn] is set as other values, this binary input is invalid.
2. Binary input: [BI_Print]
It is used to manually trigger printing latest report when the equipment is configured as manual
printing mode by logic setting [En_AutoPrint]=0. The printer button is located on the panel usually.
If the equipment is configured as automatic printing mode ([En_AutoPrint] =1), report will be
printed automatically as soon as it is formed.
3. Binary input: [BI_Maintenance]
It is used to block communication export when this binary input is energized. During device
maintenance or testing, this binary input is then energized not to send reports via communication
port, local display and printing still work as usual. This binary input should be de-energized when
the device is restored back to normal.
4. Binary input: [BI_RstTarg]
It is used to reset latching signal relay and LCD displaying. The reset is done by pressing a button
on the panel.
NOTICE!
The rated voltage of binary input is optional: 110V, 125V, 220V or 250V, which MUST be
specified when placing an order. It is necessary to CHECK whether the rated voltage of
BI module complies with site DC supply rating before put the relay in service.
6.4.7 BO Module (Binary Output)

6.4.7.1 Tripping Output Module (NR1521)
Two standard binary output modules, NR1521A, and NR1521H, can be selected. Output contact
can be configured as a specified tripping output contact by PCS-Explorer2 software according to
user requirement.
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6 Hardware
Up to two tripping output modules (located in slot 11 and 15 respectively) can be equipped with
one device.
The details of the BO modules are as follows:
 NR1521A
NR1521A can provide 11 output contacts controlled by fault detector.
01
BO_Trip_01
NR1521A 02
03
BO_Trip_02
04
05
BO_Trip_03
06
07
BO_Trip_04
08
09
BO_Trip_05
10
11
BO_Trip_06
12
13
BO_Trip_07
14
15
BO_Trip_08
16
17
BO_Trip_09
18
19
BO_Trip_10
20
21
BO_Trip_11
22
Figure 6.4-9 View of BO plug-in module (NR1521A)
 NR1521H
NR1521H can provide 11 output contacts controlled by fault detector. The first four output contacts
are in parallel with instantaneous operating contacts which are recommended to be configured as
fast signaling contacts.
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01
BO_Trip_01
NR1521H 02
03
BO_Trip_02
04
05
BO_Trip_03
06
07
BO_Trip_04
08
09
BO_Trip_05
10
11
BO_Trip_06
12
13
BO_Trip_07
14
15
BO_Trip_08
16
17
BO_Trip_09
18
19
BO_Trip_10
20
21
BO_Trip_11
22
Figure 6.4-10 View of BO plug-in module (NR1521H)
6.4.7.2 Signal Output Module
Four standard binary output modules, NR1523A, NR1523B, NR1523C, and NR1523D, can be
selected to provide protection operation signal and abnormality alarm signal.
Up to three signal output modules (located in slot 12, 13 and 15 respectively) can be equipped
with one device.
The details of the BO modules are as follows:
 NR1523A
The NR1523A module is a standard binary output module for signal, which can provide 8 signal
relays (11 signal output contacts, for the first three signal output relays, each relay includes two
contacts) without controlled by fault detector. All the contacts are normally open (NO) contacts,
and among which, [BO_Signal_6], [BO_Signal_7] and [BO_Siganl_8] are magnetic latched NO
contacts.
All contacts of the module can be configured as specified signal output contacts of certain
protections by PCS-Explorer2 software according to users’ requirement. [BO_Signal_4] and
[BO_Siganl_5] are recommended to be configured as alarm signal output contacts, other contacts
are recommended to be configured as tripping signal output contacts.
A 22-pin connector is fixed on the front of this module. The pin definition of the connector is
described as below.
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NR1523A
NR1523A
01 01
BO_Signal_1-1 BO_Signal_1-1
02 02
03 03
04 04
05 05
06 06
07 07
08 08
09 09
10 10
11 11
12 12
13 13
BO_Signal_4 BO_Signal_4
14 14
15 15
16
16
17 17
18
18
19 19
20 20
21 21
22 22
Figure 6.4-11 Pin definition of signal output module NR1523A
 NR1523B
The NR1523B module is a standard binary output module for signal, which can provide 11 signal
output contacts without controlled by fault detector. Among those contacts, [BO_Signal_5] and
[BO_Siganl_6] are normally closed (NC) contacts, others are normally open (NO) contacts. All
contacts of the module can be configured as specified signal output contacts of some protections
by PCS-Explorer2 software according to user requirement. Besides, only the contact
[BO_Siganl_8] is a magnetic latched NO contact.
described as below.
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NR1523B
NR1523B
01 01
02 02
03 03
04 04
05 05
06 06
07 07
08 08
09 09
10 10
11 11
12 12
13 13
14 14
15 15
16 16
17 17
18 18
19 19
20 20
21 21
22 22
Figure 6.4-12 Pin definition of signal output module NR1523B
 NR1523C
The NR1523C module is a standard binary output module for signal, which can provide 11 signal
output contacts without controlled by fault detector. Among those contacts, [BO_Signal_3-2],
[BO_Signal_5] and [BO_Siganl_7] are normally closed (NC) contacts, others are normally open
(NO) contacts. All contacts of the module can be configured as specified signal output contacts of
some protections by PCS-Explorer2 software according to user requirement.
described as below.
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NR1523C
NR1523C
01 01
02 02
03 03
04 04
05 05
06 06
07 07
08 08
09 09
10 10
11 11
12 12
13 13
14 14
15 15
16 16
17 17
18 18
19 19
20 20
21 21
22 22
Figure 6.4-13 Pin definition of signal output module NR1523C
 NR1523D
The NR1523D module is a standard binary output module for signal, which can provide 11 signal
output contacts without controlled by fault detector. All the contacts are normally open (NO), and
among which, only [BO_Siganl_8] is magnetic latched NO contact. All contacts of the module can
be configured as specified signal output contacts of certain protections by PCS-Explorer2 software
according to users’ requirement.
described as below.
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NR1523D
NR1523D
01 01
02 02
03 03
04 04
05 05
06 06
07 07
08 08
09 09
10 10
11 11
12 12
13 13
14 14
15 15
16
16
17 17
18
18
19 19
20 20
21 21
22 22
Figure 6.4-14 Pin definition of signal output module NR1523D
6.4.8 Mechanical Signal Input and Output Module (MR module)
NR1536A (220Vdc) and NR1536B (110Vdc/125V) are input and output modules (IO module) for
mechanical protection.
At most two MR modules can be equipped located in slot 10 and 14.
described as below.
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NR1536A NR1536B
MR IO Module x (NR1536A/B)
0601 Reset Signal ResetInput
0602 MRx.Input1
High Voltage
Binary Input
0603 Signals of MRx.Input2
Mechanical MRx.Input3
0604
protection
0605 MRx.Input4
0606 BO_MRx.Sig1_1
0607 BO_MRx.Sig2_1
0608 BO_MRx.Sig3_1
0609 BO_MRx.Sig4_1
0610 Common1
0611 BO_MRx.Sig1_2
0612 BO_MRx.Sig2_2
0613 BO_MRx.Sig3_2
0614 BO_MRx.Sig4_2
0615 Common2
0616 BO_MRx.Sig1_3
0617 BO_MRx.Sig2_3
0618 BO_MRx.Sig3_3
0619 BO_MRx.Sig4_3
0620 Common3
0621 Pwr+
Module Power Input
0622 Pwr -
Figure 6.4-15 Pin definition of mechanical relay IO module (x=1, 2)
Pin No. Symbol Description

Reset input, when a reset signal is issued, the corresponding magnetic latched
01 ResetInput
contacts of mechanical signals are reset.
Mechanical signal inputs
st
1 group output contacts (magnetic latched contact)
06-10 BO_MRx.Sig1_1 Output alarm signal contact 1 of channel 1 of mechanical protection x (NO contact).
nd
2 group output contacts
rd
3 group output contacts
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Pin No. Symbol Description

Power supply input of the module

21 Pwr+ Positive pole of power of the board connected to DC power supply
22 Pwr- Negative pole of power of the board connected to DC power supply
6.4.9 AI Module (Analog Input)
The analog input module is applicable for power plant with conventional VT and CT, the module is
not required if the device is used with ECT/EVT. The analog input module can transform these
high AC input values to relevant low AC output value for the DSP module. The transformers are
used both to step-down the currents and voltages to levels appropriate to the electronic circuitry of
this device and to provide effective isolation between this device and the power system. A low
pass filter circuit is connected to each transformer (CT or VT) secondary circuit for reducing the
noise of each analog AC input signal.
NOTICE!
The rated value of the input current transformer is optional: 1A or 5A. The rated value of
the CT MUST be definitely declared in the technical scheme and the contract.
Maximum linear range of the current converter is 40In.
Because the rated value of the input current transformer is optional, it is necessary to
CHECK whether the rated values of the current transformer inputs are accordant to the
demand of the engineering before putting the device into operation.
For AI module, if the plug is not put in the socket, external CT circuit is closed itself. It is shown as
below.
Plug
Socket
In
Out
plug is not put in the socket
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6 Hardware
In
Out
Put the plug in the socket
Figure 6.4-16 Schematic diagram of CT circuit automatically closed
The analog input module NR1401 can provide 12-channel analog signal inputs and each channel
can be configured as a specified current or voltage channel by PCS-Explorer2 software according
to user requirements. Up to two NR1401 modules can be configured for the device. Three kinds of
AI modules can be used for PCS-985GE:
1) 12I-A: 12-channel current AI module, all current channels are for protection;
2) 12I-D: 12-channel current AI module, the first 9 current channels are for protection and the
last 3 current channels for metering.
3) 9I3U: 9-channel current and 3-channel voltage AI module, the rated voltages of all voltage
channels are 100~130V.
4) 6I6U-I: 6-channel current and 6-channel voltage AI module. It includes 4 current channels for
protection, one high sensitive current channel and one current channel for metering. And the
rated voltages of all voltage channels are 100~130V and the 5th current channel is for zero
sequence current inputting of zero sequence overcurrent protection of stator ground fault.
5) 6I6U-I: 6-channel current and 6-channel voltage AI module. It includes 4 current channels for
protection and two high sensitive current channels. And the rated voltages of all voltage
channels are 100~130V and the 5th current channel is for zero sequence current inputting of
directional stator ground fault protection.
The rated values of current inputs are selected at order.
described as below.
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6 Hardware
NR1401
NR1401 NR1401 NR1401 NR1401 NR1401
01 02 01 02
level current
I1 I1n 01 02 01 02 I1 I1n 01 02
level current
I1 I1n I1 I1n I1 I1n
Protection
Protection
input
input
I2 03 I2n 04 I2 03 I2n 04 I2 03 I2n 04 I2 03 I2n 04 I2 03 I2n 04
Protection level current input

#1
#1
#2
#2
#3
#3
I7 13 I7n 14 I7 13 I7n 14 I7 13 I7n 14 U1 13 U1n 14 U1 13 U1n 14
voltage input
voltage input
Measurement
voltage input
I10 19 I10n 20 I10 19 I10n 20 U1 19 U1n 20 19 20
level current
U4 U4n U4 19 U4n 20
input
I11 21 I11n 22 I11 21 I11n 22 U2 21 U2n 22 U5 21 U5n 22 U5 21 U5n 22
I12 23 I12n 24 I12 23 I12n 24 U3 23 U3n 24 U6 23 U6n 24 U6 23 U6n 24
12I-A 12I-D 9I3U 6I6U-I 6I6U-J

#1:Sensitive current input #1:Sensitive current input 1
#2:Measurement level current input #2:Sensitive current input 2
#3:Protection level current input #3:Protection level current input
Figure 6.4-17 Pin definition of AC analog output module
In above figure, I1~I12 and U1~U6 are polarity terminals of corresponding relevant current and
voltage inputs respectively. For the 9I3U 1401 module and 6I6U 1401 module, the rated voltage of
voltage channels is 100~130V.
If user needs other analog input configuration, please declare in the technical scheme and the
contract.
Following two figures shows the default terminal definition of the two NR1401 modules.
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6 Hardware
AI module 2 (1401T-6I6U-I)
0601
Three-phase current
Ia
input channel 5
0602
Ian
0603
Ib
0604
Ibn
AI module 1 (1401T-12I-D) 0605
Ic
0401 0606
Ia Icn
Three-phase current
input channel 1
0402 Ian
current
0607
Shaft
0403 Ib I
0404 0608 In
Ibn
0405 Ic
64S1 ROC
0406
Current
Icn 0609 I
0610 In
0407
Three-phase current
Ia
input channel 2
0408
Ian
Transverse
differential
current
0409 0611 I
Ib
0410 0612 In
Ibn
0411
Ic
0412 0613 Ua
Icn
Three-phase voltage
input channel 1
0614 Uan
0413 Ia 0615
Three-phase current
Ub
input channel 3
0414 Ian 0616 Ubn

0415 Ib 0617 Uc
0416 Ibn 0618 Ucn
0417 Ic
Generator Generator
0418
terminal
Icn 0619 3U0

VT1
0620 3U0n
(measurement level CT)
0419
Three-phase current
Ia
input channel 4
0420 Ian
neutral
0621
point
3U0
0421 Ib 0622
3U0n
0422 Ibn
0423 Ic
Generator
terminal
0623 3U0
VT2
0424 Icn
0624 3U0n
Figure 6.4-18 Default terminal definition 1 of two NR1401 modules
Three-phase current input channel 4 (AI module 1) can be used as the measurement level CT
input for power calculation (if the configuration setting [PowerCal.En_CT_Measmt] is set as “1”).
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6 Hardware
AI module 2 (1401T-6I6U-I)
0601
Three-phase current
Ia
input channel 4
0602
Ian
0603
Ib
0604
Ibn
AI module 1 (1401T-9I3U-A)
0605
Ic
0401 Ia 0606
Three-phase current
input channel 1 Icn
0402 Ian
0403 Ib
current
0607
Shaft
I
0404 Ibn 0608 In
0405 Ic
0406
64S1 ROC
Icn
Current
0609 I
0407 0610
Three-phase current
Ia In
input channel 2
0408
Ian
Transverse
differential
0409
Ib
current
0611 I
0410
Ibn 0612 In
0411
Ic
0412
Icn 0613 Ua
Three-phase voltage
input channel 1
0614 Uan
0413 Ia
Three-phase current
0615 Ub
input channel 3
0414 Ian
0616 Ubn
0415 Ib
0617 Uc
0416 Ibn
0618 Ucn
0417 Ic
0418
Icn
Generator Generator
terminal
0619 3U0
VT1
0620 3U0n
0419
Three-phase voltage
Ua
input channel 2
0420 Uan
neutral
0621
point
0421 Ub 3U0
0622
0422 Ubn 3U0n
0423 Uc
Generator
terminal
0424 Ucn 0623 3U0

VT2
0624 3U0n
Figure 6.4-19 Default terminal definition 2 of two NR1401 modules
Three-phase voltage input channel 2 (AI module 1) can be used as the second VT input for voltage
balance protection (if the generator system setting [60.En] is set as “1”).
The generator shaft overcurrent protection used CT is configured to pin 07-08 (high-sensitivity
CT1) of the AI module located in slot 06 by default.
6.4.10 Rotor Ground Fault Protection Input Module
The rotor ground fault protection input module NR1417 or NR1418 is generally located in slot 08.
For rotor ground fault protection with low-frequency square-wave voltage injection, NR1417
module should be selected. For Ping-Pang type rotor ground fault protection rotor earth-fault
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6 Hardware
protection with ping-pang type, NR1418 module should be selected.
described as below.
B08 NR1418 B08 NR1417

IR+ 01 IR+ 01
02 DC 02
DC Transducer
Transducer
input IR- 03 input IR- 03
04 04
Loss of UR2+ 05 UR2+ 05
excitation Rotor
06 06
protection used voltage
rotor voltage UR2- 07 UR2- 07
08 08
09 09
UR1+ 10 UOUT 10
11 11
12 Rotor 12
ground fault
13 13
element with
Ping-Pang type 14 low- 14
rotor ground RGND 15 frequency RGND 15
fault protection 16 square- 16
wave
TEST 17 TEST 17
voltage
18 injection 18
19 UIN+ 19
UR1- 20 20
21 UIN- 21
22 22
Figure 6.4-20 Rotor ground fault protection input module
In NR1417 module, UR2+ should be connected to positive pole of rotor winding, and UR2- should
be connected to negative pole of rotor winding. The rotor voltage is not only used for rotor low
voltage element of loss of excitation protection, it is also used to calculate the ground fault location
for rotor ground fault protection with low-frequency square-wave voltage injection. UOUT is the
input terminal of big power resistor (47kΩ). RGND is applied to connect the shaft of rotor winding.
TEST is the test terminal (the test resistor is 18kΩ). UIN+ and UIN- are applied to connect to the
external power supply, the external power supply can be 220V (NR1417E) or 110V (NR1417F)
(predetermined when ordering) DC power supply.
In NR1418 module, UR2+ should be connected to positive pole of rotor winding, and UR2- should
be connected to negative pole of rotor winding, the rotor voltage is used for rotor low voltage
element of loss of excitation protection. UR1+ and UR1- are the input terminals of big power
resistor (13.6kΩ), UR1+ and UR1- are connected to the positive and negative pole of rotor winding
respectively via the big power resistor. RGND is applied to connect the shaft of rotor winding.
TEST is the test terminal (the test resistor is 18kΩ).
6.4.11 HMI Module
The display panel consists of liquid crystal display module, keyboard, LED and ARM processor.
The functions of ARM processor include display control of the liquid crystal display module,
keyboard processing, and exchanging data with the CPU through serial port etc. The liquid crystal
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6 Hardware
display module is a high-performance grand liquid crystal panel with soft back lighting, which has a
user-friendly interface and an extensive display range.
Date: 2019-02-21
6 Hardware
Date: 2019-02-21
7 Settings
7 Settings
Table of Contents
7 Settings .............................................................................................. 7-a
7.1 Overview .......................................................................................................... 7-1
7.2 System Settings .............................................................................................. 7-1
7.2.1 Setting List ........................................................................................................................... 7-1
7.2.2 Access Path ......................................................................................................................... 7-1
7.3 Generator System Settings ............................................................................ 7-1

7.3.1 Setting List ........................................................................................................................... 7-1
7.3.2 Access Path ......................................................................................................................... 7-3
7.4 Excitation Transformer System Settings ...................................................... 7-3

7.4.1 Setting List ........................................................................................................................... 7-3
7.4.2 Access Path ......................................................................................................................... 7-3
7.5 Configuration Settings ................................................................................... 7-3

7.5.1 Setting List ........................................................................................................................... 7-4
7.5.2 Access Path ......................................................................................................................... 7-5
7.6 Device Setup Settings .................................................................................... 7-6

7.6.1 Device Settings .................................................................................................................... 7-6
7.6.2 Communication Settings ...................................................................................................... 7-7
7.6.3 Label Settings .....................................................................................................................7-11
7.7 Protection Settings ........................................................................................ 7-11
List of Tables
Table 7.2-1 List of system settings ............................................................................................ 7-1
Table 7.3-1 List of generator system settings .......................................................................... 7-1
Table 7.4-1 List of excitation transformer system settings .................................................... 7-3
Table 7.5-1 List of configuration settings ................................................................................. 7-4
Table 7.6-1 List of device settings ............................................................................................. 7-6
PCS-985GE Generator Protection 7-a

Date: 2016-08-16
7 Settings
Table 7.6-2 List of communication settings.............................................................................. 7-7
Table 7.6-3 List of label settings .............................................................................................. 7-11
7-b PCS-985GE Generator Protection
Date: 2016-08-16
7 Settings
7.1 Overview
Settings are classified into two kinds, protection settings and common settings. Each protection
element has its independent setting menu which are given detailed description in Chapter 3. In this
chapter only common settings are introduced. Common settings consist of device settings,
communication settings, label settings, system settings and configuration settings.
PCS-985GE has ten protection setting groups to coordinate with the different modes of power
system operation. One of these setting groups is assigned to be active. However, common
settings are shared by all protection setting groups, and settings of protection element are set
according to secondary values.
7.2 System Settings

7.2.1 Setting List
Table 7.2-1 List of system settings
No. Settings item Range Description
The number of active setting group, ten setting

1 Active_Grp 1~10 groups can be configured for protection settings, and
only one is active at a time.
2 Opt_SysFreq 0: 50Hz; 1: 60Hz Select system working frequency.
Name of the protected primary equipment, such as

3 PrimaryEquip_Name Max 20 characters
generator, transformer, etc.
7.2.2 Access Path
MainMenuSettingsSystem Settings
7.3 Generator System Settings

7.3.1 Setting List
Table 7.3-1 List of generator system settings

The active power capacity of generator, it shall be
1 Gen.Pn_Plate 0.1~2000.0(MW)
configured as the value stated in generator name plate.
2 Gen.PFn_Plate 0.01~1.00 Rated power factor of generator.
The rated primary voltage that stated in generator name
plate. This setting is used for calculating the rated
3 Gen.U1n_Plate 0.01~800.00(kV)
current of generator. It should be set according to the
real operating voltage of the power system.
4 G_Term.VT1.U1n 0.01~2000.00(kV) The primary rated voltage of VT1 of generator terminal.
The secondary rated voltage of VT1 of generator
5 G_Term.VT1.U2n 0.01~300.00(V)
terminal.
PCS-985GE Generator Protection 7-1

Date: 2016-08-16
7 Settings
The secondary rated broken-delta voltage of VT1 of

6 G_Term.VT1.U2n_Delt 0.01~300.00(V)
generator terminal.
7 G_Term.VT2.U1n 0.01~2000.00(kV) The primary rated voltage of VT2 of generator terminal.
The secondary rated voltage of VT2 of generator
8 G_Term.VT2.U2n 0.01~300.00(V)
terminal.
The secondary rated broken-delta voltage of VT2 of
9 G_Term.VT2.U2n_Delt 0.01~300.00(V)
generator terminal.
Rated primary voltage of VT at the neutral point of
10 G_NP.U1n 0.01~2000.00(kV)
generator.
Rated secondary voltage of VT at the neutral point of
11 G_NP.U2n_Delt 0.01~300.00(V)
generator.
12 G_Term.I1n 0~60000(A) The primary rated current of CT of generator terminal.
The secondary rated current of CT of generator
13 G_Term.I2n 1A/5A
terminal.
The primary rated current of CT of generator neutral
14 G_NP.I1n 0~60000(A)
point.
The secondary rated current of CT of generator neutral
15 G_NP.I2n 1A/5A
point.
The primary rated current of CT used for generator
16 G_Bak.I1n 0~60000(A)
backup protection.
The secondary rated current of CT used for generator
17 G_Bak.I2n 1A/5A
backup protection.
The primary rated current of CT used for power
18 32.I1n 0~60000(A)
protection.
The secondary rated current of CT used for power
19 32.I2n 1A/5A
protection.
The primary rated current of CT used for neutral point
20 87NTG.I1n 0~60000(A)
transverse differential protection.
The secondary rated current of CT used for neutral
21 87NTG.I2n 1A/5A
point transverse differential protection.
Correction coefficient of rotor voltage. For the occasion
that partial rotor voltage is connected to the device,
rotor voltage need to be corrected by the setting. For
22 K_U_Rot 0.00~20.00 example, if only one quarter of rotor voltage is
connected to the device, this setting should be set as
“4”, if total rotor voltage is connected to the device, this
setting should be set as “1”.
Logic setting indicating whether a circuit breaker is
23 En_GCB 0/1
equipped at generator terminal.
Wiring mode selection of HV side of main transformer:
0: DblBus
24 Opt_Conn_Tr 0: double-busbars wiring
1: 3/2BusCB
1: 3/2 breakers wiring
25 60.En 0: disable Logic setting of enabling/disabling voltage balance
7-2 PCS-985GE Generator Protection
Date: 2016-08-16
7 Settings
1: enable protection
7.3.2 Access Path
MainMenuSettingsGen Sys Settings
7.4 Excitation Transformer System Settings

7.4.1 Setting List
Table 7.4-1 List of excitation transformer system settings

The rated capacity of excitation transformer, it shall be
1 ET.Sn_Plate 0.01~2000.00(MVA) configured as the value stated in excitation transformer
name plate.
The rated primary voltage of side 1 that stated in
excitation transformer name plate. This setting is used
2 ET_S1.U1n_Plate 0.01~2000.00(kV)
to calculate the rated current of side 1 of excitation
transformer.
The rated primary voltage of side 2 that stated in
excitation transformer name plate. This setting is used
3 ET_S2.U1n_Plate 0.01~2000.00(kV)
to calculate the rated current of side 2 of excitation
transformer.
The relative o’clock for excitation transformer side 2
4 ET_S2.Clk_WRT_S1 0~11(clk) winding relative to excitation transformer side 1
winding.
The primary rated current of CT of side 1 of excitation
5 ET_S1.I1n 0~60000(A)
transformer.
The secondary rated current of CT of side 1 of
6 ET_S1.I2n 1A/5A
The primary rated current of CT of side 2 of excitation
7 ET_S2.I1n 0~60000(A)
transformer.
The secondary rated current of CT of side 2 of
8 ET_S2.I2n 1A/5A
0: Wye The winding connection mode of side 1 of excitation
9 ET_S1.WdgConn
1: Delta transformer.
0: Wye The winding connection mode of side 2 of excitation
10 ET_S2.WdgConn
1: Delta transformer.
7.4.2 Access Path
MainMenuSettingsExc Sys Settings
7.5 Configuration Settings

Configuration settings are associated with application-specific primary layout of generator and

Date: 2016-08-16
7 Settings
excitation transformer, tripping logics. Configuration settings are usually configured in factory or
configured by field commission engineer according to the design drawing and project requirement.
Modifying configuration settings need special warrant to input the special password.
7.5.1 Setting List

Table 7.5-1 List of configuration settings

Logic setting to configure which output relays will
delay drop-off since corresponding tripping signal
drop-off. If any bit is set as “1”, the corresponding
1 Cfg_DDO_TrpOut 0-3FFFFFFF
output relay will delay drop-off since corresponding
tripping signal drop-off. DDO (delay drop-off) time is
decided by [t_Ext_TrpOut].
DDO (delay drop-off) time of tripping output relays,
2 t_DDO_TrpOut 0.00~0.45(s)
its default value is 140ms.
Reverse the polarity direction of generator terminal
CT. Its default value is “0” and it should be set as “1”
if the polarity direction of generator terminal CT on
3 G_Term.En_RevCT 0/1 site is reversed due to incorrect wiring connecting,
then the program will reverse the generator terminal
current polarity before calculation. The following
eight settings are similar to it.
Reverse the polarity direction of generator neutral
4 G_NP.En_RevCT 0/1
point CT.
Reverse the polarity direction of CT of generator
5 G_Bak.En_RevCT 0/1
backup protection.
Reverse the polarity direction of CT of power
6 32.En_RevCT 0/1
protection.
Reverse the polarity direction of CT of side 1 of
7 ET_S1.En_RevCT 0/1
Reverse the polarity direction of CT of side 2 of
8 ET_S2.En_RevCT 0/1
Logic setting to decide whether measurement level
9 PowerCal.En_CT_Measmt 0/1
CT is adopted for power calculation.
The neutral line failure judge coefficient for VT1 of
10 G_Term.VT1.K_VTNS 0.10~1.00
generator terminal. The default value is 0.2.
Logic setting of enabling/disabling neutral line failure
11 G_Term.VT1.En_VTNS 0/1
supervision for VT1 of generator terminal.
The neutral line failure judge coefficient for VT2 of
12 G_Term.VT2.K_VTNS 0.10~1.00
generator terminal. The default value is 0.2.
Logic setting of enabling/disabling neutral line failure
13 G_Term.VT2.En_VTNS 0/1
supervision for VT2 of generator terminal.
14 G_Term.VT1.Opt_3U0 0/1 Logic setting to decide calculated or measured
Date: 2016-08-16
7 Settings
residual voltage is adopted for VT1 of generator

terminal.
0: measured residual voltage
1: calculated residual voltage
The maximum permissive adjustment multiple of 3rd
harmonic differential stator ground fault element. If
15 64S2.Kmax_U_Hm3_Diff 3.00~6.00 the automatic tracking adjustment coefficient is
larger than it, 3rd harmonic differential stator ground
fault element will quit.
Rotor voltage fluctuation coefficient, it is used to
adjust the permissible rotor voltage fluctuation for
rotor ground fault protection. The permissible rotor
16 K_dU_Rot 0.05~0.30
voltage fluctuation is bigger if the coefficient is
bigger. Rotor ground fault protection will be blocked
if rotor voltage fluctuation is too big.
The upper limit of input voltage of the transducer, it
should be set according to the rotor voltage that
17 Umax_Rot_Transducer 0~4000(V) corresponds to 20mA signal. Please refer to Section
“Rotor Voltage Element” of loss of excitation
protection element in Chapter 3 for details.
The phase angle adjust setting for impedance
18 40G.phi_Z_Cr -10.00~10.00(deg)
element of loss of excitation protection.
Logic setting of enabling non-volatile memory for
accumulate duration of underfrequency protection.
19 81U.En_NVM_Accu 0/1 When it is set as “1”, the accumulate duration of
underfrequency protection will not be cleared even
when the device is not powered.
Logic setting of enabling non-volatile memory for
accumulate duration of overfrequency protection.
20 81O.En_NVM_Accu 0/1 When it is set as “1”, the accumulate duration of
overfrequency protection will not be cleared even
when the device is not powered.
7.5.2 Access Path
MainMenuSettingsConfig Settings

Date: 2016-08-16
7 Settings
7.6 Device Setup Settings

7.6.1 Device Settings
7.6.1.1 Setting List
Table 7.6-1 List of device settings
No. Setting Item Range Description
Select encoding format of header (HDR) file

1 HDR_EncodedMode GB18030, UTF-8 COMTRADE recording file. Default value is
“UTF-8”.
Select the caption language sent to SAS via

IEC103 protocol. Default value is 0.
2 Opt_Caption_103 0~2
0: Current language; 1: Fixed Chinese; 2: Fixed
English
Enable/disable moveable disk to realize the

3 En_MDisk 0, 1 backup and recovery function.
Default value is 0, and the function is reserved.
Voltage level of binary input for the module that

located in slot No.x. For high-voltage BI
0:24V, 1:48V
modules, 110V, 125V or 220V can be set
4 Bx.Un_BinaryInput 2:110V, 3:220V, 4: 30V,
according to the actual requirement. For
5: 125V
low-voltage BI modules, 24V, 30V or 48V can be
set according to the actual requirement.
7.6.1.2 Setting Description
1. [HDR_EncodedMode]
Default value of [HDR_EncodedMode] is 1 (i.e. UTF-8 code) and please set it to 0 (i.e. GB18030)
according to the special requirement.
2. [Opt_Caption_103]
0: the group caption of IEC103 protocol is in current language
1: the group caption of IEC103 protocol is in Chinese
2: the group caption of IEC103 protocol is in English
It is recommended to be set as “1” if the device communicate with SCADA in Chinese.
3. [En_MDisk]
1: Use moveable disk to realize the backup and recovery function.
0: Moveable disk will be disabled.
A moveable mdisk is implemented on the MON plug-in module to backup and restore programs,
settings and configurations.
Date: 2016-08-16
7 Settings
If MON plug-in module is broken, remove the mdisk and put it into a new MON plug-in module, use
the menu on HMI to restore the backup programs and configurations. If DSP plug-in module is
broken, after a new DSP plug-in module is installed, use the menu on HMI to restore the backup
programs and configurations. If the moveable mdisk is broken, after a new mdisk is installed on
the MON plug-in module, use the menu on HMI to back up the current programs and
configurations into the new mdisk.
The default setting is 0.
7.6.1.3 Access Path
MainMenuSettingsDevice SetupDevice Settings
7.6.2 Communication Settings

Table 7.6-2 List of communication settings
000.000.000.000~
1 IP_LAN1 IP address of Ethernet port 1.
255.255.255.255
000.000.000.000~
2 Mask_LAN1 Subnet mask of Ethernet port 1.
255.255.255.255
000.000.000.000~
255.255.255.255
000.000.000.000~
255.255.255.255
5 En_LAN2 0: disable, 1: enable Enable/disable the IP address of port 2.
000.000.000.000~
255.255.255.255
000.000.000.000~
255.255.255.255
000.000.000.000~
255.255.255.255
000.000.000.000~
255.255.255.255
000.000.000.000~
12 Gateway Gateway of router.
255.255.255.255
Enable/disable sending message in broadcast mode of

13 En_Broadcast1 0: disable, 1: enable
Ethernet port 1 via network. (IEC103).
14 En_Broadcast2 0: disable, 1: enable Enable/disable sending message in broadcast mode of

Date: 2016-08-16
7 Settings


17 Addr_Net_103 0~65535 Communication address of the network (IEC103).
Communication address between the protective device

18 Addr_RS485A 0~255
with the SCADA or RTU via RS-485 serial port 1.
4800,9600,19200,
19 Baud_RS485A 38400,57600,115200 Baud rate of rear RS-485 serial port 1.
(bps)
0: IEC103;
1: MODBUS;
20 Protocol_RS485A Communication protocol of rear RS-485 serial port 1.
2: DNP;
3: DLT645.
Communication address between the protective device

21 Addr_RS485B 0~255
with the SCADA or RTU via RS-485 serial port 2.
4800,9600,19200,
22 Baud_RS485B 38400,57600,115200 Baud rate of rear RS-485 serial port 2.
(bps)
0: IEC103;
1: MODBUS;
23 Protocol_RS485B Communication protocol of rear RS-485 serial port 2.
2: DNP;
3: DLT645.
Threshold value of sending measurement values to

24 Threshold_Measmt_Net 0.00~100.00(%) SCADA through IEC103 or IEC61850 protocol.
Default value: “1%”.
The time period when the equipment sends

25 Period_Measmt_Net 0~65535s measurement data to SCADA through IEC103 protocol.
Default value:”60”.
Select the format of measurement data sent to SCADA

26 Format_Measmt 0, 1
through IEC103 protocol.
4800,9600,19200,
27 Baud_Printer 38400,57600,115200 Baud rate of printer port.
(bps)
0: disable
28 En_AutoPrint Enable/disable automatic printing function.
1: enable
Conventional
29 Opt_TimeSyn Select the mode of time synchronization of equipment.
SAS
Date: 2016-08-16
7 Settings
Advanced
NoTimeSyn
000.000.000.000~ The address of the external SNTP clock synchronization

30 IP_Server_SNTP
255.255.255.255 server sending SNTP message to the equipment.
The address of the external SNTP clock synchronization

000.000.000.000~
31 IP_StandbyServer_SNTP standby server sending SNTP message to the
255.255.255.255
equipment.
The local time zone also refered to as the hour offset

32 OffsetHour_UTC -12~12hrs
hour from UTC .
33 OffsetMinute_UTC 0~60 The offset minute of local time from UTC.
34 IEDNAME The IED name defined in 61850 protocol.
The recorded waveform cycle number before triggering,

35 Num_Cyc_PreTrigDFR 0~140(cycle)
the default value is 3-cycle.
7.6.2.2 Setting Description
1. [En_LANx] (x= 2, 3, 4)
These setting are used to enable/disable IP addresses of Ethernet 2, 3 and 4 respectively. IP

address of Ethernet 1 is enabled fixedly.
“1”: enable the IP address of Ethernet port and the corresponding IP address setting is need to be
set.
“0”: disable the IP address of Ethernet port and the corresponding IP address setting is not need to
be set.
2. [En_Broadcast]
This setting is only used for IEC 103 protocol. If NR network IEC103 protocol is used, the setting
must be set as “1”.
0: the device does not send UDP messages through network;
1: the device sends UDP messages through network.
3. [Protocol_RS485x] (x=A, B)
The setting is used to select the communication protocol of rear RS-485 serial port x.
0: IEC 60870-5-103 protocol
1: Modbus protocol
2: DNP protocol
3: DLT645
4. [Format_Measmt]

Date: 2016-08-16
7 Settings
The setting is used to select the format of measurement data sent to SCADA through IEC103
protocol.
0: GDD data type through IEC103 protocol is 12;
1: GDD data type through IEC103 protocol is 7, i.e. 754 short real number of IEEE standard.
5. [En_AutoPrint]
If automatic print is required for disturbance report after protection operating, the setting should be
set as “1”.
6. [Opt_TimeSyn]
There are four selections for clock synchronization of device, each selection includes different time
clock synchronization signals shown in following table.
Item Description
PPS(RS-485): Pulse per second (PPS) via RS-485 differential level.
IRIG-B(RS-485): IRIG-B via RS-485 differential level.
Conventional
PPM(DIN): Pulse per minute (PPM) via the binary input [BI_TimeSyn].
PPS(DIN): Pulse per second (PPS) via the binary input [BI_TimeSyn].
SNTP(PTP): Unicast (point to point) SNTP mode via Ethernet network.
SAS SNTP(BC): Broadcast SNTP mode via Ethernet network.
Message (IEC103): Clock messages through IEC103 protocol.
IEEE1588: Clock message via IEEE1588.
Advanced IRIG-B(Fiber): IRIG-B via optical-fibre interface.
PPS(Fiber) PPS: Pulse per second (PPS) via optical-fibre interface.
When no time synchronization signal is connected to the equipment, please select
NoTimeSyn
this option and the alarm message [Alm_TimeSyn] will not be issued anymore.
“Conventional” mode and “SAS” mode are always be supported by device, but “Advanced” mode
is only supported when NET-DSP module is equipped. The alarm signal [Alm_TimeSyn] may be
issued to remind user loss of time synchronization signals.
1) When “SAS” is selected, if there is no conventional clock synchronization signal, the device
will not send the alarm signal [Alm_TimeSyn]. When “Conventional” mode is selected, if there
is no conventional clock synchronization signal, “SAS” mode will be enabled automatically
with the alarm signal [Alm_TimeSyn] being issued simultaneously.
2) When “Advanced” mode is selected, if there is no conventional clock synchronization signal

connected to NET-DSP module，“SAS” mode is enabled automatically with the alarm signal
[Alm_TimeSyn] being issued simultaneously.
3) When “NoTimeSyn” mode is selected, the device will not send alarm signals without time
synchronization signal. But the device can be still synchronized if receiving time
synchronization signal.
The clock message via IEC103 protocol is invalid when the device receives the IRIG-B signal
through RS-485 port.
Date: 2016-08-16
7 Settings
7. [IP_Server_SNTP]
It is the address of the SNTP time synchronization server which sends SNTP timing messages to
the relay or BCU.
8. OffsetHour_UTC, OffsetMinute_UTC
If the IEC61850 protocol is adopted in substations, the time tags of communication messages are
required according to UTC (Universal Time Coordinated) time.
The setting [OffsetHour_UTC] is used to set the hour offset of the current time zone to the GMT
(Greenwich Mean Time) zone; for example, if a relay is applied in China, the time zone of China is
east 8th time zone, so this setting is set as “8”. The setting [OffsetMinute_UTC] is used to set the
minute offset of the current time zone to the GMT zone.
st nd rd th th
Time zone GMT zone East 1 East 2 East 3 East 4 East 5
Setting 0 1 2 3 4 5
th th th th th
Time zone East 6 East 7 East 8 East 9 East 10 East 11th
Setting 6 7 8 9 10 11
th st nd rd th
Time zone East/West 12 West 1 West 2 West 3 West 4 West 5th
Setting -12/12 -1 -2 -3 -4 -5
th th th th th
Time zone West 6 West 7 West 8 West 9 West 10 West 11th
Setting -6 -7 -8 -9 -10 -11
7.6.2.3 Access Path
MainMenuSettingsDevice SetupComm Settings
7.6.3 Label Settings

Label settings are used to definite the label of each tripping output. Label settings will not affect
protection logics and it will only affect the displayed names of corresponding tripping output on
LCD, PCS-Explorer2 software etc.
Table 7.6-3 List of label settings
No. Setting Item Description
1 Name_TrpOutpx (x=1~29) Label settings of tripping output x
7.6.3.2 Access Path
MainMenuSettingsDevice SetupLabel Settings
7.7 Protection Settings

All the protection settings have be given in Section “Settings” of each protection element in
Chapter 3.

Date: 2016-08-16
7 Settings
Date: 2016-08-16
Table of Contents
8.1 Overview .......................................................................................... 8-1
8.1.1 Keypad Operation................................................................................................................. 8-2
8.1.2 LED Indications .................................................................................................................... 8-3
8.1.3 Front Communication Port ................................................................................................... 8-3
8.1.4 Ethernet Port Setup .............................................................................................................. 8-4
8.2 Understand the HMI Menu Tree ..................................................... 8-5
8.2.1 Overview ............................................................................................................................... 8-5
8.2.2 Measurements ...................................................................................................................... 8-8
8.2.3 Status .................................................................................................................................. 8-10
8.2.4 Records .............................................................................................................................. 8-11
8.2.5 Settings ............................................................................................................................... 8-11
8.2.6 Print .................................................................................................................................... 8-13
8.2.7 Local Cmd .......................................................................................................................... 8-15
8.2.8 Information.......................................................................................................................... 8-16
8.2.9 Test ..................................................................................................................................... 8-16
8.2.10 Clock ................................................................................................................................. 8-17
8.2.11 Language .......................................................................................................................... 8-17
8.3 Understand the LCD Display ....................................................... 8-17
8.3.1 Overview ............................................................................................................................. 8-17
8.3.2 Display during Normal Operation ....................................................................................... 8-17
8.3.3 Display When Tripping ....................................................................................................... 8-18
8.3.4 Display under Abnormal Condition ..................................................................................... 8-20
8.3.5 Display When Binary State Changes ................................................................................. 8-20
Date: 2016-08-16
8.3.6 Display Device Logs ........................................................................................................... 8-23
8.4 Keypad Operation ......................................................................... 8-24
8.4.1 View Device Analog ............................................................................................................ 8-24
8.4.2 View Device Status ............................................................................................................. 8-24
8.4.3 View Device Records ......................................................................................................... 8-24
8.4.4 View Device Setting ........................................................................................................... 8-25
8.4.5 Print Device Records.......................................................................................................... 8-25
8.4.6 Modify Device Setting......................................................................................................... 8-26
8.4.7 Copy Device Setting ........................................................................................................... 8-29
8.4.8 Switch Setting Group.......................................................................................................... 8-29
8.4.9 Delete Records ................................................................................................................... 8-30
8.4.10 Modify Device Clock ......................................................................................................... 8-31
8.4.11 Check Software Version ................................................................................................... 8-32
8.4.12 View Module Information .................................................................................................. 8-32
8.4.13 Select Language .............................................................................................................. 8-32
List of Figures
Figure 8.1-1 Front panel of the device ...................................................................................... 8-1
Figure 8.1-2 Keypad mounted on the front panel .................................................................... 8-2
Figure 8.1-3 LED indications ...................................................................................................... 8-3
Figure 8.1-4 Corresponding cable of the RJ45 port in the front panel .................................. 8-4
Figure 8.1-5 Rear view and terminal definition of NR1102M .................................................. 8-5
Figure 8.2-1 Tree diagram of total command menu ................................................................ 8-7
Figure 8.3-1 LCD display of single line diagram .................................................................... 8-18
Figure 8.3-2 LCD display 1 of trip report ................................................................................ 8-18
Figure 8.3-3 LCD display 2 of trip report and alarm report ................................................... 8-20
Figure 8.3-4 LCD display of alarm report ................................................................................ 8-20
Figure 8.3-5 Display of binary change report ......................................................................... 8-21
Figure 8.3-6 Display of control report ..................................................................................... 8-23
Date: 2016-08-16
Figure 8.4-1 Display of inputting password ........................................................................... 8-27
Figure 8.4-2 Display 1 of modifying settings.......................................................................... 8-28
Figure 8.4-3 Display 2 of modifying settings.......................................................................... 8-28
Figure 8.4-4 Display of copy settings...................................................................................... 8-29
Figure 8.4-5 Display of switching setting group .................................................................... 8-30
Figure 8.4-6 Display of deleting report.................................................................................... 8-31
Figure 8.4-7 Display of modifying clock ................................................................................. 8-31
Figure 8.4-8 Display of selecting language ............................................................................ 8-33
List of Tables
Table 8.1-1 Definition of the 8-core cable ................................................................................. 8-4
Table 8.3-1 Tripping reports related to oscillography ........................................................... 8-19
Table 8.3-2 Contact inputs list ................................................................................................. 8-21
Table 8.3-3 Contact outputs list ............................................................................................... 8-22
Table 8.3-4 User Operating event list ...................................................................................... 8-23
Date: 2016-08-16
Date: 2016-08-16
The operator can access the protective device from the front panel. Local communication with the
protective device is possible using a computer via a multiplex RJ45 port on the front panel.
Furthermore, remote communication is also possible using a PC with the substation automation
system via rear RS485 port or rear Ethernet port. The operator is able to check the protective
device status at any time.
This chapter describes human machine interface (HMI), and give operator an instruction about
how to display or print event report, setting and so on through HMI menu tree and display metering
value, including RMS current, voltage and frequency etc. through LCD. Procedures to change
active setting group or a settable parameter value through keypad are also described in details.
8.1 Overview
NOTICE!
The LCD interface in this chapter is ONLY a reference and available for explaining
specific definition of LCD. The displayed interface of the actual protection device may
be some DIFFERENT from it.
1 11
5
HEALTHY
2 12 PCS-985GE
ALARM
3
TRIP
13
GENERATOR RELAY
4 14
5 15
C GRP
6 16
7 17 ENT
ES
8 18
9 19 1
4
3
10 20
Figure 8.1-1 Front panel of the device
The function of HMI module:

A 320×240 dot matrix backlight LCD display is visible in dim lighting
1 LCD conditions. The corresponding messages are displayed when there is
operation implemented.
20 status indication LEDs, first three LEDs are fixed as the signals of
2 LED
“HEALTHY” , “ALARM” and “TRIP”, others are configurable.
3 Keypad Navigation keypad and command keys for full access to device
4 Communication port a multiplex RJ45 port for local communication with a PC
5 Logo Type and designation and manufacturer of device
Date: 2016-08-16
8.1.1 Keypad Operation

NOTICE!
Press “+”, “”, “”, “-“, “ENT” IN SEQUENCE to confirm the setting change and press
“+”, “-“, “+”, “-“, “ENT” IN SEQUENCE to execute the report deletion.
+
P
GR
ENT
ESC -
Figure 8.1-2 Keypad mounted on the front panel
1. “ESC”:
 Cancel the operation
 Quit the current menu
2. “ENT”:
 Execute the operation
 Confirm the interface
3. “GRP”
 Activate the switching interface of setting group
4. leftward and rightward direction keys (“◄” and “►”):
 Move the cursor horizontally
 Enter the next menu or return to the previous menu
5. upward and downward direction keys (“▲” and “▼”)
 Move the cursor vertically
 Select command menu within the same level of menu
6. plus and minus sign keys (“＋” and “－”)
 Modify the value
 Modify and display the message number
 Page up/down
Date: 2016-08-16
8.1.2 LED Indications

01 11
HEAL TH Y 01 HEALTHY
02 ALAR M 12
13 ALA RM
03
Recommended 02
04 14
05 15 03 TRIP
06 16
LED_03 is configured as shown in the right
07 17
side, and other LEDs (LED_04~LED_20)
08 18 are configured according to the practical
09 19 requirement through the PCS-Explorer2
10 20 software.
LED_03 ~ LED_ 20 are configurable
Figure 8.1-3 LED indications
A brief explanation has been made as bellow.
LED Display Description

When the device is out of service or any hardware error is defected during
Off
HEALTHY self-check.
Steady Green Lit when the device is in service and ready for operation.
Off When the device in normal operating condition.

ALARM
Steady Yellow Lit when VT circuit failure, CT circuit failure or other abnormal alarm is issued.
Off When the device in normal operating condition.

TRIP
Red Lit when any protection element trips.
“HEALTHY” LED can only be turned on by energizing the device and no abnormality detected.
“ALARM” LED is turned on when abnormalities of device occurs like above mentioned and can be
turned off after abnormalities are removed except CT circuit failure alarm signal which can only be
reset when the failure is removed and the device is rebooted or re-energized.
“TRIP” LED is turned on and latched once any protection element operates and can be turned off
by pressing the signal RESET button on the front panel.
Other LED indicators with no labels are configurable and user can configure them to be lit by
signals of operation element, alarm element and binary output contact according to requirement
through PCS-Explorer2 software, and there are three colors (green, yellow and red) for user
selection.
8.1.3 Front Communication Port

There is a multiplex RJ45 port on the front panel. This port can be used as an RS-232 serial port
as well as a twisted-pair Ethernet port. As shown in the following figure, a customized cable is
applied for debugging via this multiplex RJ45 port.
Date: 2016-08-16
P2
P1
P3
Figure 8.1-4 Corresponding cable of the RJ45 port in the front panel
In the above figure and the following table:
P1: To connect the multiplex RJ45 port. An 8-core cable is applied here.
P2: To connect the twisted-pair Ethernet port of the computer.
P3: To connect the RS-232 serial port of the computer.
The definition of the 8-core cable in the above figure is introduced in the following table.
Table 8.1-1 Definition of the 8-core cable
Terminal Device side Computer side

Core color Function
No. (Left) (Right)
1 Orange & white TX+ of the Ethernet port P1-1 P2-1
2 Orange TX- of the Ethernet port P1-2 P2-2
3 Green & white RX+ of the Ethernet port P1-3 P2-3
4 Blue TXD of the RS-232 serial port P1-4 P3-2
5 Brown & white RXD of the RS-232 serial port P1-5 P3-3
6 Green RX- for the Ethernet port P1-6 P2-6
7 Blue & white P1-7
The ground connection of the RS-232 port. P3-5
8 Brown P1-8
8.1.4 Ethernet Port Setup
MON plug-in module is equipped with two or four 100Base-TX Ethernet interface, takes NR1102M
as an example, its rear view and the definition of terminals is shown in Figure 8.1-5.
The Ethernet port can be used to communication with PC via auxiliary software (PCS-Explorer2)
after connecting the protection device with PC, so as to fulfill on-line function (please refer to the
instruction manual of PCS-Explorer2). At first, the connection between the protection device and
PC must be established. Through setting the IP address and subnet mask of corresponding
Ethernet interface in the menu “Settings→Device Setup→Comm Settings”, it should be ensured
that the protection device and PC are in the same network segment. For example, setting the IP
address and subnet mask of network A. (using network A to connect with PC)
PC: IP address is set as “198.87.96.102”, subnet mask is set as “255.255.255.0”
Date: 2016-08-16
The IP address and subnet mask of protection device should be [IP_LAN1]= 198.87.96.XXX,
[Mask_LAN1]=255.255.255.0, [En_LAN1]=1. (XXX can be any value from 0 to 255 except 102)
If the logic setting [En_LAN1] is non-available, it means that network A is always enabled. If using
other Ethernet port, for example, Ethernet port B, the logic setting [En_LAN2] must be set as “1”.
NR1102M
ETHERNET
Network A
Network B
ETHERNET
Network C
Network D
SYN+
SYN-
SGND
RTS
TXD
SGND
Figure 8.1-5 Rear view and terminal definition of NR1102M
8.2 Understand the HMI Menu Tree
8.2.1 Overview
Pressing “▲” at any running interface can return to the main menu. Select different submenu by
“▲” and “▼”. Enter the selected submenu by pressing “ENT” or “►”. Press “◄” and return to the
previous menu. Press “ESC” and exit the main menu directly. For fast return to the command
menu, one command menu will be recorded in the quick menu after its first execution. Up to five
latest menu commands can be recorded in the quick menu by “first in first out” principle. It is
arranged from top to bottom and in accordance with the execution order of command menus.
Press “▲” to enter the main menu, the interface is shown in the following diagram:
Date: 2016-08-16
Quick Menu
Language
Clock
Device Settings
Mainmenu
If the protective device is powered for the first time, there is no recorded shortcut menu. Press “▲”
to enter the main menu with the interface as shown in the following diagram:
Measurements
Status
Records
Settings
Print
Local Cmd
Information
Test
Clock
Language
NOTICE!
The menu shown in following figure is NOT the specific-application menu. For each
project, the menu VARIES with the protection configuration.
Date: 2016-08-16
MAIN MENU
Measurements Records Print
Measurements 1 Disturb Records Device Info

Superv Events Settings
Gen Values
IO Events
System Settings
Gen Diff Values Device Logs
Gen Sys Settings
Gen Curr Values
Settings Exc Sys Settings
Gen Volt Values
Config Settings
Gen Misc Values System Settings
Prot Settings
Exc Values Gen Sys Settings
Exc Sys Settings Submenus same to those in the
Exc AC Values menu“Settings->Prot Settings”
Config Settings
Measurements 2 Prot Settings Device Setup
Gen Diff Settings Submenus same to those in the

Gen Values menu“Settings->Device Setup”
Gen IntTurn Settings
Gen Diff Values
Gen NPTrvDiff Settings All Settings
Gen Curr Values
Gen OC Settings Latest Chgd Settings
Gen Volt Values
Gen Impedance Settings Disturb Records
Gen Misc Values
Gen ROVStaEF Settings Superv Events
Exc Values Gen Hm3StaEF Settings IO Events
Exc AC Values Gen SwitchRotEF Settings Device Logs
Gen InjRotEF Settings Device Status
Phase Angle
Gen StaOvLd Settings Waveforms
Gen PhaseAngle Values Gen NegOC Settings
Gen Diff Wave
Exc PhaseAngle Values Gen ExcLoss Settings
Gen Curr Wave
Cal Param Display Gen OOS Settings
Gen Volt Wave
Gen OV Settings
Sec Rated Curr Values Gen Misc Wave
Gen UV Settings
Diff Corr Coef Values Exc Curr Wave
Gen OvExc Settings
Prot Values Gen RevPower Settings IEC103 Info
Gen FwdPower Settings Cancel Print

Misc Prot Values
Gen Diff Prot Values UnderFreq Settings Local Cmd
Gen IntTurn Prot Values OverFreq Settings
Reset Target
Gen PPF Prot Values Gen StShut Settings
Trig Oscillograph
Gen StaEF Prot Values Gen AccEnerg Settings
Download
Gen SwitchRot EF Prot Values Gen BFP Settings
Gen InjRotEF Prot Values Gen Shaft OC Settings Information
Gen ExcLoss Prot Values Exc Diff Settings

Version Info
Gen OOS Prot Values Exc OC Settings
Board Info
Gen Volt Prot Values Exc OvLd Settings
Test
Gen Power Prot Values MechRly Settings
Freq Prot Values Copy Settings Device Test
Gen StShut Prot Values Disturb Events

Gen AccEnerg Prot Values Device Setup
All Test
Exc Diff Prot Values Device Settings Select Test
Comm Settings
Superv Events
Status Label Settings
All Test
Inputs
Select Test
Contact Inputs
IO Events
Outputs All Test
Contact Outputs Select Test

Clock
FD Status Contact Outputs
Internal Signal
Language
DC Zero Adjust
Disturb Item
HMI Setup
BackLitDur
Contrast
SupervLCD
SupervLED
Figure 8.2-1 Tree diagram of total command menu
Under the main interface, press “▲” to enter the main menu, and select submenu by pressing “▲”,
Date: 2016-08-16
“▼” and “ENT”. The command menu adopts a tree shaped content structure. The above diagram
provides the integral structure and all the submenus under menu tree of the protection device.
8.2.2 Measurements
This menu is mainly used to display the real time sampling value of current, voltage and phase
angle. This menu and “Status” menu can fully reflects of the running environment of the protection
device. As long as the displayed values consist with the actual running situation, basically, the
protection device can work normally. This menu is set to greatly facilitate the debugging and
maintenance of people on site. Please refer to Section “Inputs and Outputs” of each protection
element about the detailed description of each sampled values.
The menu “Measurements” has following submenus.

1 Measurements 1 Display sampled and calculated values on protection DSP module.
2 Measurements 2 Display sampled and calculated values on fault detector DSP module.
8.2.2.1 Measurements1
The menu “Measurement1” has following submenus.

1 Gen Values Display the value of generator on protection DSP module.
2 Exc Values Display the value of excitation transformer on protection DSP module.
(1) The submenu “Gen Values” includes the following command menus.
Display magnitude of differential current and restraint current of current

1 Gen Diff Values
differential protection of generator on protection DSP module.
2 Gen Curr Values Display magnitude of AC current of generator on protection DSP module.
3 Gen Volt Values Display magnitude of AC voltage of generator on protection DSP module.
Display other measured or calculated values of generator on protection

4 Gen Misc Values
DSP module.
(2) The submenu “Exc Values” includes the following command menus.
Display magnitude of differential current, restraint current and AC current

1 Exc AC Values
of excitation transformer on protection DSP module.
8.2.2.2 Measurements2
The menu “Measurements2” has following lower submenus.

1 Gen Values Display the value of generator on fault detector DSP module.
Date: 2016-08-16

2 Exc Values Display the value of excitation transformer on fault detector DSP module.
3 Phase Angle Display the value of phase angle on fault detector DSP module.
4 Cal Param Display Display the calculated values on fault detector DSP module.
5 Prot Values Display the values related with protection element.
(1) The submenu “Gen Values” includes the following command menus.
Display magnitude of differential current and restraint current of current

1 Gen Diff Values
differential protection of generator on fault detector DSP module.
Display magnitude of AC current of generator on fault detector DSP

2 Gen Curr Values
module.
Display magnitude of AC voltage of generator on fault detector DSP

3 Gen Volt Values
module.
Display other measured or calculated values of generator on fault

4 Gen Misc Values
detector DSP module.
(2) The submenu “Exc Values” includes the following command menus.
Display magnitude of differential current, restraint current and AC current

1 Exc AC Values
of excitation transformer on fault detector DSP module.
(3) The submenu “Phase Angle” includes the following command menus.
Display the phase angle values of generator protection on fault detector

1 Gen PhaseAngle Values
DSP module.
Display the phase angle values of excitation transformer protection on

2 Exc PhaseAngle Values
fault detector DSP module.
(4) The submenu “Cal Param Display” includes the following command menus.
Display the secondary current value for differential protection of generator

1 Sec Rated Curr Values
and excitation transformer.
Display the coefficients for current differential protection of generator and

2 Diff Corr Coef Values
(5) The submenu “Prot Values” includes the following command menus.
Display status values related to interconnection status element on fault

1 Misc Prot Values
Date: 2016-08-16
Display status values related to generator current differential protection

2 Gen Diff Prot Values
on fault detector DSP module.
Display status values related to generator inter-turn protection on fault

3 Gen IntTurn Prot Values
Display status values related to generator phase-to-phase fault protection

4 Gen PPF Prot Values
Display status values related to generator stator ground fault protection

5 Gen StaEF Prot Values
Display status values related to generator Ping-Pang type rotor ground

6 Gen SwitchRotEF Prot Values
fault protection on fault detector DSP module.
Display status values related to generator rotor ground fault protection

7 Gen InjRotEF Prot Values (with low-frequency square-wave voltage injection) on fault detector DSP
module.
Display status values related to loss of excitation protection on fault

8 Gen ExcLoss Prot Values
Display status values related to generator out-of-step protection on fault

9 Gen OOS Prot Values
Display status values related to generator voltage protection on fault

10 Gen Volt Prot Values
Display status values related to generator power protection on fault

11 Gen Power Prot Values
Display status values related to frequency protection on fault detector

12 Freq Prot Values
DSP module.
Display status values related to generator startup and shutdown

13 Gen StShut Prot Values
protection on fault detector DSP module.
Display status values related to inadvertent energization protection on

14 Gen AccEnerg Prot Values
fault detector DSP module.
Display status values related to excitation transformer current differential

15 Exc Diff Prot Values
protection on fault detector DSP module.
8.2.3 Status
This menu is mainly used to display the real time input signals and output signals of the device.
This menu and “Measurements” menu fully reflects the running environment of the protection
device. As long as the displayed signals are in accordance with the actual running situation,
basically, the protection device can work normally. This menu is set to greatly facilitate the
debugging and maintenance of people on site.
The menu “Status” has following submenus.

1 Inputs Display all input signal states
Date: 2016-08-16

2 Outputs Display all output signal states
8.2.3.1 Inputs
The menu “Inputs” has following submenus.

1 Contact Inputs Display states of binary inputs derived from opto-isolated channels
8.2.3.2 Outputs
The menu “Outputs” has following submenus.

1 Contact Outputs Display states of tripping output contacts
2 FD Status The operating flag of fault detector element of each protection element
8.2.4 Records
This menu is used to display all kinds of records, including the disturbance records, supervision
events, binary events and device logs, so that the operator can load to view and use as the
reference of analyzing accidents and repairing the device. All records are stored in non-volatile
memory, it can still record them even if it loses its power.
This menu includes the following command menus.
No. Item Function description

1 Disturb Records Display disturbance records of the device
2 Superv Events Display supervision events of the device
3 IO Events Display binary events of the device
4 Device Logs Display device logs of the device
8.2.5 Settings
This menu is used to browse, modify and set all settings including device setup parameters,
protection settings and system parameters etc. Moreover, it can also execute the setting copy
between different setting groups.
1 System Settings To display and modify the system settings
2 Gen Sys Settings To display and modify the system settings of generator protection.
To display and modify the system settings of excitation transformer

3 Exc Sys Settings
protection.
4 Config Settings To display and modify the configuration settings.
5 Prot Settings To display and modify the settings of each protection elements.
6 Device Setup To display and modify the settings related to device setup
Date: 2016-08-16
8.2.5.1 Prot Settings
The submenu “Prot Settings” includes the following command menus.
1 Gen Diff Settings To display and modify the settings of generator differential protection.
2 Gen IntTurn Settings To display and modify the settings of generator inter-turn protection.
To display and modify the settings of generator neutral point transverse

3 Gen NPTrvDiff Settings
To display and modify the settings of generator phase overcurrent

4 Gen OC Settings
protection.
5 Gen Impedance Settings To display and modify the settings of impedance protection.
To display and modify the settings of generator fundamental zero-sequence

6 Gen Hm1StaEF Settings
stator ground fault protection.
To display and modify the settings of generator 3rd harmonic stator ground
fault protection.
To display and modify the settings of generator Ping-Pang type rotor ground
8 Gen SwitchRotEF Settings
fault protection.
To display and modify the settings of generator rotor ground fault protection
9 Gen InjRotEF Settings
(with low-frequency square-wave voltage injection).
10 Gen StaOvLd Settings To display and modify the settings of generator stator overload protection.
To display and modify the settings of generator negative-sequence

11 Gen NegOC Settings
12 Gen ExcLoss Settings To display and modify the settings of loss of excitation protection.
13 Gen OOS Settings To display and modify the settings of generator out-of-step protection.
14 Gen OV Settings To display and modify the settings of phase overvoltage protection.
15 Gen UV Settings To display and modify the settings of undervoltage protection.
16 Gen OvExc Settings To display and modify the settings of overexcitation protection.
17 Gen RevPower Settings To display and modify the settings of generator reverse power protection.
To display and modify the settings of generator low forward power

18 Gen FwdPower Settings
protection.
19 UnderFreq Settings To display and modify the settings of underfrequency protection.
20 OverFreq Settings To display and modify the settings of overfrequency protection.
To display and modify the settings of generator startup and shutdown

21 Gen StShut Settings
protection.
22 Gen AccEnerg Settings To display and modify the settings of inadvertent energization protection.
23 Gen BFP Settings To display and modify the settings of breaker failure protection.
24 Gen Shaft OC Settings To display and modify the settings of generator shaft overcurrent protection.
25 Exc Diff Settings To display and modify the settings of excitation transformer current
Date: 2016-08-16
To display and modify the settings of excitation transformer overcurrent

26 Exc OC Settings
protection.
27 Exc OvLd Settings To display and modify the settings of rotor winding overload protection.
28 MechRly Settings To display and modify the settings of mechanical protection.
29 Copy Settings Copy setting between different setting groups.
8.2.5.2 Device Setup
The menu “Device Setup” has following submenus.
1 Device Settings To display and modify the device settings.
2 Comm Settings To display and modify the communication settings.
3 Label Settings To display and modify the label settings of the output signals.
8.2.6 Print
This menu is used for printing device description, setting, all kinds of records, waveform and
information related with 103 Protocol.
This menu includes the following command menus and submenus.
To print the description information of protective device including software

1 Device Info
version.
To print settings. It can print by different classifications as well as printing all

2 Settings settings of the device. Besides, it can also print out the latest modified
setting item.
3 Disturb Records To print tripping reports.
4 Superv Events To print self-check alarm and device operation abnormal alarm reports.
5 IO Events To print status change of binary signal.
6 Device Logs To print operation logs of the device.
To print present status of device, including measurement, signal status,

7 Device Status
settings, etc.
8 Waveforms To print recorded waveforms.
To print 103 protocol information, including function type (FUN), information

9 IEC103 Info serial number (INF), general classification service group number and
channel number (ACC).
10 Cancel Print To cancel the undergoing printing task.
Date: 2016-08-16
8.2.6.1 Settings
The menu “Settings” has following submenus.
1 System Settings To print the system settings
2 Gen Sys Settings To print the system settings of generator protection.
3 Exc Sys Settings To print the system settings of excitation transformer protection.
4 Config Settings To print the configuration settings.
5 Prot Settings To print the settings of each protection elements.
6 Device Setup To print the settings related to device setup
7 All Settings Print all settings included in “Settings” submenu
8 Latest Chgd Settings Print the latest modified settings
(1) The submenu “Prot Settings” includes the following command menus.
1 Gen Diff Settings To print the settings of differential protection of main transformer.
2 Gen IntTurn Settings To print the settings of generator inter-turn protection.
To print the settings of generator neutral point transverse differential

3 Gen NPTrvDiff Settings
protection.
4 Gen OC Settings To print the settings of generator phase overcurrent protection.
5 Gen Impedance Settings To print the settings of impedance protection.
To print the settings of generator fundamental zero-sequence voltage stator

6 Gen ROVStaEF Settings
To print the settings of generator 3rd harmonic stator ground fault

protection.
To print the settings of generator Ping-Pang type rotor ground fault

8 Gen SwitchRotEF Settings
protection.
To print the settings of generator rotor ground fault protection (with

9 Gen InjRotEF Settings
low-frequency square-wave voltage injection).
10 Gen StaOvLd Settings To print the settings of generator stator overload protection.
11 Gen NegOC Settings To print the settings of generator negative-sequence overload protection.
12 Gen ExcLoss Settings To print the settings of loss of excitation protection.
13 Gen OOS Settings To print the settings of generator out-of-step protection.
14 Gen OV Settings To print the settings of phase overvoltage protection.
15 Gen UV Settings To print the settings of undervoltage protection.
16 Gen OvExc Settings To print the settings of overexcitation protection.
17 Gen RevPower Settings To print the settings of generator reverse power protection.
18 Gen FwdPower Settings To print the settings of generator low forward power protection.
Date: 2016-08-16
19 UnderFreq Settings To print the settings of underfrequency protection.
20 OverFreq Settings To print the settings of overfrequency protection.
21 Gen StShut Settings To print the settings of generator startup and shutdown protection.
22 Gen AccEnerg Settings To print the settings of inadvertent energization protection.
23 Gen BFP Settings To print the settings of breaker failure protection.
24 Gen Shaft OC Settings To print the settings of generator shaft overcurrent protection.
25 Exc Diff Settings To print the settings of excitation transformer current differential protection.
26 Exc OC Settings To print the settings of excitation transformer overcurrent protection.
27 Exc OvLd Settings To print the settings of rotor winding overload protection.
28 MechRly Settings To print the settings of mechanical protection.
29 All Settings Print all settings included in “Prot Settings” submenu
(2) The submenu “Device Setup” includes the following command menus.
1 Device Settings To print the device settings
2 Comm Settings To print the communication settings
3 Label Settings To print the label settings
(3) The menu “Waveforms” has following submenus.
To print the recorded current waveforms of generator current differential

1 Gen Diff Wave
protection.
2 Gen Curr Wave To print the recorded current waveforms of generator protection.
3 Gen Volt Wave To print the recorded voltage waveforms of generator protection.
4 Gen Misc Wave To print the recorded miscellaneous waveforms of generator protection.
To print the recorded current waveforms of excitation transformer

5 Exc Curr Wave
protection.
8.2.7 Local Cmd
This menu is used for resetting the tripping relay with latch, protection device signal lamp, LCD
display, as the same as the resetting function of binary input. Record the currently acquired
waveform data of the protection device under normal condition for printing and uploading SAS.
Besides, it can send out the request of program download.
1 Reset Target Reset the local signal, the signal indicator lamp and the LCD display
Date: 2016-08-16
2 Trig Oscillograph Trigger waveform recording
3 Download Send out the download request
8.2.8 Information
In this menu the LCD displays software information of DSP module, MON module and HMI module,
which consists of version, creating time of software, CRC codes and management sequence
number. Besides, hardware board information can also be viewed.
Display software information of DSP module, MON module and HMI

1 Version Info module, which consists of version, creating time of software, CRC codes
and management sequence number.
Monitor the current working state of each intelligent module of the

2 Board Info
equipment
8.2.9 Test
This menu is used for developers to debug the program and for engineers to maintain the device.
It can be used to check item fault message, and fulfill the communication test function. It is also
used to generate all kinds of report or event to transmit to the SAS without any external input, so
as to debug the communication on site.
This menu includes the following command menu.
Automatically generate all kinds of reports or events to transmit to SCADA,

including disturbance records, self-supervision events and binary events. It
1 Device Test
can realize the report uploading by different classification, as well as the
uploading of all kinds of reports.
2 Internal Signal Display some internal alarm or tripping signals.
3 DC_Zero_Adjust DC zero drift calibration.
4 Disturb Item Check the fault report one by one.
5 HMI Setup Test the LED and the LCD display.
(1) The menu “Device Test” has following submenus.
Generate protection element operation messages to transmit to SCADA

(only used for debugging persons). Users can respectively execute the test
1 Disturb Events
automatically or manually by selecting sub-commands “All Test” or “Select
Test”.
Generate alarm messages to transmit to SCADA (only used for debugging

2 Superv Events
persons). Users can respectively execute the test automatically or manually
Date: 2016-08-16
by selecting sub-commands “All Test” or “Select Test”.
Generate BI and BO events to transmit to SCADA (only used for debugging

3 IO Events persons). Users can respectively execute the test automatically or manually
by selecting sub-commands “All Test” or “Select Test”.
4 Contact Output To test the output contacts of the BO intelligent module.
(2) The menu “HMI Setup” has following submenus.
1 BacklitDur To set the backlighting duration of the LCD screen
2 Contrast To set the contrast of the LCD screen
3 SupervLCD To test the LCD screen.
4 SupervLED To test the LED indicators.
8.2.10 Clock
The current time of internal clock can be viewed here. The time is displayed in the form
YY-MM-DD and hh:mm:ss. All values are presented with digits and can be modified.
8.2.11 Language
This menu is mainly used for set LCD display language.
8.3 Understand the LCD Display
8.3.1 Overview
There are five kinds of LCD display: SLD (single line diagram) display, tripping reports, alarm
reports, binary input changing reports and device logs. Tripping reports and alarm reports will not
disappear until these reports are acknowledged by pressing the “RESET” button in the protection
panel (i.e. energizing the binary input [BI_RstTarg]). User can press “ESC” first then “ENT”
simultaneously to switch the display among trip reports, alarm reports and the SLD display. Binary
change reports will be displayed for 5s and then it’ll return to the previous display interface
automatically. Device logs will not pop up and can only be viewed by navigating the corresponding
menu.
8.3.2 Display during Normal Operation
After the protection device is powered and turns into the initiating interface, it takes 45 seconds to
complete the initialization of protection device. During the initialization, the “HEALTHY” indicator of
the protection device goes out.
Under normal condition, the LCD will display the interface similar as Figure 8.3-1. The LCD adopts
white color as its backlight that is activated if once there is any keyboard operation, and is
extinguished automatically after 60 seconds of no operation.
Date: 2016-08-16
When the device is powered on, the LCD will display single line diagram as following:
Date and time
Communication address Addr:102 2014-10-28 10:10:00 Group 01 Active setting group number
IdG: 0.00pu Generator differential current
f: 0.00Hz Frequency
Generator terminal current 0.00A
P: 0.00% Active power
Q: 0.00% Reactive power
Neutral point current 0.00A Ug: 0.00V Average value of generator
terminal three-phase voltage
Figure 8.3-1 LCD display of single line diagram
breaker open. breaker closed.
The displayed content of the interface contains: the current date and time of the protection device
(with a format of yy-mm-dd hh:mm:ss:), the currently valid setting group number, the three-phase
current and voltage sampled values (phase-to-phase voltage), differential current etc.
8.3.3 Display When Tripping

This protection device can store 64 fault reports and 64 fault waveforms. When there is protection
element operating, the LCD will automatically display the latest fault report, and two kinds of LCD
display will be available depending on whether there is self-check report at present.
If the device has no self-check report, the display interface will only show the fault report.
Disturb Records NO.2

2014-11-28 07:10:00:200
0000ms TrigDFR
0024ms 87G.Op_Biased
Figure 8.3-2 LCD display 1 of trip report
Disturb Records NO.2 shows the title and SOE number of the report.
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2014-11-28 07:10:00:200 shows the time when fault detector picks up, the format is
year–month-date and hour: minute:second:millisecond.
0000ms TrigDFR shows fault detector of protection element and operation time of fault detector is
fixed as 0ms.
0024ms 87G.Op_Biased shows the relative operation time and operation element of protection
element
All the protection elements have been listed in Chapter 3 “Operation Theory”, and please refer to
Section “Inputs and Outputs” of each protection element for details. Operation reports of fault
detector and the reports related to oscillography function are shown in the following table.
Table 8.3-1 Tripping reports related to oscillography
No. Message Description

1 TrigDFR_Man Oscillography function is triggered manually.
2 TrigDFR_Rmt Oscillography function is triggered remotely.
3 TrigDFR Fault detector operates to trigger oscillography.
Oscillography function is triggered by alarm signals on
4 ProtBrd.TrigDFR_Alm
protection board.
Oscillography function is triggered by failure signals on
5 ProtBrd.TrigDFR_Fail
protection board.
For the situation that the fault report and the self-check alarm report occur simultaneously in the
following figure, the upper half part is fault report, and the lower half part is self-check report. As to
the upper half part, it displays separately the record number of fault report, fault name, generating
time of fault report (with a format of yy-mm-dd hh:mm:ss:), protection element and tripping element.
If there is protection element, there is relative time on the basis of fault detector element. At the
same time, if the total lines of protection element and tripping element are more than 3, a scroll bar
will appear at the right. The height of the black part of the scroll bar basically indicates the total
lines of protection element and tripping element, and its position suggests the position of the
currently displayed line in the total lines. The scroll bar of protection element and tripping element
will roll up at the speed of one line per time. When it rolls to the last three lines, it’ll roll from the
earliest protection element and tripping element again. The displayed content of the lower half part
is similar to that of the upper half part.
Date: 2016-08-16
NO.010 2014-11-28 10:10:00:083 Disturb
0000ms TrigDFR
0024ms 87G.Op_Biased
Superv Events
24.Alm
Figure 8.3-3 LCD display 2 of trip report and alarm report
8.3.4 Display under Abnormal Condition
This protection device can store 1024 self-check reports. During the running of protection device,
the self-check report of hardware errors or system running abnormity will be displayed
immediately.
Superv Events NO.4

2014-11-29 9:18:47:500ms
Settings_Chgd 0 1
Figure 8.3-4 LCD display of alarm report
Superv Events NO.4 shows the SOE number and title of the report
2014-11-29 09:18:47:500 shows the data and time of the report occurred: year–month-date
and hour:minute:second:millisecond
Settings_Chgd 0->1 shows the content of abnormality alarm
All the alarm elements have been listed in Chapter 4 “Supervision”.
8.3.5 Display When Binary State Changes

When a binary input is energized or de-energized, output contacts operate, the corresponding IO
Date: 2016-08-16
event report will be automatically displayed on LCD as follows. This protective equipment can
store 1024 events of binary signals. During the running of the equipment, the binary signals will be
displayed once the input signal state changes.
IO Events NO.4
2014-11-29 09:18:47:500ms
BI_Maintenance 0 1
Figure 8.3-5 Display of binary change report
IO Events NO.4 shows the number and title of the report
2014-11-29 09:18:47:500 shows the date and time of the report occurred, the format is
year–month-date and hour:minute:second:millisecond
BI_Maintenance 0->1 shows the state change of binary input, including binary input name,
original state and final state
Contact inputs and contact outputs are listed in the following two tables, and user can define
undefined binary inputs as the specific binary inputs via PCS-Explorer2 software.
NOTICE!
The binary input number of BI intelligent module of different type may be DIFFERENT
and signals list in following table are just for reference, please refer to Chapter
“Hardware” for details.
Table 8.3-2 Contact inputs list
No. Binary input Description

1 BI_TimeSyn Binary input of time synchronization pulse
2 BI_Print Binary input of triggering printing
3 BI_Maintenance Binary input of indicating the protection device is under maintenance state
4 BI_RstTarg Binary input of resetting signal of protective device
5 Bxx.BI_01 Binary input 01 of binary input module at slot xx position.
Date: 2016-08-16

Table 8.3-3 Contact outputs list

1 TrpOut01 The 1st group of tripping outputs contacts.
2 TrpOut02 The 2nd group of tripping outputs contacts.
3 TrpOut03 The 3rd group of tripping outputs contacts.
4 TrpOut04 The 4th group of tripping outputs contacts.
th
11 TrpOut11 The 11 group of tripping outputs contacts.
th
th
th
th
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th
th
th
8.3.6 Display Device Logs
This protection device can store 1024 pieces of equipment logs. During the running of the
protection device, equipment logs will be displayed after user operations.
Device Logs NO.4

2008-11-28 10:18:47:569ms
Device_Reboot
Figure 8.3-6 Display of control report
Device Logs NO. 4 shows the title and the number of the report
2008-11-28 10:18:47:569 shows the date and time when the report occurred, the format is
year–month-date and hour:minute:second:millisecond
Device_Reboot shows the state content of the user operation report.
User operating information listed below may be displayed.
Table 8.3-4 User Operating event list
No. Message Description

1 Reboot The device has been reboot.
2 Settings_Chgd The device′s settings have been changed.
3 ActiveGrp_Chgd Active setting group has been changed.
4 Report_Cleared All reports have been deleted. (Device logs cannot be deleted)
5 Waveform_Cleared All waveforms have been deleted.
6 Process_Exit A process has exited.
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8.4 Keypad Operation

8.4.1 View Device Analog
The operation is as follows:
1. Press the key “▲” to enter the main menu.
2. Press the key “▲” or “▼” to move the cursor to the “Measurements” menu, and then
press the “ENT” or “►” to enter the menu.
3. Press the key “▲” or “▼” to move the cursor to any command menu item, and then press
the key “ENT” to enter the submenu.
4. Press the “▲” or “▼” to page up/down (if all information cannot be displayed in one
display screen, one screen can display 14 lines of information at most).
5. Press the key “◄” or “►” to select pervious or next command menu.
6. Press the key “ENT” or “ESC” to exit this menu (returning to the “Measurements” menu).
8.4.2 View Device Status

2. Press the key “▲” or “▼” to move the cursor to the “Status” menu, and then press the
“ENT” or “►” to enter the menu.
3. Press the key “▲” or “▼” to move the cursor to any command menu item, and then press
the key “ENT” to enter the submenu.
4. Press the “▲” or “▼” to page up/down (if all information cannot be displayed in one
display screen, one screen can display 14 lines of information at most).
6. Press the key “ENT” or “ESC” to exit this menu (returning to the “Status” menu).
8.4.3 View Device Records

2. Press the key “▲” or “▼” to move the cursor to the “Records” menu, and then press the
key “ENT” or “►” to enter the menu.
3. Press the key “▲” or “▼” to move the cursor to any command menu, and then press the
key “ENT” to enter the submenu.
4. Press the key “▲” or “▼” to page up/down.
5. Press the key “＋” or “－” to select pervious or next record.
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7. Press the key “ENT” or “ESC” to exit this menu (returning to the “Records” menu).
8.4.4 View Device Setting

2. Press the key “▲” or “▼” to move the cursor to the “Settings” menu, and then press the
key “ENT” or “►” to enter the menu.
key “ENT” to enter the menu.
4. Press the key “▲” or “▼” to move the cursor.
5. Press the key “+” or “-” to page up/down.
7. Press the key “ESC” to exit this menu (returning to the menu “Settings”).
If the displayed information exceeds 14 lines, the scroll bar will appear on the right side of
the LCD to indicate the quantity of all displayed information of the command menu and the
relative location of information where the current cursor points at.
8.4.5 Print Device Records

2. Press the key “▲” or “▼” to move the cursor to the “Print” menu, and then press the
“ENT” or “►” to enter the menu.
“ENT” to enter the menu.
 Selecting the “Disturb Records”, and then
Press the “＋” or “－” to select pervious or next record. After pressing the key “ENT”,
the LCD will display “Start Printing... ”, and then automatically exit this menu
(returning to the menu “Print”). If the printer doesn’t complete its current print task
and re-start it for printing, and the LCD will display “Printer Busy…”. Press the key
“ESC” to exit this menu (returning to the menu “Print”).
 Selecting the command menu “Superv Events” or “IO Events”, and then press the
key “▲” or “▼” to move the cursor. Press the “＋” or “－” to select the starting and
ending numbers of printing message. After pressing the key “ENT”, the LCD will
display “Start Printing…”, and then automatically exit this menu (returning to the
menu “Print”). Press the key “ESC” to exit this menu (returning to the menu “Print”).
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4. If selecting the command menu “Device Info”, “Device Status“ or “IEC103 Info”, press
the key “ENT”, the LCD will display “Start printing..”, and then automatically exit this menu
(returning to the menu “Print”).
5. If selecting the “Settings”, press the key “ENT” or “►” to enter the next level of menu.
6. After entering the submenu of “Settings”, press the key “▲” or “▼” to move the cursor,
and then press the key “ENT” to print the corresponding default value. If selecting any
item to printing:
Press the key “＋” or “－” to select the setting group to be printed. After pressing the key
“ENT”, the LCD will display “Start Printing…”, and then automatically exit this menu
(returning to the menu “Settings”). Press the key “ESC” to exit this menu (returning to the
menu “Settings”).
7. After entering the submenu “Waveforms”, press the key “ENT” or “►” to enter the next
level of menu. After entering the submenu of “Waveforms”, press the “＋” or “－” to
select the waveform item to be printed and press “ENT” to enter. If there is no any
waveform data, the LCD will display “No Waveform Data!” (If there is no any waveform
data, users can execute the command menu “Trig Oscillograph” in the menu “Local
Cmd”, then waveform data can be generated). With waveform data existing:
Press the key “＋” or “－” to select pervious or next record. After pressing the key “ENT”,
the LCD will display “Start Printing…”, and then automatically exit this menu (returning to
the menu “Waveforms”). If the printer does not complete its current print task and
re-start it for printing, and the LCD will display “Printer Busy…”. Press the key “ESC” to
exit this menu (returning to the menu “Waveforms”).
8.4.6 Modify Device Setting

2. Press the key “▲” or “▼” to move the cursor to the “Settings” menu, and then press
the key “ENT” or “►” to enter the menu.
3. Press the key “▲” or “▼” to move the cursor to any command menu, and then press
the key “ENT” to enter the menu.
4. Press the key “▲” or “▼” to move the cursor.
5. Press the key “+” or “-” to page up/down.
7. Press the key “ESC” to exit this menu (returning to the menu “Settings”).
Following takes modification of device settings as an example.
8. Select the command menu “Device Settings” “Comm Settings” or “Label Settings”,
users need to enter the submenu “Device Setup” firstly.
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9. Selecting the command menu “Device Settings”, move the cursor to the setting item
to be modified, and then press the key “ENT”.
Press the key “＋” or “－” to modify the value (if the modified value is of multi-bit, press
the key “◄” or “►” to move the cursor to the digit bit, and then press the “＋” or “－” to
modify the value), press the key “ESC” to cancel the modification and return to the
displayed interface of the command menu “Device Settings”. Press the key “ENT” to
automatically exit this menu (returning to the displayed interface of the command menu
“Device Settings”).
Move the cursor to continue modifying other setting items. After all setting values are
modified, press the key “◄”, “►” or “ESC”, and the LCD will display “Save or Not?”.
Directly press the “ESC” or press the key “◄” or “►” to move the cursor. Select the
“Cancel”, and then press the key “ENT” to automatically exit this menu (returning to the
displayed interface of the command menu “Device Settings”).
Press the key “◄” or “►” to move the cursor. Select “No” and press the key “ENT”, all
modified setting item will restore to its original value, exit this menu (returning to the
menu “Settings”).
Press the key “◄” or “►” to move the cursor to select “Yes”, and then press the key
“ENT”, the LCD will display password input interface.
Password:
____
Figure 8.4-1 Display of inputting password
Input a 4-bit password (“＋”, “◄”, “▲” or “－”). If the password is incorrect, continue
inputting it, and then press the “ESC” to exit the password input interface and return to
the displayed interface of the command menu “Device Settings”. If the password is
correct, LCD will display “Save Settings…”, and then exit this menu (returning to the
displayed interface of the command menu “Device Settings”), with all modified setting
items as modified values.
10. If selecting the command menu of protection element such as “Gen Diff Settings”,
the LCD will display the following interface:
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Gen Diff Settings
Please Select Group for Config
Active Group: 01
Selected Group: 02
Figure 8.4-2 Display 1 of modifying settings
Then move the cursor to the modified value and press “ENT” to enter. If the setting
[87G.I_Biased] is selected to modify, then press the “ENT” to enter and the LCD will
display the following interface. is shown the “＋” or “－” to modify the value and then press
the “ENT” to enter.
87G.I_Biased
Current Value 0.22
Modified Value 0.2 2
Min Value 0.10
Max Value 1.50
Figure 8.4-3 Display 2 of modifying settings
11. If selecting the other menus, move the cursor to the setting to be modified, and then
press the “ENT”.
For different setting items, their displayed interfaces are different but their modification methods
are the same.
After modifying the settings (except for communication settings), the “HEALTHY” indicator of the
protection device will go out, and the protection device will automatically restart and re-check the
protection setting. If the check doesn’t pass, the protection device will be blocked.
Date: 2016-08-16
8.4.7 Copy Device Setting

1. Press the key “▲” to enter the main menu;
2. Press the key “▲” or “▼” to move the cursor to the “Settings” menu, and then press the
key “ENT” or “►” to enter the menu;
3. Press the key “▲” or “▼” to move the cursor to the command menu “Copy Settings”,
and then press the key “ENT” to enter the menu. The following display will be shown on
LCD.
Copy Settings
Active Group: 01
Copy To Group: 02
Figure 8.4-4 Display of copy settings
Press the key “＋” or “－” to modify the value. Press the key “ESC”, and return to the
menu “Settings”. Press the “ENT”, the LCD will display the interface for password input,
if the password is incorrect, continue inputting it, press the key “ESC” to exit the
password input interface and return to the menu “Settings”. If the password is correct,
the LCD will display “Copy Settings Success!”, and exit this menu (returning to the menu
“Settings”).
8.4.8 Switch Setting Group

1. Exit the main menu.
2. Press the “GRP” button.
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Change Active Group
Active Group: 01
Change To Group: 02
Figure 8.4-5 Display of switching setting group
Press the “＋” or “－” to modify the value, and then press the key “ESC” to exit this menu
(returning to the main menu). After pressing the key “ENT”, the LCD will display the password
input interface. If the password is incorrect, continue inputting it, and then press the key “ESC” to
exit the password input interface and return to its original state. If the password is correct, the
“HEALTHY” indicator of the protection device will go out, and the protection device will re-check
the protection setting. If the check doesn’t pass, the protection device will be blocked. If the check
is successful, the LCD will return to its original state.
8.4.9 Delete Records

NOTICE!
The operation of deleting device records will delete ALL messages saved by the
protection device, including disturbance records, supervision events and binary events,
but it will NOT DELETE the user operation reports (i.e. device logs). Furthermore, all
deleted records are IRRECOVERABLE after deletion, please do the operation with
great cautious.
1. Exit the main menu.
2. Press the “＋”, “－”, “＋”, “－” and key “ENT”; Press the key “ESC” to exit this menu
(returning to the original state). Press the key “ENT” to carry out the deletion.
Date: 2016-08-16
Press <ENT> To Clear

Press <ESC> To Exit
Figure 8.4-6 Display of deleting report
8.4.10 Modify Device Clock

2. Press the key “▲” or “▼” to move the cursor to the “Clock” menu, and then press the key
“ENT” to enter clock display.
Clock
Year 2008
Month 11
Day 28
Hour 20
Minute 59
Second 14
Figure 8.4-7 Display of modifying clock
3. Press the key “▲” or “▼” to move the cursor to the date or time to be modified.
4. Press the key “＋” or “－”, to modify value, and then press the key “ENT” to save the
modification and return to the main menu.
5. Press the key “ESC” to cancel the modification and return to the main menu.
Date: 2016-08-16
8.4.11 Check Software Version

2. Press the key “▲” or “▼” to move the cursor to the “Information” menu, and then press
the “ENT” to enter the menu.
3. Press the key “▲” or “▼” to move the cursor to the command menu “Version Info”, and
then press the key “ENT” to display the software version.
4. Press the key “ESC” to return to the main menu.
8.4.12 View Module Information

2. Press the key “▲” or “▼” to move the cursor to the “Information” menu, and then press
the key “ENT” or “►” to enter the menu.
3. Press the key “▲” or “▼” to move the cursor to the command menu “Board Info”, and
then press the “ENT” to enter the menu.
4. Press the key “▲” or “▼” to move the scroll bar.
5. Press the key “ENT” or “ESC” to exit this menu (returning to the “Information” menu).
8.4.13 Select Language
2. Press the key “▲” or “▼” to move the cursor to the command menu “Language”, and
then press the key “ENT” to enter the menu and the following display will be shown on
LCD.
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Please Select Language:
1 中文
2 English
Figure 8.4-8 Display of selecting language
3. Press the key “▲” or “▼” to move the cursor to the language user preferred and press
the key “ENT” to execute language switching. After language switching is finished, LCD
will return to the menu “Language”, and the display language is changed. Otherwise,
press the key “ESC” to cancel language switching and return to the menu “Language”.
Date: 2016-08-16
Date: 2016-08-16
Table of Contents
9 Configurable Function ...................................................................... 9-1
9.1 General Description ........................................................................................ 9-1
9.2 Introduction on PCS-Explorer2 Software ...................................................... 9-1
9.3 Device Setup.................................................................................................... 9-1
9.3.1 Device Information ............................................................................................................... 9-1
9.3.2 MOT Configuration .............................................................................................................. 9-2
9.3.3 System Configuration .......................................................................................................... 9-3
9.3.4 Function Group Configuration ............................................................................................. 9-4
9.4 Program Configuration ................................................................................... 9-4

9.4.1 LED Configuration ............................................................................................................... 9-4
9.4.2 Configuration of BI and BO .................................................................................................. 9-6
9.5 Setting Configuration ..................................................................................... 9-8

9.5.1 Active Setting Group Selection ............................................................................................ 9-8
9.5.2 Browsing Settings ................................................................................................................ 9-9
9.5.3 Modify Name and Value of Settings .................................................................................... 9-9
List of Figures
Figure 9.3-1 Setting device information .................................................................................... 9-2
Figure 9.3-2 MOT configuration interface ................................................................................. 9-3
Figure 9.3-3 System configuration interface ............................................................................ 9-3
Figure 9.3-4 Function group configuration interface .............................................................. 9-4
Figure 9.5-1 “Setting” node ..................................................................................................... 9-9
Figure 9.5-2 The editing page of the “Setting” node ............................................................. 9-10
Figure 9.5-3 Modify setting name dialog box ......................................................................... 9-10

Date: 2019-02-21
Date: 2019-02-21
9.1 General Description
By adoption of PCS-Explorer2 software, it is able to make device configuration, function

configuration, LCD configuration, binary input and binary output configuration, LED indicator
configuration, setting configuration and programming logic for PCS-985GE.
9.2 Introduction on PCS-Explorer2 Software
PCS-Explorer2 software is developed in order to meet customer’s demand on functions of UAPC

platform device such as device configuration and programmable design. It selects substation as
the core of data management and the device as fundamental unit, supporting one substation to
govern many devices. The software provides on-line and off-line functions: on-line mode: Ethernet
connected with the device supporting IEC60870-5-103 and capable of uploading and downloading
configuration files through Ethernet net; off-line mode: off-line setting configuration. In addition, it
also supports programmable logic to meet customer’s demand. Please refer to instruction Manual
of “PCS-Explorer Auxiliary Software” for details.
Overall functions:
 Programmable logic (off-line function)
 Device configuration (off-line function)
 Function configuration (off-line function)
 LCD configuration (off-line function)
 LED indicators configuration (off-line function)
 Binary input signals configuration (off-line function)
 Binary output signals configuration (off-line function)
 Setting configuration (off-line & on-line function)
 Real-time display of analogue and digital quantity of device (on-line function)
 Display of sequence of report (SOE) (on-line function)
 Analysis of waveform (off-line & on-line function)
 File downloading/uploading (on-line function)
9.3 Device Setup
9.3.1 Device Information
Click “Device Config”→“Device Information” in the left part to view the basic information of the
device. All these information are default settings in the selected driver package for creating the

Date: 2019-02-21
device. Part of the basic information can be modified including “Config File Version”, “Modify Time”
and “User Information”.
Figure 9.3-1 Setting device information
9.3.2 MOT Configuration
Click “Device Config”→“Global Config”→“MOT” in the left part to enter MOT configuration interface
as shown below. According to the selected series number of MOT, the application scenario, some
software and hardware related function can be configured.
Date: 2019-02-21
Figure 9.3-2 MOT configuration interface
9.3.3 System Configuration
Click “Device Config”→“Global Config”→“System” in the left part to enter system configuration
interface as shown below (the content may vary subject to created projects). Click the pull-down
list in “Option” column to perform system configuration.
Figure 9.3-3 System configuration interface

Date: 2019-02-21
9.3.4 Function Group Configuration
Click “Device Config”→“Global Config”→“Function” in the left part to enter function group
configuration interface as shown below (the content may vary subject to created projects). Click
the pull-down list in “Code” column to perform function group configuration.
Figure 9.3-4 Function group configuration interface
9.4 Program Configuration
9.4.1 LED Configuration
On front panel of the device, two columns of indicators are normally provided. The first two
indicators indicate device running status (Healthy) and alarm status (Alarm). Colors of these
indicators may vary with functions of device.
The third LED (i.e. in3) is configured as the protection tripping LED indicator (TRIP) as default. If
Date: 2019-02-21
user want to configure the third LED as other functions, please inform manufacturer when placing
an order.
The control of these indicators is configured by LED element configuration in PCS-Explorer2.
Click “Program”→“B02:PROT_DSP”→“Main” node, and select the page “UswePage_LED” to view

and configure LED element.
The following is an example of LED configuration:
Figure 9.4-1 Example of LED configuration
Double click LED element to open its attributes setup window. users can see that it consists of 3
sub-pages. Here, indicators LED3~20 can be set.
Each indicator has two items to be set: Parameter “Latched”: click corresponding entry under
“Latched” to select “yes” or “no”. If “yes” is selected, indicator attribute is “latched”, indicating that
after this indicator is lit, it will remain on even the initiation signal disappears until it is reset. If “no”
is selected, indicator attribute is “un-latched”, indicating that the indicator status will follow the
change of its initiation signal.
The other parameter is “Color”: The color of indicator can be selected as required: green, yellow,
and red.
After completion of setup, click “OK” to close attributes setup window. The set parameters will be
displayed on the element, as shown below.

Date: 2019-02-21
Figure 9.4-2 LED indicators configuration interface
Next, indicators initiation signals should be placed on the page and connect them to corresponding
input interfaces of LED element: select the output signal from the “Out” tab (under the subnode of
“B02: PROT_DSP”) at the right side of the window to be used as input source. Press and hold left
button of mouse, and directly drag it to the page. When this signal passes input signal connection
point, a red dot will appear to prompt connection. After placing it at a suitable position, connection
line will be automatically generated to connect this input signal.
9.4.2 Configuration of BI and BO
The device is normally configured with a number of IO modules. Quantities may vary with different
project.
These BI and BO modules are normally configured according to general configuration.

Corresponding modules are usually selected according to the application. However, in some
cases, addition of IO modules may be required according to the changing requirements. At this
time, configuration of signals and parameters of additional IO modules is required. After creation of
a device using the template driver package by PCS-Explorer2, required configuration can be
Date: 2019-02-21
performed on editable page.
9.4.2.1 Configuration of BI
Takes BI module in slot No.09 as an example.
Click “Program” node. Unfold module node “B10:BI_S09”, one page node: “NR1504” is shown.
Click the page “NR1504”, the corresponding BI configuration graph is shown in an editing window.
Figure 9.4-3 Configuration graph of NR1504
In the graph, numbers in the “PIN” column are input terminal numbers of NR1504 module, and
name or function of each pin is described in the “BI_NAME” column.
All configurable binary inputs can be viewed in the “In” tab (under the subnode of “B02:
PROT_DSP”) at the right side of the window (variable library). The input signals of BI modules can
be configured or modified according to the application or drag the required signals from the
variable library.
Please refer to the input signals table in Section “Inputs and Outputs” of each protection element in
Chapter 3 for the detailed description of each configurable binary inputs.
9.4.2.2 Configuration of BO
Takes BO module in slot No.13 as an example.
Click “Program” node. Unfold module node “B13:BO_S13”, one page node: “NR1523A” is shown.

Date: 2019-02-21
Figure 9.4-4 Configuration graph of NR1523A
In the graph, numbers in the “PIN” column are input terminal numbers of NR1523A module, and
name or function of each pin is described in the “BO_NAME” column.
Inputs of all configurable binary outputs can be viewed in the “Out” tab (under the subnode of “B02:
PROT_DSP”) at the right side of the window (variable library). As shown in the figure, each input
corresponds to one output contact of the BO module. The output contact of BO module will
operate (output relay pickup or reset) in response to the status change of corresponding input
signal. The output contacts of BO modules can be configured or modified according to the
application or drag the required signals from the variable library.
Please refer to the output signals table in Section “Inputs and Outputs” of each protection element
in Chapter 3 for the detailed description of each configurable binary outputs.
9.5 Setting Configuration
9.5.1 Active Setting Group Selection
Click “Setting” node to enter “Settings” interface. Several sub-nodes: “Global” and “Group x” (x:
1~10). Among them, global settings (the sub-node “Global”) are common for all setting groups. In
setting groups Group 1~Group 10, only one group is the current active setting group used in
device operation, and mainly includes protection settings, the current active setting group can be
switched among Group 1~Group 10 when required.
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Figure 9.5-1 “Setting” node
9.5.2 Browsing Settings
Click “Setting”→“Global” node, several sub-nodes are unfolded (number of sub-nodes may vary
with different device models) in the edit window. These sub-nodes are used to set system settings,
configuration settings, device settings, communication settings and label settings.
Click “Settings”→“Group x” node, all the protective settings of corresponding group can be shown
by clicking corresponding setting menu item.
9.5.3 Modify Name and Value of Settings
Although there are many setting group nodes, settings under these nodes have the same layout in
editing page. Therefore, steps of modification of settings are basically the same. It is seen from the
graph that when any setting node is clicked and open, the editing page will display name, default
value, value, range, step, and unit of the settings in this sequence. Here, user can modify name
and set value of the settings according to actual application requirements.

Date: 2019-02-21
Figure 9.5-2 The editing page of the “Setting” node
The name of a setting is the name user will finally see on the device. Users can suitably modify
this name according to actual project requirements: right click on the name entry to be modified to
pop up a right-key context menu, execute the command “Set Description”; the following window
will pop up:
Figure 9.5-3 Modify setting name dialog box
In the “Set Description” dialog box, users will see two entries, “Original Name” is the default name
of this setting in the symbol library, and “Name” is the name currently used, and can be modified.
Modified setting value must not exceed its range (if there has an ordain). There are two types of
set value modification operation: direct input of the value after double clicking corresponding entry
of the setting value, or selection from a pull-down menu.
User can also right click the entry of set value and select “Load Default Value” in the right-key
context menu, so as to obtain default set value of this entry from the symbol library.
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10 Communication
10 Communication
Table of Contents
10 Communication ............................................................................. 10-a
10.1 General Description .................................................................................... 10-1
10.2 Rear Communication Port Information ..................................................... 10-1
10.2.1 RS-485 Interface.............................................................................................................. 10-1
10.2.2 Ethernet Interface ............................................................................................................ 10-3
10.2.3 IEC60870-5-103 Communication .................................................................................... 10-4
10.3 IEC60870-5-103 Interface over Serial Port ................................................ 10-4

10.3.1 Physical Connection and Link Layer ............................................................................... 10-5
10.3.2 Initialization ...................................................................................................................... 10-5
10.3.3 Time Synchronization ...................................................................................................... 10-5
10.3.4 Spontaneous Events ........................................................................................................ 10-5
10.3.5 General Interrogation ....................................................................................................... 10-6
10.3.6 General Functions ........................................................................................................... 10-6
10.3.7 Disturbance Records ....................................................................................................... 10-6
10.4 IEC60870-5-103 Interface over Ethernet .................................................... 10-6

10.5 Messages Description for IEC61850 Protocol .......................................... 10-6
10.5.1 Overview .......................................................................................................................... 10-6
10.5.2 Communication Profiles ................................................................................................... 10-7
10.5.3 MMS Communication Network Deployment ................................................................... 10-8
10.5.4 Server Data Organization ...............................................................................................10-11
10.5.5 Server Features and Configuration ............................................................................... 10-14
10.5.6 ACSI Conformance ........................................................................................................ 10-16
10.5.7 Logical Nodes ................................................................................................................ 10-20
10.6 DNP3.0 Interface........................................................................................ 10-23

10.6.1 Overview ........................................................................................................................ 10-23

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10 Communication
10.6.2 Link Layer Functions...................................................................................................... 10-24
10.6.3 Transport Functions ....................................................................................................... 10-24
10.6.4 Application Layer Functions........................................................................................... 10-24
List of Figures
Figure 10.2-1 EIA RS-485 bus connection arrangements ..................................................... 10-2
Figure 10.2-2 Ethernet communication cable ........................................................................ 10-3
Figure 10.2-3 Ethernet communication structure .................................................................. 10-4
Figure 10.5-1 Dual-net full duplex mode sharing the RCB block instance ......................... 10-9
Figure 10.5-2 Dual-net hot-standby mode sharing the same RCB instance ..................... 10-10
Figure 10.5-3 Dual-net full duplex mode with 2 independent RCB instances .................. 10-11
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10 Communication
10.1 General Description
This section introduces NR’s remote communications interfaces. The protective device is
compatible with three protocols via the rear communication interface (RS-485 or Ethernet). The
protocol provided by the protective device is indicated in the submenu in the “Comm Settings”
column. Using the keypad and LCD to set the parameter [Protocol_RS485A] and
[Protocol_RS485B], the corresponding protocol will be selected.
The rear EIA RS-485 interface is isolated and is suitable for permanent connection no matter
whichever protocol is selected. It has advantage that 32 protective devices can be “daisy chained”
together in electrical connection using a twisted pair.
It should be noted that the descriptions in this section do not aim to fully introduce the protocol
itself. The relevant documentation for the protocol should be referred for this information. This
section serves to describe the specific implementation of the protocol in the relay.
10.2 Rear Communication Port Information
10.2.1 RS-485 Interface

This protective device provides two rear RS-485 communication ports, and each port has three
terminals in the 12-terminal screw connector located on the back of the relay. Each port has a
ground terminal for earth shield of communication cable. The rear ports provide RS-485 serial data
communication and are intended for permanently wired connection to a remote control center.
10.2.1.1 EIA RS-485 Standardized Bus
The EIA RS-485 two-wire connection provides a half-duplex fully isolated serial connection to the
product. The connection is polarized and whilst the product’s connection diagrams indicate the
polarization of the connection terminals it should be borne in mind that there is no agreed
definition of which terminal is which. If the master is unable to communicate with the product, but
the communication parameters match, then it is possible that the two-wire connection is reversed.
10.2.1.2 Bus Termination
The EIA RS-485 bus must have 120Ω (Ohm) ½ Watt terminating resistors fitted at either end
across the signal wires (refer to Figure 10.2-1). Some devices may be able to provide the bus
terminating resistors by different connection or configuration arrangements, in which case
separate external components will not be required. However, this product does not provide such a
facility, so an external termination resistor is required when it is located at the bus terminus.

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10 Communication
EIA RS-485
Master 120 Ohm
120 Ohm
Slave Slave Slave
Figure 10.2-1 EIA RS-485 bus connection arrangements
10.2.1.3 Bus Connections & Topologies
The EIA RS-485 requires that each device is directly connected to the physical cable i.e. the
communications bus. Stubs and tees are strictly forbidden, such as star topologies. Loop bus
topologies are not part of the EIA RS-485 standard and are forbidden also.
Two-core screened cable is recommended. The specification of the cable will be dependent on the
application, although a multi-strand 0.5mm2 per core is normally adequate. Total cable length
must not exceed 500m. The screen must be continuous and connected to ground at one end,
normally at the master connection point; it is important to avoid circulating currents, especially
when the cable runs between buildings, for both safety and noise reasons.
This product does not provide a signal ground connection. If a signal ground connection is present
in the bus cable then it must be ignored, although it must have continuity for the benefit of other
devices connected to the bus. The signal ground shall not be connected to the cables screen or to
the product’s chassis at any stage. This is for both safety and noise reasons.
10.2.1.4 Biasing
It may also be necessary to bias the signal wires to prevent jabber. Jabber occurs when the signal
level has an indeterminate state due to inactively driven of tubs. This can occur when all the slaves
are in receive mode and the master unit is slow to turn from receive mode to transmit mode. The
reason is that the master purposefully waits in receive mode, or even in a high impedance state,
until it has something to transmit. Jabber can result in the loss of first bits of the first character in
the packet for receiving device(s), which will lead to the rejection of messages for slave units,
causing non-responding between master unit and slave unit. This could brings poor response
times (due to retries), increase in message error counters, erratic communications, and even a
complete failure to communicate.
Biasing requires that the signal lines shall be weakly pulled to a defined voltage level of about 1V.
There should be only one bias point on the bus, which is best situated at the master connection
point. The DC source used for the bias must be clean; otherwise noise will be injected. Please
note that some devices may (optionally) be able to provide the bus bias that the external
components will not be required.
NOTICE!
It is extremely IMPORTANT that the 120Ω termination resistors are fitted. Failure to do
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10 Communication
will result in an excessive bias voltage that may damage the devices connected to the
bus.
As the field voltage is much higher than that required, NR CANNOT assume
responsibility for any damage that may occur to a device connected to the network as a
result of incorrect application of this voltage.
ENSURE that the field voltage is not being used for other purposes (i.e. powering logic
inputs) as this may cause noise to be passed to the communication network.
10.2.2 Ethernet Interface

This protective device can provide four rear Ethernet interfaces (optional) and they are unattached
to each other. Parameters of each Ethernet port can be configured in the submenu “Comm
Settings”.
10.2.2.1 Ethernet Standardized Communication Cable
It is recommended to use twisted screened eight-core cable as the communication cable. A picture
is shown bellow.
Figure 10.2-2 Ethernet communication cable
10.2.2.2 Connections and Topologies
Each device is connected with an exchanger via communication cable, and thereby it forms a star
structure network. Dual-network is recommended in order to increase reliability. SCADA is also
connected to the exchanger acting as the master station, and every device which has been
connected to the exchanger will act as a slave unit.

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10 Communication
SCADA
Exchanger A
Exchanger B
Equipment Equipment Equipment
Figure 10.2-3 Ethernet communication structure
10.2.3 IEC60870-5-103 Communication

The IEC specification IEC60870-5-103: Telecontrol Equipment and Systems, Part 5: Transmission
Protocols Section 103 defines the use of standards IEC60870-5-1 to IEC60870-5-5 to perform
communication with protective device. The standard configuration of IEC60870-5-103 protocol is
using a twisted pair EIA RS-485 connection over distances up to 500m. It also supports an
Ethernet for communication between devices. The relay operates as a slave unit in the system to
respond commands received from master station.
To use the rear port with IEC60870-5-103 communication, the relevant settings of the protective
device must be configured by using keypad and LCD user interface. In the submenu “Comm
Settings”, set the parameters [Protocol_RS485A], [Protocol_RS485B] and [Baud_RS485]. To use
the Ethernet port with IEC60870-5-103 communication, the IP address and the submask of each
Ethernet port shall be set in the same submenu. Please refer to the corresponding section in
Chapter “Settings” for further details.
10.3 IEC60870-5-103 Interface over Serial Port
The IEC60870-5-103 interface over serial port (RS-485) is a master/slave interface and the
protective device is the slave device.
The protective device conforms to compatibility level 3.
The following IEC60870-5-103 facilities are supported by this interface:
 Initialization (reset)
 Time synchronization
 Event record extraction
 General interrogation
 General commands
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 Disturbance records
10.3.1 Physical Connection and Link Layer

Two EIA RS-485 standardized ports are available for IEC60870-5-103 in this protective device.
The transmission speed is optional: 4800 bit/s, 9600 bit/s, 19200 bit/s or 38400 bit/s.
The link layer strictly abides by the rules defined in the IEC60870-5-103.
10.3.2 Initialization
When the protective device is powered up, or the communication parameters are changed, a reset
command is required to initialize the communications. The protective device will respond to either
of the two reset commands (Reset CU or Reset FCB), the difference is that the Reset CU will clear
any unsent messages in the transmit buffer.
The protective device will respond to the reset command with an identification message ASDU 5,
the COT (Cause Of Transmission) of this response will be either Reset CU or Reset FCB
depending on the nature of the reset command.
10.3.3 Time Synchronization

The time and date of protective device can be set by time synchronization feature of the
IEC60870-5-103 protocol. The transmission delay as specified in IEC60870-5-103 will be
corrected in the protective device. If the time synchronization message is sent as a send/confirm
message, then the protective device will respond with a confirmation. Whether the
time-synchronization message is sent as a send confirmation or a broadcast (send/no reply)
message, a time synchronization class 1 event will be generated/produced.
If the protective device clock is synchronized using the IRIG-B input, the protection device will not
be able to set the time using the IEC60870-5-103 interface. For attempt to set the time via the
interface, the protective device will create an event with the date and time taken from the IRIG-B
synchronized internal clock.
10.3.4 Spontaneous Events

Events are categorized by the following information:
 Type identification (TYP)
 Function type (FUN)
 Information number (INF)
Messages sent to substation automation system are grouped according to IEC60870-5-103

protocol. Operation elements are sent by ASDU2 (time-tagged message with relative time), and
status of binary Input and alarm element are sent by ASDU1 (time-tagged message). The cause of
transmission (COT) of these responses is 1.
The complete list of all events produced by the protective device can be printed by choosing the
submenu “IEC103 Info” in the menu “Print”.

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10.3.5 General Interrogation

The GI can be used to read the status of the relay, the function numbers, and the information
numbers that will be returned during the GI cycle. The GI cycle strictly abides by the rules defined
in the IEC60870-5-103.
Refer the IEC60870-5-103 standard can get the enough details about general interrogation.
10.3.6 General Functions

The general functions can be used to read the setting and protection measurement of the relay,
and modify the setting. Two supported type identifications are ASDU 21 and ASDU 10. For more
details about generic functions, please see the IEC60870-5-103 standard.
Generic service group numbers supported by the relay can be printed by the submenu “IEC103
Info” in the menu “Print”.
10.3.7 Disturbance Records

This protective device can store up to 32 disturbance records in its memory. Pickup of fault
detector or operation of relay will be stored as disturbance recorders in the protective device.
The disturbance records are stored in uncompressed format and can be extracted using the
standard mechanisms described in IEC60870-5-103.
It can be printed by the submenu “IEC103 Info” in the menu “Print”
10.4 IEC60870-5-103 Interface over Ethernet
The IEC60870-5-103 interface over Ethernet is a master/slave interface with the relay as the slave
device. All the functions provided by this relay are based on generic functions of the
IEC60870-5-103. This relay will send all the relevant information on group caption to SAS or RTU
after establishing a successful communication link.
10.5 Messages Description for IEC61850 Protocol
10.5.1 Overview
The IEC 61850 standard is the result of years of work by electric utilities and vendors of electronic
device to produce standardized communications systems. IEC 61850 is a series of standards
describing client/server and peer-to-peer communications, substation design and configuration,
testing, environmental and project standards. The complete set includes:
 IEC 61850-1: Introduction and overview
 IEC 61850-2: Glossary
 IEC 61850-3: General requirements
 IEC 61850-4: System and project management
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 IEC 61850-5: Communications and requirements for functions and device models
 IEC 61850-6: Configuration description language for communication in electrical substations

related to IEDs
 IEC 61850-7-1: Basic communication structure for substation and feeder device - Principles
and models
 IEC 61850-7-2: Basic communication structure for substation and feeder device - Abstract
communication service interface (ACSI)
 IEC 61850-7-3: Basic communication structure for substation and feeder device – Common
data classes
 IEC 61850-7-4: Basic communication structure for substation and feeder device – Compatible
logical node classes and data classes
 IEC 61850-8-1: Specific Communication Service Mapping (SCSM) – Mappings to MMS (ISO
9506-1 and ISO 9506-2) and to ISO/IEC 8802-3
 IEC 61850-9-1: Specific Communication Service Mapping (SCSM) – Sampled values over
serial unidirectional multidrop point to point link
 IEC 61850-9-2: Specific Communication Service Mapping (SCSM) – Sampled values over
ISO/IEC 8802-3
 IEC 61850-10: Conformance testing
These documents can be obtained from the IEC (http://www.iec.ch). It is strongly recommended
that all those involved with any IEC 61850 implementation obtain this document set.
10.5.2 Communication Profiles

The relay supports IEC 61850 server services over TCP/IP communication protocol stacks. The
TCP/IP profile requires IP address to establish communications. These addresses are located in
the submenu “Settings→Device Setup→Comm Settings”.
1. MMS protocol
IEC 61850 specifies the use of the Manufacturing Message Specification (MMS) at the upper
(application) layer for transfer of real-time data. This protocol has been in existence for a number
of years and provides a set of services suitable for the transfer of data within a substation LAN
environment. IEC 61850-7-2 abstract services and objects are mapped to actual MMS protocol
services in IEC61850-8-1.
2. Client/server
This is a connection-oriented type of communication. The connection is initiated by the client, and
communication activity is controlled by the client. IEC61850 clients are often substation computers
running HMI programs or SOE logging software. Servers are usually substation device such as
protection relays, meters, RTUs, instrument transformers, tap changers, or bay controllers.
Please note that gateways can be considered as clients and servers subject to the communication

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object. When retrieving data from IEDs within the substation, the gateways are considered as
servers whereas transmitting data to control centers, the gateways are considered as clients.
3. Peer-to-peer
This is a non-connection-oriented high speed communication between substation device, such as

protection relays. GOOSE is the method of peer-to-peer communication.
4. Substation configuration language (SCL)
A substation configuration language is a number of files used to describe IED configurations and
communication systems according to IEC 61850-5 and IEC 61850-7. Each configured device has
an IED Capability Description (ICD) file and a Configured IED Description (CID) file. The
substation single line information is stored in a System Specification Description (SSD) file. The
entire substation configuration is stored in a Substation Configuration Description (SCD) file. The
SCD file is the combination of the following items: individual ICD files, SSD file, communication
system parameters (MMS, GOOSE control block, SV control block), as well as GOOSE/SV
connection relationship amongst IEDs.
10.5.3 MMS Communication Network Deployment

To enhance the stability and reliability of SAS, dual-MMS Ethernet is widely adopted. This section
is applied to introduce the details of dual-MMS Ethernet technology. Generally, single-MMS
Ethernet is recommended to be adopted in the SAS of 110kV and lower voltage levels, while
dual-MMS Ethernet is recommended to be adopted in the SAS of voltage levels above 110kV.
Client-server mode is adopted: clients (SCADA, control center and etc.) communicate with the
IEDs via MMS communication network, and the IEDs operate as the servers. IEDs are connected
to clients passively, and they can interact with the clients according to the configuration and the
issued command of the clients.
Three modes for dual-MMS Ethernet (abbreviated as dual-net) are provided as below.
Hereinafter, the normal operation status of net means the physical link and TCP link are both OK.
The abnormal operation status of net means physical link or TCP link is broken.
1) Mode 1: Dual-net full duplex mode sharing the same RCB instance
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Client Client
Net A Net B Net A Net B
Report Instance 1 Report Instance 1
RptEna = true RptEna = true
Report Control Block Report Control Block

IED (Server) IED (Server)
Normal operation status Abnormal operation status
TCP Link
MMS Link
Figure 10.5-1 Dual-net full duplex mode sharing the RCB block instance
Net A and Net B share the same report control block (abbreviated as RCB) enabled by the client.
IED sends undifferentiated date through dual-net to the clients. If one net is physically
disconnected, the flag of RCB instance (i.e.: “RptEna” in above figure) is still “true”. Only when
both Net A and Net B are disconnected, the flag of the RCB instance will automatically change to
“false”.
In normal operation status of mode 1, IED provides the same MMS service for Net A and Net B. If
one net is physically disconnected (i.e.: “Abnormal operation status” in above figure), the working
mode will switch to single-net mode seamlessly and immediately. Network communication
supervision is unnecessary here, and Buffered Report Control Block (abbreviated as BRCB) need
not to be used. On the other net, date alternation works normally. Therefore, MMS service can
interact normally without interruption. This mode ensures no data loss during one net is in
abnormal operation status.
In mode 1, one report will be transmitted twice via dual nets for the same report instance, so the
client needs to distinguish whether two reports are same according to corresponding EntryIDs.
2) Mode 2: Dual-net hot-standby mode sharing the same RCB instance

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Client Client
Report Instance 1 Report Instance 1
RptEna = true RptEna = true

Normal operation status Abnormal operation status
TCP Link
Main MMS Link
Standby MMS Link
Figure 10.5-2 Dual-net hot-standby mode sharing the same RCB instance
In mode 2, the MMS service is provided on main MMS link, no MMS service interacts on the
standby MMS link. The definitions of two links are as follows:
 Main MMS Link: Physically connected, TCP level connected, MMS report service available.
 Standby MMS Link: Physically connected, TCP level connected, MMS report service not
available.
If the main net fails to operate (i.e.: “Abnormal operation status” in the above figure), the IED will
set “RptEna” to “false”. Meanwhile the client will detect the failure by heartbeat message or
“keep-alive”, it will automatically enable the RCB instance by setting “RptEna” back to “true”
through standby MMS link. By the buffer function of BRCB, the IED can provide uninterrupted
MMS service on the standby net. However, the differences of BRCB standards among different
manufacturers may cause data loss. Moreover, if duration of net switch is too long, the data loss is
positively as the capacity of BRCB’s buffer function is limited.
In mode 1 and mode 2, Net A IED host address and Net B IED host address must be the same.
E.g.: if the subnet mask is 255.255.0.0, network prefix of Net A is 198.120.0.0, network prefix of
Net B is 198.121.0.0, Net A IP address of the IED is 198.120.1.2, and then Net B IP address of the
IED must be configured as 198.121.1.2, i.e.: Net A IED host address =1x256+2=258, Net B IED
host address =1x256+2=258, Net A IED host address equals to Net B IED host address.
3) Mode 3: Dual-net full duplex mode with 2 independent RCB instances
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Client Client
Report Instance 1 Report Instance 2 Report Instance 1 Report Instance 2
RptEna = true RptEna = true RptEna = false RptEna = true

TCP Link
MMS Link
Figure 10.5-3 Dual-net full duplex mode with 2 independent RCB instances
In mode 3, IED provides 2 report instances for each RCB, Net A and Net B work independently
from each other, failures of one net will not affect the other net at all.
In this mode, 2 report instances are required for each client. Therefore, the IED may be unable to
provide enough report instances if there are too many clients.
Net A and Net B send the same report separately when they operates normally, To ensure no
repeated data is saved into database, massive calculation is required for the client.
Moreover, accurate clock synchronization of the IED is required to distinguish whether 2 reports
are the same report according to the timestamps. Clock synchronization error of the IED may lead
to report loss/redundancy.
As a conclusion:
In mode 2, it’s difficult to realize seamless switchover between dual nets;
In mode 3, the IED may be unable to provide enough report instances if too many clients are
applied on site.
For the consideration of client treatment and IED implementation, mode 1 (Dual-net full duplex
mode sharing the same report instance) is recommended for MMS communication network
deployment.
10.5.4 Server Data Organization

IEC61850 defines an object-oriented approach to data and services. An IEC61850 physical device
can contain one or more logical device(s) (for proxy). Each logical device can contain many logical
nodes. Each logical node can contain many data objects. Each data object is composed of data
attributes and data attribute components. Services are available at each level for performing

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various functions, such as reading, writing, control commands, and reporting.
Each IED represents one IEC61850 physical device. The physical device contains one or more
logical device(s), and the logical device contains many logical nodes. The logical node LPHD
contains information about the IED physical device. The logical node LLN0 contains common
information about the IED logical device.
10.5.4.1 Digital Status Values
The GGIO logical node is used to provide access to digital status points (including general I/O
inputs and warnings) and associated timestamps and quality flags. The data content must be
configured before using. GGIO provides digital status points for access by clients. It is intended for
the use of GGIO by client to access to digital status values from PCS-985GE relays. Clients can
utilize the IEC61850 buffered report from GGIO to build sequence of events (SOE) logs and HMI
display screens. Buffered reporting should generally be used for SOE logs since the buffering
capability reduces the chances of missing data state changes. All needed status data objects are
transmitted to HMI clients via buffered reporting, and the corresponding buffered reporting control
block (BRCB) is defined in LLN0.
10.5.4.2 Analog Values
Most of measured analog values are available through the MMXU logical nodes, and m etering
values in MMTR, the others in MMXN, MSQI and so on. Data of each MMXU logical node is
provided from a IED current/voltage “source”. There is one MMXU available for each configurable
source. Data of MMXU1 is provided from CT/VT source 1 (usually for protection purpose), and
data of MMXU2 is provided from CT/VT source 2 (usually for monitor and display purpose). All
these analog data objects are transmitted to HMI clients via unbuffered reporting periodically, and
the corresponding unbuffered reporting control block (URCB) is defined in LLN0. MMXUx logical
nodes provide the following data for each source:
 MMXU.MX.Hz: frequency
 MMXU.MX.PPV.phsAB: phase AB voltage magnitude and angle
 MMXU.MX.PPV.phsBC: phase BC voltage magnitude and angle
 MMXU.MX.PPV.phsCA: Phase CA voltage magnitude and angle
 MMXU.MX.PhV.phsA: phase AG voltage magnitude and angle
 MMXU.MX.PhV.phsB: phase BG voltage magnitude and angle
 MMXU.MX.PhV.phsC: phase CG voltage magnitude and angle
 MMXU.MX.A.phsA: phase A current magnitude and angle
 MMXU.MX.A.phsB: phase B current magnitude and angle
 MMXU.MX.A.phsC: phase C current magnitude and angle
10.5.4.3 Protection Logical Nodes
The following list describes the protection elements for PCS-985GE relays. The specified relay will
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10 Communication
contain a subset of protection elements from this list.
 PDIF: current differential and transfer trip
 RBRF:Breaker failure
 PTOC: Time overcurrent
 SCAS: Mechanical relay protection
 PDIS: Distance protection
 PDOP: Directional over power
 PDUP: Directional underpower
 PPAM: Out-of-step protection
 PTOF: Overfrequency
 PTUF: Underfrequency
 PTOV: Time overvoltage
 PTUV: Undervoltage
 PVPH: Volts per Hz
 PDIR: Fault direction comparison
 PSEF: 3rd harmonic stator earth fault protection
 PREF: Rotor earth fault protection
 PVCE: Voltage control element
 PTTR: Thermal overload
 PVOC: Voltage controlled time overcurrent
 PIOC: Instantaneous overcurrent
 PGSS: Startup and shutdown protection
 PNVL: Negative-sequence overload protection
 PISG: Stator ground fault protection with 20Hz voltage injection
 PMOP: Inadvertent energization protection
 PZSG: Fundamental zero-sequence voltage stator ground fault protection
 PITF: Longitudinal zero-sequence voltage inter-turn protection
The protection elements listed above contain start (pickup) and operate flags, instead of any
element has its own start (pickup) flag separately, all the elements share a common start (pickup)
flags “PTRC.ST.Str.general”. The operate flag for PDIF1 is “PDIF1.ST.Op.general”. For
PCS-985GE relay protection elements, these flags take their values from related module for the

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corresponding element. Similar to digital status values, the protection trip information is reported
via BRCB, and it also locates in LLN0.
10.5.4.4 LLN0 and Other Logical Nodes
Logical node LLN0 is essential for an IEC61850 based IED. This LN shall be used to address
common issues for Logical Devices. Most of the public services, the common settings, control
values and some device oriented data objects are available here. The public services may be
BRCB, URCB and GSE control blocks and similar global defined for the whole device; the
common settings include all the setting items of communication settings, system settings and
some of the protection setting items, which can be configured to two or more protection elements
(logical nodes). In LLN0, the item Loc is a device control object, this item indicates the local
operation for complete logical device, when it is true, all the remote control commands to the IED
will be blocked until Loc is changed to false. In PCS-985GE relays, besides the logical nodes
described above, there are some other logical nodes in the IEDs:
 LPHD: Physical device information, the logical node to model common issues for physical
device.
 PTRC: Protection trip conditioning, it is used to connect the “operate” outputs of one or more
protection functions to a common “trip” to be transmitted to XCBR. In addition or alternatively, any
combination of “operate” outputs of protection functions may be combined to a new “operate” of
PTRC.
 RDRE: Disturbance recorder function. It triggers fault wave recorder and its output refers to
the “IEEE Standard Format for Transient Data Exchange (COMTRADE) for Power System” (IEC
60255-24). All enabled channels are included in the recording and is independent of the trigger
mode.
 TCTR: Current transformer
 TVTR: Voltage transformer
 YPTR: Power transformer
 ZGEN: Generator
10.5.5 Server Features and Configuration

10.5.5.1 Buffered/unbuffered Reporting
IEC61850 buffered and unbuffered reporting control blocks are located in LLN0, they can be
configured to transmit information of protection trip information (in the Protection logical nodes),
binary status values (in GGIO) and analog measured/calculated values (in MMXU, MMTR and
MSQI). The reporting control blocks can be configured in CID files, and then be sent to the IED via
an IEC61850 client. The following items can be configured.
 TrgOps: Trigger options.
The following bits are supported by PCS-985GE relays:
－ Bit 1: Data-change
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－ Bit 4: Integrity
－ Bit 5: General interrogation
 OptFlds: Option Fields.
The following bits are supported by PCS-985GE relays:
－ Bit 1: Sequence-number
－ Bit 2: Report-time-stamp
－ Bit 3: Reason-for-inclusion
－ Bit 4: Data-set-name
－ Bit 5: Data-reference
－ Bit 6: Buffer-overflow (for buffered reports only)
－ Bit 7: EntryID (for buffered reports only)
－ Bit 8: Conf-revision
－ Bit 9: Segmentation
 IntgPd: Integrity period.
 BufTm: Buffer time.
10.5.5.2 File Transfer
MMS file services allows transfer of oscillography, event record or other files from a PCS-985GE
relay.
10.5.5.3 Timestamps
The timestamp values associated with all IEC61850 data items represent the time of the last
change of either the value or quality flags of the data item.
10.5.5.4 Logical Node Name Prefixes
IEC61850 specifies that each logical node can have a name with a total length of 11 characters.
The name is composed of:
 A five or six-character name prefix.
 A four-character standard name (for example, MMXU, GGIO, PIOC, etc.).
 A one or two-character instantiation index.
Complete names are in the form of xxxxxxPTOC1, where the xxxxxx character string is
configurable. Details regarding the logical node naming rules are given in IEC61850 parts 6 and
7-2. It is recommended that a consistent naming convention be used for an entire substation
project.

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10 Communication
10.5.5.5 GOOSE Services
IEC61850 specifies the type of broadcast data transfer services: Generic Object Oriented
Substation Events (GOOSE). IEC61850 GOOSE services provide virtual LAN (VLAN) support,
Ethernet priority tagging, and Ether-type Application ID configuration. The support for VLANs and
priority tagging allows for the optimization of Ethernet network traffic. GOOSE messages can be
given a higher priority than standard Ethernet traffic, and they can be separated onto specific
VLANs. Devices that transmit GOOSE messages also function as servers. Each GOOSE
publisher contains a “GOOSE control block” to configure and control the transmission.
The GOOSE transmission (including subscribing and publishing) is controlled by GOOSE logic link
settings in device.
The relay supports IEC61850 Generic Object Oriented Substation Event (GOOSE)
communication. All GOOSE messages contain IEC61850 data collected into a dataset. It is this
dataset that is transferred using GOOSE message services. The GOOSE related dataset is
configured in the CID file and it is recommended that the fixed GOOSE be used for
implementations that require GOOSE data transfer between PCS-985GE relays.
IEC61850 GOOSE messaging contains a number of configurable parameters, all of which must be
correct to achieve the successful transfer of data. It is critical that the configured datasets at the
transmission and reception devices are an exact match in terms of data structure, and that the
GOOSE addresses and name strings match exactly.
10.5.6 ACSI Conformance

10.5.6.1 ACSI Basic Conformance Statement
Services Client Server PCS-985GE
Client-Server Roles
B11 Server side (of Two-party Application-Association) － C1 Y
B12 Client side (of Two-party Application-Association) C1 － N
SCSMS Supported
B21 SCSM: IEC 61850-8-1 used N N Y
B22 SCSM: IEC 61850-9-1 used N N N
B23 SCSM: IEC 61850-9-2 used N N N
B24 SCSM: other N N N
Generic Substation Event Model (GSE)
B31 Publisher side － O Y
B32 Subscriber side O － Y
Transmission Of Sampled Value Model (SVC)
B41 Publisher side － O N
B42 Subscriber side O － N
Where:
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10 Communication
C1: Shall be "M" if support for LOGICAL-DEVICE model has been declared
O: Optional
M: Mandatory
Y: Supported by PCS-985GE relay
N: Currently not supported by PCS-985GE relay
10.5.6.2 ACSI Models Conformance Statement
M1 Logical device C2 C2 Y
M2 Logical node C3 C3 Y
M3 Data C4 C4 Y
M4 Data set C5 C5 Y
M5 Substitution O O Y
M6 Setting group control O O Y
Reporting
M7 Buffered report control O O Y
M7-1 sequence-number Y Y Y
M7-2 report-time-stamp Y Y Y
M7-3 reason-for-inclusion Y Y Y
M7-4 data-set-name Y Y Y
M7-5 data-reference Y Y Y
M7-6 buffer-overflow Y Y N
M7-7 entryID Y Y Y
M7-8 BufTm N N N
M7-9 IntgPd Y Y Y
M7-10 GI Y Y Y
M8 Unbuffered report control M M Y
M8-1 sequence-number Y Y Y
M8-2 report-time-stamp Y Y Y
M8-3 reason-for-inclusion Y Y Y
M8-4 data-set-name Y Y Y
M8-5 data-reference Y Y Y
M8-6 BufTm N N N
M8-7 IntgPd N Y Y
Logging
M9 Log control O O N

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M9-1 IntgPd N N N
M10 Log O O N
GSE
M12 GOOSE O O Y
M13 GSSE O O N
M14 Multicast SVC O O N
M15 Unicast SVC O O N
M16 Time M M Y
M17 File transfer O O Y
Where:
C2: Shall be "M" if support for LOGICAL-NODE model has been declared
C3: Shall be "M" if support for DATA model has been declared
C4: Shall be "M" if support for DATA-SET, Substitution, Report, Log Control, or Time models has
been declared
C5: Shall be "M" if support for Report, GSE, or SMV models has been declared
M: Mandatory
Y: Supported by the relay
N: Currently not supported by the relay
10.5.6.3 ACSI Services Conformance Statement
Service Server/Publisher PCS-985GE
Server
S1 ServerDirectory M Y
Application association
S2 Associate M Y
S3 Abort M Y
S4 Release M Y
Logical device
S5 LogicalDeviceDirectory M Y
Logical node
S6 LogicalNodeDirectory M Y
S7 GetAllDataValues M Y
Data
S8 GetDataValues M Y
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S9 SetDataValues M Y
S10 GetDataDirectory M Y
S11 GetDataDefinition M Y
Data set
S12 GetDataSetValues M Y
S13 SetDataSetValues O Y
S14 CreateDataSet O N
S15 DeleteDataSet O N
S16 GetDataSetDirectory M Y
Substitution
S17 SetDataValues M Y
Setting group control
S18 SelectActiveSG M/O Y
S19 SelectEditSG M/O Y
S20 SetSGValuess M/O Y
S21 ConfirmEditSGValues M/O Y
S22 GetSGValues M/O Y
S23 GetSGCBValues M/O Y
Reporting
Buffered report control block
S24 Report M Y
S24-1 data-change M Y
S24-2 qchg-change M N
S24-3 data-update M N
S25 GetBRCBValues M Y
S26 SetBRCBValues M Y
Unbuffered report control block
S27 Report M Y
S27-1 data-change M Y
S27-2 qchg-change M N
S27-3 data-update M N
S28 GetURCBValues M Y
S29 SetURCBValues M Y
Logging
Log control block

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S30 GetLCBValues O N
S31 SetLCBValues O N
Log
S32 QueryLogByTime O N
S33 QueryLogAfter O N
S34 GetLogStatusValues O N
Generic substation event model (GSE)
GOOSE control block
S35 SendGOOSEMessage M Y
S36 GetGoReference O Y
S37 GetGOOSEElementNumber O N
S38 GetGoCBValues M Y
S39 SetGoCBValuess M N
Control
S51 Select O N
S52 SelectWithValue M Y
S53 Cancel M Y
S54 Operate M Y
S55 Command-Termination O Y
S56 TimeActivated-Operate O N
File transfer
S57 GetFile M/O Y
S58 SetFile O N
S59 DeleteFile O N
S60 GetFileAttributeValues M/O Y
Time
SNTP M Y
10.5.7 Logical Nodes

10.5.7.1 Logical Nodes Table
The relay support IEC61850 logical nodes as indicated in the following table. Note that the actual
instantiation of each logical node is determined by the product order code.
Nodes PCS-985GE
L: System Logical Nodes
LPHD: Physical device information YES
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10 Communication
Nodes PCS-985GE
LLN0: Logical node zero YES
P: Logical Nodes For Protection Functions
PDIF: Differential YES
PDIR: Direction comparison YES
PDIS: Distance YES
PDOP: Directional overpower YES
PDUP: Directional underpower YES
PFRC: Rate of change of frequency －
PHAR: Harmonic restraint －
PHIZ: Ground detector －
PIOC: Instantaneous overcurrent YES
PMRI: Motor restart inhibition －
PMSS: Motor starting time supervision －
POPF: Over power factor －
PPAM: Phase angle measuring －
PSCH: Protection scheme －
PSDE: Sensitive directional earth fault －
PTEF: Transient earth fault －
PTOC: Time overcurrent YES
PTOF: Overfrequency YES
PTOV: Overvoltage YES
PTRC: Protection trip conditioning YES
PTTR: Thermal overload YES
PTUC: Undercurrent －
PTUV: Undervoltage YES
PUPF: Underpower factor －
PTUF: Underfrequency YES
PVOC: Voltage controlled time overcurrent YES
PVPH: Volts per Hz YES
PZSU: Zero speed or underspeed －
R: Logical Nodes For Protection Related Functions
RDRE: Disturbance recorder function YES
RADR: Disturbance recorder channel analogue －
RBDR: Disturbance recorder channel binary －
RDRS: Disturbance record handling －

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Nodes PCS-985GE
RBRF: Breaker failure YES
RDIR: Directional element YES
RFLO: Fault locator －
RPSB: Power swing detection/blocking －
RREC: Autoreclosing －
RSYN: Synchronism-check or synchronizing －
C: Logical Nodes For Control
CALH: Alarm handling －
CCGR: Cooling group control －
CILO: Interlocking －
CPOW: Point-on-wave switching －
CSWI: Switch controller －
G: Logical Nodes For Generic References
GAPC: Generic automatic process control －
GGIO: Generic process I/O YES
GSAL: Generic security application －
I: Logical Nodes For Interfacing And Archiving
IARC: Archiving －
IHMI: Human machine interface －
ITCI: Telecontrol interface －
ITMI: Telemonitoring interface －
A: Logical Nodes For Automatic Control
ANCR: Neutral current regulator －
ARCO: Reactive power control －
ATCC: Automatic tap changer controller －
AVCO: Voltage control －
M: Logical Nodes For Metering And Measurement
MDIF: Differential measurements YES
MHAI: Harmonics or interharmonics －
MHAN: Non phase related harmonics or interharmonic －
MMTR: Metering －
MMXN: Non phase related measurement YES
MMXU: Measurement YES
MSQI: Sequence and imbalance YES
MSTA: Metering statistics －
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Nodes PCS-985GE
S: Logical Nodes For Sensors And Monitoring
SARC: Monitoring and diagnostics for arcs －
SIMG: Insulation medium supervision (gas) －
SIML: Insulation medium supervision (liquid) －
SPDC: Monitoring and diagnostics for partial discharges －
X: Logical Nodes For Switchgear
TCTR: Current transformer YES
TVTR: Voltage transformer YES
Y: Logical Nodes For Power Transformers
YEFN: Earth fault neutralizer (Peterson coil) －
YLTC: Tap changer －
YPSH: Power shunt －
YPTR: Power transformer YES
Z: Logical Nodes For Further Power System Equipment
ZAXN: Auxiliary network －
ZBAT: Battery －
ZBSH: Bushing －
ZCAB: Power cable －
ZCAP: Capacitor bank －
ZCON: Converter －
ZGEN: Generator YES
ZGIL: Gas insulated line －
ZLIN: Power overhead line －
ZMOT: Motor －
ZREA: Reactor －
ZRRC: Rotating reactive component －
ZSAR: Surge arrestor －
ZTCF: Thyristor controlled frequency converter －
ZTRC: Thyristor controlled reactive component －
10.6 DNP3.0 Interface
10.6.1 Overview
The descriptions given here are intended to accompany this relay. The DNP3.0 protocol is not
described here; please refer to the DNP3.0 protocol standard for the details about the DNP3.0

Date: 2016-08-16
10 Communication
implementation. This manual only specifies which objects, variations and qualifiers are supported
in this relay, and also specifies what data is available from this relay via DNP3.0.
The relay operates as a DNP3.0 slave and supports subset level 3 of the protocol, plus some of
the features from level 4. The DNP3.0 communication uses the Ethernet ports (electrical or optical)
at the rear side of this relay.
10.6.2 Link Layer Functions

Please see the DNP3.0 protocol standard for the details about the linker layer functions.
10.6.3 Transport Functions

Please see the DNP3.0 protocol standard for the details about the transport functions.
10.6.4 Application Layer Functions

10.6.4.1 Function Code
Function Code Function

0 (0x00) Confirm
1 (0x01) Read
2 (0x02) Write
3 (0x03) Select
4 (0x04) Operate
5 (0x05) Direct Operate
6 (0x06) Direct Operate No Acknowledgment
13 (0x0D) Cold Restart
14 (0x0E) Warm Restart
20 (0x14) Enable Unsolicited Responses
21 (0x15) Disable Unsolicited Responses
22 (0x16) Assign Class
23 (0x17) Delay Measurement
10.6.4.2 Supported Object List
The supported object groups and object variations are show in the following table.
Request: Master may issue/Outstation shall parse
Function code: decimalism
Qualifier code: hexadecimal
OBJECT GROUP & VARIATION REQUEST

Group/Variation
Description Function code Qualifier code
No.
1 (read) 00, 01 (start ~ stop)
1 0 Binary Input: Any Variation
22 (assign class) 06 (no range, or all)
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10 Communication

Group/Variation
No.
00, 01 (start ~ stop)
1 1 Binary Input: Packed format 1 (read)
06 (no range, or all)
1 2 Binary Input: With flags 1 (read)
2 0 Binary Input Event: Any Variation 1 (read)
07, 08 (limited qty)
2 1 Binary Input Event: Without time 1 (read)
2 2 Binary Input Event: With absolute time 1 (read)
2 3 Binary Input Event: With relative time 1 (read)
10 0 Binary output: Any Variation 1 (read)
10 0 Binary output: Any Variation 1 (read)
10 1 Binary output: Packed format 2 (write) 00, 01 (start ~ stop)
3 (select)
Binary Command: Control relay output block 4 (operate) 17, 28 (index)
12 1
(CROB) 5 (direct op)
6 (dir. op, no ack) 17, 28 (index)
1 (read) 00, 01 (start ~ stop)
30 0 Analog Input: Any Variation
22 (assign class) 06 (no range, or all)
30 1 Analog Input: 32 ~ bit with flag 1 (read)
30 2 Analog Input: 16 ~ bit with flag 1 (read)
30 3 Analog Input: 32 ~ bit without flag 1 (read)
30 4 Analog Input: 16 ~ bit without flag 1 (read)
30 5 Analog Input: Single ~ prec flt ~ pt with flag 1 (read)
32 0 Analog Input Event: Any Variation 1 (read)
07,08 (limited qty)
32 1 Analog Input Event: 32 ~ bit without time 1 (read)
07,08 (limited qty)
32 2 Analog Input Event: 16 ~ bit without time 1 (read)
07,08 (limited qty)

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Group/Variation
No.
Analog Input Event: Single ~ prec flt ~ pt 06 (no range, or all)
32 5 1 (read)
without time 07,08 (limited qty)
34 0 Analog Input Deadband: Any Variation 1 (read)
1 (read)
34 1 Analog Input Deadband: 16 ~ bit
2 (write)
17,28 (index)
1 (read)
2 (write)
17,28 (index)
1 (read)
34 3 Analog Input Deadband: Single ~ prec flt ~ pt
2 (write)
17,28 (index)
40 0 Analog Output Status: Any Variation 1 (read)
40 1 Analog Output Status: 32 ~ bit with flag 1 (read)
40 2 Analog Output Status: 16 ~ bit with flag 1 (read)
Analog Output Status: single ~ prec flt ~ pt with 00, 01 (start ~ stop)
40 3 1 (read)
flag 06 (no range, or all)
3 (select)
4 (operate) 17,28 (index)
41 1 Analog Output: 32 ~ bit
5 (direct op)
6 (dir. Op, no ack) 17,28 (index)
3 (select)
41 2 Analog Output: 16 ~ bit
5 (direct op)
3 (select)
41 3 Analog Output: Single ~ prec ft ~ pt
5 (direct op)
1 (read) 07 (limited qty = 1)
50 1 Time and Data: Absolute time
2 (write) 07 (limited qty = 1)
Time and Data: Absolute time at last recorded
50 3 2 (write) 07 (limited qty = 1)
time
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Group/Variation
No.
Time and Data CTO: Absolute time,
51 1
synchronized
Time and Data CTO: Absolute time,
51 2
unsynchronized
1 (read)
60 1 Class Objects: Class 0 data 06 (no range, or all)
22 (assign class)
1 (read)
07,08 (limited qty)
60 2 Class Objects: Class 1 data 20 (enable unsol.)
21 (disable unsol.) 06 (no range, or all)
22 (assign class)
1 (read)
07,08 (limited qty)
60 3 Class Objects: Class 2 data 20 (enable unsol.)
22 (assign class)
1 (read)
07,08 (limited qty)
60 4 Class Objects : Class 3 data 20 (enable unsol.)
22 (assign class)
Response: Master shall parse\Outstation may issue
Function code: decimalism
Qualifier code: hexadecimal
OBJECT GROUP & VARIATION RESPONSE

Group/Variation
No.
1 0 Binary Input: Any Variation
1 1 Binary Input: Packed format 129 (response) 00, 01 (start ~ stop)
1 2 Binary Input: With flags 129 (response) 00, 01 (start ~ stop)
2 0 Binary Input Event: Any Variation
129 (response)
2 1 Binary Input Event: Without time 17, 28 (index)
130 (unsol. resp)
129 (response)
2 2 Binary Input Event: With absolute time 17, 28 (index)
130 (unsol. resp)
129 (response)
2 3 Binary Input Event: With relative time 17, 28 (index)
130 (unsol. resp)
10 0 Binary output: Any Variation

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Group/Variation
No.
10 0 Binary output: Any Variation
10 1 Binary output: Packed format
Binary Command: Control relay output block 129 (response) echo of request
12 1
(CROB)
30 0 Analog Input: Any Variation
30 1 Analog Input: 32 ~ bit with flag 129 (response) 00, 01 (start ~ stop)
30 2 Analog Input: 16 ~ bit with flag 129 (response) 00, 01 (start ~ stop)
30 3 Analog Input: 32 ~ bit without flag 129 (response) 00, 01 (start ~ stop)
30 4 Analog Input: 16 ~ bit without flag 129 (response) 00, 01 (start ~ stop)
30 5 Analog Input: Single ~ prec flt ~ pt with flag 129 (response) 00, 01 (start ~ stop)
32 0 Analog Input Event: Any Variation
129 (response)
32 1 Analog Input Event: 32 ~ bit without time 17,28 (index)
130 (unsol. resp)
129 (response)
32 2 Analog Input Event: 16 ~ bit without time 17,28 (index)
130 (unsol. resp)
Analog Input Event: Single ~ prec flt ~ pt without 129 (response)
32 5 17,28 (index)
time 130 (unsol. resp)
34 0 Analog Input Deadband: Any Variation
129 (response) 00, 01 (start ~ stop)


34 3 Analog Input Deadband: Single ~ prec flt ~ pt
40 0 Analog Output Status: Any Variation

40 1 Analog Output Status: 32 ~ bit with flag 129 (response) 00, 01 (start ~ stop)
40 2 Analog Output Status: 16 ~ bit with flag 129 (response) 00, 01 (start ~ stop)
Analog Output Status: single ~ prec flt ~ pt with
40 3 129 (response) 00, 01 (start ~ stop)
flag
Analog Output: 129 (response) echo of request
41 1
32 ~ bit
41 2
16 ~ bit
41 3
Single ~ prec ft ~ pt
129 (response) 07 (limited qty = 1)
50 1 Time and Data: Absolute time
Time and Data: Absolute time at last recorded

50 3
time
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10 Communication

Group/Variation
No.
Time and Data CTO: Absolute time, 129 (response)
51 1 07 (limited qty = 1)
synchronized 130 (unsol. resp)
Time and Data CTO: Absolute time, 129 (response)
51 2 07 (limited qty = 1)
unsynchronized 130 (unsol. resp)
60 1 Class Objects: Class 0 data
60 4 Class Objects : Class 3 data
10.6.4.3 Communication Table Configuration
This relay now supports 4 Ethernet clients and 2 serial port clients. Each client can be set the DNP
related communication parameters respectively and be selected the user-defined communication
table. This relay supports a default communication table and 4 user-defined communication tables,
and the default communication table is fixed by the manufacturer and not permitted to configure by
the user.
The user can configure the user-defined communication table through the PCS-Explorer2
configuration tool auxiliary software. The object groups “Binary Input”, “Binary Output”, “Analog
Input” and “Analog Output” can be configured according to the practical engineering demand.
10.6.4.4 Analog Input and Output Configuration
To the analog inputs, the attributes “deadband” and “factor” of each analog input can be configured
independently. To the analog outputs, only the attribute “factor” of each analog output needs to be
configured. If the integer mode is adopted for the data formats of analog values (to “Analog Input”,
“Object Variation” is 1, 2 and 3; to “Analog Output”, “Object Variation” is 1 and 2.), the analog
values will be multiplied by the “factor” respectively to ensure their accuracy. And if the float mode
is adopted for the data formats of analog values, the actual float analog values will be sent directly.
The judgment method of the analog input change is as below: Calculate the difference between
the current new value and the stored history value and make the difference value multiply by the
“factor”, then compare the result with the “deadband” value. If the result is greater than the
“deadband” value, then an event message of corresponding analog input change will be created.
In normal communication process, the master can online read or modify a “deadband” value by
reading or modifying the variation in “Group34”.
10.6.4.5 Binary Output Configuration
The remote control signals, logic links and external extended output commands can be configured
into the “Binary Output” group. The supported control functions are listed as below.

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10 Communication
Information Point Pulse On/Null Pulse On/Close Pulse On/Trip Latch On/Null Latch Off/Null
Remote Control Not supported Close Trip Close Trip
Logic Link Not supported Set Clear Set Clear
Extended Output See following description
To an extended output command, if a selected command is controlled remotely, this command

point will output a high ~ level pulse. The pulse width can be decided by the “On ~ time” in the
related “Binary Command” which is from the DNP3.0 master. If the “On ~ time” is set as “0”, the
default pulse width is 500ms.
10.6.4.6 Unsolicited Messages
This relay does not transmit the unsolicited messages if the related logic setting is set as “0”. If the
unsolicited messages want to be transmitted, the related logic setting should be set as “1” or the
DNP3.0 master will transmit “Enable Unsolicited” command to this relay through “Function Code
20” (Enable Unsolicited Messages). If the “Binary Input” state changes or the difference value of
the “Analog Input” is greater than the “deadband” value, this device will transmit unsolicited
messages. If the DNP3.0 master needs not to receive the unsolicited messages, it should forbid
this relay to transmit the unsolicited messages by setting the related logic setting as “0” or through
the “Function Code 21” (Disable Unsolicited Messages).
10.6.4.7 Class Configuration
If the DNP3.0 master calls the Class0 data, this relay will transmit all actual values of the “Analog
Input”, “Binary Input” and “Analog Output”. The classes of the “Analog Input” and “Binary Input”
can be defined by modifying relevant settings. In communication process, the DNP3.0 master can
online modify the class of an “Analog Input” or a “Binary Input” through “Function Code 22” (Assign
Class).
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11 Installation
11 Installation
Table of Contents
11 Installation ...................................................................................... 11-a
11.1 Overview ....................................................................................................... 11-1
11.2 Safety Information ........................................................................................ 11-1
11.3 Check the Shipment ..................................................................................... 11-2
11.4 Material and Tools Required ........................................................................ 11-2
11.5 Device Location and Ambient Conditions .................................................. 11-2
11.6 Mechanical Installation ................................................................................ 11-3
11.7 Electrical Installation and Wiring ................................................................ 11-4
11.7.1 Grounding Guidelines .......................................................................................................11-4
11.7.2 Cubicle Grounding ............................................................................................................11-4
11.7.3 Ground Connection on the Device ...................................................................................11-5
11.7.4 Grounding Strips and their Installation ..............................................................................11-5
11.7.5 Guidelines for Wiring.........................................................................................................11-6
11.7.6 Wiring for Electrical Cables ...............................................................................................11-6
List of Figures
Figure 11.6-1 Dimensions and panel cut-out of PCS-985GE ................................................ 11-3
Figure 11.6-2 Demonstration of plugging a board into its corresponding slot .................. 11-3
Figure 11.7-1 Cubicle grounding system ................................................................................ 11-5
Figure 11.7-2 Ground terminal of this device ......................................................................... 11-5
Figure 11.7-3 Ground strip and termination ........................................................................... 11-6
Figure 11.7-4 Glancing demo about the wiring for electrical cables ................................... 11-7

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11 Installation
11.1 Overview
The device must be shipped, stored and installed with the greatest care.
Choose the place of installation such that the communication interface and the controls on the
front of the device are easily accessible.
Air must circulate freely around the device. Observe all the requirements regarding place of
installation and ambient conditions given in this instruction manual.
Take care that the external wiring is properly brought into the device and terminated correctly and
pay special attention to grounding. Strictly observe the corresponding guidelines contained in this
section.
11.2 Safety Information

Modules and units may only be replaced by correspondingly trained personnel. Always observe
the basic precautions to avoid damage due to electrostatic discharge when handling the device.
In certain cases, the settings have to be configured according to the demands of the engineering
configuration after replacement. It is therefore assumed that the personnel who replace modules
and units are familiar with the use of the operator program on the service PC.
WARNING!
ONLY insert or withdraw a module while the device power supply is switched off. To this
end, disconnect the power supply cable that connects with the PWR module.
NOTICE!
Industry packs and ribbon cables may ONLY be replaced on a workbench for electronic
equipment. Electronic components are sensitive to electrostatic discharge when not in
the unit's housing.
NOTICE!
Jumper links may ONLY be changed on a workbench for electronic equipment.

Electronic components are sensitive to electrostatic discharge when not in the unit's
housing.
NOTICE!
A module can ONLY be inserted in the slot designated in the chapter 6. Components
can be damaged or destroyed by inserting module in a wrong slot.
The basic precautions to guard against electrostatic discharge are as follows:
 Should boards have to be removed from this device installed in a grounded cubicle in an HV
switchgear installation, please discharge yourself by touching station ground (the cubicle)
beforehand.

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11 Installation
 Only hold electronic boards at the edges, taking care not to touch the components.
 Only works on the board which has been removed from the cubicle on a workbench designed
for electronic equipment and wear a grounded wristband. Do not wear a grounded wristband,
however, while inserting or withdrawing units.
 Always store and ship the electronic boards in their original packing. Place electronic parts in
electrostatic screened packing materials.
11.3 Check the Shipment

Check that the consignment is complete immediately upon receipt. Notify the nearest NR
Company or agent, should departures from the delivery note, the shipping papers or the order be
found.
Visually inspect all the material when unpacking it. When there is evidence of transport damage,
lodge a claim immediately in writing with the last carrier and notify the nearest NR Company or
agent.
If the equipment is not going to be installed immediately, store all the parts in their original packing
in a clean dry place at a moderate temperature. The humidity at a maximum temperature and the
permissible storage temperature range in dry air are listed in Chapter “Technical Data”.
11.4 Material and Tools Required

The necessary mounting kits will be provided, including screws, pincers and assembly
instructions.
A suitable drill and spanners are required to secure the cubicles to the floor using the plugs
provided (if this device is mounted in cubicles).
11.5 Device Location and Ambient Conditions

NOTICE!
Excessively high temperature can appreciably reduce the operating life of this device.
The place of installation should permit easy access especially to front of the device, i.e. to the
human machine interface of the equipment.
There should also be free access at the rear of the equipment for additions and replacement of
electronic boards.
Since every piece of technical equipment can be damaged or destroyed by inadmissible ambient
conditions, such as:
1. The location should not be exposed to excessive air pollution (dust, aggressive substances).
2. Surge voltages of high amplitude and short rise time, extreme changes of temperature, high
levels of humidity, severe vibration and strong induced magnetic fields should be avoided as
far as possible.
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3. Air must not be allowed to circulate freely around the equipment.
The equipment can in principle be mounted in any attitude, but it is normally mounted vertically
(visibility of markings).
11.6 Mechanical Installation

NOTICE!
It is necessary to leave enough space top and bottom of the cut-out in the cubicle for
heat emission of this device.
The device is made of one 4U height 19" chassis with 8 connectors on its rear panel. Following
figure shows the dimensions and cut-out size in the cubicle of this device for reference in
mounting.
482.6 (290.0)
465.0
101.6
177.0
465.0±0.2
+0.4
451.0 -0.0
4-Φ6.8
+0.4
179.0 -0.0
101.6±0.1
Figure 11.6-1 Dimensions and panel cut-out of PCS-985GE
Following figure shows the installation way of a module being plugged into a corresponding slot.
Figure 11.6-2 Demonstration of plugging a board into its corresponding slot

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11 Installation
In the case of equipment supplied in cubicles, place the cubicles on the foundations that have
been prepared. Take care while doing so not to jam or otherwise damage any of the cables that
have already been installed. Secure the cubicles to the foundations.
11.7 Electrical Installation and Wiring

11.7.1 Grounding Guidelines
NOTICE!
All these precautions can only be effective if the station ground is of good quality.
Switching operations in HV installations generate transient over voltages on control signal cables.
There is also a background of electromagnetic RF fields in electrical installations that can induce
spurious currents in the devices themselves or the leads connected to them.
All these influences can influence the operation of electronic apparatus.
On the other hand, electronic apparatus can transmit interference that can disrupt the operation of
other apparatus.
In order to minimize these influences as far as possible, certain standards have to be observed
with respect to grounding, wiring and screening.
11.7.2 Cubicle Grounding

The cubicle must be designed and fitted out such that the impedance for RF interference of the
ground path from the electronic device to the cubicle ground terminal is as low as possible.
Metal accessories such as side plates, blanking plates etc., must be effectively connected
surface-to-surface to the grounded frame to ensure a low-impedance path to ground for RF
interference. The contact surfaces must not only conduct well, they must also be non-corroding.
NOTICE!
If the above conditions are not fulfilled, there is a possibility of the cubicle or parts of it
forming a resonant circuit at certain frequencies that would amplify the transmission of
interference by the devices installed and also reduce their immunity to induced
interference.
Movable parts of the cubicle such as doors (front and back) or hinged equipment frames must be
effectively grounded to the frame by three braided copper strips (see Figure 11.7-1).
The metal parts of the cubicle housing and the ground rail are interconnected electrically
conducting and corrosion proof. The contact surfaces shall be as large as possible.
NOTICE!
For metallic connections please observe the voltage difference of both materials
according to the electrochemical code.
The cubicle ground rail must be effectively connected to the station ground rail by a
grounding strip (braided copper).
Date: 2016-08-16
11 Installation
Door or hinged
equipment frame
Cubicle ground
rail close to floor
Braided
copper strip
Station
ground
Conducting
connection
Figure 11.7-1 Cubicle grounding system
11.7.3 Ground Connection on the Device

There is a ground terminal on the rear panel, and the ground braided copper strip can be
connected with it. Take care that the grounding strip is always as short as possible. The main thing
is that the device is only grounded at one point. Grounding loops from unit to unit are not allowed.
There are some ground terminals on some connectors of this device, and the sign is “GND”. All the
ground terminals are connected in the cabinet of this device. Therefore, the ground terminal on the
rear panel (see Figure 11.7-2) is the only ground terminal of this device.
Figure 11.7-2 Ground terminal of this device
11.7.4 Grounding Strips and their Installation

High frequency currents are produced by interference in the ground connections and because of
skin effect at these frequencies, only the surface region of the grounding strips is of consequence.
The grounding strips must therefore be of (preferably tinned) braided copper and not round copper
conductors, as the cross-section of round copper would have to be too large.
Proper terminations must be fitted to both ends (press/pinch fit and tinned) with a hole for bolting
them firmly to the items to be connected.

Date: 2016-08-16
11 Installation
The surfaces to which the grounding strips are bolted must be electrically conducting and
non-corroding.
The following figure shows the ground strip and termination.
Press/pinch fit
cable terminal
Braided
copper strip Terminal bolt
Contact surface
Figure 11.7-3 Ground strip and termination
11.7.5 Guidelines for Wiring
There are several types of cables that are used in the connection of this device: braided copper
cable, serial communication cable etc. Recommendation of each cable:
 Grounding: braided copper cable, 2.5mm 2 ~ 6.0mm 2
 Power supply, binary inputs & outputs: brained copper cable, 1.0mm 2 ~ 2.5mm 2
 AC voltage inputs: brained copper cable, 1.0mm 2 ~ 2.5mm 2
 AC current inputs: brained copper cable, 1.5mm 2 ~ 4.0mm 2
 Serial communication: 4-core shielded braided cable
 Ethernet communication: 4-pair shielded twisted category 5E cable
11.7.6 Wiring for Electrical Cables
DANGER!
NEVER allow a open current transformer (CT) secondary circuit connected to this
device while the primary system is live. Open CT circuit will produce a dangerously high
voltage that cause death.
A female connector is used for connecting the wires with it, and then a female connector plugs into
a corresponding male connector that is in the front of one board. See Chapter “Hardware” for
further details about the pin defines of these connectors.
The following figure shows the glancing demo about the wiring for the electrical cables.
Date: 2016-08-16
11 Installation
01 02
03 04
Tighten 05 06
07 08
09 10
11 12
01
13 14
15 16
17 18
19 20
21 22
23 24
Figure 11.7-4 Glancing demo about the wiring for electrical cables

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11 Installation
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12 Commissioning
12 Commissioning
Table of Contents
12 Commissioning ............................................................................ 12-a
12.1 Overview ...................................................................................................... 12-1
12.2 Safety Instructions ...................................................................................... 12-1
12.3 Commission Tools ...................................................................................... 12-1
12.4 Setting Familiarization ................................................................................ 12-2
12.5 Product Checks ........................................................................................... 12-2
12.5.1 With the Device De-energized ......................................................................................... 12-3
12.5.2 With the Device Energized .............................................................................................. 12-5
12.5.3 On-load Checks ............................................................................................................... 12-6
12.6 Final Checks ................................................................................................ 12-7

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12 Commissioning
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12 Commissioning
12.1 Overview
This device is numerical in their design, implementing all functions in software. The device
employs a high degree self-checking, so in the unlikely event of a failure, it will give an alarm.
Blank commissioning test and setting records are provided at the end of this manual for
completion as required.
Before carrying out any work on the device, the user should be familiar with the contents of the
safety and technical data sections and the ratings on the device’s rating label.
12.2 Safety Instructions
DANGER!
Current transformer secondary circuits MUST be short-circuited BEFORE the current

leads to the device are disconnected.
WARNING!
ONLY qualified personnel should work on or in the vicinity of this device. This
personnel MUST be familiar with all safety regulations and service procedures
described in this manual. During operating of electrical device, certain part of the
device is under high voltage. Severe personal injury and significant device damage
could result from improper behavior.
Particular attention must be drawn to the following:
 The earthing screw of the device must be connected solidly to the protective earth conductor
before any other electrical connection is made.
 Hazardous voltages can be present on all circuits and components connected to the supply
voltage or to the measuring and test quantities.
 Hazardous voltages can be present in the device even after disconnection of the supply
voltage (storage capacitors!).
 The limit values stated in the Chapter “Technical Data” must not be exceeded at all, not even
during testing and commissioning.
 When testing the device with secondary test equipment, make sure that no other
measurement quantities are connected. Take also into consideration that the trip circuits and
may be close commands to the circuit breakers and other primary switches are disconnected
from the device unless expressly stated.
12.3 Commission Tools

Minimum equipment required:

Date: 2016-08-16
12 Commissioning
NOTICE!
Modern test set may contain many of the above features in one unit.
 Multifunctional dynamic current and voltage injection test set with interval timer.
 Multimeter with suitable AC current range and AC/DC voltage ranges of 0~440V and 0~250V
respectively.
 Continuity tester (if not included in the multimeter).
 Phase angle meter.
 Phase rotation meter.
Optional equipment:
 An electronic or brushless insulation tester with a DC output not exceeding 500V (for
insulation resistance test when required).
 A portable PC, with appropriate software (this enables the rear communications port to be
tested, if this is to be used, and will also save considerable time during commissioning).
 EIA RS-485 to EIA RS-232 converter (if EIA RS-485 IEC60870-5-103 port is being tested).
 Tester: HELP-9000.
12.4 Setting Familiarization

When commissioning this device for the first time, sufficient time should be allowed to become
familiar with the method by which the settings are applied. A detailed description of the menu
structure of this device is contained in Chapter “Operation Theory” and Chapter “Settings”.
With the front cover in place all keys are accessible. All menu cells can be read. The LED
indicators and alarms can be reset. Protection or configuration settings can be changed, or fault
and event records cleared. However, menu cells will require the appropriate password to be
entered before changes can be made.
Alternatively, if a portable PC is available together with suitable setting software (such as

PCS-9700 HMI software), the menu can be viewed one page at a time to display a full column of
data and text. This PC software also allows settings to be entered more easily, saved to a file on
disk for future reference or printed to produce a setting record. Refer to the PC software user
manual for details. If the software is being used for the first time, allow sufficient time to become
familiar with its operation.
12.5 Product Checks

These product checks cover all aspects of the device which should be checked to ensure that it
has not been physically damaged prior to commissioning, is functioning correctly and all input
quantity measurements are within the stated tolerances.
If the application-specific settings have been applied to the device prior to commissioning, it is
Date: 2016-08-16
12 Commissioning
advisable to make a copy of the settings so as to allow them restoration later. This could be done
by extracting the settings from the device itself via printer or manually creating a setting record.
12.5.1 With the Device De-energized
This device is fully numerical and the hardware is continuously monitored. Commissioning tests
can be kept to a minimum and need only include hardware tests and conjunctive tests. The
function tests are carried out according to user’s correlative regulations.
The following tests are necessary to ensure the normal operation of the equipment before it is first
put into service.
 Hardware tests
These tests are performed for the following hardware to ensure that there is no hardware
defect. Defects of hardware circuits other than the following can be detected by
self-monitoring when the DC power is supplied.
 User interfaces test
 Binary input circuits and output circuits test
 AC input circuits test
 Function tests
These tests are performed for the following functions that are fully software-based.
 Measuring elements test
 Timers test
 Conjunctive tests
The tests are performed after the device is connected with the primary equipment and other
external equipment.
 On load test.
 Phase sequence check and polarity check.
12.5.1.1 Visual Inspection
After unpacking the product, check for any damage to the device case. If there is any damage, the
internal module might also have been affected, contact the vendor. The following items listed are
necessary.
 Device panel
Carefully examine the device panel, device inside and other parts inside to see that no
physical damage has occurred since installation.
 Panel wiring
Check the conducting wire which is used in the panel to assure that their cross section

Date: 2016-08-16
12 Commissioning
meeting the requirement.
Carefully examine the wiring to see that they are no connection failure exists.
 Device plug-in modules
Check each plug-in module of the equipment on the panel to make sure that they are well
installed into the equipment without any screw loosened.
 Earthing cable
Check whether the earthing cable from the panel terminal block is safely screwed to the panel
steel sheet.
 Switch, keypad, isolator binary inputs and push button
Check whether all the switches, equipment keypad, isolator binary inputs and push buttons
work normally and smoothly.
12.5.1.2 Insulation Test (if required)
Insulation resistance tests are only necessary during commissioning if it is required for them to be
done and they have not been performed during installation.
Isolate all wiring from the earth and test the isolation with an electronic or brushless insulation
tester at a DC voltage not exceeding 500V, The circuits need to be tested should include:
 Voltage transformer circuits
 Current transformer circuits
 DC power supply
 Optic-isolated control inputs
 Output contacts
 Communication ports
The insulation resistance should be greater than 100MΩ at 500V.
Test method:
To unplug all the terminals sockets of this device, and do the Insulation resistance test for each
circuit above with an electronic or brushless insulation tester.
On completion of the insulation resistance tests, ensure all external wiring is correctly
reconnected to the device.
12.5.1.3 External Wiring
Check that the external wiring is correct to the relevant device diagram and scheme diagram.
Ensure as far as practical that phasing/phase rotation appears to be as expected.
Check the wiring against the schematic diagram for the installation to ensure compliance with the
customer’s normal practice.
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12 Commissioning
12.5.1.4 Auxiliary Power Supply
WARNING!
Energize this device ONLY if the power supply is within the specified operating range in
the Chapter “Technical Data”.
The device only can be operated under the auxiliary power supply depending on the device’s
nominal power supply rating.
The incoming voltage must be within the operating range specified in Chapter “Technical Data”,
before energizing the device, measure the auxiliary supply to ensure it within the operating range.
Other requirements to the auxiliary power supply are specified in Chapter “Technical Data”. See
this section for further details about the parameters of the power supply.
12.5.2 With the Device Energized
The following groups of checks verify that the device hardware and software is functioning
correctly and should be carried out with the auxiliary supply applied to the device.
The current and voltage transformer connections must remain isolated from the device for these
checks. The trip circuit should also remain isolated to prevent accidental operation of the
associated circuit breaker.
12.5.2.1 Front Panel LCD Display
Connect the device to DC power supply correctly and turn the device on. Check program version
and forming time displayed in command menu to ensure that are corresponding to what ordered.
12.5.2.2 Date and Time
If the time and date is not being maintained by substation automation system, the date and time
should be set manually.
Set the date and time to the correct local time and date using menu item “Clock”.
In the event of the auxiliary supply failing, with a battery fitted on CPU board, the time and date
will be maintained. Therefore when the auxiliary supply is restored the time and date will be
correct and not need to set again.
To test this, remove the auxiliary supply from the device for approximately 30s. After being
re-energized, the time and date should be correct.
12.5.2.3 Light Emitting Diodes (LEDs)
On power up, the green LED “HEALTHY” should have illuminated and stayed on indicating that
the device is healthy.
The device has latched signal devices which remember the state of the trip, auto-reclose when
the device was last energized from an auxiliary supply. Therefore these indicators may also
illuminate when the auxiliary supply is applied. If any of these LEDs are on then they should be

Date: 2016-08-16
12 Commissioning
reset before proceeding with further testing. If the LED successfully reset, the LED goes out.
There is no testing required for that that LED because it is known to be operational.
It is likely that alarms related to voltage transformer supervision will not reset at this stage.
12.5.2.4 Testing HEALTHY and ALARM LEDs
Apply the rated DC power supply and check that the “HEALTHY” LED is lighting in green. We
need to emphasize that the “HEALTHY” LED is always lighting in operation course except that the
equipment find serious errors in it.
Produce one of the abnormal conditions listed in Chapter “Supervision”, the “ALARM” LED will
light in yellow. When abnormal condition reset, the “ALARM” LED extinguishes.
12.5.2.5 Testing AC Current Inputs
NOTICE!
The closing circuit should remain isolated during these checks to prevent accidental
operation of the associated circuit breaker.
This test verified that the accuracy of current measurement is within the acceptable tolerances.
Apply rated current to each current transformer input in turn; checking its magnitude using a
multimeter/test set readout. The corresponding reading can then be checked in the devices menu.
12.5.2.6 Testing AC Voltage Inputs
NOTICE!
The closing circuit should remain isolated during these checks to prevent accidental
operation of the associated circuit breaker.
This test verified that the accuracy of voltage measurement is within the acceptable tolerances.
Apply rated voltage to each voltage transformer input in turn; checking its magnitude using a
multimeter/test set readout. The corresponding reading can then be checked in the devices menu.
12.5.2.7 Testing Binary Inputs
This test checks that all the binary inputs on the equipment are functioning correctly.
The binary inputs should be energized one at a time, see external connection diagrams for
terminal numbers.
Ensure that the voltage applied on the binary input must be within the operating range.
The status of each binary input can be viewed using device menu. Sign “1” denotes an energized
input and sign “0” denotes a de-energized input.
12.5.3 On-load Checks
The objectives of the on-load checks are:
1. Confirm the external wiring to the current and voltage inputs is correct.
Date: 2016-08-16
12 Commissioning
2. Measure the magnitude of on-load current and voltage (if applicable).
3. Check the polarity of each current transformer.
However, these checks can only be carried out if there are no restrictions preventing the
tenderization of the plant being protected.
Remove all test leads, temporary shorting leads, etc. and replace any external wiring that has
been removed to allow testing.
If it has been necessary to disconnect any of the external wiring from the device in order to
perform any of the foregoing tests, it should be ensured that all connections are replaced in
accordance with the relevant external connection or scheme diagram. Confirm current and
voltage transformer wiring.
12.6 Final Checks

After the above tests are completed, remove all test or temporary shorting leads, etc. If it has been
necessary to disconnect any of the external wiring from the device in order to perform the wiring
verification tests, it should be ensured that all connections are replaced in accordance with the
relevant external connection or scheme diagram.
Ensure that the device has been restored to service.
If the device is in a new installation or the circuit breaker has just been maintained, the circuit
breaker maintenance and current counters should be zero. If a test block is installed, remove the
test plug and replace the cover so that the device is put into service.
Ensure that all event records, fault records and alarms have been cleared and LED’s has been
reset before leaving the device.

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12 Commissioning
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13 Maintenance
13 Maintenance
Table of Contents
13 Maintenance .................................................................................. 13-a
13.1 Appearance Check ...................................................................................... 13-1
13.2 Failure Tracing and Repair ......................................................................... 13-1
13.3 Replace Failed Modules ............................................................................. 13-2
13.4 Cleaning ....................................................................................................... 13-3
13.5 Storage ......................................................................................................... 13-3

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13 Maintenance
Date: 2016-08-16
13 Maintenance
This device is designed to require no special maintenance. All measurement and signal
processing circuit are fully solid state. All input modules are also fully solid state. The output relays
are hermetically sealed.
Since the device is almost completely self-monitored, from the measuring inputs to the output
relays, hardware and software defects are automatically detected and reported. The
self-monitoring ensures the high availability of the device and generally allows for a corrective
rather than preventive maintenance strategy. Therefore, maintenance checks in short intervals are
not required.
Operation of the device is automatically blocked when a hardware failure is detected. If a problem
is detected in the external measuring circuits, the device normally only provides alarm messages.
13.1 Appearance Check

1. The device case should be clean without any dust stratification. Case cover should be sealed
well. No component has any mechanical damage and distortion, and they should be firmly
fixed in the case. Device terminals should be in good condition. The keys on the front panel
with very good feeling can be operated flexibly.
2. It is only allowed to plug or withdraw device board when the supply is reliably switched off.
Never allow the CT secondary circuit connected to this equipment to be opened while the
primary system is live when withdrawing an AC module. Never try to insert or withdraw the
device board when it is unnecessary.
3. Check weld spots on PCB whether they are well soldered without any rosin joint. All dual
inline components must be well plugged.
13.2 Failure Tracing and Repair

Failures will be detected by automatic supervision or regular testing.
When a failure is detected by supervision, a remote alarm is issued and the failure is indicated on
the front panel with LED indicators and LCD display. It is also recorded in the event record.
Failures detected by supervision are traced by checking the “Superv State” screen on the LCD.
When a failure is detected during regular testing, confirm the following:
1. Test circuit connections are correct
2. Modules are securely inserted in position
3. Correct DC power voltage is applied
4. Correct AC inputs are applied
5. Test procedures comply with those stated in the manual

Date: 2016-08-16
13 Maintenance
13.3 Replace Failed Modules
WARNING!
Module can ONLY be replaced while the device power supply is switched off.
ONLY appropriately trained and qualified personnel can perform the replacement by
strictly observing the precautions against electrostatic discharge.
WARNING!
Five seconds is NECESSARY for discharging the voltage. Hazardous voltage can be
present in the DC circuit just after switching off the DC power supply.
CAUTION!
Take anti-static measures such as wearing an earthed wristband and placing modules
on an earthed conductive mat when handling a module. Otherwise, electronic
components could be damaged.
CAUTION!
Check the device configuration after a replacement of module. Unintended operation of

device may occur.
If the failure is identified to be in the device module and the user has spare modules, the user can
recover the device by replacing the failed modules.
Repair at the site should be limited to module replacement. Maintenance at the component level is
not recommended.
Check that the replacement module has an identical module name (AI, PWR, MON, BI, BO, etc.)
and hardware type-form as the removed module. Furthermore, the MON module replaced should
have the same software version. In addition, the AI and PWR module replaced should have the
same ratings.
The module name is indicated on the top front of the module. The software version is indicated in
LCD menu “Information”->“Version Info”.
1) Replacing a module
 Switch off the DC power supply
 Disconnect the trip outputs
 Short circuit all AC current inputs and disconnect all AC voltage inputs
 Unscrew the module connector
 Unplug the connector from the target module.
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13 Maintenance
 Unscrew the module.
 Pull out the module
 Inset the replacement module in the reverser procedure.
 After replacing the MON module, input the application-specific setting values again.
2) Replacing the Human Machine Interface Module (front panel)
 Open the device front panel
 Unplug the ribbon cable on the front panel by pushing the catch outside.
 Detach the HMI module from the device
 Attach the replacement module in the reverse procedure.
13.4 Cleaning
Before cleaning the device, ensure that all AC/DC supplies, current transformer connections are
isolated to prevent any chance of an electric shock whilst cleaning. Use a smooth cloth to clean
the front panel. Do not use abrasive material or detergent chemicals.
13.5 Storage
The spare device or module should be stored in a dry and clean room. Based on IEC standard
60255-1 the storage temperature should be from -40°C to +70°C, but the temperature of from 0°C
to +40°C is recommended for long-term storage.

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13 Maintenance
Date: 2016-08-16
Table of Contents
14 Decommissioning and Disposal ................................................. 14-a
14.1 Decommissioning ....................................................................................... 14-1
14.2 Disposal ....................................................................................................... 14-1

Date: 2016-08-16
Date: 2016-08-16
14.1 Decommissioning
DANGER!
Switch OFF the circuit breaker for primary CTs and VTs BEFORE disconnecting the
cables of AI module.
WARNING!
Switch OFF the external miniature circuit breaker of device power supply BEFORE
disconnecting the power supply cable connected to the PWR module.
WARNING!
KEEP an adequate safety distance to live parts of the power substation.
1. Switching off
To switch off this device, switch off the external miniature circuit breaker of the power supply.
2. Disconnecting cables
Disconnect the cables in accordance with the rules and recommendations made by relational
department.
3. Dismantling
The device rack may now be removed from the system cubicle, after which the cubicles may
also be removed.
14.2 Disposal
NOTICE!
Strictly observe all local and national laws and regulations when disposing the device.

Date: 2016-08-16
Date: 2016-08-16

In the latest version of the instruction manual, several descriptions on existing features have been
modified.
Manual version and modification history records
Manual Version Software

Date Description of change
Source New Version
R1.00 R1.00 2016-03-18 Form the original manual.
1. Update the protective function table in Section 1.2.
2. Update the parameters in Section 2.10.5.
3. Update the protection theory and logic diagram
R1.00 R1.01 R1.11 2016-08-16
according to the lastest programe in Chapter 3.
4. Add new alarm signals in Section 4.2.
5. Update the hardware description in Section 6.4.
1. The terminal definition of NR1504 module is modified.
R1.01 R1.02 R1.11 2019-02-21
2. Chapter 9 is modified.

Date: 2019-02-21
Date: 2019-02-21

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Health and Safety

Qualified personnel are individuals who:

 Are trained in emergency procedures (first aid).

Instructions and Warnings

PCS-985GE Generator Relay i

Securely earthed the earthing terminal of the device.

ii PCS-985GE Generator Relay

 Printed circuit board

Carefully handle connection cables without applying excessive force.

The firmware may be upgraded to add new features or enhance/modify existing

Copyright © 2016 NR. All rights reserved.

We reserve the rights to make technical improvements without notice.

NR ELECTRIC CO., LTD. Tel: +86-25-87178888

P/N: ZL_PCS-985GE_X_Instruction Manual_EN_Overseas General_X Version: R1.02

PCS-985GE Generator Relay iii

All contents provided by this manual are summarized as below:

8 Human Machine Interface

iv PCS-985GE Generator Relay

14 Decommissioning and Disposal

15 Manual Version History

Typographic and Graphical Conventions

The following symbols are used in drawings:

BI Binary signal via opto-coupler

SET I> Input signal from comparator with setting

EN Input signal of logic setting for function enabling

SIG Input of binary signal except those signals via opto-coupler

OTH Input of other signal

PCS-985GE Generator Relay v

XXX Output signal

IDMT Timer (inverse-time characteristic)

---xxx is the symbol

Symbol Corresponding Relationship

vi PCS-985GE Generator Relay

1.1 Application ....................................................................................................... 1-1

Figure 1.1-1 Typical protection scheme 1 of PCS-985GE........................................................... 1-1

Figure 1.1-2 Typical protection scheme 2 of PCS-985GE........................................................... 1-2

Figure 1.1-3 Typical protection scheme 3 of PCS-985GE........................................................... 1-2

Table 1.2-1 Protective functions of PCS-985GE....................................................................... 1-3

Table 1.2-2 Miscellaneous functions of PCS-985GE ............................................................... 1-4

PCS-985GE Generator Relay 1-a

1-b PCS-985GE Generator Relay

Figure 1.1-1 ~ Figure 1.1-3 show typical protection schemes of PCS-985GE.

64R 51GN StShut

Figure 1.1-1 Typical protection scheme 1 of PCS-985GE

PCS-985GE Generator Relay 1-1

Figure 1.1-2 Typical protection scheme 2 of PCS-985GE

Figure 1.1-3 Typical protection scheme 3 of PCS-985GE

1-2 PCS-985GE Generator Relay

Table 1.2-1 Protective functions of PCS-985GE

No. Function ANSI

PCS-985GE Generator Relay 1-3

Table 1.2-2 Miscellaneous functions of PCS-985GE

Measurement 24 samples per cycle for current and voltage measurement

Programmable binary inputs

Programmable binary outputs

Configurable protection functions

Self-supervision Relay hardware supervision and secondary circuit supervision

Disturbance 64 fault reports

1024 supervision alarm events

Event recording 1024 binary input events

1024 device log events