LTC6228/LTC6229

0.88nV/√Hz 730MHz, 500V/µs,

Low Distortion Rail-to-Rail Output Op
Amps with Shutdown
FEATURES DESCRIPTION
nn Ultra Low Voltage Noise: 0.88nV/√Hz The LTC®6228/LTC6229 are single/dual very fast, low
nn Low Distortion at High Speeds: noise rail-to-rail output, unity gain stable op amps. They
HD2/HD3 < −100dBc (Av = +1, 4VP-P, 2MHz, RL = 1kΩ) have a gain-bandwidth product of 890MHz and a slew
nn High Slew Rate: 500V/μs rate of 500V/μs. The low input referred voltage noise of
nn GBW = 890MHz only 0.88nV/√Hz and low distortion performance of bet-
nn –3dB Frequency (A = +1): 730MHz ter than −100dB at 4VP-P even for large signals as fast as
V
nn Input Offset Voltage: 250μV Max Across Temperature 2MHz make them ideal for applications that require high
nn Offset Drift :0.4μV/°C dynamic range and deal with high slew rate signals, such
nn Input Common Mode Range Includes Negative Rail
as driving A/D converters. Additional features include
nn Output Swings Rail-to-Rail
Shutdown and the ability to enable/disable internal bias
current cancellation to optimize noise performance.
nn Supply Current: 16mA/Channel Typ
nn Shutdown Supply Current = 500µA The combination of low offset, low offset drift, high gain
nn Operating Supply Range: 2.8V to 11.75V and high CMRR make the LTC6228 family the superior
nn Large Output Current: 80mA Min choice for wide dynamic range applications.
nn Very High Open Loop Gain: 5.6V/μV (135dB), R = 1kΩ The LTC6228 family maintains excellent performance for
L
nn Operating Temp Range: –40°C to 125°C supply voltages of 2.8V to 11.75V and the devices are
nn Singles in 8-Lead SOIC, TSOT-23, DC-6, Duals in specified at supplies of 3V, 5V and 10V(±5V). With an
DD10, MS8 input range extending to the negative rail and an out-
put range that encompasses the entire supply range, the
APPLICATIONS operational amplifier can accommodate wide swinging
signals, and single supply operation.
nn Optical Electronics: Fast Transimpedance Amplifiers
nn Driving High Dynamic Range A/D Converters For space constrained PCB layouts, the LTC6228 is avail-
nn Active Filters able in a 2mm × 2mm DFN and the LTC6229 is available in a
nn Video Amplifiers
3mm × 3mm DFN. The amplifiers are also available in con-
nn High Speed Differential to Single-Ended Conversion
ventional leaded packages. These amplifiers can be used
nn Low Voltage Hi-Fi Amplification
as improved replacements for many high speed op amps
to improve speed, noise, distortion and dynamic range.
All registered trademarks and trademarks are the property of their respective owners.

TYPICAL APPLICATION System Performance: 2 x LTC6228 Driving LTC2387-18

8192 Point FFT, –1dBFS
LTC6228 Based Driver for the LTC2387-18 SAR ADC fSMPL = 15Msps, fIN = 1MHz
0
7.3VP-P 1MHz INPUT SIGNAL
7.5V SNR = 93.4dB
4.096V + –20
SFDR = 95dB
CLK THD = –93.8dB
LTC6228
0V DCO –40
LVDS
AMPLITUDE (dBFS)

– 25Ω
INTERFACE
IN+ DA
–60
82pF DB

LTC2387-18 –80
82pF TWOLANES
–100
IN– TESTPAT
4.096V + 25Ω
VCM PD –120
LTC6228 0.1µF SAMPLE
0V CNV
– REFB CLOCK –140
–2.5V 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5
6228 TA01a
FREQUENCY (MHz)
6228 TA02

Rev. A

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LTC6228/LTC6229
ABSOLUTE MAXIMUM RATINGS (Note 1)

Total Supply Voltage (V– to V+)..................................12V
Input Voltage (–IN, +IN, SHDN).... V– – 0.3V to V+ + 0.3V
Input Current (–IN, +IN, SHDN) (Note 2)............... ±10mA
Operating Temperature Range
LTC6228I/LTC6229I (Note 4)................–40°C to 85°C
LTC6228H/LTC6229H (Note 4)........... –40°C to 125°C
Specified Temperature Range
LTC6228I/LTC6229I (Note 4)................–40°C to 85°C
LTC6228H/LTC6229H (Note 4)........... –40°C to 125°C
Output Current (OUT, FB)(Note 3)....................... ±100mA
Output Short-Circuit Duration..............Thermally Limited
Storage Temperature Range................... –65°C to 150°C
Maximum Junction Temperature........................... 150°C
Lead Temperature (Soldering 10s)
(MSOP/S8/TSOT Only).......................................... 300°C

PIN CONFIGURATION
TOP VIEW
TOP VIEW
FB 1 8 SHDN
OUT 1 6 V+
–IN 2 7 V+
V– 2
– +

+ – 5 SHDN
+IN 3 6 OUT
+IN 3 4 –IN
V– 4 5 V–
S6 PACKAGE
S8 PACKAGE 6-LEAD PLASTIC TSOT-23
8-LEAD PLASTIC SO TJMAX = 150°C, θJA = 192°C/W (NOTE 7)
TJMAX = 150°C, θJA = 120°C/W (NOTE 7)

TOP VIEW
TOP VIEW

OUTA 1 10 V+
V+ 1 6 OUT
–INA 2 9 OUTB
7 11
+IN 2 5 –IN +INA 3 8 –INB
V– V–
V– 3 4 SHDN V– 4 7 +INB
SHDNA 5 6 SHDNB
DC PACKAGE
6-LEAD (2mm × 2mm) PLASTIC DFN DD PACKAGE
TJMAX = 150°C, θJA = 80°C/W (NOTE 7) 10-LEAD (3mm × 3mm) PLASTIC DFN
EXPOSED PAD (PIN 7) IS V–, MUST BE SOLDERED TO PCB TJMAX = 125°C, θJA = 43°C/W (NOTE 2)
EXPOSED PAD (PIN 11) IS V–, MUST BE SOLDERED TO PCB

TOP VIEW
OUTA 1 8 V+
–INA 2 7 OUTB
– +

+INA 3 9 6 –INB
+ –

V– 4 V– 5 +INB
MSE PACKAGE
8-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 35°C/W (NOTE 8)
EXPOSED PAD (PIN 9) IS V–, MUST BE SOLDERED TO PCB

Rev. A

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 LTC6228/LTC6229
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC6228IS6#TRMPBF LTC6228IS6#TRPBF LTHGB 6-Lead TSOT-23 –40°C to 85°C
LTC6228HS6#TRMPBF LTC6228HS6#TRPBF LTHGB 6-Lead TSOT-23 –40ºC to 125°C
LTC6228IDC#TRMPBF LTC6228IDC#TRPBF LHGC 6-Lead 2mm × 2mm DFN –40°C to 85°C
LTC6228HDC#TRMPBF LTC6228HDC#TRPBF LHGC 6-Lead 2mm × 2mm DFN –40ºC to 125°C
LTC6228IS8#TRMPBF LTC6228IS8#TRPBF 6228 8-Lead SOIC-8 –40°C to 85°C
LTC6228HS8#TRMPBF LTC6228HS8#TRPBF 6228 8-Lead SOIC-8 –40ºC to 125°C
LTC6229IMS8E#PBF LTC6229IMS8E#TRPBF LTGHD 8-Lead MSOP –40ºC to 85°C
LTC6229HMS8E#PBF LTC6229HMS8E#TRPBF LTGHD 8-Lead MSOP –40ºC to 125°C
LTC6229IDD#PBF LTC6229IDD#TRPBF LHGF 10-Lead 3mm × 3mm DFN –40ºC to 85°C
LTC6229HDD#PBF LTC6229HDD#TRPBF LHGF 10-Lead 3mm × 3mm DFN –40ºC to 125°C
Consult ADI Marketing for parts specified with wider operating temperature ranges.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.

ELECTRICAL
The CHARACTERISTICS (VS = ±5V) l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. VS = ±5V,VCM = 0V, VSHDN = floating unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOS Input Offset Voltage –95 20 95 μV
l –250 250 μV
∆VOS Input Offset Voltage Match (LTC6229) –140 18 140 µV
l –400 400 µV
TCVOS Input Offset Voltage Drift l 0.4 μV/°C
IB Input Bias Current (Note 6) Bias Cancellation Disabled –40 –16 μA
l –44 μA
Bias Cancellation Enabled –2.5 0.6 2.5 μA
l –4.1 4.1 μA
∆IB Input Bias Current Match (LTC6229) Bias Cancellation Disabled –2 0.3 2 µA
l –3 3 µA
Bias Cancellation Enabled –3 0.3 3 µA
l –4 4 µA
IOS Input Offset Current Bias Cancellation Disabled –0.55 0.1 0.55 μA
l –0.8 0.8 μA
Bias Cancellation Enabled –0.9 0.1 0.9 μA
l –1 1 μA
∆IOS Input Offset Current Match (LTC6229) Bias Cancellation Disabled –1 0.15 1 µA
l –1.4 1.4 µA
Bias Cancellation Enabled –1.3 0.25 1.3 µA
l –1.6 1.6 µA
en Input Noise Voltage Spectral Density f = 1MHz 0.88 nV/√Hz
Integrated 1/f Noise 0.1Hz to 10Hz 0.94 μVP-P
in Input Current Noise Spectral Density f = 1MHz Bias Cancellation Disabled 3 pA/√Hz
f = 1MHz Bias Cancellation Enabled 6.3 pA/√Hz
CIN Input Capacitance Differential Mode 3.5 pF
Common Mode 1.5 pF
RIN Input Resistance Differential Mode 2.6 kΩ
Common Mode 4 MΩ

Rev. A

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LTC6228/LTC6229
ELECTRICAL
The CHARACTERISTICS (VS = ±5V) l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. VS = ±5V,VCM = 0V, VSHDN = floating unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
AVOL Large Signal Voltage Gain RL = 1kΩ to Half Supply VOUT = ±4V 120 135 dB
l 113 dB
RL = 100Ω to Half Supply VOUT = ±3V 100 120 dB
l 92 dB
CMRR Common Mode Rejection Ratio VCM = V– – 0.1 to V+ – 1.2V 100 110 dB
l 94 dB
VCMR Input Common Mode Range l V– – 0.1 V+ – 1.2 V
PSRR+ Positive Power Supply Rejection Ratio V– = –1V, V+ = 1.8V to 10.75V 100 110 dB
l 95 dB
PSRR– Negative Power Supply Rejection Ratio V+ = 1.5V, V– = –1.3V to –10.25V 101 126 dB
l 99 dB
Supply Voltage Range (V+ – V–) (Note 5) l 2.8 11.75 V
VOL Output Swing Low (VOUT – V–) No Load 8 16 mV
l 20 mV
ISINK = 5mA 46 70 mV
l 85 mV
ISINK = 25mA 140 220 mV
l 280 mV
VOH Output Swing High (V+ – VOUT) No Load 27 50 mV
l 60 mV
ISINK = 5mA 90 140 mV
l 180 mV
ISOURCE = 25mA 250 340 mV
l 450 mV
ISC Output Short-Circuit Current Sourcing –130 –80 mA
l –65 mA
Sinking 80 140 mA
l 60 mA
IS Supply Current per Channel 16 16.9 mA
l 19.8 mA
ISD Disable Supply Current per Channel, Amplifier VSHDN = V+ – 2.75V 500 610 μA
Off l 770 μA
VL_SHDN SHDN Pin Input Voltage Low, Disable Amplifier l V+ – 2.75 V
VH_SHDN SHDN Pin Input Voltage High, Enable Amplifier l V+ – 1.6 V
VL_IBIAS SHDN Pin Input Voltage Low, Disable Bias l V+ – 1 V
Cancellation
VH_IBIAS SHDN Pin Input Voltage Low, Enable Bias l V+ – 0.35 V
Cancellation
IL_SHDN SHDN Pin Input Current, Disable Amplifier VSHDN = V+ – 2.75V l –10 –2.5 10 μA
IH_SHDN SHDN Pin Input Current, Enable Amplifier VSHDN = V+ – 1.6V l –10 –0.3 10 μA
IL_IBIAS SHDN Pin Input Current Low, Disable Bias VSHDN = V+ – 1V l –10 0.265 10 μA
Cancellation
IH_IBIAS SHDN Pin Input Current Low, Enable Bias VSHDN = V+ – 0.35V l –10 1 10 μA
Cancellation
IOSD Output Leakage Current in Shutdown VSHDN = V+ – 2.75V, OUT Shorted to V+ or V– 100 nA
BW –3dB Closed Loop Bandwidth AV = 1, RL = 1kΩ to Half Supply 730 MHz
GBW Gain-Bandwidth Product f = 5MHz, RL = 1kΩ to Half Supply 700 890 MHz
l 650 MHz
tON Turn-On Time VSHDN = V+ – 2.75V to V+ – 1.6V 900 ns
Rev. A

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 LTC6228/LTC6229
ELECTRICAL
The CHARACTERISTICS (VS = ±5V) l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. VS = ±5V,VCM = 0V, VSHDN = floating unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tOFF Turn-Off Time VSHDN = V+ – 1.6V to V+ – 2.75V 500 ns
tS_0.1 Settling Time to 0.1% AV = 1, 2V Output Step, RL = 1kΩ 26 ns
AV = 1, 4V Output Step, RL = 1kΩ 34 ns
tS_0.01 Settling Time to 0.01% AV = 1, 6V Output Step, RL = 1kΩ 53 ns
SR Slew Rate AV = +4, 8V Output Step (Note 8) 320 500 V/μs
l 250 V/μs
FPBW Full Power Bandwidth VOUT = 8VP-P, AV = +2, THD < –40dBc 12.5 MHz
HD2/HD3 Harmonic Distortion, RL = 1kΩ to Half Supply, fC = 100kHz, VO = 4VP-P –113/–119 dBc
AV = +1 fC = 100kHz, VO = 2VP-P –126/–131 dBc
fC = 1MHz, VO = 4VP-P –107/–114 dBc
fC = 1MHz, VO = 2VP-P –119/–132 dBc
fC = 5MHz, VO = 4VP-P –83/–96 dBc
fC = 5MHz, VO = 2VP-P –90/–113 dBc
fC = 10MHz, VO = 2VP-P –74/–89 dBc
Harmonic Distortion, RL = 100Ω to Half fC = 100kHz, VO = 4VP-P –105/–106 dBc
Supply, AV = +1 fC = 100kHz, VO = 4VP-P –118/–124 dBc
fC = 1MHz, VO = 4VP-P –97/–107 dBc
fC = 1MHz, VO = 2VP-P –100/–114 dBc
fC = 5MHz, VO = 4VP-P –79/–75 dBc
fC = 5MHz, VO = 2VP-P –83/–82 dBc
fC = 10MHz, VO = 2VP-P –72/–68 dBc
ΔG Differential Gain (NTSC) AV = 2, RL = 150Ω 0.008 %
AV = +1, RL = 1kΩ 0.001 %
Δθ Differential Phase (NTSC) AV = 2, RL = 150Ω 0.004 Deg
AV = +1, RL = 1kΩ 0.09 Deg

ELECTRICAL
The CHARACTERISTICS (VS = 5V, 0V) l denotes the specifications which apply
over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = 5V, 0V,VCM = VOUT = 2.5V, VSHDN = floating
unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOS Input Offset Voltage –105 20 105 μV
l –290 290 μV
∆VOS Input Offset Voltage Match (LTC6229) –140 18 140 µV
l –400 400 µV
TCVOS Input Offset Voltage Drift l 0.4 μV/°C
IB Input Bias Current (Note 6) Bias Cancellation Disabled –40 –16 μA
l –44 μA
Bias Cancellation Enabled –3 1 3 μA
l –4.4 4.4 μA
∆IB Input Bias Current Match (LTC6229) Bias Cancellation Disabled –2 0.3 2 µA
l –3 3 µA
Bias Cancellation Enabled –3 0.3 3 µA
l –4 4 µA
IOS Input Offset Current Bias Cancellation Disabled –0.55 0.1 0.55 μA
l –0.8 0.8 μA
Bias Cancellation Enabled –0.9 0.15 0.9 μA
l –1 1 μA
∆IOS Input Offset Current Match (LTC6229) Bias Cancellation Disabled –1 0.15 1 µA
l –1.4 1.4 µA
Bias Cancellation Enabled –1.3 0.25 1.3 µA
l –1.6 1.6 µA
Rev. A

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LTC6228/LTC6229
ELECTRICAL
The CHARACTERISTICS (VS = 5V, 0V) l denotes the specifications which apply
over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = 5V, 0V,VCM = VOUT = 2.5V, VSHDN = floating
unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
en Input Noise Voltage Spectral Density f = 1MHz 0.88 nV/√Hz
Integrated 1/f Noise 0.1Hz to 10Hz 0.94 μVP-P
in Input Current Noise Spectral Density f = 1MHz Bias Cancellation Disabled 3 pA/√Hz
f = 1MHz Bias Cancellation Enabled 6.3 pA/√Hz
CIN Input Capacitance Differential Mode 3.5 pF
Common Mode 1.5 pF
RIN Input Resistance Differential Mode 2.6 kΩ
Common Mode 4 MΩ
AVOL Large Signal Voltage Gain RL = 1kΩ to Half Supply, VOUT = VCM ±2 120 140 dB
l 115 dB
RL = 100Ω to Half Supply, VOUT = VCM ±2 106 120 dB
l 100 dB
CMRR Common Mode Rejection Ratio VCM = V– – 0.1 to V+ – 1.2V 97 110 dB
l 92 dB
VCMR Input Common Mode Range l V– – 0.1 V+ – 1.2 V
PSRR+ Positive Power Supply Rejection Ratio V– = –1V, V+ = 1.8V to 10.75V 100 110 dB
l 95 dB
PSRR– Negative Power Supply Rejection Ratio V+ = 1.5V, V– = –1.3V to –10.25V 103 126 dB
l 100 dB
Supply Voltage Range (V+ – V–) (Note 5) l 2.8 11.75 V
VOL Output Swing Low (VOUT – V–) No Load 7 18 mV
l 32 mV
ISINK = 5mA 40 70 mV
l 90 mV
ISINK = 25mA 150 220 mV
l 300 mV
VOH Output Swing High (VCC – V+) No Load 26 48 mV
l 58 mV
ISINK = 5mA 93 144 mV
l 185 mV
ISOURCE = 25mA 255 347 mV
l 459 mV
ISC Output Short-Circuit Current Sourcing –110 –65 mA
l –52 mA
Sinking 70 110 mA
l 45 mA
IS Supply Current per Channel 16.5 17.8 mA
l 19.6 mA
ISD Disable Supply Current per Channel, Amplifier VSHDN = V+ – 2.65V 300 380 μA
Off l 430 μA
VL_SHDN SHDN Pin Input Voltage Low, Disable Amplifier l V+ – 2.65 V
VH_SHDN SHDN Pin Input Voltage High, Enable Amplifier l V+ – 1.6 V
VL_IBIAS SHDN Pin Input Voltage Low, Disable Bias l V+ – 1 V
Cancellation
VH_IBIAS SHDN Pin Input Voltage Low, Enable Bias l V+ – 0.35 V
Cancellation
IL_SHDN SHDN Pin Input Current, Disable Amplifier VSHDN = V+ – 2.65V l –10 –2.5 10 μA

Rev. A

6 For more information www.analog.com

 LTC6228/LTC6229
ELECTRICAL
The CHARACTERISTICS (VS = 5V, 0V) l denotes the specifications which apply
over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = 5V, 0V,VCM = VOUT = 2.5V, VSHDN = floating
unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IH_SHDN SHDN Pin Input Current, Enable Amplifier VSHDN = V+ – 1.6V l –10 –0.3 10 μA
IL_IBIAS SHDN Pin Input Current Low, Disable Bias VSHDN = V+ – 1V l –10 0.265 10 μA
Cancellation
IH_IBIAS SHDN Pin Input Current Low, Enable Bias VSHDN = V+ – 0.35V l –10 1 10 μA
Cancellation
IOSD Output Leakage Current in Shutdown VSHDN = V+ – 2.65V, OUT Shorted to V+ or V– 100 nA
BW –3dB Closed Loop Bandwidth AV = 1, RL = 1kΩ to Half Supply 800 MHz
GBW Gain-Bandwidth Product f = 5MHz, RL = 1kΩ to Half Supply 700 865 MHz
l 600 MHz
tON Turn-On Time VSHDN = V+ – 2.65V to V+ – 1.6V 900 ns
tOFF Turn-Off Time VSHDN = V+ – 1.6V to V+ – 2.65V 500 ns
tS_0.1 Settling Time to 0.1% AV = 1, 2V Output Step, RL = 1kΩ 26 ns
SR Slew Rate AV = +4, 4V Output Step (Note 8) 350 V/μs
FPBW Full Power Bandwidth VOUT = 4VP-P, AV = +2, THD < –40dBc 18 MHz
HD2/HD3 Harmonic Distortion, RL = 1kΩ to Half Supply fC = 100kHz, VO = 2VP-P –106/–130 dBc
fC = 1MHz, VO = 2VP-P –95/–105 dBc
fC = 5MHz, VO = 2VP-P –88/–114 dBc
fC = 10MHz, VO = 2VP-P –78/–90 dBc
Harmonic Distortion, RL = 100Ω to Half fC = 100kHz, VO = 2VP-P –112/–115 dBc
Supply fC = 1MHz, VO = 2VP-P –99/–120 dBc
fC = 5MHz, VO = 2VP-P –83/–88 dBc
fC = 10MHz, VO = 2VP-P –70/–73 dBc
ΔG Differential Gain (NTSC) AV = 2, RL = 150Ω 0.005 %
AV = +1, RL = 1kΩ 0.002 %
Δθ Differential Phase (NTSC) AV = 2, RL = 150Ω 0.007 Deg
AV = +1, RL = 1kΩ 0.018 Deg

ELECTRICAL
The CHARACTERISTICS (VS = 3V, 0V) l denotes the specifications which apply
over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = 3V, 0V,VCM = 1.5V, VSHDN = floating unless
otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOS Input Offset Voltage –110 24 110 μV
l –300 300 μV
∆VOS Input Offset Voltage Match (LTC6229) –140 18 140 µV
l –400 400 µV
TCVOS Input Offset Voltage Drift l 0.4 μV/°C
IB Input Bias Current (Note 6) Bias Cancellation Disabled –38 –16 μA
l –44 μA
Bias Cancellation Enabled –3.5 1.5 3.5 μA
l –4.3 4.1 μA
∆IB Input Bias Current Match (LTC6229) Bias Cancellation Disabled –2 0.3 2 µA
l –3 3 µA
Bias Cancellation Enabled –3 0.3 3 µA
l –4 4 µA

Rev. A

For more information www.analog.com 7

LTC6228/LTC6229
ELECTRICAL
The CHARACTERISTICS (VS = 3V, 0V) l denotes the specifications which apply
over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = 3V, 0V,VCM = 1.5V, VSHDN = floating unless
otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IOS Input Offset Current Bias Cancellation Disabled –0.55 0.1 0.55 μA
l –0.8 0.8 μA
Bias Cancellation Enabled –0.9 0.15 0.9 μA
l –1 1 μA
∆IOS Input Offset Current Match (LTC6229) Bias Cancellation Disabled –1 0.15 1 µA
l –1.4 1.4 µA
Bias Cancellation Enabled –1.3 0.25 1.3 µA
l –1.6 1.6 µA
en Input Noise Voltage Spectral Density f = 1MHz 0.88 nV/√Hz
Integrated 1/f Noise 0.1Hz to 10Hz 0.94 μVP-P
in Input Current Noise Spectral Density f = 1MHz Bias Cancellation Disabled 3 pA/√Hz
f = 1MHz Bias Cancellation Enabled 6.3 pA/√Hz
CIN Input Capacitance Differential Mode 3.5 pF
Common Mode 1.5 pF
RIN Input Resistance Differential Mode 2.6 kΩ
Common Mode 4 MΩ
AVOL Large Signal Voltage Gain RL = 1kΩ to Half Supply, 118 130 dB
(VOUT = VCM ±1V) l 113 dB
RL = 100Ω to Half Supply, 120 dB
(VOUT = VCM ±1V)
CMRR Common Mode Rejection Ratio VCM = V– to V+ – 1.2V 95 110 dB
l 91 dB
VCMR Input Common Mode Range l V– – 0.1 V+ – 1.2 V
PSRR+ Positive Power Supply Rejection Ratio V– = –1V, V+ = 1.8V to 10.75V 100 110 dB
l 95 dB
PSRR– Negative Power Supply Rejection Ratio V+ = 1.5V, V– = –1.3V to –10.25V 101 126 dB
l 99 dB
Supply Voltage Range (V+ – V–) (Note 5) l 2.8 11.75 V
VOL Output Swing Low (VOUT – V–) No Load 7 10 mV
l 18 mV
ISINK = 5mA 48 74 mV
l 100 mV
ISINK = 25mA 165 320 mV
l 430 mV
VOH Output Swing High (VCC – V+) No Load 27 49 mV
l 59 mV
ISINK = 5mA 106 166 mV
l 213 mV
ISOURCE = 25mA 290 520 mV
l 580 mV
ISC Output Short-Circuit Current Sourcing –67 mA
Sinking 84 mA
IS Supply Current per Channel 16.4 17.6 mA
l 19 mA
ISD Disable Supply Current per Channel, Amplifier VSHDN = V+ – 2.65V 260 305 μA
Off l 350 μA

Rev. A

8 For more information www.analog.com

 LTC6228/LTC6229
ELECTRICAL
The CHARACTERISTICS (VS = 3V, 0V) l denotes the specifications which apply
over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = 3V, 0V,VCM = 1.5V, VSHDN = floating unless
otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VL_SHDN SHDN Pin Input Voltage Low, Disable Amplifier l V+ – 2.65 V
VH_SHDN SHDN Pin Input Voltage High, Enable Amplifier l V+ – 1.6 V
VL_IBIAS SHDN Pin Input Voltage Low, Disable Bias l V+ – 1 V
Cancellation
VH_IBIAS SHDN Pin Input Voltage Low, Enable Bias l V+ – 0.35 V
Cancellation
IL_SHDN SHDN Pin Input Current, Disable Amplifier VSHDN = V+ – 2.65V l –10 –2.5 10 μA
IH_SHDN SHDN Pin Input Current, Enable Amplifier VSHDN = V+ – 1.6V l –10 –0.3 10 μA
IL_IBIAS SHDN Pin Input Current Low, Disable Bias VSHDN = V+ – 1V l –10 0.265 10 μA
Cancellation
IH_IBIAS SHDN Pin Input Current Low, Enable Bias VSHDN = V+ – 0.35V l –10 1 10 μA
Cancellation
IOSD Output Leakage Current in Shutdown VSHDN = V+ – 2.65V, OUT Shorted to V+ or V– 100 nA
BW –3dB Closed Loop Bandwidth AV = 1, RL = 1kΩ to Half Supply 763 MHz
GBW Gain-Bandwidth Product f = 5MHz, RL = 1kΩ to Half Supply 700 845 MHz
l 560 MHz
tON Turn-On Time VSHDN = V+ – 2.5V to V+ – 1.6V 900 ns
tOFF Turn-Off Time VSHDN = V+ – 1.6V to V+ – 2.5V 500 ns
tS_0.1 Settling Time to 0.1% AV = 1, VCM = 1V, 1V Output Step, 31 ns
RL = 1kΩ
SR Slew Rate AV = +4, 2V Output Step 200 V/μs
FPBW Full Power Bandwidth VOUT = 2VP-P, VCM = 1V, AV = –1, 22 MHz
THD < –40dBc
HD2/HD3 Harmonic Distortion, RL = 1kΩ to Half Supply, fC = 100kHz –106/–127 dBc
VOUT = 1VP-P, VCM = 1.25V fC = 1MHz –110/–128 dBc
fC = 5MHz –82/–105 dBc
fC = 10MHz –77/–96 dBc
Harmonic Distortion, RL = 100Ω to Half fC = 100kHz –116/–123 dBc
Supply, VOUT = 1VP-P, VCM = 1.25V fC = 1MHz –105/–132 dBc
fC = 5MHz –89/–98 dBc
fC = 10MHz –77/–86 dBc

Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The inputs are protected by back-to-back diodes. If any of
the input or shutdown pins goes 300mV beyond either supply or the
differential input voltage exceeds 0.7V, the input current should be limited
to less than 10mA.
Note 3: A heat sink may be required to keep the junction temperature
below the absolute maximum rating when the output current is high.
Note 4: The LTC6228I/LTC6229I is guaranteed functional and specified
over the temperature range of –40°C to 85°C. The LTC6228H/LTC6229H is
guaranteed functional and specified over the temperature range of –40°C
to 125°C.
Note 5: Supply range voltage is guaranteed by power supply rejection ratio test.
Note 6: The input bias current is the average of the currents through the
non-inverting and inverting input pins.
Note 7: Thermal resistance varies with the amount of PC board metal
connected to the package. The specified values are with short traces
connected to the leads with minimal metal area.
Note 8: Middle 2/3 of the output waveform is observed. RL = 1kΩ at half supply.

Rev. A

For more information www.analog.com 9

LTC6228/LTC6229
TYPICAL PERFORMANCE CHARACTERISTICS
VS = ±5V, VCM = 0V, TA = 25°C, unless otherwise noted.

Offset Distribution Offset Distribution Offset Distribution

50 50 50
VS = ±5V VS = 5V, 0V VS = 3V, 0V
45 VCM = 0V 45 VCM = 2.5V 45 VCM = 1.5V
40 TA = 25°C TA = 25°C TA = 25°C
40 40
PERCENT OF UNITS (%)

PERCENT OF UNITS (%)

PERCENT OF UNITS (%)
35 35 35
30 30 30
25 25 25
20 20 20
15 15 15
10 10 10
5 5 5
0 0 0
–60–50–40–30–20–10 0 10 20 30 40 50 60 –60–50–40–30–20–10 0 10 20 30 40 50 60 –60–50–40–30–20–10 0 10 20 30 40 50 60
INPUT OFFSET VOLTAGE (µV) INPUT OFFSET VOLTAGE (µV) INPUT OFFSET VOLTAGE (µV)
6228 G01 6228 G02 6228 G03

VOS vs Temperature, 10V Supply VOS vs Temperature, 5V Supply VOS vs Temperature, 3V Supply
160 160 160
VS = ±5V VS = ±2.5V VS = 3V, 0V
140 VCM = 0V 140 VCM = 0V 140 VCM = 1.5V
5 DEVICES 5 DEVICES 5 DEVICES
INPUT OFFSET VOLTAGE (µV)

INPUT OFFSET VOLTAGE (µV)

INPUT OFFSET VOLTAGE (µV)

120 120 120

100 100 100

80 80 80

60 60 60

40 40 40

20 20 20

0 0 0
–55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
6228 G04 6228 G05 6228 G06

Offset Voltage vs Input Common

Mode Voltage Offset Voltage vs Output Current Warm Up Drift
Warm–up Drift vs
vs Time
Time
100 200 50
90 VS = ±5V VS = ±5V VS = ±5V
180
80 TA=25°C
40
CHANGE IN OFFSET VOLTAGE (µV)

70 160
60
OFFSET VOLTAGE (µV)

OFFSET VOLTAGE (µV)

TA = 125°C 140
50 30
TA = 85°C 120
40
30 100 TA = 125°C 20
20
80
10 10
0 60 TA = 85°C
–10 TA = –55°C 40 TA = –55°C
–20 0
TA = 25°C 20 TA = 25°C
–30
–40 0 –10
–6 –5 –4 –3 –2 –1 0 1 2 3 4 5 –50 –40 –30 –20 –10 0 10 20 30 40 50 0 1 2 3 4 5 6 7 8
INPUT COMMON MODE VOLTAGE (V) OUTPUT CURRENT (mA) TIME AFTER POWER UP (s)
6228 G07 6228 G08 6228 G09

Rev. A

10 For more information www.analog.com

 LTC6228/LTC6229
TYPICAL PERFORMANCE CHARACTERISTICS
VS = ±5V, VCM = 0V, TA = 25°C, unless otherwise noted.

Input Bias Current vs Input Input Bias Current vs Input

Common Voltage, Bias Common Mode Voltage, Bias
Cancellation Disabled Cancellation Enabled 0.1Hz to 10Hz Voltage Noise
5 2
VS = ±5V VS = ±5V
1 TA = 125°C
0

INPUT VOLTAGE NOISE (200 nV/Div)

0
INPUT BIAS CURRENT (µA)

INPUT BIAS CURRENT (µA)

–1 TA = –55°C
–5
–2
TA = 25°C –3
–10
TA = –55°C TA = 25°C
–4
–15 –5 TA = 85°C
–6
–20 TA = 125°C –7

–25 TA = 85°C –8
–9
–30 –10 6228 G12
–5.1 –4.2 –3.3 –2.4 –1.5 –0.7 0.2 1.1 2.0 2.9 3.8 –5.1 –4.2 –3.3 –2.4 –1.5 –0.7 0.2 1.1 2.0 2.9 3.8 1s/DIV
INPUT COMMON MODE VOLTAGE (V) INPUT COMMON MODE VOLTAGE (V)
6228 G10 6228 G11

Input
InputVoltage
VoltageNoise
Noiseand Current
and Noise
Current Noise Supply Current vs Input Common
Spectral Densities
Spectral DensitiesvsvsFrequency
Frequency Supply Current vs Supply Voltage Mode Voltage
5k 20 20
iN,bias cancellation disabled VS = ±5V TA = 125°C
TA=25°C 18 TA = 125°C 19
1k
INPUT CURRENT NOISE (pA/√Hz)
INPUT VOLTAGE NOISE (nV/√Hz)

16 18
TA = 25°C

SUPPLY CURRENT (mA)

SUPPLY CURRENT (mA)

iN,bias cancellation enabled 14 17

TA = –55°C TA = 25°C
12 16
100
10 15
eN
8 14
TA = –55°C
10 13
6
4 12

2 11
1 VCM = VS/2
0.5 0 10
0.1 1 10 100 1k 10k 100k 1M 10M100M 0 2 4 6 8 10 12 –5.1 –4.2 –3.3 –2.4 –1.5 –0.6 0.3 1.2 2.1 3.0 3.9
FREQUENCY (Hz) TOTAL SUPPLY VOLTAGE (V) INPUT COMMON MODE VOLTAGE (V)
6228 G13 6228 G14 6228 G15

Supply Current vs SHDN Pin Input Bias Current vs SHDN Pin SHDN Pin Current vs SHDN Pin
Voltage Voltage
SHDN Pin Voltage Voltage
SHDN Pin Voltage
20 5.0 5.0
VS = ±5V VS = ±5V
18 TA = 125°C 2.5 2.5 VS = ±5V

16 0 0
INPUT BIAS CURRENT (µA)

SHDN PIN CURRENT (µA)

SUPPLY CURRENT (mA)

14 TA = 25°C –2.5 –2.5

12 –5.0 –5.0
TA = –55°C
10 –7.5 –7.5
8 TA = –55°C –10.0 –10.0 TA = 25°C
TA = –55°C
6 –12.5 –12.5
TA = 25°C
4 –15.0 –15.0
TA = 85°C TA = 125°C
2 –17.5 –17.5
TA = 125°C
0 –20.0 –20.0
–5 –4 –3 –2 –1 0 1 2 3 4 5 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5.0 –5 –4 –3 –2 –1 0 1 2 3 4 5
SHDN PIN VOLTAGE (V) SHDN PIN VOLTAGE (V) SHDN PIN VOLTAGE (V)
6228 G16 6228 G17 6228 G18

Rev. A

For more information www.analog.com 11

LTC6228/LTC6229
TYPICAL PERFORMANCE CHARACTERISTICS
VS = ±5V, VCM = 0V, TA = 25°C, unless otherwise noted.

Output Saturation Voltage vs Output Saturation Voltage vs

Minimum Supply Voltage Load Current (Output High) Load Current (Output Low)
200 1 1
VCM = 1V VS = ±5V VS = ±5V

OUTPUT HIGH SATURATION VOLTAGE (V)

OUTPUT LOW SATURATION VOLTAGE (V)

160
120 TA = 125°C
INPUT OFFSET VOLTAGE (µV)

TA = 125°C TA = 125°C
80
40 TA = 25°C
TA = 25°C TA = 25°C
0 0.1 0.1
–40 TA = –55°C
–80
–120 TA = –55°C
–160 TA = –55°C
–200 0.01 0.01
2 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 0.001 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 100
TOTAL SUPPLY VOLTAGE (V) LOAD CURRENT (mA) LOAD CURRENT (mA)
6228 G19 6228 G20 6228 G21

Output Short Circuit vs Supply

vs Supply Voltage
Voltage Open Loop Gain, VS = ±5V Open Loop Gain, VS = ±2.5V
250 40 40
RL = 1kΩ RL = 1kΩ
210 TA = –55°C 32 32 RL = 100Ω
SINK RL = 100Ω
SHORT CIRCUIT CURRENT (mA)

170 24 24

INPUT OFFSET VOLTAGE (µV)

INPUT OFFSET VOLTAGE (µV)

TA = 25°C
130 TA = 85°C 16 16
90 TA = 125°C 8 8
50 0 0
10 –8 –8
–30 TA = 85°C –16 –16
TA = 125°C
–70 –24 –24
–110 SOURCE TA = 25°C –32 –32
TA = –55°C TA = 25°C TA = 25°C
–150 –40 –40
2.8 3.7 4.6 5.5 6.4 7.3 8.2 9.1 10.0 10.9 11.8 –5 –4 –3 –2 –1 0 1 2 3 4 5 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5
TOTAL SUPPLY VOLTAGE (V) OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V)
6228 G22 6228 G23 6228 G24

Open Loop Gain, VS = ±1.5V Gain vs Frequency, AV = 1 Gain vs Frequency, AV = 2

40 4 9
RL = 1kΩ
32 RL = 100Ω 6
2
24 3
INPUT OFFSET VOLTAGE (µV)

0
16 0
–2 –3
8
GAIN (dB)

GAIN (dB)

–6
0 –4
–9
–8 –6 –12
–16
–8 –15 VS = ±5V
–24 VS = ±5V –18 TA = 25°C
–10 RL = 1kΩ RF = RG = 301Ω C F = 2.7pF
–32 –21
TA = 25°C TA = 25°C RL = 1kΩ
–40 –12 –24
–1.5 –1 –0.5 0 0.5 1 1.5 10k 100k 1M 10M 100M 1G 10k 100k 1M 10M 100M 1G
OUTPUT VOLTAGE (V) FREQUENCY (Hz) FREQUENCY (Hz)
6228 G25 6228 G26 6228 G27

Rev. A

12 For more information www.analog.com

 LTC6228/LTC6229
TYPICAL PERFORMANCE CHARACTERISTICS
VS = ±5V, VCM = 0V, TA = 25°C, unless otherwise noted.

Open Loop Gain

Gain and
and Phase
Phase vs Gain Bandwidth and Phase Gain Bandwidth and Phase
Frequency
vs Frequency Margin vs Supply Voltage Margin vs Temperature
70 920 60 1000 60
65 Gain
Phase 910 59 970 PHASE MARGIN 55
60

GAIN BANDWIDTH PRODUCT (MHz)

55 900 57 940 50
PHASE MARGIN

GAIN BANDWIDTH (MHz)

50
890 56 910 45

PHASE MARGIN (°)

45

PHASE MARGIN (°)

40 880 54 880 40
PHASE (°)
GAIN (dB)

35 VS = ±5V 870 53 850 35

30 TA = 25 °C
25 860 GAIN BANDWIDTH 51 820 30
RL = 1kΩ PRODUCT
20
850 50 790 RL = 1kΩ GAIN 25
15
BANDWIDTH
10 840 VCM = HALF SUPPLY 48 760 VS = ±5V 20
5 RL = 1kΩ TO HALF SUPPLY VS = ±2.5V
830 47 730 15
0 TA = 25 °C VS = ±1.5V
–5 820 45 700 10
500k 1M 10M 100M 1G 2.80 4.29 5.78 7.27 8.77 10.26 11.75 –55 –35 –15 5 25 45 65 85 105 125
FREQUENCY (Hz) TOTAL SUPPLY VOLTAGE (V) TEMPERATURE (°C)
6228 G28 6228 G29 6228 G30

Common Mode Rejection Ratio vs Power Supply Rejection Ratio vs

Output Impedance vs Frequency Frequency Frequency
80 110 130
VS = ±5 V VS = ±5V PSRR+
100 PSRR–
COMMON MODE REJECTION RATIO (dB)

TA = 25°C
110
90
10
OUTPUT IMPEDANCE (Ω)

80 90
70 PSRR (dB)
60 70
AV = 10
1
AV = 2 50 50
40
AV = 1 30 30
0.1
20 VS = ±5V
10 VCM = 0V
10
TA = 25°C
0.01 0 –10
10k 100k 1M 10M 100M 1G 100k 1M 10M 100M 500M 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz)
6228 G31 6228 G32 6228 G33

Series Output Resistor vs Series Output Resistor vs

Slew Rate vs Temperature Capacitive Load, AV = 1 Capacitive Load, AV = 2
700 55 150
AV = 4, R L=1kΩ VS = ±5V VS = ±5V
FALLING 50 – VOUT
RS 135
600
45 + 120 C1 301Ω
VS = ±5V, VOUT = 8VP-P VIN
RISING 1kΩ CL 301Ω – VOUT RS
40 105
SLEW RATE (V/µS)

500
OVERSHOOT (%)

+
OVERSHOOT (%)

RISING
35 90 VIN
1kΩ CL
400 30 RS = 20Ω 75
FALLING RS = 10Ω
25 60
VS = ±2.5V, VOUT = 4VP-P
300
20 RS = 50Ω 45
VS = ±1.5V, VOUT = 2VP-P RISING
15 30
200
FALLING 10 15
100 5 0
–55 –35 –15 5 25 45 65 85 105 125 10 100 1000 10000 10 100 1000 10000
TEMPERATURE (°C) CAPACITIVE LOAD (pF) CAPACITIVE LOAD (pF)
6228 G35
SLEW RATE MEASURED AT RS = 10Ω, CF = 0pF RS = 10Ω, CF = 2.7pF
MIDDLE 2/3 OF OUTPUT 6228 G34
RS = 20Ω, CF = 0pF RS = 20Ω, CF = 2.7pF
RS = 50Ω, CF = 0pF RS = 50Ω, CF = 2.7pF
6228 G36
Rev. A

For more information www.analog.com 13

 LTC6228/LTC6229
TYPICAL PERFORMANCE CHARACTERISTICS
VS = ±5V, VCM = 0V, TA = 25°C, unless otherwise noted.

Distortion vs
Distortion vs Frequency,
Frequency, AAVV == 11, Distortion vs
Distortion vs Frequency,
Frequency, AAVV == 11, Distortion vs Frequency, AV = 11,
±5V Supply
Supply 5V Supply
5V 3V Supply
Supply
–30 –30 –10
VS = ±5V VS = 5V,0V VS = 3V,0V
–40 VOUT = 4VP–P TA=25°C –40 VOUT=2VP–P –20 VOUT=1VP–P
RL =1kΩ, 2nd RL to Mid–Supply –30 VCM=1.25V
–50 VOUT = 2VP–P –50 TA=25°C RL to VCM
VOUT = 4VP–P –40
–60 RL = 1kΩ, 3
rd RL = 1kΩ, 2nd –60 TA=25°C
RL = 100Ω, 2nd

DISTORTION (dBc)

DISTORTION (dBc)
–50
DISTORTION (dBc)

–70 VOUT = 4VP–Pnd –70 RL = 100Ω, 2nd

–60
RL = 100Ω, 2
–80 –80 RL = 1kΩ, 2nd –70 RL = 1kΩ, 2nd
VOUT = 4VP–P –80
–90 R = 100Ω, 3rd –90
L
–90
–100 –100
–100
–110 –110 RL = 1kΩ, 3rd
–110 RL = 1kΩ, 3rd
–120 VOUT = 2VP–P –120
RL = 100Ω, 3rd –120
RL = 1kΩ, 3rd RL = 100Ω, 3rd
–130 –130 –130
100k 1M 10M 100k 1M 10M 100k 1M 10M 50M
FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz)
6228 G37 6228 G38 6228 G39

Distortion vs Frequency, AV = 22, Distortion

Distortion vs
vs Frequency,
Frequency, A
AVV == 2,
2 Distortion vs Frequency, AV = 2,
±5V Supply
Supply 5V Supply
Supply 3V Supply
–30 –30 –20
VS = ±5V VS = 5V,0V VS = 3V, 0V
–40 TA=25°C –40 VOUT=2VP–P –30 VCM = 1V
VOUT = 4VP–P RL to Mid–Supply VOUT = 1VP-P
–50 VOUT = 4VP–P –50 TA=25°C
–40
RL = 1kΩ, 3rd RL =1kΩ, 2nd RL = 100Ω, 2nd
RL to VCM
–60 –50 TA = 25°C
–60
DISTORTION (dBc)

DISTORTION (dBc)
DISTORTION (dBc)

V = 4VP–P –60
–70 ROUT nd –70
L = 100Ω, 2 RL = 100Ω, 2ND
–70
–80 –80
VOUT = 4VP–P RL = 1kΩ, 2nd –80 RL = 1kΩ, 2ND
–90 RL = 100Ω, 3rd –90
–90
–100 –100 –100
RL = 100Ω, 3RD
–110 VOUT = 2VP–P –110 RL = 1kΩ, 3rd –110
RL = 1kΩ, 2nd
–120 VOUT = 2VP–P –120 –120
RL = 1kΩ, 3rd RL = 100Ω, 3rd RL = 1kΩ, 3RD
–130 –130 –130
100k 1M 10M 100k 1M 10M 100k 1M 10M 50M
FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz)
6228 G40 6228 G41 6228 G42

Maximum Undistorted Output 0.1% Settling Time vs Output 0.1% Settling Time vs Output
Signal vs Frequency Step
vs (Non-Inverting)
Output Step (Non–inverting) Step (Inverting)
vs Output Step (Inverting)
10 50 50
VS = ±5V AV = –1 Av = +1
2.7pF
9 AV = 2
TA=25°C
45 45 301Ω
OUTPUT VOLTAGE SWING (VP-P)

8 VS=±5V (5.5V/–4.5V for step size>7V)

VIN
301Ω –
7 + VOUT
SETTLING TIME (ns)

SETTLING TIME (ns)

VOUT
40 – 40
6 1kΩ
VS = ±2.5V AV = 2 VIN +
5 35 1kΩ 35
AV = –1
4
VS = ±1.5V 30 30
3
AV = –1
2 TA = 25°C Av = –1
25 25
1 RL = 1kΩ TA=25°C
HD2, HD3 < –40dBc VS=±5V
0 20 20
0.1 1 10 40 –8 –7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 7 8 –8 –7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 7 8
FREQUENCY (MHz) OUTPUT STEP (V) OUTPUT STEP (V)
6228 G43 6228 G44 6228 G45

Rev. A

14 For more information www.analog.com

 LTC6228/LTC6229
TYPICAL PERFORMANCE CHARACTERISTICS
VS = ±5V, VCM = 0V, TA = 25°C, unless otherwise noted.

SHDN Pin Response Time Large Signal

Large Signal Response
Response
Input VS = ±5V
0V AV=1
500mV/DIV VS = ±5V RL=1kΩ
TA=25°C TA=25°C
Output AV=1
0V 0V
500mV/DIV 1.5V/DIV

SHDN
2.25V
1V/DIV
6228 G46 6228 G47
1µs/DIV 20ns/DIV

Small Signal Response Output Overdrive Recovery

VS = ±5V Input
RL=1kΩ
Input Output
AV=1
0
TA=25°C
50mV/DIV Input
1V/DIV
Output VS = ±5V
2V/DIV AV=2
Output RF=RG=500Ω
0 CF=2.7pF
50mV/DIV RL=1kΩ
TA=25°C
6228 G48 6228 G49
5ns/DIV 25ns/DIV

Rev. A

For more information www.analog.com 15

LTC6228/LTC6229
PIN FUNCTIONS
FB (SOIC-8 Only): Feedback Pin. Internally connected to
OUT.
+IN: Non-Inverting Input of Amplifier. Valid input range is
from V– to V+ – 1.2V
–IN: Inverting Input of Amplifier. Valid input range is from
V– to V+ – 1.2V
OUT: Output of the Amplifier. Swings rail to rail and can
typically source/sink more than 90mA of current.
SHDN: Shutdown Pin (Active Low). Referenced to V+.
When taken 2.75V below V+, the amplifier shuts down
and enters low power mode, with the outputs in a high
impedance state. When taken to within 350mV of V+, bias
current cancellation is enabled. When left floating, the
amplifier is on but bias cancellation is not enabled.
V+: Positive Supply to Amplifier. Valid range is from 2.8V
to 11.75V when V– is 0V.
V–: Negative Supply to Amplifier. Typically 0V. This can be
made a negative voltage as long as 2.8V ≤ (V+ – V–) ≤ 11.75V

Rev. A

16 For more information www.analog.com


APPLICATIONS INFORMATION
Circuit Description
The LTC6228/LTC6229 have an input signal range that
extends from the negative power supply to 1.25V below
the positive power supply. Figure 1 depicts a simplified
schematic of the amplifier. The input stage consists of
PNP transistors Q1 and Q2. At the input stage, devices
Q18 and Q19 act to cancel the bias current of the input
pair when bias cancellation is enabled. Bootstrap transistor
Q13 and R5 match the collector and emitter voltages of
Q11 and Q12, thus enhancing gain by improving output
impedance. By making the collector current of Q13 twice
that of Q11 and Q12, the base currents of Q11 and Q12
do not contribute towards mismatch between the collec-
tor currents of Q9 and Q8. This improves DC accuracy. A
pair of complementary common emitter stages, Q15 and
Q14, enables the output to swing to either rail. The SHDN
Interface block translates the SHDN signal into 2 signals,
pwr_dn for powering down the device (by deactivating
current sources I1 - I4) and putting the output in a high
impedance state (by shorting the bases of Q15/Q14 to the
LTC6228/LTC6229
supplies via M2 and M1), and disable_bias, which disables
the input bias cancellation circuit, by shorting the base of
Q19 to V– through M3.
Input Bias Current
The LTC6228 family has an input bias current of approxi-
mately 16μA. For the LTC6228 and the LTC6229DD10,
the input bias current can be reduced to under 2.5μA at
room temperature when the SHDN pin voltage is taken to
within 350mV of the positive power supply. This capabil-
ity enables the input bias current cancellation circuitry,
allowing the amplifiers to be used in DC applications
involving source impedances.
When input bias current cancellation is enabled and the
input common mode voltage is within approximately
500mV of V–, the bias cancellation is no longer effec-
tive, because transistors Q18 and Q19 in Figure 1 enter
saturation. The input bias current can then exceed 50μA
or higher, which is more than the input bias current

V+
pwr_dn I3 pwr_dn M2

Q15
+ V+ V– + R3 R4 R5
pwr_dn I2 pwr_dn I1 C2 ESDD5
ESDD1 ESDD2 Q12
Q11 Q13
+IN
pwr_dn V– CC
SHDN D5 D7
INTERFACE Q1 Q2 OUT
SHDN
BLOCK
–IN V+
disable_bias
ESDD4 ESDD3 pwr_dn I4 BUFFER
AND
OUTPUT BIAS
Q16 V– V+
Q9 Q8 ESDD6
Q10
Q17 Q18
Q19
pwr_dn M1 C1

disable_bias M3 Q14
R1 R2 R3
V–
6228 F01

Figure 1. LTC6228 Simplified Schematic Diagram

Rev. A

For more information www.analog.com 17

LTC6228/LTC6229
APPLICATIONS INFORMATION
without input bias cancellation. Additionally when input
bias current cancellation is enabled, the current noise
increases. The decision to use input bias cancellation
should be made with the end application’s specifications
and conditions in mind.
If the SHDN pin is left floating, input bias cancellation is
not enabled, which may be suitable for many applications.
Output
The LTC6228 family has excellent output drive capability.
The amplifiers can typically deliver more than 90mA of
output current at a total supply of 10V, and can typically
swing to within 320mV of the supply with load currents
as high as 25mA. As the supply voltage to the amplifier
decreases, the output current capability also decreases.
Attention must be paid to keep the junction temperature
of the IC below 150°C (refer to Power Dissipation section)
when the output is in continuous short-circuit. The output
of the amplifier has reverse-biased diodes connected to
each supply. If the output is forced beyond either supply,
extremely high currents will flow through those diodes,
which may result in damage to the device.
Input Protection
The LTC6228 has a pair of back to back diodes (D5 and
D7) to prevent the emitter base breakdown of the input
transistors and limit the differential input to ±700mV.
Unlike many other high performance amplifiers, the
bases of the input pair transistors Q1 and Q2 are not
connected to the pins through internal resistors to limit
input current, since doing so would cause the noise to
increase. For instance, a 100Ω resistor in series with
each input generates 1.8nV/√Hz of noise, and the total
amplifier noise voltage would rise from 0.88nV/√Hz to
2nV/√Hz. If the input differential voltage exceeds ±0.7V,
current conducted though the protection diodes D5 and
D7 should be limited to under 10mA. This implies 25Ω of
protection resistance per quarter volt (250mV) of overdrive
beyond ±0.7V. In addition, the input and shutdown pins
18 For more information www.analog.com
have reverse biased diodes connected to the supplies. The
current in these diodes must be limited to under 10mA.
The amplifiers should not be used as comparators or in
other open loop applications.
ESD
The LTC6228 family has reverse biased ESD protection
diodes on all inputs as shown in Figure 1. There is an
additional clamp between the positive and negative sup-
plies that further protects the device during ESD strikes.
Hot plugging of the device into a powered socket should
be avoided since this can trigger the clamp resulting in
larger currents flowing between the supply pins.
Capacitive Loads
Because the LTC6228/LTC6229 is designed for high
bandwidth applications, the output has not been designed
to drive capacitive loads directly. Load capacitance at the
output creates a non-dominant pole in the open loop fre-
quency response, worsening the phase margin. When
driving capacitive loads, a resistor of 10Ω to 100Ω should
be connected between the amplifier output and the capac-
itive load to avoid ringing or oscillation. The feedback
should be taken directly from the amplifier output. Higher
voltage gain configurations tend to have better capaci-
tive drive capability than lower gain configurations due
to lower closed loop bandwidth. The graphs titled Series
Output Resistor vs Capacitive Load demonstrate the tran-
sient response of the amplifier when driving capacitive
loads with various series resistors.
Feedback Components
When feedback resistors are used to set up gain, care
must be taken to ensure that the non-dominant pole
formed by the feedback resistors and the parasitic capaci-
tance at the inverting input does not degrade stability. For
example if the amplifier is set up in a gain of +2 configu-
ration with gain and feedback resistors of 1k, a parasitic
capacitance of 7pF (device + PC board) at the amplifier’s
Rev. A

APPLICATIONS INFORMATION
inverting input will cause the part to oscillate, due to the
pole formed at 45MHz. Adding a capacitor of 7pF across
the feedback resistor as shown in Figure 2 will eliminate
any ringing or oscillation. In general, if the resistive feed-
back network results in a pole whose frequency lies within
the closed loop bandwidth of the amplifier, a capacitor can
be added in parallel with the feedback resistor to introduce
a zero whose frequency is close to the frequency of the
pole, improving stability.
7pF
1k
– half of either supply voltage for a given load resistance.
1k CPAR VOUT
+ output load current) given by:
VIN 6228 F02
Figure 2. 7pF Feedback Cancels Parasitic Pole
For high speed designs, minimizing parasitic inductance
is important. The use of capacitors where the electrodes
are terminated on the long side instead of the short side
(for example the use of 0306 instead of 0603 compo-
nents) can help in this regard.
Shutdown
The LTC6228/LTC6229 have shutdown pins (SHDN),
which disable the amplifiers and reduce the quiescent
current per channel to approximately 500µA. The SHDN
pin needs to be driven at least 2.75V below V+ to disable
amplifier operation. For total supply voltages of 5V and or
less, the amplifier can be disabled at a pin voltage of V+ –
2.65V. During shutdown, the output transistors Q15 and
Q14 in Figure 1 are placed into a high impedance state. If
SHDN is left floating, the pin is internally biased to 1.2V
below the positive supply, and the amplifier remains on.
For more information www.analog.com
LTC6228/LTC6229
Power Dissipation
Care must be taken to ensure that the junction tempera-
ture of the die does not exceed 150°C.
The junction temperature, TJ, is calculated from the ambi-
ent temperature, TA, power dissipation, PD, and thermal
resistance, θJA:
TJ = TA + (PD • θJA).
The power dissipation in the IC is a function of the supply
voltage, output voltage and load resistance. For a given
supply voltage with output load connected to mid supply,
the worst-case power dissipation PD(MAX) occurs when
the supply current is maximum and the output voltage at
PD(MAX) is approximately (since IS actually changes with
PD(MAX) = (2 • VS • IS(MAX)) + (VS/2)2/RL
Example: For an LTC6228 in a 6-lead DC package operat-
ing on ±5V supplies and driving a 500Ω load to ground,
the worst-case power dissipation is approximately given
by PD(MAX)/Amp = (10 • 19mA) + (5)2/500 = 240mW.
At the Absolute Maximum ambient operating temperature,
the junction temperature under these conditions will be:
TJ = TA + (PD • θJA) = 125 + 0.24 • 80 = 144.2°C
which is slightly less than the absolute maximum junction
temperature for the LTC6228/LTC6229.
Refer to the Pin Configuration section for thermal resis-
tances of various packages
Board Layout and Bypass Capacitors
High speed and RF board layout techniques should be
used due to the very high speeds of the signals involved.
For the LTC6228 SOIC-8 package option, the feedback
should be taken from the FB pin rather than from the
output pin, to reduce signal trace length.
Rev. A
19
LTC6228/LTC6229
APPLICATIONS INFORMATION
Stray capacitances at the –IN and +IN pins should be
made as low as possible to reduce stability degradation.
For example, ground or supply planes on a PCB should
not encompass the areas just beneath the input pins.
For single supply applications, it is recommended that high
quality 0.1µF||1000pF ceramic bypass capacitors be placed
directly between each V+ pin and its closest V– pin with
short connections. The V– pins (including the Exposed Pad)
should be tied directly to a low impedance ground plane
with minimal routing. For dual (split) power supplies, it is
recommended that additional high quality 0.1µF||1000pF
ceramic capacitors be used to bypass V+ pins to ground
and V– pins to ground, again with minimal routing.
Noise Considerations
The ultralow input referred voltage noise of 0.88nV/√Hz is
equivalent to that of a 47Ω resistor at room temperature.
As with all BJT input amplifiers, lowering input referred
voltage noise is achieved by increasing the collector cur-
rent of the input differential pair, which increases the input
referred current noise.
RG RF
in
–
en LTC6228
RS1
+ As evident from the previous section, gain stage noise
in
6228 F03
Figure 3.
Figure 3 shows the LTC6228 in a typical gain configuration.
As can be seen, the input referred noise spectral density
of the gain stage (eT) can be calculated by the following
equations:
eT2 = en2 + in2REQ2 + 4KTREQ
}
}
Op amp input referred noise dominates the input referred
noise of the gain stage when
REQ << en2/4KT
Resistor noise dominates the input referred noise of the
gain stage when
REQ >> en2/4KT and REQ << 4KT/in2
Op amp input referred current noise dominates the input
referred noise when
REQ >> 4kT/in2
To summarize, initially en dominates for low resistance val-
ues. As the resistance increased, resistor noise starts to
dominate, then on further increase current noise dominates.
With an input referred voltage noise spectral density of
0.88nV/Hz and an input referred current noise of 3pA/Hz
(bias cancellation disabled), it is easy to see that the gain
stage’s input referred noise is dominated by op amp volt-
age noise when REQ << 47Ω and by resistor noise when
55Ω << REQ << 1.8kΩ.
Above an REQ of 1.8kΩ, input referred current noise
dominates.
Distortion/Noise Trade-Off
can be reduced by reducing REQ. However, reducing REQ,
by reducing RF and RG, has its disadvantages. In addition
to increasing power dissipation in the presence of large
output signals, the use of smaller resistors for a given
gain results in increased distortion, because the internal
nonlinearities of the op amp worsen with increasing load
current. In addition, smaller resistors decrease op amp
gain and hence can affect bandwidth. The disadvantage,
however of making the resistors too large is that parasitic
capacitance can start to affect the gain at high frequen-
cies. Hence when designing a system using the LTC6228,

opamp opamp resistor

voltage current thermal it is recommended that the resistor values be limited only
noise noise noise by the system noise requirements, with the caveat that the
effect of the impedances parasitic capacitances shouldn’t
Where
affect the gain below the intended bandwidth. For exam-
REQ = RS1 + RG||RF ple, for a feedback resistor of 5k, a parasitic capacitor of
400F will impact gain at frequencies above 79MHz.
Rev. A

20 For more information www.analog.com

 LTC6228/LTC6229
TYPICAL APPLICATIONS
18-Bit High Speed ADC Driver of supply voltage. An RC snubber is used at the common
terminal of the 30Ω gain setting resistors to reduce the
The ultralow noise and distortion performance of the
effects of any board induced layout coupling from the
LTC6228 makes it an excellent candidate for driving high
output of one amplifier to the negative input of the other.
speed high resolution ADCs with fast, large amplitude
Figure 7 shows the measured frequency response of the
signals. Figure 4 shows a pair of LTC6228s driven by a dif-
instrumentation amplifier for a load of 1kΩ. Figure  8
ferential input, driving an LTC2387-18, a 15Msps, 18-bit
shows the measured CMRR of the instrumentation
ADC. Figure 5 shows an FFT obtained with a –1dBFS,
amplifier, and Figure 9 shows the transient response for
1MHz input signal. The obtained SNR is 93.4dB, better
a 50mVP-P input square wave applied to the positive input,
than the LTC2387-18’s guaranteed SNR of 93dB, and
with the negative input grounded. The total supply voltage
close to its typical value of 95.7dB. Spurious free dynamic
was 3.3V. The extremely low offset voltage and low 1/f
range is an excellent 95dB, close to the LTC2387-18’s
noise at the LTC6229 inputs allow for wide band instru-
guaranteed SFDR of 97dB.
mentation amplifier operation, down to DC. Note, the bias
High Speed Low Voltage Low Noise Instrumentation currents of the LTC6229 are higher than might appear in
Amplifier a traditional low speed instrumentation amplifier. High
speed instrumentation such as in Figure 6 assume a cor-
Figure 6 shows a three op amp instrumentation amplifier respondingly low enough impedance excitation.
with a gain of 41V/V which can operate on a wide range

7.5V

4.096V + CLK
LTC6228 DCO LVDS
0V 25Ω
IN+ DA INTERFACE
–
82pF DB

LTC2387-18
82pF TWOLANES
4.096V + IN–
TESTPAT
25Ω
LTC6228 VCM PD
0V
0.1µF
– REFB CNV
SAMPLE
CLOCK
–2.5V 6228 F04

Figure 4. High Speed Driver for 18-Bit ADC

8192 Point FFT, –1dBFS

fSMPL = 15Msps, fIN = 1MHz
0
7.3VP-P 1MHz INPUT SIGNAL
SNR = 93.4dB
–20
SFDR = 95dB
THD = –93.8dB
–40
AMPLITUDE (dBFS)

–60

–80

–100

–120

–140
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5
FREQUENCY (MHz)
6228 F05

Figure 5. Measured Performance of LTC6228 Based Driver Driving the LTC2387-18

Rev. A

For more information www.analog.com 21

LTC6228/LTC6229
TYPICAL APPLICATIONS
VS+

+IN + R4 R6
U1 750Ω 750Ω
1/2 LTC6229
–
R1 R2 VS+
30Ω 1.2k
R9 +
49.9Ω U3
R8 R3 VOUT
30Ω 1.2k LTC6228
C2 –
200pF
– VS– VS = ±1.65V
R5 R7 GAIN = 41V/V
U2 750Ω 750Ω ISUPPLY = 49mA
1/2 LTC6229 BW = 24MHz
+ en (1MHz) = 1.79nV/√Hz
–IN
C1
VS–
2.2pF 6228 F06

Figure 6. High Speed Low Voltage Low Noise Instrumentation Amplifier

40 100
COMMON MODE REJECTION RATIO (dB) 90
30
80
20
70
10 60
GAIN (dB)

0 50
40
–10
30
–20
20
–30 10
–40 0
10k 100k 1M 10M 100M 500M 10k 100k 1M 10M 100M 500M
FREQUENCY (Hz) FREQUENCY (Hz)
6228 F07 6228 F08

Figure 7. Instrumentation Amplifier Frequency Response Figure 8. Instrumentation Amplifier CMRR

OUTPUT
1V/DIV
0V

INPUT
25mV/DIV
0V

6228 F09
50ns/DIV

Figure 9. Transient Response

Rev. A

22 For more information www.analog.com


TYPICAL APPLICATIONS
Wideband Differential to Single-Ended Converter
The combination of high slew rate and bandwidth enables
the LTC6228 to be used as a translator for large signals
at high frequencies.
Figure 10 shows the implementation of a wide band, dif-
ferential to single-ended converter with a gain of –6dB
LTC6228/LTC6229
using just one LTC6228. Figure 11 shows the frequency
response of the circuit for a differential input of 2VP-P. The
bandwidth obtained was 50MHz. The common mode gain
of the driver is shown in Figure 12, and is limited by the
matching between the resistors in the circuit. Figure 13
shows the response of the driver to a 1VP-P differential
square wave signal.
CF1
18pF

R1
200Ω

R3 R7 5V
49.9Ω 348Ω – RO1
VIN1
+ 49.9Ω
CF2 LTC6228 VOUT
18pF + –
–5V
R6 R5 R4
49.9Ω 150Ω 100Ω
VIN2
6228 F10

Figure 10. Wideband Differential to Single-Ended Converter

0 10
–3 0 USING 1% RESISTORS
–6 –10
–9 –20
–12 –30
GAIN (dB)

GAIN (dB)

–15 –40
–18 –50
–21 –60
–24 –70
–27 –80
–30 –90
100kHz 1MHz 10MHz 100MHz 100k 1M 10M 100M
FREQUENCY(Hz) FREQUENCY (Hz)
6228 F11 6228 F12

Figure 11. Frequency Response of Differential to Figure 12. Common Mode Gain vs Frequency

Single-Ended Converter

100mV/DIV

6228 F13
200ns/DIV

Figure 13. Pulse Response of the Differential to Single-Ended Converter

Rev. A

For more information www.analog.com 23

LTC6228/LTC6229
PACKAGE DESCRIPTION
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610 Rev G)
.189 – .197
.045 ±.005 (4.801 – 5.004)
.050 BSC NOTE 3
8 7 6 5

.245
MIN .160 ±.005
.150 – .157
.228 – .244
(3.810 – 3.988)
(5.791 – 6.197)
NOTE 3

.030 ±.005
TYP
1 2 3 4
RECOMMENDED SOLDER PAD LAYOUT

.010 – .020
× 45° .053 – .069
(0.254 – 0.508)
(1.346 – 1.752)
.004 – .010
.008 – .010
0°– 8° TYP (0.101 – 0.254)
(0.203 – 0.254)

.016 – .050
.014 – .019 .050
(0.406 – 1.270)
(0.355 – 0.483) (1.270)
NOTE: TYP BSC
INCHES
1. DIMENSIONS IN
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) SO8 REV G 0212

4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE

Rev. A

24 For more information www.analog.com

 LTC6228/LTC6229
PACKAGE DESCRIPTION
DC6 Package
6-Lead Plastic DFN (2mm × 2mm)
(Reference LTC DWG # 05-08-1703 Rev C)

0.70 ±0.05

2.55 ±0.05
1.15 ±0.05 0.60 ±0.10
(2 SIDES)
PACKAGE
OUTLINE

0.25 ±0.05
0.50 BSC
1.37 ±0.10
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.125 0.40 ±0.10
TYP
0.60 ±0.10 4 6
(2 SIDES)

2.00 ±0.10 PIN 1 NOTCH

(4 SIDES) R = 0.20 OR
PIN 1 BAR
TOP MARK 0.25 × 45°
(SEE NOTE 6) CHAMFER
R = 0.05 (DC6) DFN REV C 0915

TYP 3 1
0.25 ±0.05
0.200 REF 0.75 ±0.05 0.50 BSC
1.37 ±0.10
(2 SIDES)
0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD

NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WCCD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE

Rev. A

For more information www.analog.com 25

LTC6228/LTC6229
PACKAGE DESCRIPTION
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)

0.62 0.95 2.90 BSC

MAX REF (NOTE 4)

1.22 REF

2.80 BSC 1.50 – 1.75

3.85 MAX 2.62 REF 1.4 MIN (NOTE 4)

PIN ONE ID

RECOMMENDED SOLDER PAD LAYOUT 0.30 – 0.45

0.95 BSC
PER IPC CALCULATOR 6 PLCS (NOTE 3)

0.80 – 0.90

0.20 BSC
0.01 – 0.10
1.00 MAX
DATUM ‘A’

0.30 – 0.50 REF

0.09 – 0.20 1.90 BSC
(NOTE 3) S6 TSOT-23 0302
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193

Rev. A

26 For more information www.analog.com

 LTC6228/LTC6229
PACKAGE DESCRIPTION
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699 Rev C)

0.70 ±0.05

3.55 ±0.05 1.65 ±0.05

2.15 ±0.05 (2 SIDES)

PACKAGE
OUTLINE

0.25 ±0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R = 0.125 0.40 ±0.10

TYP
6 10

3.00 ±0.10 1.65 ±0.10

(4 SIDES) (2 SIDES) PIN 1 NOTCH
PIN 1 R = 0.20 OR
TOP MARK 0.35 × 45°
(SEE NOTE 6) CHAMFER
(DD) DFN REV C 0310

5 1
0.200 REF 0.75 ±0.05 0.25 ±0.05
0.50 BSC
2.38 ±0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD

NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE

Rev. A

For more information www.analog.com 27

LTC6228/LTC6229
PACKAGE DESCRIPTION
MS8E Package
8-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1662 Rev K)
BOTTOM VIEW OF
EXPOSED PAD OPTION
1.88
1 (.074) 0.29
1.88 ±0.102 1.68 REF
(.074 ±.004) 0.889 ±0.127
(.035 ±.005) (.066)

0.05 REF
5.10 DETAIL “B”
1.68 ±0.102 3.20 – 3.45 CORNER TAIL IS PART OF
(.201)
(.066 ±.004) (.126 – .136)
MIN DETAIL “B” THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
8
NO MEASUREMENT PURPOSE
3.00 ±0.102
0.65 0.52
0.42 ±0.038 (.118 ±.004)
(.0256)
(.0165 ±.0015) (NOTE 3) 8 7 6 5 (.0205)
BSC
TYP REF
RECOMMENDED SOLDER PAD LAYOUT

3.00 ±0.102
4.90 ±0.152
DETAIL “A” (.118 ±.004)
0.254 (.193 ±.006)
(NOTE 4)
(.010)
0° – 6° TYP
GAUGE PLANE
1 2 3 4
0.53 ±0.152
(.021 ±.006) 1.10 0.86
(.043) (.034)
DETAIL “A” MAX REF
0.18
(.007)
SEATING
PLANE 0.22 – 0.38 0.1016 ±0.0508
(.009 – .015) (.004 ±.002)
0.65
TYP MSOP (MS8E) 0213 REV K
(.0256)
NOTE:
BSC
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD
SHALL NOT EXCEED 0.254mm (.010") PER SIDE.

Rev. A

28 For more information www.analog.com

 LTC6228/LTC6229
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 09/19 Added LTC6229 to Data Sheet All

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
Forgranted
subject to change without notice. No license is morebyinformation www.analog.com
implication or otherwise under any patent or patent rights of Analog Devices. 29
LTC6228/LTC6229
TYPICAL APPLICATION
Photodiode Amplifier Noise Spectrum
1000

OUTPUT VOLTAGE NOISE (nV√Hz)

High Speed High Dynamic Range Photodiode Amplifier 800

R1 600
1MΩ

5 400

C3 R3 200
1µF 604Ω
C1 0
0.055pF 100kHz 1MHz 10MHz
J1 (PARASITIC)
5 6228 TA02b
ON-SEMI
D1 2SK932-22 –
PHOTODIODE + Photodiode Amplifier Transient Response
SFH213 R7
LTC6228
–5 1.21kΩ
+ – OUT

–5
–5 RISE TIME = 77ns
–3dB BW = 4.6MHz
200mV/DIV
INTEGRATED NOISE = 661µVRMS
OVER 4.6MHz 6228 TA02a

6228 TA02c
100ns/DIV

RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
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LTC6246/LTC6247/ Single/Dual/Quad High Speed Rail-to-Rail Input and Output 180MHz, 1mA, 4.2nV/√Hz, 90V/µs, 0.5mV
LTC6248 Op Amps
LT6238/LT6237/ Single/Dual/Quad Low Noise Rail-to-Rail Output Op Amps 215MHz, 3.5mA, 1.1nV/√Hz, 70V/µs, 350µV
LT6232
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LT1468 16-Bit Accurate Precision High Speed Op Amp 90MHz, 3.9mA, 5nV/√Hz, 22V/µs, 175µV,
–96.5dB THD at 10VP-P, 100kHz
ADA4899-1 Unity Gain Stable Ultra Low Distortion 1nV/√Hz 600MHz, 310V/µs, 4.5V to 10V Operation
LT1028/LT1128 Ultralow Noise, Precision High Speed Op Amps 75MHz, 9.5mA, 0.85nV/√Hz, 11V/µs, 40µV
ADCs
LTC2387-18 18-Bit, 15Msps SAR-ADC 95.7dB SNR
LTC2393-16 1Msps 16-Bit SAR-ADC 94dB DNR
LTC2378-20 20-bit,1 Msps Low Power SAR-ADC 104 dB SNR/105 dB THD at 100kHz
AD7625 16-Bit 6Msps PulSAR ADC ®
93dB SNR
AD4020 20-Bit, 1.8Msps Precision SAR-ADC 99dB SNR/100db THD at 100kHz
Rev. A

30
09/19
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