Summary

A flyback converter is designed which shows a full load efficiency of 91.77%. The
switching frequency used is 100 kHz and for designing the transformer, an EE70
core has been used. The converter operates in continuous current mode. Both
Voltage mode and current mode control system have been developed that allows
to meet all the design specifications i.e. output voltage ripple, overshoot etc. The
analog implementation of the control system has also been carried out.

Complaince Table
Parameters Design Requirements Achieved Results
Vin (V) 65-85 75
Vout (V) & Pout (W) 25 V, 150 W 24.65 V, 145.83 W
50 V, 100 W 49.54 V, 98.17 W
150 V, 300 W 150 V, 300 W
Efficiency (%) 91-92 91.77
Vout (ripple) (%) 1 0.37
(Peak-Peak) 0.3
0.12
Switching frequency 50 kHz (min.) or 100 kHz
higher
Section 1:
Design of the converter (Steady-state analysis)
The circuit diagram of single input three output flyback converter is as follows:

Subinterval 0 ≤ t ≤ DTs

−𝑉𝑉𝑔𝑔 + 𝑉𝑉𝐿𝐿 𝑚𝑚 = 0

⇒ 𝑉𝑉𝑔𝑔 = 𝑉𝑉𝐿𝐿 𝑚𝑚

𝐼𝐼𝑔𝑔 = 𝐼𝐼
 𝑉𝑉1
𝐼𝐼𝐶𝐶 1 = −
𝑅𝑅1
𝑉𝑉2
𝐼𝐼𝐶𝐶 2 = −
𝑅𝑅2
𝑉𝑉3
𝐼𝐼𝐶𝐶 3 = −
𝑅𝑅3
Subinterval DTs ≤ t ≤ Ts

−𝑉𝑉𝐿𝐿 𝑚𝑚 + 𝑉𝑉𝑃𝑃 = 0

⇒ 𝑉𝑉𝑃𝑃 = 𝑉𝑉𝐿𝐿 𝑚𝑚

𝑉𝑉𝑆𝑆1 = 𝑉𝑉1

𝑉𝑉𝑆𝑆 2 = 𝑉𝑉2

𝑉𝑉𝑆𝑆 3 = 𝑉𝑉3

𝑉𝑉𝑃𝑃 𝑉𝑉𝑆𝑆 𝑉𝑉𝑆𝑆 𝑉𝑉𝑆𝑆

=− 1=− 2=− 3
𝑛𝑛𝑃𝑃 𝑛𝑛𝑆𝑆 1 𝑛𝑛𝑆𝑆 2 𝑛𝑛𝑆𝑆 3
𝑛𝑛𝑃𝑃 𝑛𝑛𝑃𝑃 𝑛𝑛𝑃𝑃
⇒ 𝑉𝑉𝑃𝑃 = − 𝑉𝑉𝑆𝑆1 = − 𝑉𝑉𝑆𝑆 2 = − 𝑉𝑉
𝑛𝑛𝑆𝑆 1 𝑛𝑛𝑆𝑆 2 𝑛𝑛𝑆𝑆 3 𝑆𝑆 3
 𝑛𝑛𝑃𝑃 𝑛𝑛𝑃𝑃 𝑛𝑛𝑃𝑃
⇒ 𝑉𝑉𝐿𝐿𝑚𝑚 = − 𝑉𝑉1 = − 𝑉𝑉2 = − 𝑉𝑉
𝑛𝑛𝑆𝑆 1 𝑛𝑛𝑆𝑆 2 𝑛𝑛𝑆𝑆 3 3
𝑛𝑛𝑆𝑆 1
𝑉𝑉1 = − 𝑉𝑉
𝑛𝑛𝑃𝑃 𝐿𝐿 𝑚𝑚
𝑛𝑛𝑆𝑆 2
𝑉𝑉2 = − 𝑉𝑉
𝑛𝑛𝑃𝑃 𝐿𝐿 𝑚𝑚
𝑛𝑛𝑆𝑆 3
𝑉𝑉3 = − 𝑉𝑉
𝑛𝑛𝑃𝑃 𝐿𝐿 𝑚𝑚
𝑛𝑛𝑆𝑆 1 + 𝑛𝑛𝑆𝑆 2 + 𝑛𝑛𝑆𝑆 3
𝑉𝑉1 + 𝑉𝑉2 + 𝑉𝑉3 = − 𝑉𝑉𝐿𝐿 𝑚𝑚
𝑛𝑛𝑃𝑃
𝑉𝑉1 + 𝑉𝑉2 + 𝑉𝑉3
⇒ 𝑉𝑉𝐿𝐿 𝑚𝑚 = − 𝑛𝑛
𝑛𝑛𝑆𝑆 1 + 𝑛𝑛𝑆𝑆 2 + 𝑛𝑛𝑆𝑆 3 𝑃𝑃

𝑛𝑛𝑃𝑃 𝐼𝐼𝑃𝑃 = −�𝑛𝑛𝑆𝑆1 𝐼𝐼𝑆𝑆 1 + 𝑛𝑛𝑆𝑆2 𝐼𝐼𝑆𝑆 2 + 𝑛𝑛𝑆𝑆3 𝐼𝐼𝑆𝑆 3 �

𝜆𝜆1
𝐼𝐼𝑚𝑚,𝑝𝑝𝑝𝑝 =
2𝐿𝐿𝑚𝑚
Volt-sec balance in inductor Lm
𝑉𝑉1 + 𝑉𝑉2 + 𝑉𝑉3
〈𝑉𝑉𝐿𝐿 𝑚𝑚 〉 = 𝑉𝑉𝑔𝑔 𝐷𝐷𝑇𝑇𝑠𝑠 + �− 𝑛𝑛 � 𝐷𝐷′ 𝑇𝑇𝑠𝑠 = 0
𝑛𝑛𝑆𝑆 1 + 𝑛𝑛𝑆𝑆 2 + 𝑛𝑛𝑆𝑆 3 𝑃𝑃
𝑉𝑉1 + 𝑉𝑉2 + 𝑉𝑉3
⇒ 𝑉𝑉𝑔𝑔 𝐷𝐷 − 𝑛𝑛 𝐷𝐷′ = 0
𝑛𝑛𝑆𝑆 1 + 𝑛𝑛𝑆𝑆 2 + 𝑛𝑛𝑆𝑆 3 𝑃𝑃

𝑉𝑉1 + 𝑉𝑉2 + 𝑉𝑉3 𝐷𝐷′

⇒ 𝑉𝑉𝑔𝑔 = 𝑛𝑛𝑃𝑃
𝑛𝑛𝑆𝑆 1 + 𝑛𝑛𝑆𝑆 2 + 𝑛𝑛𝑆𝑆 3 𝐷𝐷

𝐷𝐷′
⇒ 𝑉𝑉𝑔𝑔 = −𝑉𝑉𝐿𝐿 𝑚𝑚
𝐷𝐷
𝑛𝑛𝑃𝑃 𝐷𝐷′
⇒ 𝑉𝑉𝑔𝑔 = 𝑉𝑉
𝑛𝑛𝑆𝑆 1 1 𝐷𝐷
𝑉𝑉1 𝑛𝑛𝑆𝑆 1 𝐷𝐷
=
𝑉𝑉𝑔𝑔 𝑛𝑛𝑃𝑃 (1 − 𝐷𝐷)

Similarly,
𝑉𝑉2 𝑛𝑛𝑆𝑆 2 𝐷𝐷
=
𝑉𝑉𝑔𝑔 𝑛𝑛𝑃𝑃 (1 − 𝐷𝐷)
 𝑉𝑉3 𝑛𝑛𝑆𝑆 3 𝐷𝐷
=
𝑉𝑉𝑔𝑔 𝑛𝑛𝑃𝑃 (1 − 𝐷𝐷)

For an operating point, D, V1, V2, V3, Vg are known. We can calculate ns1/np, ns2/np, ns3/np.
𝑉𝑉𝑂𝑂 1 𝑁𝑁𝑆𝑆 1 𝐷𝐷
𝑀𝑀𝑉𝑉 1 = =
𝑉𝑉𝑃𝑃 𝑁𝑁𝑃𝑃 (1 − 𝐷𝐷)
𝑉𝑉𝑂𝑂 2 𝑁𝑁𝑆𝑆 2 𝐷𝐷
𝑀𝑀𝑉𝑉 2 = =
𝑉𝑉𝑃𝑃 𝑁𝑁𝑃𝑃 (1 − 𝐷𝐷)
𝑉𝑉𝑂𝑂 3 𝑁𝑁𝑆𝑆 3 𝐷𝐷
𝑀𝑀𝑉𝑉 3 = =
𝑉𝑉𝑃𝑃 𝑁𝑁𝑃𝑃 (1 − 𝐷𝐷)
Charge balance on capacitor C1
𝑉𝑉1 𝑉𝑉1
〈𝐼𝐼𝐶𝐶 1 〉 = �− � 𝐷𝐷𝑇𝑇𝑠𝑠 + �𝐼𝐼𝑆𝑆 1 − � 𝐷𝐷′ 𝑇𝑇𝑠𝑠 = 0
𝑅𝑅1 𝑅𝑅1
𝑉𝑉1
⇒ 𝐼𝐼𝑆𝑆 1 𝐷𝐷′ 𝑇𝑇𝑠𝑠 − =0
𝑅𝑅1
𝑉𝑉1
𝐼𝐼𝑆𝑆 1 =
𝑅𝑅1 𝐷𝐷′
Similarly,
𝑉𝑉2
𝐼𝐼𝑆𝑆 2 =
𝑅𝑅2 𝐷𝐷′
𝑉𝑉3
𝐼𝐼𝑆𝑆 3 =
𝑅𝑅3 𝐷𝐷′

Circuit analysis of non-ideal flyback converter is also done by taking the non-idealities of the
components into account as follows:
Subinterval 0 ≤ t ≤ DTs

𝑉𝑉𝐿𝐿 𝑚𝑚 = 𝑉𝑉𝑔𝑔 − 𝐼𝐼𝑔𝑔 𝑅𝑅𝑂𝑂𝑂𝑂

Subinterval DTs ≤ t ≤ Ts

𝑉𝑉𝑆𝑆1 − 𝑉𝑉𝑓𝑓 = 𝑉𝑉1

1

𝑉𝑉𝑆𝑆 2 − 𝑉𝑉𝑓𝑓 = 𝑉𝑉2

2

𝑉𝑉𝑆𝑆 3 − 𝑉𝑉𝑓𝑓 = 𝑉𝑉3

3
 𝑛𝑛𝑃𝑃 𝑛𝑛𝑃𝑃 𝑛𝑛𝑃𝑃
𝑉𝑉𝐿𝐿 𝑚𝑚 = 𝑉𝑉𝑃𝑃 = − 𝑉𝑉𝑆𝑆1 = − 𝑉𝑉𝑆𝑆 2 = − 𝑉𝑉
𝑛𝑛𝑆𝑆 1 𝑛𝑛𝑆𝑆 2 𝑛𝑛𝑆𝑆 3 𝑆𝑆 3
𝑛𝑛𝑃𝑃 𝑛𝑛𝑃𝑃 𝑛𝑛𝑃𝑃
𝑉𝑉𝐿𝐿 𝑚𝑚 = 𝑉𝑉𝑃𝑃 = − �𝑉𝑉𝑓𝑓 + 𝑉𝑉1 � = − �𝑉𝑉𝑓𝑓 + 𝑉𝑉2 � = − �𝑉𝑉 + 𝑉𝑉3 �
𝑛𝑛𝑆𝑆 1 1 𝑛𝑛𝑆𝑆 2 2 𝑛𝑛𝑆𝑆 3 𝑓𝑓 3

Volt-sec balance in inductor:

〈𝑉𝑉𝐿𝐿 𝑚𝑚 〉 = 0

𝑛𝑛𝑃𝑃
⇒ �𝑉𝑉𝑔𝑔 − 𝐼𝐼𝑔𝑔 𝑅𝑅𝑂𝑂𝑂𝑂 �𝐷𝐷𝑇𝑇𝑠𝑠 + �− �𝑉𝑉 + 𝑉𝑉1 �� 𝐷𝐷′ 𝑇𝑇𝑠𝑠 = 0
𝑛𝑛𝑆𝑆 1 𝑓𝑓 1

𝑛𝑛𝑃𝑃 𝐷𝐷′
⇒ 𝑉𝑉𝑔𝑔 = 𝐼𝐼𝑔𝑔 𝑅𝑅𝑂𝑂𝑂𝑂 + �𝑉𝑉𝑓𝑓 + 𝑉𝑉1 �
𝑛𝑛𝑆𝑆 1 1 𝐷𝐷
𝑃𝑃𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡 𝑛𝑛𝑃𝑃 (1 − 𝐷𝐷)
⇒ 𝑉𝑉𝑔𝑔 = 𝑅𝑅𝑂𝑂𝑂𝑂 + �𝑉𝑉𝑓𝑓 + 𝑉𝑉1 �
𝑉𝑉𝑔𝑔 √𝐷𝐷 𝑛𝑛𝑆𝑆 1 1 𝐷𝐷

From the above equation, we can see that the non-idealities affect the value of required D to
meet the specifications of the converter.

-------------------------------------------------------------------------------------------------------------------------------
Now comes the selection of device and transformer design. For that, we need to allocate the loss
to different component. We start the design by assuming 91.5% efficiency of the flyback
converter, which is according to the specification of the project.

Section 2, 3, 4:

Designing the single input three output flyback transformer (MATLAB

code Transformer_Design_Kg_method.m is used for doing the transformer design iterations)

At first, 30% of the loss, i.e. 15 W is allocated to the transformer. Transformer magnetizing
current was assumed to have a ripple factor of 0.4. Magnetizing inductance, Lm was chosen to
be 120 uH to avoid DCM operation of the converter at light load condition.
The table below shows the values of different parameters for primary design of the transformer:

Components Value
Vg 75 V
V1 25 V
 V2 50 V
V3 150 V
P1 150 W
P2 100 W
P3 300 W
D 0.38
fs 100kHz
R1 4.17 Ω
R2 25 Ω
R3 75 Ω
rf 0.4
Lm 120μH

The rms currents in the primary and secondary windings are given below:

𝐼𝐼𝑃𝑃,𝑟𝑟𝑟𝑟𝑟𝑟 = 𝐼𝐼𝑀𝑀 √𝐷𝐷

𝐼𝐼𝑆𝑆1,𝑟𝑟𝑟𝑟𝑟𝑟 = 𝐼𝐼𝑆𝑆1 √𝐷𝐷

𝐼𝐼𝑆𝑆2,𝑟𝑟𝑟𝑟𝑟𝑟 = 𝐼𝐼𝑆𝑆2 √𝐷𝐷

𝐼𝐼𝑆𝑆3,𝑟𝑟𝑟𝑟𝑟𝑟 = 𝐼𝐼𝑆𝑆3 √𝐷𝐷

The total rms winding current is equal to:
𝑛𝑛𝑆𝑆 1 𝑛𝑛𝑆𝑆 𝑛𝑛𝑆𝑆
𝐼𝐼𝑡𝑡𝑡𝑡𝑡𝑡 = 𝐼𝐼𝑃𝑃,𝑟𝑟𝑟𝑟𝑟𝑟 + 𝐼𝐼𝑆𝑆 1,𝑟𝑟𝑟𝑟𝑟𝑟 + 2 𝐼𝐼𝑆𝑆 2,𝑟𝑟𝑟𝑟𝑟𝑟 + 3 𝐼𝐼𝑆𝑆 3,𝑟𝑟𝑟𝑟𝑟𝑟
𝑛𝑛𝑃𝑃 𝑛𝑛𝑃𝑃 𝑛𝑛𝑃𝑃
∆𝑖𝑖𝑀𝑀 = (𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟 𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓)𝐼𝐼𝑀𝑀
𝑉𝑉𝑔𝑔 𝐷𝐷𝑇𝑇𝑠𝑠
𝐿𝐿𝑀𝑀 =
2∆𝑖𝑖𝑀𝑀
Steps for designing the transformer: (Reference Erickson’s Book)

1. Determine core size

𝜌𝜌𝐿𝐿2𝑀𝑀 𝐼𝐼𝑡𝑡𝑡𝑡𝑡𝑡
2 2
𝐼𝐼𝑀𝑀,𝑚𝑚𝑚𝑚𝑚𝑚 8
𝐾𝐾𝑔𝑔 ≥ 2 𝑃𝑃 𝐾𝐾
10
𝐵𝐵𝑚𝑚𝑚𝑚𝑚𝑚 𝑐𝑐𝑐𝑐 𝑢𝑢

2. Determine air gap length

2
𝜇𝜇0 𝐿𝐿𝑀𝑀 𝐼𝐼𝑀𝑀,𝑚𝑚𝑚𝑚𝑚𝑚
𝑙𝑙𝑔𝑔 = 2 𝐴𝐴
104
𝐵𝐵𝑚𝑚𝑚𝑚𝑚𝑚 𝑐𝑐
3. Determine number of winding 1 turns
 𝐿𝐿𝑀𝑀 𝐼𝐼𝑀𝑀,𝑚𝑚𝑚𝑚𝑚𝑚 4
𝑛𝑛1 = 10
𝐵𝐵𝑚𝑚𝑚𝑚𝑚𝑚 𝐴𝐴𝑐𝑐

4. Determine number of secondary turns

𝑛𝑛2
𝑛𝑛2 = � � 𝑛𝑛
𝑛𝑛1 1
𝑛𝑛3
𝑛𝑛3 = � � 𝑛𝑛1
𝑛𝑛1
𝑛𝑛4
𝑛𝑛4 = � � 𝑛𝑛1
𝑛𝑛1

5. Evaluate fraction of window area allocated to each winding

𝑛𝑛1 𝐼𝐼1
𝛼𝛼1 =
𝑛𝑛1 𝐼𝐼𝑡𝑡𝑡𝑡𝑡𝑡
𝑛𝑛2 𝐼𝐼1
𝛼𝛼2 =
𝑛𝑛1 𝐼𝐼𝑡𝑡𝑡𝑡𝑡𝑡
𝑛𝑛3 𝐼𝐼1
𝛼𝛼3 =
𝑛𝑛1 𝐼𝐼𝑡𝑡𝑡𝑡𝑡𝑡
𝑛𝑛4 𝐼𝐼1
𝛼𝛼4 =
𝑛𝑛1 𝐼𝐼𝑡𝑡𝑡𝑡𝑡𝑡
6. Evaluate wire sizes
𝛼𝛼1 𝐾𝐾𝑢𝑢 𝑊𝑊𝐴𝐴
𝐴𝐴𝑤𝑤1 ≤
𝑛𝑛1
𝛼𝛼2 𝐾𝐾𝑢𝑢 𝑊𝑊𝐴𝐴
𝐴𝐴𝑤𝑤2 ≤
𝑛𝑛2
𝛼𝛼3 𝐾𝐾𝑢𝑢 𝑊𝑊𝐴𝐴
𝐴𝐴𝑤𝑤3 ≤
𝑛𝑛3
𝛼𝛼4 𝐾𝐾𝑢𝑢 𝑊𝑊𝐴𝐴
𝐴𝐴𝑤𝑤4 ≤
𝑛𝑛4
𝑉𝑉𝑔𝑔 𝐷𝐷𝐷𝐷𝑠𝑠 104
∆𝐵𝐵 =
2𝑛𝑛1 𝐴𝐴𝑐𝑐

The Loss Density is obtained using the following figure which relates ΔB and power loss density:
 𝑃𝑃𝑓𝑓𝑓𝑓 = (𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿 𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷)𝐴𝐴𝑐𝑐 𝑙𝑙𝑚𝑚

𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇 𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿 = 𝑃𝑃𝑐𝑐𝑐𝑐 + 𝑃𝑃𝑓𝑓𝑓𝑓

For the current design, the core loss, Pfe was found to be negligible at the switching frequency
of 100 kHz. Kg was calculated to be equal to 3.6945 for a Bmax of 0.2. Thus, only the EE70 core is
suitable to meet the requirement.

The transformer parameters are as follows:

Kg 3.6945
Core Type EE70
Bmax 0.2 T
 Copper Loss, Pcu 15 W
Core Loss, Pfe Approximated to 0 W (negligible)
Ac 3.24
Wa 6.7
MLT 14
Lm 18
np1 51
ns1 28
ns2 56
ns3 167
Awp 0.0349 (AWG #11)
Aws1 0.0223 (AWG #13)
Aws2 0.0074 (AWG #18)
Aws3 0.0074 (AWG #18)
[Ref: Erickson page 868 for American wire gauge data]

Selection of power switches and diodes

For device (MOSFET and diode) selection, we first give the formula of blocking voltage and
conduction current for each of the devices. Then we allocate 1.5 safety margin while choosing
the individual devices.
Selection of MOSFET: (MATLAB code switch_details_loss_cal.m is used for getting the voltage
and current values specific to our case)
Voltage blocked by MOSFET:
𝑛𝑛𝑝𝑝
𝐵𝐵𝐵𝐵𝐵𝐵𝐵𝐵𝐵𝐵𝐵𝐵𝐵𝐵𝐵𝐵 𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣 = 𝑉𝑉𝑔𝑔 + 𝑉𝑉
𝑛𝑛𝑠𝑠1 1
𝑛𝑛𝑝𝑝
𝐵𝐵𝐵𝐵𝐵𝐵𝐵𝐵𝐵𝐵𝐵𝐵𝐵𝐵𝐵𝐵 𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣 𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟 = 1.5 �𝑉𝑉𝑔𝑔 + 𝑉𝑉 �
𝑛𝑛𝑠𝑠1 1
RMS current through the MOSFET:
𝑃𝑃𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡
𝐼𝐼𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀,𝑟𝑟𝑟𝑟𝑟𝑟 =
𝑉𝑉𝑔𝑔 √𝐷𝐷

𝑃𝑃𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡
𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶 𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐 𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟 𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟 = 1.5 � �
𝑉𝑉𝑔𝑔 √𝐷𝐷

Loss in the MOSFET = Conduction Loss + Switching Loss

2 1 1 𝑛𝑛𝑝𝑝
𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝑺𝒉𝒉𝒍𝒍𝒍𝒍𝒍𝒍𝒍𝒍 = 𝐼𝐼𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀,𝑟𝑟𝑟𝑟𝑟𝑟 𝑅𝑅𝑜𝑜𝑜𝑜 + 2 𝐼𝐼𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀 𝑉𝑉𝑔𝑔 �𝑡𝑡𝑟𝑟 + 𝑡𝑡𝑑𝑑,𝑜𝑜𝑜𝑜 �𝑓𝑓𝑠𝑠 + 2 𝐼𝐼𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀 �𝑉𝑉𝑔𝑔 + 𝑛𝑛 𝑉𝑉1 � �𝑡𝑡𝑓𝑓 + 𝑡𝑡𝑑𝑑,𝑜𝑜𝑜𝑜 �𝑓𝑓𝑠𝑠
𝑠𝑠1
After couple of iterations, the MOSFET chosen for the converter is as follows (Datasheet attached
at the end):

MOSFET Details
Part Number IXTR 30N25
Blocking Voltage 250
Continuous Current 25
ON resistance (RON) (mΩ) 75
Rise Time (tr) (ns) 19
Fall Time (tf) (ns) 17
Time Delay ON (tdON) (ns) 19
Time Delay OFF (tdOFF) (ns) 79

Selection of Diode: (MATLAB code switch_details_loss_cal.m is used for getting the voltage and
current values specific to our case)
Similarly like above, for diode, we took 1.5 safety margin.
Voltages blocked by diodes:
𝑛𝑛𝑠𝑠1
𝑉𝑉𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷,1 = 𝑉𝑉1 + 𝑉𝑉
𝑛𝑛𝑝𝑝 𝑔𝑔
𝑛𝑛𝑠𝑠1
𝑉𝑉𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷,2 = 𝑉𝑉2 + 𝑉𝑉
𝑛𝑛𝑝𝑝 𝑔𝑔
𝑛𝑛𝑠𝑠1
𝑉𝑉𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷,3 = 𝑉𝑉3 + 𝑉𝑉
𝑛𝑛𝑝𝑝 𝑔𝑔

RMS currents through the diodes

𝐼𝐼𝐷𝐷1,𝑟𝑟𝑟𝑟𝑟𝑟 = 𝐼𝐼𝑆𝑆1,𝑟𝑟𝑟𝑟𝑟𝑟

𝐼𝐼𝐷𝐷2,𝑟𝑟𝑟𝑟𝑟𝑟 = 𝐼𝐼𝑆𝑆2,𝑟𝑟𝑟𝑟𝑟𝑟

𝐼𝐼𝐷𝐷3,𝑟𝑟𝑟𝑟𝑟𝑟 = 𝐼𝐼𝑆𝑆3,𝑟𝑟𝑟𝑟𝑟𝑟

Diode Losses are given as follows:

𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐷𝐷1 = 𝐼𝐼𝐷𝐷1,𝑟𝑟𝑟𝑟𝑟𝑟 𝑉𝑉𝑓𝑓1

𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐷𝐷2 = 𝐼𝐼𝐷𝐷1,𝑟𝑟𝑟𝑟𝑟𝑟 𝑉𝑉𝑓𝑓1

𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐷𝐷3 = 𝐼𝐼𝐷𝐷1,𝑟𝑟𝑟𝑟𝑟𝑟 𝑉𝑉𝑓𝑓1

 Diode Details (Datasheets attached at the end)
Component D1 D2 D3
Part Number FSV15100V 1N3070 6A6
Blocking Voltage (V) 100 200 600
Continuous Current (A) 15 4 6
Vf (V) 0.613 1 0.9

Selection of capacitors: (MATLAB code switch_details_loss_cal.m is used for getting the

voltage and current values specific to our case)
The required voltage rating of each capacitor will be respectively output voltage with a safety
margin of 1.5 .
Now, the formulas for current ripples through the capacitors are as follows:

2 2
∆𝐼𝐼𝑐𝑐1 = �𝐼𝐼𝐼𝐼1,𝑟𝑟𝑟𝑟𝑟𝑟 − 𝐼𝐼01

2 2
∆𝐼𝐼𝑐𝑐2 = �𝐼𝐼𝐼𝐼2,𝑟𝑟𝑟𝑟𝑟𝑟 − 𝐼𝐼02

2 2
∆𝐼𝐼𝑐𝑐3 = �𝐼𝐼𝐼𝐼3,𝑟𝑟𝑟𝑟𝑟𝑟 − 𝐼𝐼03

Hence, capacitor losses are given by:

2
𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐶𝐶1 = ∆𝐼𝐼𝑐𝑐1 𝐸𝐸𝐸𝐸𝐸𝐸𝐶𝐶1
2
𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐶𝐶2 = ∆𝐼𝐼𝑐𝑐1 𝐸𝐸𝐸𝐸𝐸𝐸𝐶𝐶2
2
𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐶𝐶3 = ∆𝐼𝐼𝑐𝑐1 𝐸𝐸𝐸𝐸𝐸𝐸𝐶𝐶3
The value of the capacitor is related to the voltage ripple and other terms (e.g. switching
frequency etc.) as follows:
𝑉𝑉𝑉𝑉𝑇𝑇𝑠𝑠
𝐶𝐶 =
∆𝑉𝑉𝑉𝑉

To match the required capacitance value (obtained from the MATLAB code
switch_details_loss_cal.m) and to keep the ESR loss less, we used 5 capacitor in parallel in first
output (25V); each capacitor with ESR 2 mΩ and capacitance 39 μF.
 Capacitor details (Datasheets attached at the end)
Component C1 C2 C3
Part Number FFB34E0396K FFB34E0396K 406PHC250K
Rated Voltage 100 100 250
Capacitance(μF) 195 39 40

ESR (mΩ) 0.4 2 3.9

Section 5:
Efficiency calculation and power loss distribution (MATLAB code
Vg_vs_efficiency.m is used for getting the plot)
The initial loss distribution is as follows:

Figure 1: Initial loss distribution allocated at Vg=75V

After rounds of iterations and final design of transformer and device selection, the actual loss
distribution is as follows:
 Figure 2: loss distribution after finalizing the design at Vg=75V

Following Table shows the values for all the losses at different input voltages. It is evident that
the losses are more or less same for the whole range of Vg from 65 V to 85 V.

Loss (Watts) Vg=65V Vg=70V Vg=75V Vg=80V Vg=85V

MOSFET loss 26.36 25.366 24.596 24.006 23.56
Diode Loss 9.83 9.67 9.54 9.42 9.31
Transformer 15 15 15 15 15
Loss
Capacitor 0.027 0.0256 0.0238 0.0223 0.0209
Loss
Total Loss 51.21 50.06 49.15 48.44 47.89

The corresponding loss-distribution of the above table is shown below:

Figure 3: Loss distribution for V=65V

Figure 4: Loss distribution for V=70V

Figure 5: Loss distribution for V=75V

Figure 6: Loss distribution for V=80V

 Figure 7: Loss distribution for V=85V

Figure 8: Plot of Vg vs efficiency

The above figure indicates that the frequency remains within 91% to 92% for variation in input voltage
as per specification.
 Figure 9: Plot of efficiency for varying load conditions

Section 6:
Deriving converter transfer function
Small signal analysis is performed to derive the required transfer function taking only one winding
at a time and ideal components. So, the single input-single output ideal flyback converter circuit
is as follows:
Subinterval 0 ≤ t ≤ DTs

𝑉𝑉𝐿𝐿 𝑚𝑚 (𝑡𝑡) = 𝑉𝑉𝑔𝑔 (𝑡𝑡)

𝑉𝑉(𝑡𝑡)
𝑖𝑖𝐶𝐶 (𝑡𝑡) = −
𝑅𝑅
𝑖𝑖𝑔𝑔 (𝑡𝑡) = 𝑖𝑖𝐿𝐿 𝑚𝑚 (𝑡𝑡)

Subinterval DTs ≤ t ≤ Ts

𝑉𝑉(𝑡𝑡)
𝑉𝑉𝐿𝐿 𝑚𝑚 (𝑡𝑡) = −
𝑛𝑛
𝑖𝑖𝐿𝐿 𝑚𝑚 (𝑡𝑡) 𝑉𝑉(𝑡𝑡)
𝑖𝑖𝐶𝐶 (𝑡𝑡) = −
𝑛𝑛 𝑅𝑅
Inductor volt-sec balance gives:
〈𝑉𝑉(𝑡𝑡)〉 𝑇𝑇 𝑠𝑠
〈𝑉𝑉𝐿𝐿 𝑚𝑚 (𝑡𝑡)〉 𝑇𝑇 = 𝑑𝑑(𝑡𝑡) �〈𝑉𝑉𝑔𝑔 (𝑡𝑡)〉 𝑇𝑇 � + 𝑑𝑑 ′ (𝑡𝑡) �− �
𝑠𝑠 𝑠𝑠 𝑛𝑛
𝑑𝑑〈𝑖𝑖𝐿𝐿 𝑚𝑚 (𝑡𝑡)〉 𝑇𝑇 〈𝑉𝑉(𝑡𝑡)〉 𝑇𝑇 𝑠𝑠
𝑠𝑠
𝐿𝐿𝑚𝑚 = 𝑑𝑑(𝑡𝑡) �〈𝑉𝑉𝑔𝑔 (𝑡𝑡)〉 𝑇𝑇 � − 𝑑𝑑′(𝑡𝑡) � �
𝑑𝑑𝑑𝑑 𝑠𝑠 𝑛𝑛
Capacitor charge balance gives:

〈𝑉𝑉(𝑡𝑡)〉 𝑇𝑇 𝑠𝑠 〈𝑖𝑖𝐿𝐿 𝑚𝑚 (𝑡𝑡)〉 𝑇𝑇 〈𝑉𝑉(𝑡𝑡)〉 𝑇𝑇 𝑠𝑠

𝑠𝑠
〈𝑖𝑖𝐶𝐶 (𝑡𝑡)〉 𝑇𝑇 𝑠𝑠 = 𝑑𝑑(𝑡𝑡) �− � + 𝑑𝑑′(𝑡𝑡) � − �
𝑅𝑅 𝑛𝑛 𝑅𝑅

𝑑𝑑〈𝑉𝑉(𝑡𝑡)〉 𝑇𝑇 𝑠𝑠 〈𝑉𝑉(𝑡𝑡)〉 𝑇𝑇 𝑠𝑠 〈𝑖𝑖𝐿𝐿 𝑚𝑚 (𝑡𝑡)〉 𝑇𝑇 〈𝑉𝑉(𝑡𝑡)〉 𝑇𝑇 𝑠𝑠

𝑠𝑠
𝐶𝐶 = −𝑑𝑑(𝑡𝑡) � � + 𝑑𝑑′(𝑡𝑡) � − �
𝑑𝑑𝑑𝑑 𝑅𝑅 𝑛𝑛 𝑅𝑅

For the input current

〈𝑖𝑖𝑔𝑔 (𝑡𝑡)〉 𝑇𝑇 = 𝑑𝑑(𝑡𝑡)〈𝑖𝑖𝐿𝐿 𝑚𝑚 (𝑡𝑡)〉 𝑇𝑇
𝑠𝑠 𝑠𝑠

Now,

〈𝑉𝑉𝑔𝑔 (𝑡𝑡)〉 = 𝑉𝑉𝑔𝑔 + 𝑉𝑉�𝑔𝑔 (𝑡𝑡)

𝑑𝑑(𝑡𝑡) = 𝐷𝐷 + 𝑑𝑑̂ (𝑡𝑡)

〈𝑉𝑉(𝑡𝑡)〉 = 𝑉𝑉 + 𝑉𝑉� (𝑡𝑡)
〈𝑖𝑖𝐿𝐿 𝑚𝑚 (𝑡𝑡)〉 = 𝐼𝐼𝐿𝐿 𝑚𝑚 + 𝚤𝚤�
𝐿𝐿 𝑚𝑚 (𝑡𝑡)

〈𝑖𝑖𝑔𝑔 (𝑡𝑡)〉 = 𝐼𝐼𝑔𝑔 + 𝚤𝚤�𝑔𝑔 (𝑡𝑡)

𝑑𝑑′ (𝑡𝑡) = 1 − 𝑑𝑑(𝑡𝑡) = 1 − 𝐷𝐷 + 𝑑𝑑̂ (𝑡𝑡) = 𝐷𝐷′ − 𝑑𝑑̂(𝑡𝑡)

Hence,

𝐿𝐿 𝑚𝑚 (𝑡𝑡)〉 𝑇𝑇
𝑑𝑑〈𝐼𝐼𝐿𝐿 𝑚𝑚 + 𝚤𝚤� 〈𝑉𝑉 + 𝑉𝑉� (𝑡𝑡)〉 𝑇𝑇 𝑠𝑠
𝐿𝐿𝑚𝑚 𝑠𝑠
= (𝐷𝐷 + 𝑑𝑑̂ (𝑡𝑡)) �〈𝑉𝑉𝑔𝑔 + 𝑉𝑉�𝑔𝑔 (𝑡𝑡)〉 𝑇𝑇 � − (𝐷𝐷′ − 𝑑𝑑̂ (𝑡𝑡)) � �
𝑑𝑑𝑑𝑑 𝑠𝑠 𝑛𝑛

Ignoring all DC and 2nd order ac terms:

𝑳𝑳 𝒎𝒎 (𝒕𝒕)
𝒊𝒊� � (𝒕𝒕)
𝑽𝑽 𝑽𝑽
𝑳𝑳𝒎𝒎 �𝒈𝒈 (𝒕𝒕) − 𝑫𝑫′
= 𝑫𝑫𝑽𝑽 � (𝒕𝒕)
+ �𝑽𝑽𝒈𝒈 + � 𝒅𝒅
𝒅𝒅𝒅𝒅 𝒏𝒏 𝒏𝒏

Again,
�(𝑡𝑡)〉𝑇𝑇
𝑑𝑑〈𝑉𝑉+𝑉𝑉 � (𝑡𝑡)〉𝑇𝑇
〈𝑉𝑉+𝑉𝑉 〈𝐼𝐼𝐿𝐿 𝑚𝑚 +𝚤𝚤𝐿𝐿�𝑚𝑚 (𝑡𝑡)〉𝑇𝑇 �(𝑡𝑡)〉𝑇𝑇
〈𝑉𝑉+𝑉𝑉
𝐶𝐶 𝑠𝑠
= −(𝐷𝐷 + 𝑑𝑑̂(𝑡𝑡)) � 𝑠𝑠
� + (𝐷𝐷′ − 𝑑𝑑̂(𝑡𝑡)) � 𝑠𝑠
− 𝑠𝑠
�
𝑑𝑑𝑑𝑑 𝑅𝑅 𝑛𝑛 𝑅𝑅

Ignoring all DC and 2nd order ac terms:

� (𝑡𝑡)
𝑑𝑑𝑉𝑉 � (𝑡𝑡)
𝑉𝑉 𝑉𝑉 � (𝑡𝑡)
𝑉𝑉 𝐼𝐼 𝑉𝑉
𝐶𝐶 = −𝐷𝐷 − 𝑑𝑑̂(𝑡𝑡) 𝑅𝑅 + 𝐷𝐷′ �− � − 𝑑𝑑̂(𝑡𝑡) � 𝐿𝐿𝑛𝑛𝑚𝑚 − 𝑅𝑅�
𝑑𝑑𝑑𝑑 𝑅𝑅 𝑅𝑅
� (𝒕𝒕)
𝒅𝒅𝑽𝑽 𝑳𝑳 𝒎𝒎 (𝒕𝒕)
𝒊𝒊� � (𝒕𝒕)
𝑽𝑽 𝑰𝑰𝑳𝑳 𝒎𝒎
⇒ 𝑪𝑪 = 𝑫𝑫′ − − � (𝒕𝒕)
𝒅𝒅
𝒅𝒅𝒅𝒅 𝒏𝒏 𝑹𝑹 𝒏𝒏
Again for the input current,

〈𝐼𝐼𝑔𝑔 + 𝚤𝚤�𝑔𝑔 (𝑡𝑡)〉 𝑇𝑇 = (𝐷𝐷 + 𝑑𝑑̂(𝑡𝑡))〈𝐼𝐼𝐿𝐿 𝑚𝑚 + 𝚤𝚤�

𝐿𝐿 𝑚𝑚 (𝑡𝑡)〉 𝑇𝑇
𝑠𝑠 𝑠𝑠

Ignoring all DC and 2nd order ac terms:

𝒊𝒊�𝒈𝒈 (𝒕𝒕) = 𝑫𝑫𝒊𝒊� �

𝑳𝑳 𝒎𝒎 (𝒕𝒕) + 𝒅𝒅(𝒕𝒕)𝑰𝑰𝑳𝑳 𝒎𝒎

Figure 10: Circuit representation of derived equations

Small signal ac equivalent circuit model,

Setting d� sources to zero,

Pushing inductor and V� g source through transformers on the other side,

 1
𝑉𝑉� (𝑡𝑡) 𝑛𝑛𝑛𝑛 �𝑅𝑅|| 𝑠𝑠𝑠𝑠 �
𝐺𝐺𝑉𝑉 𝑔𝑔 (𝑠𝑠) = � =
𝑉𝑉�𝑔𝑔 (𝑡𝑡) 𝐷𝐷′ 1 𝑛𝑛 2
�𝑅𝑅|| 𝑠𝑠𝑠𝑠 � + � ′ � 𝑠𝑠𝐿𝐿𝑚𝑚
𝑑𝑑�(𝑠𝑠)=0
𝐷𝐷
𝑅𝑅
𝑉𝑉� (𝑡𝑡) 𝑛𝑛𝑛𝑛 1 + 𝑠𝑠𝑠𝑠𝑠𝑠
⇒ 𝐺𝐺𝑉𝑉 𝑔𝑔 (𝑠𝑠) = =
𝑉𝑉�𝑔𝑔 (𝑡𝑡) 𝐷𝐷′ 𝑅𝑅
+ �
𝑛𝑛 2
1 + 𝑠𝑠𝑠𝑠𝑠𝑠 𝐷𝐷′ � 𝑠𝑠𝐿𝐿𝑚𝑚
𝑛𝑛𝑛𝑛 1
⇒ 𝐺𝐺𝑉𝑉 𝑔𝑔 (𝑠𝑠) =
𝐷𝐷′ 𝑠𝑠𝐿𝐿𝑚𝑚 𝑛𝑛2 𝑠𝑠 2 𝐶𝐶𝐿𝐿𝑚𝑚 𝑛𝑛2
1+ ′2 +
𝑅𝑅𝐷𝐷 𝐷𝐷′2
𝑛𝑛𝑛𝑛
𝐺𝐺𝑉𝑉 𝑔𝑔0
𝐺𝐺𝑉𝑉 𝑔𝑔 (𝑠𝑠) = 𝐷𝐷′ =
𝑠𝑠 𝑠𝑠 2 𝑠𝑠 s 2
1+ ′2 + 1 + 𝑄𝑄𝑄𝑄 + �𝜔𝜔 �
𝑅𝑅𝑅𝑅 𝐷𝐷′2 0 0
𝐿𝐿𝑚𝑚 𝑛𝑛2 𝐿𝐿𝑚𝑚 𝐶𝐶𝑛𝑛2
𝑛𝑛𝑛𝑛
𝐺𝐺𝑉𝑉 𝑔𝑔0 =
𝐷𝐷′
𝐷𝐷′
𝜔𝜔0 =
𝑛𝑛�𝐿𝐿𝑚𝑚 𝐶𝐶

𝑅𝑅𝑅𝑅′ �𝐿𝐿𝑚𝑚 𝐶𝐶
𝑄𝑄 =
𝑛𝑛𝐿𝐿𝑚𝑚
Using Superposition Theorem,
At first, consider the voltage source,
L=Lm in the circuit.

1
𝑛𝑛 𝑉𝑉 𝑅𝑅|| 𝑠𝑠𝑠𝑠
𝑉𝑉� (𝑠𝑠) = ′ �𝑉𝑉𝑔𝑔 + � 𝑑𝑑̂
𝐷𝐷 𝑛𝑛 1 𝑛𝑛 2
�𝑅𝑅|| 𝑠𝑠𝑠𝑠 � + �𝑠𝑠𝐿𝐿𝑚𝑚 �𝐷𝐷′ � �

𝑅𝑅
𝑉𝑉� 𝑛𝑛𝑉𝑉𝑔𝑔 + 𝑉𝑉 1 + 𝑠𝑠𝑠𝑠𝑠𝑠
⇒ =� �
𝑑𝑑̂ 𝐷𝐷′ 𝑅𝑅 𝑛𝑛 2
+ �𝑠𝑠𝐿𝐿𝑚𝑚 �𝐷𝐷′ � �
1 + 𝑠𝑠𝑠𝑠𝑠𝑠
𝑉𝑉� 𝑛𝑛𝑉𝑉𝑔𝑔 + 𝑉𝑉 𝑅𝑅𝐷𝐷′2
⇒ =� �
𝑑𝑑̂ 𝐷𝐷′ 𝑅𝑅𝐷𝐷′2 + 𝑠𝑠𝐿𝐿𝑚𝑚 𝑛𝑛2 + 𝑠𝑠 2 𝐿𝐿𝑚𝑚 𝐶𝐶𝐶𝐶𝑛𝑛2
𝑉𝑉� (𝑛𝑛𝑉𝑉𝑔𝑔 + 𝑉𝑉)𝑅𝑅𝐷𝐷′
⇒ = = 𝐺𝐺𝑇𝑇𝑇𝑇1 (𝑠𝑠)
𝑑𝑑̂ 𝑅𝑅𝐷𝐷′2 + 𝑠𝑠𝐿𝐿𝑚𝑚 𝑛𝑛2 + 𝑠𝑠 2 𝐿𝐿𝑚𝑚 𝐶𝐶𝐶𝐶𝑛𝑛2
Now, consider the current source,
L=Lm in the circuit.

Using current division rule,

𝐼𝐼𝐿𝐿 𝑚𝑚 𝑑𝑑̂ 1 𝑛𝑛 2
�− 𝑛𝑛 � �𝑅𝑅|| 𝑠𝑠𝑠𝑠 � �𝑠𝑠𝐿𝐿𝑚𝑚 �𝐷𝐷′ � �
𝑉𝑉� (𝑠𝑠) =
1 𝑛𝑛 2
�𝑅𝑅|| 𝑠𝑠𝑠𝑠 � + �𝑠𝑠𝐿𝐿𝑚𝑚 �𝐷𝐷′ � �

𝐼𝐼𝐿𝐿 𝑚𝑚 𝑅𝑅 𝑛𝑛 2
�− � � � �𝑠𝑠𝐿𝐿 �
�
𝑉𝑉 𝑛𝑛 1 + 𝑠𝑠𝑠𝑠𝑠𝑠 𝑚𝑚 𝐷𝐷′ � �
⇒ =
𝑑𝑑̂ 𝑅𝑅 𝑛𝑛 2
�1 + 𝑠𝑠𝑠𝑠𝑠𝑠 � + �𝑠𝑠𝐿𝐿𝑚𝑚 �𝐷𝐷′ � �

𝑉𝑉� −𝐼𝐼𝐿𝐿 𝑚𝑚 𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠

⇒ = = 𝐺𝐺𝑇𝑇𝑇𝑇2 (𝑠𝑠)
𝑑𝑑̂ 𝑅𝑅𝐷𝐷 + 𝑠𝑠𝐿𝐿𝑚𝑚 𝑛𝑛2 + 𝑠𝑠 2 𝐿𝐿𝑚𝑚 𝐶𝐶𝐶𝐶𝑛𝑛2
′2

Combining GTF1(s) and GTF2(s):

(𝑛𝑛𝑉𝑉𝑔𝑔 + 𝑉𝑉)𝑅𝑅𝐷𝐷′ − 𝐼𝐼𝐿𝐿 𝑚𝑚 𝑠𝑠𝐿𝐿𝑚𝑚 𝑅𝑅𝑅𝑅
𝐺𝐺𝑉𝑉 𝑑𝑑 (𝑠𝑠) =
𝑅𝑅𝐷𝐷′2 + 𝑠𝑠𝐿𝐿𝑚𝑚 𝑛𝑛2 + 𝑠𝑠 2 𝐿𝐿𝑚𝑚 𝐶𝐶𝐶𝐶𝑛𝑛2

(𝑛𝑛𝑉𝑉𝑔𝑔 + 𝑉𝑉) ⎛ 𝑠𝑠 ⎞
⎜ 1 −
𝐷𝐷′ �𝑛𝑛𝑉𝑉𝑔𝑔 + 𝑉𝑉� ⎟
𝐷𝐷 ′
𝑠𝑠
𝑛𝑛𝐿𝐿𝑚𝑚 𝐼𝐼𝐿𝐿 𝑚𝑚 𝐺𝐺𝑉𝑉 𝑑𝑑0 �1 − 𝜔𝜔 �
𝐺𝐺𝑉𝑉 𝑑𝑑 (𝑠𝑠) = ⎝ ⎠= 𝑧𝑧
𝑠𝑠 𝑠𝑠 2 𝑠𝑠 s 2
1+ + 1 + 𝑄𝑄𝑄𝑄 + �𝜔𝜔 �
𝑅𝑅𝑅𝑅′2 𝐷𝐷′2 0 0
𝐿𝐿𝑚𝑚 𝑛𝑛2 𝐿𝐿𝑚𝑚 𝐶𝐶𝑛𝑛2

�𝑛𝑛𝑉𝑉𝑔𝑔 + 𝑉𝑉�
𝐺𝐺𝑉𝑉 𝑑𝑑0 =
𝐷𝐷′
𝐷𝐷′ �𝑛𝑛𝑉𝑉𝑔𝑔 + 𝑉𝑉�
𝜔𝜔𝑧𝑧 =
𝑛𝑛𝐿𝐿𝑚𝑚 𝐼𝐼𝐿𝐿 𝑚𝑚
 𝐷𝐷′
𝜔𝜔0 =
𝑛𝑛�𝐿𝐿𝑚𝑚 𝐶𝐶

𝑅𝑅𝑅𝑅′ �𝐿𝐿𝑚𝑚 𝐶𝐶
𝑄𝑄 =
𝑛𝑛𝐿𝐿𝑚𝑚

Section 7:
Controller Design and Implementation
For designing the controller, first we draw the bode diagram of the uncompensated system by
hand. Then, we analyze the plot to approach the controller design.

In this case, using the designed values for the components:

𝑠𝑠
636.6723 �1 − �
𝐺𝐺𝑉𝑉 𝑑𝑑 (𝑠𝑠) = 5.8964 x 104
𝑠𝑠 s 2
1+ 3 +� 3 �
8.1987 x 2.7329 x 10 2.7329 x 10

Now, the hand drawn bode diagram of the GVd(s) is given below.
It is to be noted from the above figure that the uncompensated system is having quadratic pole
(ω0=2.7329x103 rad/sec) and negative gain margin. We have to design the compensator such
that the gain margin comes between +40 degree to +60 degree.

Quadratic pole is causing the phase plot to go near -180 degree quickly. To compensate the effect
of quadratic pole, the controller should have a zero near the location of quadratic pole. Say, the
zero is at ωzc = 4100 rad/sec. Now, for the compensator, a pole has to be introduced at an higher
frequency so that the pole will not allow the controller gain to increase with frequency. The pole
will make magnitude plot of the controller follow a constant gain at high frequency. Say, the pole
is at ωzp=29x106 rad/sec.

To increase the low frequency gain, an inverted zero (1+ωL/s) is added to the controller such that
it is quite below ωc/10. We take ωL = 250 rad/sec. This ensures high gain at lower frequency and
fulfill the phase margin requirement.

So, by the above concept, with few adjustment in the location of proposed poles and zeros in the
compensator, the transfer function of the proposed controller becomes as follows:

𝑠𝑠 250
0.0063 �1 + 4100 � �1 + 𝑠𝑠 �
𝐺𝐺𝑐𝑐 (𝑠𝑠) = 𝑠𝑠
�1 + �
29 x 106
44.85𝑠𝑠 2 + 1.96 x 105 𝑠𝑠 + 4.602 x 107
⇒ 𝐺𝐺𝑐𝑐 (𝑠𝑠) =
𝑠𝑠 2 + 2.92 x 107 𝑠𝑠

Now, the hand drawn bode diagram of the Gc(s) is given below.
So, when we put the compensator together with the system, the bode plot of compensated
system looks as follows:
Now, we give the MATLAB simulated result for the bode diagram, (MATLAB code
Controller_Bode_Plot.m is used for getting the plots)
Figure 11: Bode Plot of uncompensated system

Figure 12: Bode plot of controller

Figure 13: Bode plot of the compensated system
Section 8:
Simulation result from PLECS model:
First, we will show the open loop simulation of the converter. The PLECS model for the open
loop simulation is as follows:

Figure 14: PLECS model for open loop simulation

Figure 15: Output voltage V1 for open loop simulation for Vg = 75V at 100% load

Figure 16: Ripple in V1 for open loop simulation for Vg = 75V at 100% load
Figure 17: Output voltage V2 for open loop simulation for Vg = 75V at 100% load

Figure 18: Ripple in V2 for open loop simulation for Vg = 75V at 100% load
Figure 19: Output voltage V3 for open loop simulation for Vg = 75V at 100% load

Figure 20: Ripple in V3 for open loop simulation for Vg = 75V at 100% load
 Figure 21: Voltage across MOSFET for open loop simulation for Vg = 75V at 100% load

Figure 22: Current through MOSFET for open loop simulation for Vg = 75V at 100% load

Next, we show the simulation of the model with design controller, i.e. closed loop simulation.
We take feedback from third output V3. The PLECS circuit for closed loop simulation is as follows:
 Figure 23: PLECS model for closed loop simulation

Figure 24: Output voltage V1 for closed loop simulation for Vg = 75V at 100% load
 Figure 25: Ripple in V1 for closed loop simulation for Vg = 75V at 100% load

Figure 26: Output voltage V2 for closed loop simulation for Vg = 75V at 100% load
 Figure 27: Ripple in V2 for closed loop simulation for Vg = 75V at 100% load

Figure 28: Output voltage V3 for closed loop simulation for Vg = 75V at 100% load
 Figure 29: Ripple in V3 for closed loop simulation for Vg = 75V at 100% load

Figure 30: Voltage across MOSFET for closed loop simulation for Vg = 75V at 100% load
 Figure 31: Current through MOSFET for closed loop simulation for Vg = 75V at 100% load

Now, we will analyze the step response to see the overshoot / undershoot on the response and
crosscheck with the required specification of less than 20% overshoot/undershoot. We give step
increase by 1 V to the Vref (150 V) at t=0.25 sec. The response from the PLECS is as follows:

Figure 32: Overshoot in V1 for closed loop simulation when Vg = 75V at 100% load and step change is applied at t=0.25sec
 Figure 33: Overshoot in V2 for closed loop simulation when Vg = 75V at 100% load and step change is applied at t=0.25sec

Figure 34: Overshoot in V3 for closed loop simulation when Vg = 75V at 100% load and step change is applied at t=0.25sec

From the above three plots, it is evident that the design closed loop system meets the required
overshoot/undershoot specifications because in all the above three plots, overshoots/undershoots are
less than 20%.
Now, we analyze the performance of the closed loop system with light load condition. For simulation,
we take 30% load.

Figure 35: Output voltage V1 for closed loop simulation for Vg = 75V at 30% load

Figure 36: Ripple in V1 for closed loop simulation for Vg = 75V at 30% load
Figure 37: Output voltage V2 for closed loop simulation for Vg = 75V at 30% load

Figure 38: Ripple in V2 for closed loop simulation for Vg = 75V at 30% load
Figure 39: Output voltage V3 for closed loop simulation for Vg = 75V at 30% load

Figure 40: Ripple in V3 for closed loop simulation for Vg = 75V at 30% load
Extra Credits:
Analog implementation of the controller
The bode plot of PID compensator looks as follows:

Now, opamp subtractor circuit is as follows:

|𝑍𝑍2 (𝑠𝑠)| +
𝑉𝑉𝑐𝑐 (𝑠𝑠) = (𝑉𝑉 − 𝑉𝑉 − )
|𝑍𝑍1 (𝑠𝑠)|

Now, Z1, Z2 have to be realized using resistance and capacitance.

We know the following:
An extra resistance R3 used in series with Z1 branch to get the fp frequency. The final combination
is as follows:

𝑅𝑅2
𝐺𝐺𝑐𝑐0 =
𝑅𝑅1
Gc0 = 0.0063
R2= 0.63 Ω (say)
So, R1 = 100 Ω
fL=1/(2πR2C2)=250/(2π)
So, C2 = 6.349 x 10-3 F
fZ=1/(2πR1C1)=4100/(2π)
So, C1 = 2.439 x 10-6 F
FP=1/(2πR3C1)=(2.9x107)/(2π)
So, R3 = 0.014138 Ω

The analog implementation of the controller is done in PLECS and simulation results are as
follows:
 Figure 41: PLECS model for analog implementaion

Figure 42: Output voltage V1 for analog implemented controller for Vg = 75V at 100% load
 Figure 43: Ripple in V1 for analog implemented controller for Vg = 75V at 100% load

Figure 44: Output voltage V2 for analog implemented controller for Vg = 75V at 100% load
 Figure 45: Ripple in V2 for analog implemented controller for Vg = 75V at 100% load

Figure 46: Output voltage V3 for analog implemented controller for Vg = 75V at 100% load
Figure 47: Ripple in V3 for analog implemented controller for Vg = 75V at 100% load
Current mode control of the Flyback converter
Using the equations derived in small signal analysis,

𝚤𝚤̂(𝑡𝑡) 𝑉𝑉� (𝑡𝑡) 𝑉𝑉

𝐿𝐿𝑚𝑚 = 𝐷𝐷𝑉𝑉�𝑔𝑔 (𝑡𝑡) − 𝐷𝐷′ + �𝑉𝑉𝑔𝑔 + � 𝑑𝑑̂(𝑡𝑡)
𝑑𝑑𝑑𝑑 𝑛𝑛 𝑛𝑛
𝑑𝑑𝑉𝑉� (𝑡𝑡) 𝚤𝚤̂(𝑡𝑡) 𝑉𝑉� (𝑡𝑡) 𝐼𝐼
𝐶𝐶 = 𝐷𝐷′ − − 𝑑𝑑̂(𝑡𝑡)
𝑑𝑑𝑑𝑑 𝑛𝑛 𝑅𝑅 𝑛𝑛
〈𝐼𝐼𝑔𝑔 + 𝚤𝚤�𝑔𝑔 (𝑡𝑡)〉 𝑇𝑇 = (𝐷𝐷 + 𝑑𝑑̂ (𝑡𝑡))〈𝐼𝐼 + 𝚤𝚤̂(𝑡𝑡)〉 𝑇𝑇 𝑠𝑠
𝑠𝑠

Using laplace transforms of the equations and the initial conditions set to zero.
𝐷𝐷′ 𝑉𝑉
𝑠𝑠𝐿𝐿𝑚𝑚 𝚤𝚤̂(𝑠𝑠) = 𝐷𝐷𝑉𝑉�𝑔𝑔 (𝑠𝑠) − 𝑉𝑉� (𝑠𝑠) + 𝑑𝑑̂ (𝑠𝑠) �𝑉𝑉𝑔𝑔 + �
𝑛𝑛 𝑛𝑛
𝐷𝐷′ 𝑉𝑉� (𝑠𝑠) 𝐼𝐼
𝑠𝑠𝑠𝑠𝑉𝑉� (𝑠𝑠) = 𝚤𝚤̂(𝑠𝑠) − − 𝑑𝑑̂(𝑠𝑠)
𝑛𝑛 𝑅𝑅 𝑛𝑛
𝚤𝚤�𝑔𝑔 (𝑠𝑠) = 𝐷𝐷𝚤𝚤̂(𝑠𝑠) + 𝐼𝐼𝑑𝑑̂ (𝑠𝑠)

The inductor current is assumed to be identical to the programmed control current

𝚤𝚤̂(𝑠𝑠) = 𝚤𝚤�(𝑠𝑠)
𝑐𝑐

𝐷𝐷′ 𝑉𝑉
𝑠𝑠𝐿𝐿𝑚𝑚 𝚤𝚤�(𝑠𝑠)
𝑐𝑐 = 𝐷𝐷𝑉𝑉�𝑔𝑔 (𝑠𝑠) − 𝑉𝑉� (𝑠𝑠) + 𝑑𝑑̂ (𝑠𝑠) �𝑉𝑉𝑔𝑔 + �
𝑛𝑛 𝑛𝑛
′
𝐷𝐷
𝑠𝑠𝐿𝐿𝑚𝑚 𝚤𝚤�(𝑠𝑠)
𝑐𝑐 − 𝐷𝐷𝑉𝑉�𝑔𝑔 (𝑠𝑠) + 𝑛𝑛 𝑉𝑉� (𝑠𝑠)
𝑑𝑑̂(𝑠𝑠) =
𝑉𝑉
𝑉𝑉𝑔𝑔 + 𝑛𝑛

Putting this value into the expression for 𝑠𝑠𝑠𝑠𝑉𝑉� (𝑠𝑠)

� 𝐷𝐷′ �
𝑠𝑠𝐿𝐿 𝚤𝚤
�(𝑠𝑠) − 𝐷𝐷𝑉𝑉 (𝑠𝑠) + (𝑠𝑠)
� 𝑛𝑛 𝑉𝑉 �
′
𝐷𝐷 𝑉𝑉 (𝑠𝑠) 𝐼𝐼 𝑚𝑚 𝑐𝑐 𝑔𝑔
𝑠𝑠𝑠𝑠𝑉𝑉� (𝑠𝑠) = 𝚤𝚤�(𝑠𝑠) − − �
𝑛𝑛 𝑐𝑐 𝑅𝑅 𝑛𝑛 𝑉𝑉𝑔𝑔 + 𝑛𝑛
𝑉𝑉

𝑛𝑛𝑛𝑛𝑉𝑉𝑔𝑔 𝑛𝑛𝑛𝑛 𝑛𝑛2 𝐷𝐷𝑉𝑉𝑔𝑔

Since 𝑉𝑉 = & 𝐼𝐼 = 𝐷𝐷′ 𝑅𝑅 =
𝐷𝐷 ′ 𝐷𝐷 ′2 𝑅𝑅

𝐷𝐷′ 𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛 1 𝐷𝐷 𝑉𝑉�𝑔𝑔 (𝑠𝑠)𝐷𝐷2 𝑛𝑛

𝑠𝑠𝑠𝑠𝑉𝑉� (𝑠𝑠) = 𝚤𝚤�(𝑠𝑠)
𝑐𝑐 � �
− ′ � − 𝑉𝑉 (𝑠𝑠) � + � +
𝑛𝑛 𝐷𝐷 𝑅𝑅 𝑅𝑅 𝑅𝑅 𝐷𝐷′ 𝑅𝑅

� 𝐷𝐷′ �
𝑠𝑠𝐿𝐿𝑚𝑚 𝚤𝚤�(𝑠𝑠) − 𝐷𝐷𝑉𝑉 (𝑠𝑠) + (𝑠𝑠)
𝚤𝚤�𝑔𝑔 (𝑠𝑠) = 𝐷𝐷𝚤𝚤�(𝑠𝑠) + 𝐼𝐼 �
𝑐𝑐 𝑔𝑔 𝑛𝑛 𝑉𝑉 �
𝑐𝑐 𝑉𝑉
𝑉𝑉𝑔𝑔 + 𝑛𝑛
 𝑛𝑛2 𝐷𝐷𝐷𝐷𝐷𝐷 𝑛𝑛𝑛𝑛 𝐷𝐷2 𝑛𝑛2
𝚤𝚤�𝑔𝑔 (𝑠𝑠) = 𝚤𝚤�(𝑠𝑠)
𝑐𝑐 �𝐷𝐷 + � �
� + 𝑉𝑉 (𝑠𝑠) � � − 𝑉𝑉𝑔𝑔 (𝑠𝑠) � �
𝑅𝑅𝐷𝐷′ 𝑅𝑅 𝑅𝑅𝐷𝐷′

Figure 48: Two-port equivalent circuit to model the current programmed flyback

𝑛𝑛𝑛𝑛
𝑔𝑔1 =
𝑅𝑅
𝑛𝑛2 𝑠𝑠𝑠𝑠
𝑓𝑓1 = 𝐷𝐷 �1 + �
𝑅𝑅𝐷𝐷′
−𝑅𝑅𝐷𝐷′
𝑟𝑟1 =
𝑛𝑛2 𝐷𝐷2
𝐷𝐷2 𝑛𝑛
𝑔𝑔2 =
𝑅𝑅𝐷𝐷′
1 𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛
𝑓𝑓2 = 𝐷𝐷′ � − �
𝑛𝑛 𝑅𝑅𝐷𝐷′2
𝑅𝑅
𝑟𝑟2 =
𝐷𝐷
Control to output transfer function

𝑉𝑉� (𝑠𝑠) 1
𝐺𝐺𝑉𝑉 𝑐𝑐 (𝑠𝑠) = � = 𝑓𝑓2 �𝑟𝑟2 ||𝑅𝑅|| �
𝚤𝚤�(𝑠𝑠)
𝑐𝑐 � (𝑠𝑠)=0
𝑉𝑉
𝑠𝑠𝑠𝑠
𝑔𝑔

𝑅𝑅𝑅𝑅′ 𝑛𝑛2 𝐿𝐿𝐿𝐿

�1 − 𝑠𝑠 �
(1 + 𝐷𝐷)𝑛𝑛 𝑅𝑅𝐷𝐷′2
𝐺𝐺𝑉𝑉 𝑐𝑐 (𝑠𝑠) =
𝑅𝑅𝑅𝑅
�1 + 𝑠𝑠 1 + 𝐷𝐷�

The current mode control is implemented in PLECS and simulation result is attached.
 Figure 49: PLECS model for flyback converter with current mode control

Figure 50: Output voltage V1 with current mode control for Vg = 75V at 100% load
 Figure 51: Ripple in V1 with current mode control for Vg = 75V at 100% load

Figure 52: Output voltage V2 with current mode control for Vg = 75V at 100% load
 Figure 53: Ripple in V2 with current mode control for Vg = 75V at 100% load

Figure 54: Output voltage V3 with current mode control for Vg = 75V at 100% load
Figure 55: Ripple in V3 with current mode control for Vg = 75V at 100% load
 Conclusion:
A flyback mode converter that operates for input voltage of 65-85V giving three
outputs of 25V, 150W; 50V, 100w; 150V, 300W has been designed. The converter
very closely meets all the design specifications. Both the voltage mode and current
mode control has been implemented for this converter. Analog implementation of
the control scheme is also carried out.

Reference:
[1] Robert Erickson, ‘Fundamental of Power Electronics’, 2nd edition.
[2] Application Notes AN4137- Design Guidelines for Offline Flyback Converters
using
Fairchild Power Switch .
[3] John Schönberger ‘Modeling a Current-Controlled Flyback Converter using
PLECS®’
 Appendix
MATLAB Code:
Transformer Design code: (Transformer_Design_Kg_method.m file)
clear all
close all
clc

u0 = 4*pi*10^-7;
del_Im = 0.2;
D = 0.38;
D1 = 1-D;
Vg = 75;
fs = 100e3;
Ts = 1/fs;
p = 1.724e-06;

V1 = 25;
V2 = 50;
V3 = 150;
P1 = 150;
P2 = 100;
P3 = 300;

%%%%%%% Total loss %%%%%

efficiency=0.915;

P_loss=(P1+P2+P3)*((1-efficiency)/efficiency);
%%%%%%%%%%%%%%%%%%%%%%%%

%turns ratio
N1 = (D1/D)*(V1/Vg); %ns1/np
N2 = (D1/D)*(V2/Vg); %ns2/np
N3 = (D1/D)*(V3/Vg); %ns3/np

R1 = V1^2/P1;
R2 = V2^2/P2;
R3 = V3^2/P3;
Is1 = V1/(R1*D1);
Is2 = V2/(R2*D1);
Is3 = V3/(R3*D1);

Kfe = 24;
Bet = 2.7; %Beta
Ku = 0.6;
Ptot = 15;

Ip = (Is1*N1)+(Is2*N2)+(Is3*N3);

Im = Ip

rf = 0.4; % ripple factor 40 percent assigned

del_Im = Im*rf

Im_max = Im + del_Im;

Lm = (Vg*D)/(2*fs*del_Im)

Lm=120e-6;

Id1_rms = sqrt(D1)*Is1;
Id2_rms = sqrt(D1)*Is2;
Id3_rms = sqrt(D1)*Is3;

Is1_rms = Id1_rms;
Is2_rms = Id2_rms;
Is3_rms = Id3_rms;

Itot = Ip*sqrt(D) + Ip*sqrt(D1)

Ip_rms = Ip*sqrt(D);

Pcu = 15; %assumed

Bmax = 0.2;

num_Kg = p*Lm*Lm*Itot*Itot*Im_max*Im_max*10^8;
den_Kg = Bmax*Bmax*Pcu*Ku;
Kg = num_Kg/den_Kg

Ac = 3.24; %Pot EE 70
Wa = 6.75;
MLT = 14;
lm = 18;

lg = (u0*Lm*Im_max*Im_max*10^4)/(Bmax*Bmax*Ac)

np = (Lm*Im_max*10^4)/(Bmax*Ac)

np1 = ceil(np) %rounding up the turn no.

ns1 = ceil(np1 * N1)
ns2 = ceil(np1 * N2)
ns3 = ceil(np1 * N3)

Alpha_p = (np1/np1)*(Ip_rms/Itot)
Alpha_s1 = (ns1/np1) * (Id1_rms/Itot)
Alpha_s2 = (ns2/np1) * (Id2_rms/Itot)
Alpha_s3 = (ns3/np1) * (Id3_rms/Itot)

Awp = (Alpha_p * Ku * Wa)/ np1

Aws1 = (Alpha_s1 * Ku * Wa)/ ns1
Aws2 = (Alpha_s2 * Ku * Wa)/ ns2
Aws3 = (Alpha_s3 * Ku * Wa)/ ns3

del_B = (Vg*D*10^4)/(2*np1*Ac*fs)

% Fig 14.16 -> Refering in Erickson's Book

Pfe=0; % core loss negligible

Total_transformer_loss= Pcu+Pfe

Transformer_loss_percentage=(Total_transformer_loss*100)/P_loss

Loss calculation after device selection: (switch_details_loss_cal.m file)

%Run using the parameters of Transformer_Design_Kg_method.m

Ptotal = 550;

%%%%%%%%%%%%%%% MOSFET
% IXTR 30N25 MOSFET 250 V V, 25 A
%%%%% https://www.mouser.com/datasheet/2/205/ixys_98873-
1170355.pdf
Rds = 75e-3;
tr = 19e-9;
tdon = 19e-9;
tdoff = 79e-9;
tf = 17e-9;
ton = tr+tdon;
toff = tf+tdoff;

%%%%%%%%%%%%%% Diode-1
%%% FSV15100V
%%%% https://www.fairchildsemi.com/datasheets/FS/FSV15100V.pdf
Vfd1 = 0.613;

%%%%%%%%%%%%%% Diode-2
% %% 1N3070
%%% https://www.mouser.com/datasheet/2/308/1N3070-1299871.pdf
Vfd2 = 1;

%%%%%%%%%%%%%% Diode-3
%%% 6A6
%%%% https://www.diodes.com/assets/Datasheets/ds28009.pdf
Vfd3 = 0.9;

%%%%%%%%%%%%%% Capacitor-2 %%%% FFB34E0396K

%%% C2=39uF, Voltage = 100V
%%%%%% http://datasheets.avx.com/ffb.pdf
ESR_C2 = 2e-3;
ESR_C1 = ESR_C2/5;

%%%%%%%%%%%%%% Capacitor-3 %%%% 406PHC250K

%%% C3=40uF, Voltage = 250V
%%%%%% https://www.illinoiscapacitor.com/pdf/phc.pdf
ESR_C3 = 3.9e-3;

Io1 = V1/R1;
Io2 = V2/R2;
Io3 = V3/R3;

del_Ic1 = sqrt(Is1_rms^2-Io1^2);
del_Ic2 = sqrt(Is2_rms^2-Io2^2);
del_Ic3 = sqrt(Is3_rms^2-Io3^2);

C1 = (100*D)/(R1*fs)
C2 = (100*D)/(R2*fs)
C3 = (100*D)/(R3*fs)

C1_Voltage = 1.5*25
C2_Voltage = 1.5*50
C3_Voltage = 1.5*150
%MOSFET

V_MOS_rating = 1.5*(Vg+(np1/ns1)*V1);
I_MOS_rms_rating = 1.5*(Ptotal/(Vg*sqrt(D)));

V_MOS1 = Vg+(np1/ns1)*V1;
V_MOS2 = Vg;
I_MOS_rms = Ptotal/(Vg*sqrt(D));

I_MOS = Im

%DIODE

V_diode_1 = 1.5*(V1+(ns1/np1)*Vg);
V_diode_2 = 1.5*(V2+(ns2/np1)*Vg);
V_diode_3 = 1.5*(V3+(ns3/np1)*Vg);

Id1_rms_rating = 1.5*(sqrt(D1)*Is1);
Id2_rms_rating = 1.5*(sqrt(D1)*Is2);
Id3_rms_rating = 1.5*(sqrt(D1)*Is3);

Id1_rms = sqrt(D1)*Is1;
Id2_rms = sqrt(D1)*Is2;
Id3_rms = sqrt(D1)*Is3;

%LOSSES

Mosfet_loss = I_MOS_rms*I_MOS_rms*Rds
+0.5*I_MOS*V_MOS2*fs*ton+0.5*I_MOS*V_MOS1*fs*toff

D1_Loss = Id1_rms*Vfd1;
D2_Loss = Id2_rms*Vfd2;
D3_Loss = Id3_rms*Vfd3;

Total_Diode_Loss = D1_Loss + D2_Loss + D3_Loss

Cap_loss_1 = del_Ic1*del_Ic1*ESR_C1
Cap_loss_2 = del_Ic2*del_Ic2*ESR_C2
Cap_loss_3 = del_Ic3*del_Ic3*ESR_C3

Total_Cap_loss = Cap_loss_1+Cap_loss_2+Cap_loss_3

Transformer_loss = Pfe+Pcu

Ploss =
Transformer_loss+Mosfet_loss+Total_Diode_Loss+Total_Cap_loss;
Tr_Loss_Percentage = (Transformer_loss/Ploss)*100;

Mos_Loss_Per = (Mosfet_loss*100)/Ploss;

Diode_Loss_Per = (Total_Diode_Loss*100)/Ploss;

Cap_Loss_Per = (Total_Cap_loss/Ploss)*100;

efficiency=Ptotal/(Ptotal+Ploss)

figure
pie([30 45 23 2])
legend({'Transformer Losses','Mosfet Losses','Diode
Losses','Capacitor Losses'},'Location','bestoutside')
title('Initial Loss Distribution allocated');

figure
pie([Tr_Loss_Percentage Mos_Loss_Per Diode_Loss_Per
Cap_Loss_Per])
legend({'Transformer Losses','Mosfet Losses','Diode
Losses','Capacitor Losses'},'Location','bestoutside')
title('Loss Distribution after Transformer Design and Device
Selection');

Code for plotting efficiency vs Vg (for entire range of Vg): (Vg_vs_efficiency.m

file)
clear all
close all
clc

V1=25;
V2=50;
V3=150;

Rds = 75e-3;
tr = 19e-9;
tf = 17e-9;
tdon = 19e-9;
tdoff = 79e-9;
ton = tr+tdon;
toff = tf+tdoff;
Vg0 = 65;
fs = 100e3;
ts = 1/fs;

ESR_C1 = 0.4e-3;
ESR_C2 = 2e-3;
ESR_C3 = 3.9e-3;

Vf1 = 0.613;
Vf2 = 1;
Vf3 = 0.9;

np1 = 51;
ns1 = 28;
ns2 = 56;
ns3 = 167;

i = 1;

N1 = ns1/np1;
N2 = ns2/np1;
N3 = ns3/np1;

%transformer loss
for k = 0:1:4;

Vg = Vg0 + 5*k;

P1 = 150;
P2 = 100;
P3 = 300;

Pout = P1+P2+P3;

R1=V1^2/P1;
R2=V2^2/P2;
R3=V3^2/P3;

Pcu = 15;

if Vg == 65
D = 0.421;
elseif Vg == 70
D = 0.402;
elseif Vg == 75
D = 0.385;
elseif Vg == 80
 D = 0.37;
elseif Vg == 85
D = 0.355;
end

Pfe = 0;

D1 = 1-D;

Is1 = V1/(R1*D1);
Is2 = V2/(R2*D1);
Is3 = V3/(R3*D1);

Ip = (Is1*N1)+(Is2*N2)+(Is3*N3);

Id1_rms = sqrt(D1)*Is1;
Id2_rms = sqrt(D1)*Is2;
Id3_rms = sqrt(D1)*Is3;

Is1_rms = Id1_rms;
Is2_rms = Id2_rms;
Is3_rms = Id3_rms;

Im = Ip;

V_MOS1 = Vg+(np1/ns1)*V1;
V_MOS2 = Vg;

I_MOS = Im;

Itot = Ip*sqrt(D) + Ip*sqrt(D1);

Ip_rms = Ip*sqrt(D);

I_MOS_rms = (Pout/(Vg*sqrt(D)));

Io1 = V1/R1;
Io2 = V2/R2;
Io3 = V3/R3;

Mosfet_Loss = I_MOS_rms*I_MOS_rms*Rds
+0.5*I_MOS*V_MOS2*fs*ton+0.5*I_MOS*V_MOS1*fs*toff

D1_Loss = Id1_rms*Vf1;
D2_Loss = Id2_rms*Vf2;
D3_Loss = Id3_rms*Vf3;
Diode_Losses = D1_Loss+D2_Loss+D3_Loss;

del_Ic1 = sqrt(Is1_rms^2-Io1^2);
del_Ic2 = sqrt(Is2_rms^2-Io2^2);
del_Ic3 = sqrt(Is3_rms^2-Io3^2);

Cap_Loss_1 = del_Ic1*del_Ic1*ESR_C1;
Cap_Loss_2 = del_Ic2*del_Ic2*ESR_C2;
Cap_Loss_3 = del_Ic3*del_Ic3*ESR_C3;

Cap_Losses = Cap_Loss_1+Cap_Loss_2+Cap_Loss_3;

Transformer_Loss = Pcu+Pfe;

P_Loss = Mosfet_Loss+Diode_Losses+Cap_Losses+Transformer_Loss;

P_Loss_Table(k+1)=P_Loss;
MOSFET_loss_Table(k+1)=Mosfet_Loss;
Diode_Losses_Table(k+1)=Diode_Losses;
Cap_Losses_Table(k+1)=Cap_Losses;
Transformer_Loss_Table(k+1)=Transformer_Loss;

Tr_Loss_Percentage = (Transformer_Loss/P_Loss)*100;

Mos_Loss_Per = (Mosfet_Loss*100)/P_Loss;

Diode_Loss_Per = (Diode_Losses*100)/P_Loss;

Cap_Loss_Per = (Cap_Losses/P_Loss)*100;

efficiency = (Pout*100)/(Pout+P_Loss)

n(i) = efficiency;
vg(i) = Vg;

figure(i)
pie([Tr_Loss_Percentage Mos_Loss_Per Diode_Loss_Per
Cap_Loss_Per])
legend({'Transformer Losses','Mosfet Losses','Diode
Losses','Capacitor Losses'},'Location','bestoutside')
if Vg == 65
title('Loss Distribution for Vg = 65')
elseif Vg == 70
title('Loss Distribution for Vg = 70')
elseif Vg == 75
title('Loss Distribution for Vg = 75')
elseif Vg == 80
 title('Loss Distribution for Vg = 80')
elseif Vg == 85
title('Loss Distribution for Vg = 85')
end

i = i+1

end

figure(i)
plot(vg,n,'*-','linewidth',2) %Vg vs efficiency
xlabel('Vg (V)','fontsize',20,'fontweight','bold')
ylabel('Efficiency (%)','fontsize',20,'fontweight','bold')
grid on
set(gca,'fontsize',20,'fontweight','bold')

Code for plotting efficiency vs load (from 10% to 100% load):

(efficiency_vs_load.m file)
clear all
close all
clc

V1=25;
V2=50;
V3=150;

Rds = 75e-3;
tr = 19e-9;
tf = 17e-9;
tdon = 19e-9;
tdoff = 79e-9;
ton = tr+tdon;
toff = tf+tdoff;

Vg = 85;
fs = 100e3;
ts = 1/fs;

ESR_C1 = 0.4e-3;
ESR_C2 = 2e-3;
ESR_C3 = 3.9e-3;
Vf1 = 0.613;
Vf2 = 1;
Vf3 = 0.9;

np1 = 51;
ns1 = 28;
ns2 = 56;
ns3 = 167;

i = 1;

N1 = ns1/np1;
N2 = ns2/np1;
N3 = ns3/np1;

%transformer loss
for k = 0.1:0.1:1;

P1 = k*150;
P2 = k*100;
P3 = k*300;

if k == 0.1
D = 0.352;
elseif k == 0.2
D = 0.3525;
elseif k == 0.3
D = 0.3525;
elseif k == 0.4
D = 0.353;
elseif k == 0.5
D = 0.3535;
elseif k == 0.6
D = 0.354;
elseif k == 0.7
D = 0.354;
elseif k == 0.8
D = 0.3545;
elseif k == 0.9
D = 0.3545;
else k == 1
D = 0.355;
end

D1 = 1-D;

Pout = P1+P2+P3;
R1=V1^2/P1;
R2=V2^2/P2;
R3=V3^2/P3;

Is1 = V1/(R1*D1);
Is2 = V2/(R2*D1);
Is3 = V3/(R3*D1);

Ip = (Is1*N1)+(Is2*N2)+(Is3*N3);

Id1_rms = sqrt(D1)*Is1;
Id2_rms = sqrt(D1)*Is2;
Id3_rms = sqrt(D1)*Is3;

Is1_rms = Id1_rms;
Is2_rms = Id2_rms;
Is3_rms = Id3_rms;

Im = Ip;

V_MOS1 = Vg+(np1/ns1)*V1;
V_MOS2 = Vg;
I_MOS = Im;

Itot = Ip*sqrt(D) + Ip*sqrt(D1);

Ip_rms = Ip*sqrt(D);

I_MOS_rms = (Pout/(Vg*sqrt(D)));

Io1 = V1/R1;
Io2 = V2/R2;
Io3 = V3/R3;

Mosfet_Loss = I_MOS_rms*I_MOS_rms*Rds
+0.5*I_MOS*V_MOS2*fs*ton+0.5*I_MOS*V_MOS1*fs*toff

D1_Loss = Id1_rms*Vf1;
D2_Loss = Id2_rms*Vf2;
D3_Loss = Id3_rms*Vf3;

Diode_Losses = D1_Loss+D2_Loss+D3_Loss;

del_Ic1 = sqrt(Is1_rms^2-Io1^2);
del_Ic2 = sqrt(Is2_rms^2-Io2^2);
del_Ic3 = sqrt(Is3_rms^2-Io3^2);
Cap_Loss_1 = del_Ic1*del_Ic1*ESR_C1;
Cap_Loss_2 = del_Ic2*del_Ic2*ESR_C2;
Cap_Loss_3 = del_Ic3*del_Ic3*ESR_C3;

Cap_Losses = Cap_Loss_1+Cap_Loss_2+Cap_Loss_3;

Pcu = 15;
Pfe = 0.1863;

Transformer_Loss = Pcu+Pfe;

P_Loss = Mosfet_Loss+Diode_Losses+Cap_Losses+Transformer_Loss;

Tr_Loss_Percentage = (Transformer_Loss/P_Loss)*100;

Mos_Loss_Per = (Mosfet_Loss*100)/P_Loss;

Diode_Loss_Per = (Diode_Losses*100)/P_Loss;

Cap_Loss_Per = (Cap_Losses/P_Loss)*100;

efficiency = (Pout*100)/(Pout+P_Loss)

n(i) = efficiency;

Load(i) = (Pout/550)*100;

i = i+1

end

plot(Load,n,'*-','linewidth',2) %Load against efficiency

xlabel('Load (%)','fontsize',20,'fontweight','bold')
ylabel('Efficiency (%)','fontsize',20,'fontweight','bold')
grid on
set(gca,'fontsize',20,'fontweight','bold')

Code for plotting bode plot: (Controller_Bode_Plot.m file)

clc;
clear;
close all;
D = 0.38;
D1 = 1-D;
ns3 = 167;
np1 = 51;
R3 = 75;
C3 = 40e-6;
Lm = 120e-6;
V3 = 150;
Im = (ns3/np1)*(V3/(R3*D1))

Gg0 = (ns3/np1) * (D/D1)

Vg = V3*(np1/ns3)*(D1/D)
Gd0 = ((ns3/np1)*Vg+V3)/D1
omega_0 = (np1/ns3) * (D1/ sqrt(Lm * C3))
omega_z = (np1/ns3)*(D1)*((ns3/np1)*Vg+V3)/(Lm*Im)
Q = (np1/ns3)*D1 * R3* sqrt(C3/Lm)

%%
s = tf('s')
Gvd = Gd0 * (1-s/omega_z)/(1+s/(Q*omega_0)+s^2/omega_0^2)

H = 1;
Vm = 1;
T0 = H * Gvd/Vm

Gc0=1.5757/(2.5e2);
omega_zc=4.1e3;
omega_l=2.5e2;
omega_zp=2.9e7;

Gc = Gc0 * (1+s/omega_zc)*(1+omega_l/s)/(1+s/omega_zp)

figure
margin(T0)
grid on

figure
margin(Gc)
grid on

figure
margin(Gc*T0)
grid on

The Datasheets of selected devices are attached next.