CE/EE 270: Introduction to Digital System Design

(Digital Calculator)

Project Deliverable II: Report

Group Members: ID:

Mariam Hussain 26824

Reem Aldaihani 35725

Miss. Asli Baysal

Date: 26/11/2019
Section: F9

Fall 2019
Abstract:

Digital Design is taking the market share with its maximum demands in never-ending
today’s technology. Signals that are represented digitally can be transmitted without
degradation due to noise. For example, a continuous audio signal, transmitted as a
sequence of 1s and 0s, can be reconstructed without error provided the noise picked up in
transmission is not enough to prevent identification of the 1s and 0s. An hour of music can
be stored on a compact disc as about 6 billion binary digits. In a digital system, a more
precise representation of a signal can be obtained by using more binary digits to represent it.
While this requires more digital circuits to process the signals, each digit is handled by the
same kind of hardware. In an analog system, additional resolution requires fundamental
improvements in the linearity and noise characteristics of each step of the signal chain. In
this project we were asked to build a “Digital Calculator” based on our knowledge of Digital
Designs and circuits. By having previous knowledge and concepts of Digital Design we
implemented a Calculator by the aid of digital design software like Proteus where we
simulated our circuit and as well as the coding was done in Verilog. We built some general
modules of calculator like Adder, Subtractor, Multiplier and Power by the aid of logic gates.
With the advancement in the field of Embedded Systems the value of digital circuits have
been increased to a far extent and we see further tremendous development in this regard as
well! Its application are numerous and find itself in various small scale circuits that are used
for several purpose!
Contents
1. Introduction: ................................................................................................................... 4
1.1. Problem Definition................................................................................................... 4
1.2. Criteria and Constraints .......................................................................................... 4
1.3. Objectives ............................................................................................................... 4
1.4. Structure of the Report ............................................................................................ 4
2. Available Solutions ......................................................................................................... 5
2.1. Brainstorming.......................................................................................................... 5
2.2. Advantages and Disadvantages of each solution .................................................... 5
3. Proposed Solution/idea/Method ..................................................................................... 5
3.1. Background............................................................................................................. 5
3.2. Theory Using Block Diagram. ................................................................................. 5
3.3. Components ........................................................................................................... 6
3.4. Design / Circuit diagram .......................................................................................... 6
3.5. Discussion / Simulations ......................................................................................... 8
4. Conclusion ................................................................................................................... 21
References ......................................................................................................................... 22
Appendices ......................................................................................................................... 23
Verilog HDL code D1 .......................................................................................................... 23
Verilog HDL code D2 .......................................................................................................... 24
1. Introduction:

Digital circuits are one of the most demanding things now a days. We have designed
here an application that is based on digital techniques. As assigned to design a digital
calculator. We have used logic gates that are meant to perform various arithmetic operations
like addition, subtraction, multiplication, power and as well as we have accounted the circuit
for Carry bit and checked overflow too. We have written our code on Verilog using some
commands and building functions for the operations stated above. For the purpose of
simulation we have used Prorteus as our tool and those snipes are attached herewith the
report for serving the purpose.

1.1. Problem Definition

We were assigned to design a digital calculator. The problem was to design a 4 bit device
that could easily solve the basic arithmetic operations and do the service for us and we
have been successful doing that.

1.2. Criteria and Constraints

The criteria was to Design a Multifunction calculator using K-maps, with 2 inputs (A & B)
each of size 2-bits. The calculator has 2 select lines (S1 & S0) to select one of three
functions according to the table below:

S1 S0 Function Output
00 Off Zero Value
01 ADD A+B
10 Multiply A*B
11 Power 𝐴B

1.3. Objectives
The objectives of this project was the to make the code for a digital calculator and simulate
them on a software. The objectives have been met successfully!

1.4. Structure of the Report

The report started with the abstract, introduction and now we would discuss the
implementation of some technical aspects with the help of tools used using Verilog Codes,
Schematic and simulation as well.

2. Available Solutions
This project was a diverse one and could have been solved and built in various ways by the
aid of microprocessors, Arduino, PI and other controllers. We have used here basic logic
gates that have done the same thing for us that we could achieve with expensive complex
circuitry.

2.1. Brainstorming
The use of digital techniques was the primary focus where it was difficult to decide what
approaches are to be applied and what would be the consequence for them. We went with
basic circuitry for the solution of a complex problem!

2.2. Advantages and Disadvantages of each solution

The main advantage of implementing our calculator with the help of logic gates was that it
could have been implemented easily and quite inexpensive as compared to bulky materials
like microcontroller where you have to program the IC and other measurements are to be
kept in mind as well!

3. Proposed Solution/idea/Method
We have used AND, XOR and multiplexers to serve the purpose and meet our requirements.
We have first checked the results manually and then with the use of K-maps and Verilog code
we went our business. The circuit was build on Proteus as well where the simulations were
done and the results were noted for them.

3.1. Background
The Verilog code was used primarily to build our project and the results were then verified
from simulations as well. K-maps were in use for equations and optimization purpose!

3.2. Theory Using Block Diagram.

Arithmetic
Operations like
IP Add, Subtract Multiplexe Processing
Simulation Results
,Power and r
Multiplier
The above mentioned procedure was followed during building our project. The input was 4
bit (2 bits from each signal) then logic gates were planted for computation. The multiplexer
was involved for the selection of operation. It were then simulated and the results were
shown.

3.3. Components
Combinational circuits (full adders) and MUX’ers.
FBGA device and 7-segments display and converting BCD to binary.
3.4. Design / Circuit diagram

Figure 1: 7-Segment Displayer code D2

Figure 2 Calculator Code 1

Figure 3 Calculator Code 2

Figure 4 Block Diagram

3.5. Discussion / Simulations

Figure 5 Calculator pin planner (PD1)

 Figure 6 Calculator Pinplanner2 (PD1)

Figure 7 Waveform before simulation (PD1)

Figure 8 Waveform after simulation (PD1)

Figure 9 Waveform before simulation (PD2)

Figure 10 Waveform after simulation (PD2)

Figure 11 Pin Planner D2

S1 S0 B1 B0 A1 A0 LED4 LED3 LED2 LED1 LED0

0) 0 0 0 0 0 0 0 0 0 0 0
1) 0 0 0 0 0 1 0 0 0 0 0
2) 0 0 0 0 1 0 0 0 0 0 0
3) 0 0 0 0 1 1 0 0 0 0 0
4) 0 0 0 1 0 0 0 0 0 0 0
5) 0 0 0 1 0 1 0 0 0 0 0
6) 0 0 0 1 1 0 0 0 0 0 0
7) 0 0 0 1 1 1 0 0 0 0 0
8) 0 0 1 0 0 0 0 0 0 0 0
9) 0 0 1 0 0 1 0 0 0 0 0
10) 0 0 1 0 1 0 0 0 0 0 0
11) 0 0 1 0 1 1 0 0 0 0 0
12) 0 0 1 1 0 0 0 0 0 0 0
13) 0 0 1 1 0 1 0 0 0 0 0
14) 0 0 1 1 1 0 0 0 0 0 0
15) 0 0 1 1 1 1 0 0 0 0 0
16) 0 1 0 0 0 0 0 0 0 0 0
17) 0 1 0 0 0 1 0 0 0 0 1
18) 0 1 0 0 1 0 0 0 0 1 0
19) 0 1 0 0 1 1 0 0 0 1 1
20) 0 1 0 1 0 0 0 0 0 0 1
21) 0 1 0 1 0 1 0 0 0 1 0
22) 0 1 0 1 1 0 0 0 0 1 1
23) 0 1 0 1 1 1 0 0 1 0 0
24) 0 1 1 0 0 0 0 0 0 1 0
25) 0 1 1 0 0 1 0 0 0 1 1
26) 0 1 1 0 1 0 0 0 1 0 0
27) 0 1 1 0 1 1 0 0 1 0 1
28) 0 1 1 1 0 0 0 0 0 1 1
29) 0 1 1 1 0 1 0 0 1 0 0
30) 0 1 1 1 1 0 0 0 1 0 1
31) 0 1 1 1 1 1 0 0 1 1 0
32) 1 0 0 0 0 0 0 0 0 0 0
33) 1 0 0 0 0 1 0 0 0 0 0
34) 1 0 0 0 1 0 0 0 0 0 0
35) 1 0 0 0 1 1 0 0 0 0 0
36) 1 0 0 1 0 0 0 0 0 0 0
37) 1 0 0 1 0 1 0 0 0 0 1
38) 1 0 0 1 1 0 0 0 0 1 0
39) 1 0 0 1 1 1 0 0 0 1 1
40) 1 0 1 0 0 0 0 0 0 0 0
41) 1 0 1 0 0 1 0 0 0 1 0
42) 1 0 1 0 1 0 0 0 1 0 0
43) 1 0 1 0 1 1 0 0 1 1 0
44) 1 0 1 1 0 0 0 0 0 0 0
45) 1 0 1 1 0 1 0 0 0 1 1
 46) 1 0 1 1 1 0 0 0 1 1 0
47) 1 0 1 1 1 1 0 1 0 0 1
48) 1 1 0 0 0 0 0 0 0 0 0
49) 1 1 0 0 0 1 0 0 0 0 1
50) 1 1 0 0 1 0 0 0 0 0 1
51) 1 1 0 0 1 1 0 0 0 0 1
52) 1 1 0 1 0 0 0 0 0 0 0
53) 1 1 0 1 0 1 0 0 0 0 1
54) 1 1 0 1 1 0 0 0 0 1 0
55) 1 1 0 1 1 1 0 0 0 1 1
56) 1 1 1 0 0 0 0 0 0 0 0
57) 1 1 1 0 0 1 0 0 0 0 1
58) 1 1 1 0 1 0 0 0 1 0 0
59) 1 1 1 0 1 1 0 1 0 0 1
60) 1 1 1 1 0 0 0 0 0 0 0
61) 1 1 1 1 0 1 0 0 0 0 1
62) 1 1 1 1 1 0 0 1 0 0 0
63) 1 1 1 1 1 1 1 0 0 0 0

 When the input S1=0 and S0=0 the function is off and the output equal zero as it
show in yellow the possibility.
 When the S1=0 and S0=1 the function adding and the output equal A+B as it shows
in blue the possibility of adding A and B.
 When S1=1 and S0=0 the function multiply A*B as it shows in grey the possibility of
multiplying A by B.
 When S1 =1 and S0=1 the function A^B (the power is B) as it shows in light green the
possibility of A having power B.

For each output LED we will have k-map. Also, we will have four k-map for
(LED3,LED2,LED1,LED0) and LED4 we already have it equation because it is only one as a min
term at possible (63) in truth table.
LED4 equation is = S1S0B1B0A1A0

LED0 ) k-map : divided into 4 smaller k-map to be more simple

S1=0 , S0=0
00) 0 01) 0 11) 0 10) 0
01) 0 0 0 0
11) 0 0 0 0
10) 0 0 0 0
S1=0 , S0=1
00) 0 10) 1 11) 1 10) 0
10) 1 0 0 1
11) 1 0 0 1
10) 0 1 1 0

S1=1 , S0=0
00) 0 10) 0 11) 0 10) 0
10) 0 1 1 0
11) 0 1 1 0
10) 0 0 0 0

S1=1 , S0=1
00) 0 10) 1 11) 1 10) 1
10) 0 1 1 0
11) 0 1 0 0
10) 0 1 1 0

LED0 = S0 B0` A0 + S1` S0 B0 A0` + S1 S0` B0 A0 + S1 S0 B1` B0` A1 + S0 B1` B0 A0 +S1 B0 A1` A0

LED1 ) k-map : divided into 4 smaller k-map to be more simple

S1=0 , S0=0
00) 0 01) 0 11) 0 10) 0
01)0 0 0 0
11) 0 0 0 0
10) 0 0 0 0

S1=0 , S0=1
00) 0 00) 0 11) 1 10) 1
01)0 1 0 1
11) 1 0 1 0
10) 1 1 0 0
S1=1 , S0=0
00) 0 00) 0 11) 0 10) 0
01)0 0 1 1
11) 0 1 0 1
10) 0 1 1 0

S1=1 , S0=1
00) 0 00) 0 11) 0 10) 0
01)0 0 1 1
11) 0 0 0 0
10) 0 0 0 0

LED1 = S1` S0 B1` B0` A1+S1 B1` B0 A0 +S1` S0 B1` A1 A0` + S1` S0 B1 A1` A0` + S1`
S0 B1` B0 A1` A0 + S1` S0 B1 B0 A1 A0 + S1 S0` B0 A1 A0` + S1 S0` B1 A1` A0 + S1 S0`
B1 A1` A0 + S1` S0 B1 B0` A1`

LED2 ) k-map : divided into 4 smaller k-map to be more simple

S1=0 , S0=0
00) 0 00) 0 11) 0 10) 0
01)0 0 0 0
11) 0 0 0 0
10) 0 0 0 0

S1=0 , S0=1
00) 0 00) 0 11) 0 10) 0
01)0 0 1 0
11) 0 1 1 1
10) 0 0 1 1

S1=1 , S0=0
00) 0 00) 0 11) 0 10) 0
01)0 0 0 0
11) 0 0 0 1
10) 0 0 1 1
S1=1 , S0=1
00) 0 00) 0 11) 0 10) 0
01)0 0 0 0
11) 0 0 0 0
10) 0 0 0 1

LED2 = S1` S0 B1 A1 + S1` S0 B0 A1 A0 + S1` S0 B1 B0 A0 + S1 S0` B1 B0` A1+ S1 S0`

B1 A1 A0`+ S0 B1 B0` A1 A0`

LED3 ) k-map : divided into 4 smaller k-map to be more simple

S1=0 , S0=0
00) 0 01) 0 11) 0 10) 0
01)0 0 0 0
11) 0 0 0 0
10) 0 0 0 0

S1=0 , S0=1
00) 0 00) 0 11) 0 10) 0
01)0 0 0 0
11) 0 0 0 0
10) 0 0 0 0

S1=1 , S0=0
00) 0 00) 0 11) 0 10) 0
01)0 0 0 0
11) 0 0 1 0
10) 0 0 0 0

S1=1 , S0=1
00) 0 00) 0 11) 0 10) 0
01)0 0 0 0
11) 0 0 0 1
10) 0 0 1 0

LED3 = S1 S0` B1 B0 A1 A0 + S1 S0 B1 B0` A1 A0 + S1 S0 B1 B0 A1 A0`

 The simplifies equations for each output
LED0 = S0 B0` A0 + S1` S0 B0 A0` + S1 S0` B0 A0 + S1 S0 B1` B0` A1 + S0 B1` B0 A0 +S1 B0 A1`
A0

LED1 = S1` S0 B1` B0` A1+S1 B1` B0 A0 +S1` S0 B1` A1 A0` + S1` S0 B1 A1` A0` + S1` S0 B1` B0
A1` A0 + S1` S0 B1 B0 A1 A0 + S1 S0` B0 A1 A0` + S1 S0` B1 A1` A0 + S1 S0` B1 A1` A0 + S1` S0
B1 B0` A1`

LED2 = S1` S0 B1 A1 + S1` S0 B0 A1 A0 + S1` S0 B1 B0 A0 + S1 S0` B1 B0` A1+ S1 S0` B1 A1

A0`+ S0 B1 B0` A1 A0`

LED3 = S1 S0` B1 B0 A1 A0 + S1 S0 B1 B0` A1 A0 + S1 S0 B1 B0 A1 A0`

LED4 = S1 S0 B1 B0 A1 A0

7-Segments:

Truth table:

Input Output
LED LED LED LED g f e d c b a
0 1 2 3
A B C D
0 0 0 0 1 0 0 0 0 0 0
0 0 0 1 1 1 1 1 0 0 1
0 0 1 0 0 1 0 0 1 0 0
0 0 1 1 0 1 1 0 0 0 0
0 1 0 0 0 0 1 1 0 0 1
0 1 0 1 0 0 1 0 0 1 0
0 1 1 0 0 0 0 0 0 1 0
0 1 1 1 1 1 1 1 0 0 0
1 0 0 0 0 0 0 0 0 0 0
1 0 0 1 0 0 1 1 0 0 0
K-maps:
a =A’B’C’D+A’BC’D’

00 01 11 10
00 1

01 1

11

10

b=A’BC’D+A’BCD’

00 01 11 10

00

01 1 1

11

10

C=A’B’CD’

D=A’BC’D’+A’BCD+B’C’D
 00 01 11 10

00 1

01 1 1

11 1

10

E=B’C’D+A’BC’+A’D

00 01 11 10

00 1 1

01 1 1 1

11

10
1

F=A’B’D+A’B’C+A’CD

00 01 11 10
00 1 1 1

01 1

11

10

G=A’BCD+A’B’C’

00 01 11 10

00 1 1

01 1

11

10
4. Conclusion
It was a tricky project and has added to our knowledge of digital designs that how we need
to think and design such systems! Digital Calculator has been built and its functionality can
be proved with the snipes and files attached with report.
References
Figure[1] 7-Segment Displayer code D2
Figure[2] Figure 2 Calculator Code 1
Figure[3] Calculator Code 2
Figure[4] Code
Figure[5] Calculator Pin planner 1 (PD1)
Figure[6] Calculator Pin planner 2 (PD2)
Figure[7] Waveform before simulation (PD1)
Figure[8] Waveform after simulation (PD1)
Figure[9] Waveform before simulation (PD2)
Figure[10] Waveform after simulation (PD2)
Figure[11] Pin planner (PD2)
Appendices
Verilog HDL code D1
module Pd1(S1,S0,A1,A0,B1,B0, LED0,LED1,LED2,LED3,LED4);
input S1,S0,A1,A0,B1,B0;
output reg LED0,LED1,LED2,LED3,LED4;

always @(S1,S0,A1,A0,B1,B0) begin

if (S1 == 0 && S0 == 0) begin
LED0 = 0;
LED1 = 0;
LED2 = 0;
LED3 = 0;
LED4 = 0;
end
else if (S1 == 0 && S0 == 1) begin
LED0 = 0;
LED1 = (A1&B1) | (A1&A0&B0) | (A0&B1&B0);
LED2 = (A1&~B1&~B0) | (A1&~A0&~B1) | (~A1&B1&~B0) | (~A1&~A0&B1)
| (~A1&A0&~B1&B0) | (A1&A0&B1&B0);
LED3 = (A0&~B0) | (~A0&B0);
LED4 = 0;
end
else if (S1 == 1 && S0 == 0) begin
LED0 = A1&A0&B1&B0;
LED1 = (A1&~A0&B1) | (A1&B1&~B0);
LED2 = (A1&~B1&B0) | (A1&~A0&B0) | (~A1&A0&B1) | (A0&B1&~B0);
LED3 = (A0&B0);
LED4 = 0;
end
else begin
LED0 = (A1&~A0&B1&B0) | (A1&A0&B1&~B0);
LED1 = (A1&~A0&B1&~B0);
LED2 = (A1&~B1&B0);
LED3 = (A0&~B1) | (~A1&A0) | (~B1&~B0) | (A0&~B0);
LED4 = (A1&A0&B1&B0);
end
end
endmodule
Verilog HDL code D2
module Pd2(Din, Dout);
input [3:0]Din;
output reg [6:0]Dout;

always @(Din) begin

case(Din)
0: Dout <= 7'b1000000;
1: Dout <= 7'b1111001;
2: Dout <= 7'b0100100;
3: Dout <= 7'b0110000;
4: Dout <= 7'b0011001;
5: Dout <= 7'b0010010;
6: Dout <= 7'b0000010;
7: Dout <= 7'b1111000;
8: Dout <= 7'b0000000;
9: Dout <= 7'b0011000;
endcase
end
endmodule