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Ultra low power multiplexer design using variation in CMOS inverter

Conference Paper · September 2015

DOI: 10.1109/IC4.2015.7375632

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IEEE International Conference on Computer, Communication and Control, MGI Indore, INDIA. September 10 -12, 2015.
> PAPER IDENTIFICATION NUMBER (IC4_5214) <

Ultra Low Power Multiplexer design using

Variation in CMOS Inverter
Nidhi Maheshwari Debendra Kumar Panda
Electronics & Communication Department Electronics & Communication Department
Shri G.S. Institute of Technology & Science Medicaps Institute of Technology and Management
Indore, India Indore, India
nids.maheshwari17@gmail.com debendrakumar.panda@gmail.com

Abstract— Demands for the low power VLSI have been
pushing the development of aggressive design methodologies to
reduce the power consumption or power dissipation drastically.
To meet the growing demand, we propose a new low power
multiplexer cell by reducing the MOS Transistor count that
reduces the serious threshold loss problem. In the proposed
circuit we use CMOS technique for designing of ultra low power
Multiplexer because in CMOS techniques there is almost zero
static power dissipation. In conventional multiplexer there are 12
number of transistors which consumes more power as compare
to proposed multiplexer which include only 8 number of
transistor in CMOS form, considerably increases the speed and
decreases the power when compared to the proposed multiplexer.
Also proposed circuit consumes less power as compare to
dynamic multiplexer.
or STROBE input, which needs to be active for the
multiplexer to be able to perform its intended function [3].
A multiplexer selects binary information present on
any one of the input lines, depending upon the logic status of
selection inputs, and routes it to the output line. If there are n
selection lines, then the number of maximum possible input
lines is 2n and the multiplexer is referred to as a 2n-to-1
multiplexer or 2n ×1 multiplexer[4]. Fig. 2(a) and (b)
respectively show the circuit representation and truth table of a
basic 2-to-1 multiplexer.

Keywords—CMOS, Static & Dynamic Multiplexer, low power,

static power dissipation.

I. INTRODUCTION

The increasing prominence of portable systems and need

to limit power consumption has led to rapid and innovative
developments in low power VLSI design during recent years
Fig.1: The schematic diagram, boolean equation and the truth
[1]. The driving forces behind these developments are portable
device applications requiring low power consumption and table of a 2:1 multiplexer with inputs A and B, select input S
high throughput due to their small chip size with large density and the output Z.
of components, increased complexity and high frequencies [2].
A multiplexer or multiplexer is a combinational
circuit that selects several analog or digital input signals and
forwards the selected input into a single output line. A
multiplexer of 2n inputs has n selected lines, are used to select
which input line is send to the output[1-2].
A multiplexer or MUX or data selector is a
combinational circuit with more than one input line, one
output line and more than one selection line. There are some
multiplexer ICs that provide complementary outputs. Also,
multiplexers in IC form almost invariably have an ENABLE
or STROBE input, which needs to be active for the
multiplexer to be able to perform its intended function[3].
A multiplexer or MUX or data selector is a
combinational circuit with more than one input line, one
(c)
output line and more than one selection line. There are some
multiplexer ICs that provide complementary outputs. Also,
multiplexers in IC form almost invariably have an ENABLE Fig.2: (a) 2-to-1 multiplexer circuit representation, (b) 2-to-1
multiplexer truth table and (c) 2-to-1 multiplexer.
IEEE Madhya Pradesh Sub-Section
IEEE International Conference on Computer, Communication and Control, MGI Indore, INDIA. September 10 -12, 2015.
> PAPER IDENTIFICATION NUMBER (IC4_5214) <
II. CMOS INVERTER
In Fig. 3, note that the input voltage is connected to
the gate terminals of both nMOS and pMOS transistors. Thus,
both transistors are driven directly by the input signal, Vin. The
substrate of nMOS transistor is connected to the ground, while
the substrate of pMOS transistor is connected to the power
supply voltage, VDD, in order to reverse-bias the source and
drain junctions. Since VSB = 0 for both devices, there will be
no substrate-bias effect for either device[5]. It can be seen from
the circuit diagram in Fig. 1.6 that
VGSn = Vif
VDS=Vot (1.3)
and also,
VGS,P = - (VDD- Vif)
VDS,P = - (VDD-Vut) (1.4)
We will start our analysis by considering two simple cases.
When the input voltage is smaller than the nMOS threshold
voltage, i.e., when Vi < Vtn, nMOS transistor is cut-off. At the
same time, the pMOS transistor is on and operating in linear
region. Since the drain currents of both transistors are
approximately equal to zero (except for small leakage
currents), i.e.,
IDn = IDp
the drain-to-source voltage of pMOS transistor is also equal to
zero, and the output voltage VOH is equal to the power supply
voltage.
Vout = VOH = VDD (1.5)
Fig.3: (a) CMOS inverter circuit. (b) Simplified view of
CMOS inverter consisting of two complementary non-ideal
switches.
On the other hand, when input voltage exceeds (VDD + VT);
the pMOS transistor is turned off. In this case, the nMOS
transistor is operating in linear region, but its drain-to-source
voltage is equal to zero because condition (1.4) is satisfied.
Consequently, output voltage of the circuit is
Vout=VOL=0 (1.6)
Next, we examine the operating modes of nMOS and pMOS
transistors as functions of the input and output voltages. The
nMOS transistor operates in saturation if VIN>VMon and if the
following condition is satisfied.
VDSn ≥ VGSn - VTon
& Vout ≥ Vin -VTon
.
III. PROPOSED DESIGN
For a digital circuit, the most essential parameters are
power & delay. The circuit having an optimized power and
minimum delay is best suitable for many applications, thus for
designing an low power circuit CMOS technique is best
suitable because it has almost zero static power dissipation and
its implementation and working principle is given as:
For CMOS inverter, its working principle states as
whenever the input is low means having voltage less than
threshold voltage (less than nMOS and greater than pMOS)
then pMOS will be in ON condition and behave like a
resistance so that current will flow w.r.t. the resistance and
represent an output voltage which will be lies in logic 1 level
and thus inverter inverted its output and similarly
complemented operation is repeated for nMOS.
With the operation in the threshold voltage of
pMOS & nMOS, CMOS inverter can be converted in to
NAND, NOR and NOT gate.
From the above circuit, it is conclude that a multiplexer
can also be design using only 8 numbers of transistors which
are arrange in CMOS form. From the gate level view of 2:1
multiplexer it is seen that only 4 gates are used in which one is
simple inverter and other three are 2 input NAND gate and our
proposal is to design these 2 input NAND gate using 2
MOSFET connected in CMOS style.
Fig.4: Gate analysis of Multilexer
The NAND gate can be design using CMOS logic by
variation in the threshold voltage of CMOS inverter circuit as
set the threshold voltage of pMOS as low and set the threshold
voltage of nMOS as high so that output will be high, till there
is 70-75% of input logic level and become low when the input
voltage rises above this level.
Their capacitor value can be change according to the
logic swing required and thus from the calculation of capacitor
value as:
C=qV
i.e., as the capacitance value vary the corresponding variation
in voltage value and this value is in logic swing level.
IV. SIMULATION RESULTS
The conventional multiplexer contains 12 numbers of
transistors in any logic function, the complementary CMOS is
realized by nMOS pull-down and pMOS pull-up networks
IEEE International Conference on Computer, Communication and Control, MGI Indore, INDIA. September 10 -12, 2015.
> PAPER IDENTIFICATION NUMBER (IC4_5214) <

connected between gate, output and power lines[2]. Input

signals are connected to transistor gates only.
Schematic of conventional 2:1 multiplexer and their
simulation results are shown in Fig.6 with supply voltage as
VDD=1V and analysis for 0ns to 100ns duration.

Fig.8: Schematic design of proposed 2:1 multiplexer

Fig.5: Proposed Design using MOSFET
The ultra low power proposed design using CMOS is
shown in Fig. 8 and its simulation result for supply voltage
VDD=1V & for duration 0ns to 100ns is shown in Fig. 9.

Fig.6: Schematic of conventional 2:1 multiplexer

Fig.9: Simulation result of 2:1 proposed multiplexer

On the basis of power and delay, the analysis is done

on 45nm technology and for supply voltage from 0.6v to 1.5v
and power dissipation result is in microwatt is given in Table-
1 and the delay analysis for supply voltage from 0.6v to 1.5v
Fig.7: Simulation result of 2:1 conventional multiplexer is given in Table-2.
IEEE International Conference on Computer, Communication and Control, MGI Indore, INDIA. September 10 -12, 2015.
> PAPER IDENTIFICATION NUMBER (IC4_5214) <

Table-1: Dissipation Power

Name of circuit 0.6v 0.8v 1.0v 1.2v 1.5v

Conventional 4.14 4.19 4.27 4.35 4.49
Proposed 1.02 1.05 1.08 1.11 1.21

Table-2: Delay Analysis

Name of circuit 0.6v 0.8v 1.0v 1.2v 1.5v

Conventional 5.81 5.74 5.66 5.45 5.31
Proposed 8.54 8.06 7.82 7.57 7.12

V. CONCLUSION

From the above result, it is concluded that the power

dissipation in the proposed circuit is approximately 75.19%
than static (conventional design) circuit but have 57.17% more
delay as compare to static circuit like conventional,
transmission etc. and have approximately 85.01% delay as
compare to dynamic circuit.

REFERENCES

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[2] Chang H.E., Huang J.D., Chen C.I., “Input Selection Encoding
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[3] Sun X, Feng J, “A 10 Gb/s Low-power 4:1 Multiplexer in 0.18µm
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[4] Narayanan U, Leong, Chaung, Liu, “Low power Multiplexer
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[5] S.M. Kang and Y. Leblebici, “CMOS Digital Integrated Circuits”
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[7] K.Tanaka, “High Speed 8:1 Multiplexer and 1:8 Demultiplexer
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[8] T. Seshita “A 20 GHz 8-bit Multiplexer IC Implemented with 0.5
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