VANTEDDU SAI

KIRAN REDDY
MTech Microelectronics at IIIT-Allahabad
saikiran-reddy-12839b197 Hyderabad, India
(+91) 8668460188 saikiranr3ddy@gmail.com

PROJECTS SKILLS

Top Skills Analog Design and layout, RTL Coding,

Design of a two-stage OP-AMP using UMC 180nm Technology Digital, stability analysis, signals and system
• Two stages OP-AMP with Gain=62dB, GBW=30 MHz, PM=60, Slew rate= 20v/us
power dissipation 0.3mW. Designed and simulated in Cadence Virtuoso using
UMC 180nm technology. Tools and Tech. Xilinx Vivado, Cadence Virtuoso,
Calibre & HSpice, Synopsys DC, LT-Spice
Design and Simulate of Bandgap reference Circuit (BGR) using UMC
180nm Technology Prog. & Protocol Verilog, C/C++, MATLAB, Unix Shell
• Design Current mirror-based Bandgap Voltage reference circuit with start-up circuit
(Temp range -20°C to 140°C, Vout= 1.154v, well curve voltage = 0.015v, Vdd
=1.8v) with Cadence Virtuoso, LT-Spice Also design 1v Sub BGR circuit
Skills ASIC Design Flow, Analog Design Flow,
Design Low Voltage, High PSRR, Low Dropout Voltage Regulator Logic Synthesis, Physical Design Flow Static
(LDO) Time Analysis.
• LDO work on (0.95v < Vin < 2.4v, Vout= 0.900v, PSRR@ 100KHz= 60dB, Cload
=10u with Rser=1ohm, Max load current 50ma, load regulation =0.083%, Line
regulation=1.2%, Current Efficiency= 98.5%) EDUCATION
Design and Implementation of folded and telescopic amplifier in 180nm
technology. MTech Microelectronics
IIIT, Allahabad
Design and Implement, 32 Bit RISC processor using Verilog
August 19 – June 21 CGPA- 7.5
• Implemented 32-bit RISC Architecture based processor with and without pipeline
Architecture Courses are taken: Intro. of Microelectronics, Digital VLSI Design,
• Implemented R-type, J-type, I-type Instruction set Architecture (ISA) Programming for Eng. Application, Analog VLSI Design, Embedded
Systems, Testing, and Verification, Hardware Design Methodologies,
Design fully Synthesized synchronous FIFO design VLSI IC Technology, Mix IC Design, MEMS.
• synchronous FIFO using Queue data structure, with the help of
binary pointer.

Btech Electronic system Engineering

MTECH THESIS NIELIT, Aurangabad
July 14 – June 18 7.6
LDO for SOC applications in 65nm
• working on fast transients, low load regulation, high PSRR value. Intermediate
• With the use of internal compensation techniques (work in Board of Intermediate Education Andhra Pradesh
July 12 – May 14 96.10 %
progress)

Matriculation
Board of secondary Education Andhra Pradesh
July 11 – June 12 9.5