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Introduction
Recently, current mode circuits have been receiving significant attention in analog
signal processing. A useful function block for high frequency current mode
applications is a current conveyor. The current conveyor is a three terminal device
performing many useful analog signal processing functions when the device is
connected with other electronic elements in specific circuit configurations. The
current conveyor has evolved from first generation to second generation. The first
generation current conveyor (CCI) was proposed by Smith and Sedra in 1968 [1] and
the more versatile second generation current conveyor (CCII) was introduced by the
same two authors in 1970 [2], as an extension of their first generation conveyor.
In many cases, the current conveyor simplifies circuit design in much the same way
as the conventional op-amp, but it presents an alternative method of implementing
analog systems which traditionally has been based on op-amp. This alternative
approach leads to new methods of implementing analog transfer functions, and in many
cases the conveyor-based implementation offers improved performance to the voltage
op-amp-based implementation in terms of accuracy, bandwidth and convenience.
Circuits based on voltage op-amps are generally easy to design since the behavior of a
voltage op-amp can be approximated by few simple design rules. This is also true for
current conveyors. Several hundred papers have been published on the theory and
applications of current conveyors. Some of these applications are shown in Fig. 1 [3,
4].
Section II gives an overview of the current conveyor, the proposed CMOS current
controlled conveyor is described in Section III, and the architecture of the second order
current-mode bandpass filter is described in Section IV. Section V is the conclusion.
1
Instrumentation Differentiation
CCCS
Amps
Integration
VCCS Amplifiers
Analogue
Computation
Summation
Ideal transistor
Current Conveyors
Oscillators
Current-Feedback
Filters
Op-amps
Impedance
Conversion
Inductance
Synthesis
FDNR
Synthesis
2
II. Conventional Current Conveyors
The current controlled conveyor is derived from the current conveyor. In this
section, we will describe the basic idea of the CCII circuit, and the previous Bipolar
implementation of CCIIs.
iy 0 0 0 vy
vx = 1 0 0 ix (1)
iz 0 ±1 0 vz
iy
vy Y iz
CCII Z vz
vx X
ix
3
Y
iz
Z
± ix
X
ix
4
B. CCII in Practice
Nevertheless, a practical implementation of the CCII can never be ideal. The
input resistance Z y at terminal Y and the output resistance Z z at terminal Z may not
be infinite, the input resistance Z x at terminal X may not be zero, and the voltage gain
and current gain may not be unity. In order to optimize the design for high-frequency
operation, it is necessary to consider a more realistic model for the CCII. In Fig. 4, a
widely used equivalent circuit is shown to describe the conveyor analytically at high
frequency [6, 9, 10].
Voltage Current
Ideal CCII follower
follower
i y (t ) iz (t )
Y iz' Z
Y’ Z’
vy (t) X’ vz (t)
Ry Cy Rz CZ
ix'
Rx
ix (t )
X
vx (t )
5
C. Translinear Implementation of CCII+
The circuit, shown in Fig. 5 [11], uses a mixed translinear cell between terminal Y
and X, which is biased by I o . Output Z, which duplicates the current flowing through
terminal X, is realized in a conventional manner, using two complementary mirrors.
The input cell, with mixed translinear loop, contains two PNP and two NPN
transistors. It is characterized by the translinear relationship between collector currents
of these transistors [11]:
I c1 I c3 = I c 2 I c 4 (2)
I c 2 (t )
V XY (t ) = −VT log (3)
Io
where VT ≅ kT / q ≅ 26mV at 27℃is the thermal voltage. The relationship Eq. (2)
allows, in the particular case of the loop shown in Fig. 5 (i.e., for Ic1 = I c 3 ≅ I o ), to
calculate the expressions for the currents Ic 2 (t ) and Ic 4 (t ) . They are given by [11]
I c 2 (t ) =
1 2
(i x (t ) + 4 I 02 ) 1
2
− i x (t ) (4)
2
I c 4 (t ) = ( ix (t ) + 4 I 02 ) 2 + ix (t )
1 2 1
(5)
2
Now, with the assumption, ix (t ) << 2 I o , Eq. (3) and Eq. (4) lead to
VT
V XY (t ) = ix (t ) (6)
2Io
The relationship shows that the output small signal resistance of the equivalent
voltage follower is
R X = VT / 2I o (7)
6
V+
Io Q5 Q6
Q1 Q2
ix (t )
Y X Z
Q3 Q4
Io
Q7 Q8
V−
7
D. Previous Current Controlled Conveyors
The schematic of the CCCII+ deduced from Fig.5 implemented by BJT [5, 12] and
BiCMOS [6, 8] are shown in Fig. 6. Two current mirrors (transistor Q5 to Q7 and
Q10 , Q11 ) allow the translinear loop to be biased by the current Io . Note that the
MOS transistors in Fig. 6(b) are used for the biasing to minimize noise, the main
contribution in noise coming from the current mirrors.
In this paper, we will show that it is possible to take advantage of this parasitic
resistance on terminal X of CCCII because its value depends on the bias current of the
conveyor. Thus the CCCIIs allow current conveyor applications to be extended to the
domain of electronically adjustable functions.
From Eq. (7), Rx can be controlled by Io . This property can be applied for
some useful applications [12] such as: (1) controllable voltage-current conversion (see
Fig. 7), (2) negative current controlled resistance (Fig. 8), and they are used in our
design of a bandpass filter.
(1) Controllable voltage-current conversion
When the terminal Y of the CCCII+ is grounded and terminal X constitutes the
input of the circuit, the output current I z (t ) = ix (t) is then given by
1
I out (t ) = V in (t ) (8)
Rx
Its value is therefore controllable by the bias current Io . The input resistance of this
circuit, seen from terminal X is equal to Rx .
(2) Negative current controlled resistance
The circuit represented in Fig. 8 simulates a grounded negative resistance which
value: Z in = − Rx is current controlled, and we will discuss it in Section IV-C.
8
V+
Q10 Q11 Q8 Q9
Q1 Q2
Y i y (t ) ix (t ) X iz (t ) Z
vy (t) vx (t ) vz (t)
Q3 Q4
Io
Q6
Q5 Q7 Q12 Q13
V−
(a)
V+
Q10 Q11 Q13 Q12
Q9 Q1 Q2
Y i y (t ) ix (t ) X iz (t ) Z
vy (t) vx (t ) vz (t)
Q3 Q4
Q8
Io
Q6
Q5 Q7 Q15 Q14
V−
(b)
9
Io
ix (t ) CCCII+
iz (t ) = I out
X Z
+
Vin (t ) Y
Io
CCCII+
iz (t )
Input
Y Z
Z in
X
ix (t )
10
III. CMOS Current Controlled Conveyor
In this section we will describe our design of a CMOS current controlled conveyor
and show the simulation results.
The circuit shown in Fig. 9(a) is similar to the translinear implementation of the
CCCII+ shown in Fig. 6. The input cell, M1-M4, contains two N-MOS and two P-
MOS transistors, and the voltage at terminal X follows the voltage supplied at terminal
Y. The transistors M5~M11 form a controllable bias circuit. Two complementary
current mirrors M12-M13, M14-M15 make the current flowing through terminal Z
duplicates the current flowing through the terminal X. The transistors M16-M17 and
M18-M19 improve the input impedance Ry and output impedance Rz , respectively.
Fig. 9(b) presents the equivalent model of the current conveyor giving the input and
output impedance of each terminal, and Fig. 9(c) shows the equivalent circuit between
terminal Y and X.
1
Rx = (9)
g m2 + g m4
Assume P-MOS and N-MOS transistors are matched. Including all the parasitics
in terminal X, the input impedance Z x is
1 s (C gs 1 + C gs 2 ) + g m1
Zx =
2 (sC gs 1 + g m1 )(sC gs 2 + g m 2 )
(10)
11
V+
M10 M11 M13 M12
Va M16 Vc M18
M9
M1 M2
Y i y (t ) ix (t ) X iz (t ) Z
vy (t) vx (t ) vz (t)
M3 M4
Io M8
Vb M17 Vd M19
M5 M6 M7 M14 M15
V−
(a)
Zy iz
Z
Zz
Ai ix
ix Zx
X
Av v y
(b)
12
Voltage follower
Rx
Y X' ix (t ) X
Av
vy (t) vx' (t ) vx (t )
(c)
ix
Lx
Zx
Cx Rxb
Rxa
(d)
Fig. 9 CMOS current controlled conveyor (CCCII+) (c) Equivalent circuit between
Y and X, (d) Practical circuit of terminal X including parasitic elements
13
Expressions of Rxa and Rxb are
1 (C gs1 + C gs 2 ) 2
R xa =
2 g m 2 (C gs 1 + C gs 2 )2 − (g m1C gs 2 + g m 2 C gs 1 )(C gs 1 + C gs 2 ) + C gs 1C gs 2 g m1
(11)
1 (C gs1 + C gs 2 ) 2
R xb =
2 (g m1 C gs 2 + g m 2 C gs 1 )(C gs 1 + C gs 2 ) − g m1 C gs 1 C gs 2
(12)
1 C gs1 + C gs 2
Lx = R xa (13)
2 g m1
C gs 1C gs 2
Cx = 2 (14)
C gs 1 + C gs 2
B. Simulation Results
In this design, the bias current I0 is equal to 100µA using ±2.5V power supply
voltages, and Table I gives the transistor design parameters. Fig. 10 shows the
voltage transfer characteristic Av (= vx / v y ) with an open circuit node X and a
grounded node Z. The 3dB cutoff frequency is 950MHz, and the voltage gain at low
frequency is around 0.973. Fig. 10 also shows the current transfer characteristic Ai
(= iz / ix ) when nodes Y and Z are grounded. Its 3dB bandwidth is about 380MHz, and
the gain of the current transfer is 0.927. The simulated impedance Z x is shown in
Fig. 11. The calculated value of parasitic elements ( Rxa = 2.25KΩ, Rxb = 445Ω, Lx
= 0.66μH, and C x = 0.18pF) are very approximate to the simulated curve. Table II
gives the simulation results.
Table III shows the comparison of the BJT [12], BiCMOS [8] and CMOS
implementations. In this table, I0 is equal to 50µA and supply voltages are ±2.5V.
14
TABLE I
TRANSISTOR DESIGN PARAMETERS
TABLE II
BASIC CHARACTERISTICS OF THE CCCII+ (CMOS),
I0 = 100μA, ±2.5V SUPPLY VOLTAGE
15
TABLE III
BASIC CHARACTERICTICS OF THE CCCII+
I0 = 50 µA, ±2.5V SUPPLY VOLTAGE
16
Voltage gain
Current gain
0
Voltage gain Av, Current gain Ai (dB)
-10
-20
-30
-40
0 1 2 3 4 5 6 7 8 9 10
10 10 10 10 10 10 10 10 10 10 10
Frequency (Hz)
405
Simulated
X-input impedance Zx (Ω )
400
Calculated
395
390
385
380
375
370
6 7 8 9
10 10 10 10
Frequency (Hz)
17
Since the circuit is current controlled, we are interested in the characteristics by
varying the value of the controlled current I o . Fig. 12 presents the variation of the
intrinsic Z x (see Fig. 9(d)) as a function of the dc bias current I o . Fig. 13 gives the
values Rx obtained from SPICE simulations with the CCCII+, as well as the
theoretical ones calculated from Eq. (9). As shown, the simulated values of the
controlled resistance are in good agreement with theoretical ones. Deviations less
then 10% were obtained in the range 10µA~500µA for I o . The most important
deviation, which appear either for the very low or very high values of I o principally
come from the difference that exist between I o and the current of transistors M1 and
M3. These current deviations result from the current gains of transistors operating for
very high or very low values of currents. When the bias current I o is less then 10µA,
the deviation is more then 10%; and when I o is more then 500µA, the variation of
parasitic resistance Rx is not evident, so the range of the controlled current is defined
from 10µA~500µA in practice. Simulation results show that its value is tunable from
172Ω to 1.65KΩ.
The variation of voltage gain and current gain under the bias current I o can be seen
in Fig. 14. On the range from 10µA~500µA, the gain of voltage follower and current
follower are about unity. Fig. 15 presents the 3dB cutoff frequency of the voltage
follower and current follower, obtained by varying I o . The bandwidth of Av and Ai
can be up to 2.1GHz and 640MHz respectively when I o = 500µA.
18
Rxa (Ω ) 8.0k
6.0k
4.0k
2.0k
(a)
2000
1600
(Ω )
1200
Rxb
800
400
(b)
19
10
8
Lx (µH)
0
0 100 200 300 400 500
(c)
0.200
0.195
0.190
Cx (pF)
0.185
0.180
0.175
0 100 200 300 400 500
(d)
20
1800
1600 Simulated
Theoretical
1400
Resistance Rx (Ω )
1200
1000
800
600
400
200
0
0 100 200 300 400 500
21
2.0
1.0
0.5
0.0
0 100 200 300 400 500
Fig. 14 The variation of voltage gain and current gain under the bias current I o
Voltage follower
2000
Current follower
3dB bandwidth (MHz)
1500
1000
500
0
0 100 200 300 400 500
Fig. 15 The 3dB bandwidth of voltage follower and current follower, obtained by
varying I o
22
IV. Second Order Bandpass Filter
The basic idea of a tunable bandpass filter is derived from a parallel RLC resonant
circuit, which resonant frequency and Q-factor can be tuned by a variable inductance
and a variable resistance. The variable inductance is implemented with two CCCII+s,
and a controlled negative impedance converter (NIC) in parallel with the RLC circuit
makes the resistance tunable.
The typically parallel RLC tank circuit is shown in Fig.16. Its resonant
frequency is
1
ω0 = (15)
LC
R C
Q= = ω0 RC = R (16)
ω0 L L
From Eq. (15) and Eq. (16), if the inductance is variable the ω0 can be tuned; and also
if the resistance is variable the Q can be tuned.
Iin R C L Vout
23
B. Current-Controlled Active Inductance
Consider the circuit connection shown in Fig. 17(a), where the CCII+s are ideal.
The equivalent circuit derived from this connection is shown in Fig. 17(b), where the
equivalent inductance Leq is
Leq = R x1 R x 2 C1 (17)
The input resistances of practical CCII+s can take the place of the external resistances,
and these resistances are controllable as practical CCII+s are replaced by the CCCII+s.
The circuit is shown in Fig. 17(c) [6, 8].
Rx1
CCII+ CCII+
Input Iin (t ) Rx 2
X2 Y2 Z1 X1
Z2 Y1
Z in
Vin (t ) C1
(a)
Z in
Leq Rx1 Rx 2
(b)
Fig.17 Nonideal inductance: (a) Implementation from two CCII+ and two
external resistances (b) Electrical equivalent impedance
24
Io 2 Io1
CCCII+ CCCII+
Iin (t )
Input X2 Y2 Z1 X1
Z2 Y1
Vin (t ) Z in C1
(c)
25
C. Negative Impedance Converter
The parallel resistances Rx s in Fig. 17(b) usually reduce the Q-factor. In order to
increase the Q-factor, we need to increase the resistance R in Fig. 16. A simple way to
increase R is using negative resistance in parallel with Rx s, The negative resistance
can be implemented with a CCCII+ connected as Fig. 18 [6, 8,12].
To cancel the effect of the parasitic shunt resistors, a negative resistor in parallel
with the inductance is needed. The practical current conveyor can be configured in
such a way to perform the function of the negative impedance converter (NIC), which
is useful for implementation of the filter. The circuit represented in Fig. 18 simulates
a grounded negative resistance which value: Z in = − R x is current controlled. Since
the current through the input node is iz + iy = iz = ix , and vx = v y , the input impedance
Z in = v x /(−ix ) = − Rx , that the circuit in Fig. 18 is a NIC.
Io
CCCII+
Input Y Z
iz (t )
Z in
X
ix (t )
Input
Z in − Rx
26
D. CCCII+ Bandpass Filter Design
Rx1R x 2C1
s
I out
(s ) = R x4
(18)
I in R R C
1 + x1 x 2 1 s + (R x1 Rx 2C1C2 )s 2
Req
and
1 1 1 1 1
= + + − (19)
R eq R x1 R x 2 R x 4 R x 3
1
ω0 = (20)
R x1 R x 2 C1C 2
R eq C2
Q= (21)
R x1 R x 2 C1
2. fo Tuning
From Eq. (20) and Eq. (21) it is obvious that one can modify the center frequency
fo and the Q -factor independently of each other, the way to tune the center frequency
of the filter is to vary the value of Rx1 and Rx 2 . Referring to Eq. (20), an appropriate
choice to simplify the tuning of fo is to use the same current I o for Io1 and Io 2 .
Then it follows that Rx1 = Rx 2 , and we can modify fo by varying this current I o
keeping the other currents ( Io 3 and Io 4 ) fixed.
27
3. Q Tuning
From Eq. (19) and Eq. (21) we can see that Q can be tuned either from Io 3 or Io 4
(see Fig. 19) without affecting the value of fo and with a theoretical possibility of
making Q infinite if Req in Eq. (19) tends to infinite. For example, let the first,
second and forth conveyors have the same bias current I o (i.e., Rx1 = Rx 2 = R x 4 = R x ),
when the input impedance of the third conveyor (NIC) is Rx 3 = − Rx / 3 , the Q is
theoreticaly infinite. Thus when the bias current I o and Io 4 are fixed, the Q-factor
can be modified just only by varying the current Io 3 .
Io1 Io 2 Io 3
Iin (t)
C2 C1
Io 4
Io u t (t )
28
E. Practical Inductance, NIC and Bandpass Filter
However, the parasitic effects which can not be ignored will influence the
theoretical values. The parasitics at node X are more complex (see Section III and Fig.
9(d)), and there is a parasitic resistance R p = R y 2 // R z1 in parallel with C1 , also there
is an additional resistance rp = ( Rx1 Rx 2 ) / RP appears in series with Leq . When all the
parasitics of the controlled conveyors (i.e., parasitic impedance: ( Ry // C y ) , ( Rz // C z ) ,
and nonideal values of the voltage and current transfer Av and Ai ) are taken into
account, rearrange the above equations, we can get that [6]
Leq = R x1 R x 2 C1 / Av Ai (22)
r p = ( R x1 R x 2 ) / Av Ai R P (23)
The detail equivalent circuit for this controlled inductance is shown in Fig. 20(a).
Note that the input impedance Z in of the NIC shown in Fig. 18 is now replace − Rx
with − Av Ai Zx , and the transfer functions of the practical bandpass filter are [6]
R x1 R x 2 C1
s
I out
(s) = A R
v x4
(24)
I in R x1 R x 2 C 1 R x1 R x 2 C1C 2' 2
1+ s + s
Av Ai R eq Av Ai
where
1 1 1 1 A A
= + + − v i (26)
R eq R x1 R x 2 R x 4 Rx3
C1 = C z1 + C y 2 (27)
C 2' = C 2 + C y 3 + C z 3 (28)
29
Their characteristic parameters are given as
Av Ai
ω0 = (29)
R x1 R x 2 C1C 2'
Req C 2'
Q= Av Ai (30)
R x1 R x 2 C1
Leq
Rxa / 2
2Cx Rxb / 2
rp Lx / 2
(a)
Leq
2C x Rxb / 2
rp
(b)
30
Leq C x' Rx' − Rxb 3
Fig. 21 The input impedance see from the bandpass filter’s input
31
F. Simulation Results
Fig. 22(a) shows the value of this simulated inductance, using the CCCII+ with
100µA bias current and ±2.5V voltage sources. The circuit in Fig. 17(c) was
designed with Io1 = I o 2 = 100µA, and the following parameters are extracted from the
design: C1 = 0.42pF, Rxa1,2 = 2.25kΩ, Rxb1,2 = 445Ω, the parasitic inductance Lx1,2 =
0.66µH, and the parasitic capacitor Cx1,2 = 0.18pF. Fig. 22(b) compares the impedance
variation of this circuit (Fig. 17(c)) in parallel with the value of (− Z x 2) , and the
( )
theoretical impedance rp + sLeq . We can see a good agreement between both curves.
The values of Leq and rp extracted from the simulations: 0.9µH and 2.1Ω were found
in good accordance with theoretical ones (0.92µH and 3.2Ω, respectively) from Eq. (22)
and Eq. (23).
The capacitor C 2 is always 2.3pF in our tunable bandpass filter design. Fig. 23
shows the tunability of the center frequency with the bias current I o (from Eq. (29)
and Eq. (30)). In this figure, we vary the current I o (50µA, 100µA, and 200µA) with
Io 3 = Io 4 = 350 µA. The higher the bias current I o , the higher the center frequency
fo . Fig. 24 shows the tunability of the Q -factor with the current Io 3 (Eq. (26) and
Eq. (30)). The controlled current Io 3 is varier as 300µA, 330µA, 350µA, and 360µA
with Io = I o 4 = 100 µA. From this simulation, it can be seen that Q-tuning is very
sensitive. Even with a small change of Io 3 , the Q-factor changes largely. Besides,
we find that not only the Q-factor but also fo is tuned. This is because the parasitic
capacitors in parallel with C 2 which influence the center frequency (see Eq. (28)) are
also changed.
Fig. 25 indicates that this configuration is quite useful for an IF bandpass filter which
center frequency is from 200MHz to 300MHz which is within the IF design
specification of modern wireless mobile phone. The Q-factor in this configuration is
up to 800. Table IV lists the comparison among the tunable bandpass filter
implemented with BiCMOS [8] and CMOS.
Table IV
BiCMOS CMOS
fo 30 MHz ~ 120MHz 55 MHz ~ 410MHz
Q 1 ~ 140 1~800
32
500
(Ω )
Simulated inductance ZL
400
300
200
100
0
5 6 7 8 9
10 10 10 10 10
Frequency (Hz)
(a)
Z
3
10
Z in // − X
2
(r p + sLeq )
Impedance (Ω )
2
10
1
10
0
10
5 6 7 8 9
10 10 10 10 10
Frequency (Hz)
(b)
33
I o = 50µA
10
I o =100µA
5 I o = 200µA
Gain magnitude (dB)
-5
-10
-15
-20
8 8 8 8 8 8 8
1.0x10 1.5x10 2.0x10 2.5x10 3.0x10 3.5x10 4.0x10
Frequency (Hz)
50
Io 3 =300µA
Io 3 =330µA
40 Io 3 =350µA
Io 3 =360µA
Gain magnitude (dB)
30
20
10
0
8 8 8 8 8
2.0x10 2.1x10 2.2x10 2.3x10 2.4x10
Frequency (Hz)
Fig. 24 Second order bandpass filter: Q tuning. Io 3 = 300µA, 330µA, 350µA and
360µA, Io = I o 4 = 100µA and C 2 = 2.3pF
34
V. Conclusion
The CMOS CCCII and the tunable bandpass IF filter based on the CCCII are
successfully developed. Simulations show that they are suitable for the application
around 200MHz~300MHz which is the specification of current wireless mobile phone.
35
References
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Block’’, Proc. IEEE, Vol. 56, pp. 1368-1369, Aug. 1968.
[2] K. C. Smith and A. Sedra, “A Second Generation Current Conveyor and its
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Tutorials, New York, IEEE Press, c1996.
[4] A. S. Sedra and G. W. Roberts, ‘’Current Conveyor Theory And Practice’’, Chapter
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[12] Alain Fabre, Senior Member, ‘’ High Frequency Applications Based on a New
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[13] Christophe Per mont, Nacer Abouchi, Richard Grisel, and J. P. Chante, “A Current
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36