16×16 fast signed multiplier using Booth and

Vedic architecture
Cite as: AIP Conference Proceedings 2045, 020085 (2018); https://doi.org/10.1063/1.5080898
Published Online: 06 December 2018

L. Z. Shing, R. Hussin, A. Kamarudin, S. N. Mohyar, S. Taking, M. H. A. Aziz, and N. Ahmad

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© 2018 Author(s).
 16X16 Fast Signed Multiplier Using Booth and Vedic
Architecture
L Z Shinga), R Hussin, A Kamarudin, S N Mohyar, S Taking, M H A Aziz and N
Ahmad

School of Microelectronic Engineering, Universiti Malaysia Perlis (UniMAP), Kampus Pauh Putra, 02600, Arau,
Perlis, Malaysia.
a)
Corresponding author: lzshing_pls@yahoo.com

Abstract.This paper present the new 16x16 signed multiplier design using Booth architecture and Vedic
architecture. The Booth architecture is based on Radix-4 Booth multiplier which reduces the number of partial
product generated into almost half. Vedic architecture has advantages in partial product generation and addition
which are done concurrently [1]. In order to improved the performance of signed muliplier, the 16x16 signed
multiplicand and multiplier is partition by using the 16x16 Vedic architecture (8 bits per block). Radix-4 Booth
multiplier is used to multiply each block as in 16x16 Vedic architecture. This new 16x16 signed multiplier is
taking advantages on Booth multiplier approach on top of Vedic achitecture. It has simple architecture
compared to normal 16x16 Radix-4 Booth multiplier. This new signed multiplier uses Ripple Carry Adder
(RCA) or Carry Look-Ahead Adder (CLA) to add up the generated partial product. This new 16x16 signed
multiplier has improved the performance by reducing the total propagation delay. The new 16x16 signed
multiplier design 1 (RCA) and design 2 (CLA) are 33.4% and 35.6% faster compared to the 16x16 Radix-4
Booth multiplier. It is because the partial product generation by Radix-4 Booth multiplier and partial product
addition are done concurrently using Vedic architecture.

INTRODUCTION
Digital Signal Processing (DSP) has increased the demand for fast and efficient processor unit due to the rapid
develop in technology. Performance of a processor rely mainly on the performance of the multiplier. High performance
processor nowadays concern in high speed, low area and low power consumption multiplier. These three main trade-
off parameters are the vital challenge in designing the multiplier for Very Large Scale Integration (VLSI) design.

There are two types of multiplier which are signed multiplier and unsigned multiplier. This propose design is focus
on the signed multiplication. In order to improve the performance of signed multiplication, Radix-4 Booth multiplier
architecture and Vedic multiplier architecture is used to implement the new 16x16 combined Booth and Vedic
multiplier. Radix-4 Booth multiplier reduces the number of partial product into almost half and Vedic architecture
partition the signed input for fast multiplication.

Besides, the partial product addition play an important role to improve the performance of a multiplier. The first
new design uses a simple multiple bit adder architecture which is Ripple Carry Adder (RCA). The second design uses
a fast carry propagation multiple bit adder which is Carry Look-Ahead Adder (CLA). The important and challenging
part in the partial product addition is the signed extension of the partial product. Hence, the signed extension in new
signed multiplier design will take in consideration.

4th Electronic and Green Materials International Conference 2018 (EGM 2018)
AIP Conf. Proc. 2045, 020085-1–020085-8; https://doi.org/10.1063/1.5080898
Published by AIP Publishing. 978-0-7354-1771-7/$30.00

020085-1
 Signed Number
The commonly used numbers in mathematics are unsigned number which are positive numbers. However, signed
numbers (including negative numbers) are considering in real life. When dealing with negative binary numbers, the
most significant bit is used to indicate the sign of the number. For 8 bits unsigned number, it has ranging from 0 to
255, however, signed number has the ranging from -128 to 127. Two’s complement method is use to represent the
negative binary number by inverting all the bits and then add one to the result. The additional one bit is used to make
sure there is only one zero which is represented as 00000000 (8 bits). Figure 1 shows the 8 bits signed/ unsigned
decodes to decimal form.

FIGURE 1. 8 bits signed/ unsigned decodes to decimal form

Booth Multiplier
Radix-4 Booth multiplier is a multiplier uses to multiply signed integer. Basically, Booth multiplier consists of
three important components which are Booth Encoder (BE), Booth Decoder and multiple bit partial product adder [2].
Booth Encoder system is used to reduce the number of partial product [3]. Figure 2 shows the Radix-4 Booth Encoder
encodes 3 bits of multiplier into 1 bit. Figure 3 shows the Booth Decoder (partial product generator) architecture which
is used to generate the partial product for each encoded bit.

FIGURE 2. Radix-4 Boooth Encoder system FIGURE 3. Booth Decoder architecture

Vedic Multiplier
Vedic multiplier is a multiplier uses the Vertically and Crosswise technique based on Urdhva- Tiryagbhyam sutra
in Vedas [4]. This Vedic multiplier focus on binary number multiplication and it is used to perform unsigned
multiplication. The partial product of Vedic multiplier is generated by using AND gate before perform the addition of
partial product using adder. Figure 4 shows the 8 bits x 8 bits partial product generated using AND gates. 2x2 Vedic
multiplier architecture is the basic architecture use to design a higher bit multiplier. Figure 5 shows the 16x16 Vedic
multiplier architecture designed by S.P Pohokar [5]. It uses Carry Save Adder (CSA) to add up the partial product.

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 FIGURE 4. Partial product generated using AND gate FIGURE 5. 16x16 Vedic multiplier [5]

Types of Adders
Adder is a digital circuit that mostly used in arithmetic logic unit (ALU) to perform addition of numbers. Adder
has been implemented and cascaded with difference circuit to perform multiple bit addition. The adder is operating
for binary number. The typically used adders such as half adder and full adder are the basic adder used to cascade for
multiple bit addition. Fig. 6 shows the Ripple Carry Adder (RCA) architecture by cascading the full adders [6]. Figure
7 shows the full adder with Sum, Propagate (P) and Generate (G) outputs [6]. This adder is specially design for Carry
Look-Ahead Adder (CLA). Fig. 8 shows the 16 bits Carry Look-Ahead Adder (CLA) architecture. 16 bits CLA is
designed by using four 4 bits CLA and a CLA logic. CLA logic speed up the propagation of carry.

FIGURE 7. Full adder with Sum, Propagate (P) and

FIGURE 6. Ripple Carry Adder (RCA) architecture [6]
Generate (G) outputs

FIGURE 8. 16 bits Carry Look-Ahead Adder (CLA) architecture

METHODOLOGY
This project is design using Altera Quartus II software. Before start with the new design, the reference design for
16x16 Booth multiplier is designed prior for comparison purpose. Zhou Shun’s 16x16 Booth multiplier is used as a
reference design [7]. The new design is designed by combining the Booth architecture and Vedic architecture. The

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new architecture partition each of the signed value into two block and multiply using Vedic algorithm. 8x8 Booth
multiplier is used to multiply the signed value in each block. Figure 9 shows the first design of 16x16 Combined
Booth-Vedic multiplier architecture. Figure 10 shows the Vedic multiplication overview to clearly define the
placement of each block (considering signed value and unsigned value). This first design uses the RCA to add up the
generated partial products. The second design is a modification from the first design by modifying the RCA to CLA
in order to speed up the addition of partial products. The 16x16 Combined Booth-Vedic multiplier is designed by
using four 8x8 Booth multiplier and three 16 bits RCA.

FIGURE 9. 16x16 Combined Booth-Vedic multiplier FIGURE 10. Vedic multiplication overview
architecture (RCA)

Modified 8x8 Booth Multiplier

There are four difference condition for the signed multiplication using Vedic architecture. This is the important
section to make sure the multiplication is correct. Since the 16 bits input is partition into two block, the upper part is
considering the signed value (MSB in this block indicating sign bit) and the lower part is considering the unsigned
value (MSB in this block is not indicating sign bit) as shown in Fig. 1.

Hence, the 8x8 Booth multiplier is modified in order to make sure the signed multiplication for each block is
correct. Figure 11 shows the 8x8 Radix-4 Booth multiplier architecture which used to multiply two signed numbers
[8]. The other three difference Booth multiplier is modified to multiply signed multiplicand with unsigned multiplier,
unsigned multiplicand with signed multiplier and unsigned multiplicand with unsigned multiplier. The modified 8x8
Booth multiplier (unsigned x signed) has the same architecture as the normal 8x8 Booth multiplier. However, the
difference is in term of decoder architecture.

The modified 8x8 Booth multiplier (signed x unsigned) and modified 8x8 Booth multiplier (unsigned x unsigned)
have different architecture compared to the normal 8x8 Booth multiplier. Both modified 8x8 Booth multiplier (signed
x unsigned) and (unsigned x unsigned) have one more decoder compared to normal 8x8 Booth multiplier. The
modified 8x8 Booth multiplier (signed x unsigned) and (unsigned x unsigned) have an additional multiple bit adder
(12 bits RCA or CLA) due to the additional partial product. All the 8x8 Booth multiplier has simplified the sign
extension to make the circuit simplify [2][9].

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 FIGURE 12. Modified 8x8 Booth multiplier (unsigned x
FIGURE 11. 8x8 Radix-4 Booth multiplier architecure
signed) architecture

FIGURE 13. Modified 8x8 Booth multiplier (signed x FIGURE 14. Modified 8x8 Booth multiplier (unsigned x
unsigned) architecture unsigned) architecture

Decoder

Decoder is used to generate the partial product. Decoder decodes the encoder digits with the multiplicand to
generate the partial product. There are two difference decoder for the modified 8x8 Booth multiplier. Figure 15 shows
the 10 bits decoder for the (signed x signed) and (signed x unsigned) multiplier. It decodes the 9 bits multiplicand into
10 bits partial product to make sure the 2’s complement value is generated correctly. The tenth bit is the extension of
the ninth bit. The carry of the decoder is ignored.

FIGURE 15. 10 bits decoder (signed x signed and signed x unsigned) architecture

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 FIGURE 16. 10 bits decoder (unsigned x signed and unsigned x unsigned) architecture

RESULTS AND DISCUSSION

The simulation result for reference design and new design is simulated using Altera Quartus II software. The
multiplier functional is verified before proceed to performance analysis [10].

Functional Verification
The functional verification is an important step to make sure the multiplier circuit perform its function correctly.
The functional verification for the reference design and the new design are the same. The functional verification is
tested for the boundary condition and maximum propagation of carry to make sure the partial product is added
correctly. The 16x16 signed multiplication is verified as in Fig. 17 to Fig. 19. The functional verification for the three
modified 8x8 Booth multiplier are verified as shown in Fig. 20 to Fig. 22.

FIGURE 17. Positive multiplicand (16x16 multiplier)

FIGURE 18. Negative multiplicand

FIGURE 19. Boundary condition

020085-6
 FIGURE 20. 8x8 Booth multiplier (signed x unsigned)

FIGURE 21. 8x8 Booth multiplier (unsigned x signed)

FIGURE 22. 8x8 Booth multiplier (unsigned x unsigned)

Result Analysis
The result for reference design is compared with the two newly designs in term of performance and area [10]. The
worst case total propagation delay (tpd) is used to analyse the performance of the multiplier while the total logic
elements is used to analyse the area consumption of the multiplier. Table 1 shows the tabulated result for reference
design and two new designs.

Table 1. Comparison of performance among designs

Worst case Delay, % improvement Total logic % improvement
Design
tpd (ns) in tpd elements (units) in area
Reference 60.720 - 569 -
Booth-Vedic Design 1 40.431 33.4 737 -29.5
Booth-Vedic Design 2 39.095 35.6 772 -35.7

CONCLUSION
A fast signed multiplier has been developed using the Booth architecture and Vedic architecture. The objective of
developing the fast signed multiplier has achieved with 40.431 ns and 39.095 ns for the 16x16 Booth-Vedic multiplier
design 1 and design 2 respectively. These two new designs have an improvement of 33.4% and 35.6% in term of speed
compared to the reference design (16x16 Radix-4 Booth multiplier). The new design has disadvantages in area
consumption but it has a compact and simple architecture compared to the reference design.

ACKNOWLEDGMENTS
The authors would like to thanks to the Universiti Malaysia Perlis (UniMAP) for giving permission and fund thru
Tabung Penyelidikan Jangka Pendek under a grant number of 9009-00025 to publish this paper

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