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Contents

1. Features: .......................................................................................................................... 2
2. Block Diagram of 8051: ............................................................................................. 3
3. PIN Diagram:................................................................................................................... 6
4. 8051 Oscillator & Timings: ..................................................................................... 7
5. Program Counter and Data Pointers: ................................................................... 8
6. A & B CPU Registers: ................................................................................................. 8
7. Flags and PSW: .............................................................................................................. 8
8. Internal Ram Interfacing:.......................................................................................... 9
9. Stack Pointer And Stack:........................................................................................ 10
10. Internal ROM: ............................................................................................................... 10
11. Ports: ................................................................................................................................ 10
12. SFR (Special Function Registers): ...................................................................... 13

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8051 MICROCONTROLLER

1. Features:
 128 bytes of RAM (On Chip Data Memory)
 4 KB of ROM (On Chip Program Memory)
 2 Timers (Each of 16 bit)
 1 Serial Port
 4 I/O Ports (8 bits wide)
 4 Register Banks
 32 General Purpose Registers ( Each of 8 bit)
 128 User defined software flags
 8 bit bidirectional data bus
 16 bit unidirectional address bus
 16 bit program counter and data pointer
 5 Interrupt Sources
a) 2 Internal
b) 2 External
c) 1 Serial Port Interrupt

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2. Block Diagram of 8051:

The various blocks explained below:


1. Bus – Control: 2 buses for data transfer-
1. Data Bus:
8 – Bit bus, which acts as electronic channel for
transfer of data.
2. Address Bus:
16 – Bit bus, which transfers information and not
data.
2. 4 General Purpose Parallel I/O Ports:
All ports are 8 – bit wide for data identification.
1. Port 0:
No external memory is present. It acts as general I/O Port. If external
memory is present, then it is capable of utilising in a dual mode with the
help of multiplexed address and data bus.
2. Port 1:
It is only for I/O Operation and does not perform dual function.
3. Port 2:
Similar to Port 1, can be used as General purpose I/O Port.

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4. Port 3:
Dedicated I/O Port.

3. Timer and Counters:


The internal operation can be synchronized by using a clock circuit with
the help of 2 pins connected to oscillator named XTAL1, XTAL2. The
timers and counters has 4 additional pins on it:-
a) EA – External Access
b) PSEN – Program Storage Enable
c) ALE – Address Latch Enable
d) RST – Reset

4. Internal RAM and ROM:


1. ROM has:
a) Permanent storage of data
b) Non- Volatile
c) A code of 4 KB memory is stored On Chip ROM
d) Own program memory
e) Can add program memory of 64 bytes

2. RAM has:
a) Volatile
b) 128 bytes of Internal RAM
c) Divided into 32 Working Registers (divided into 4 banks of
8 bits each)

5. Serial Ports:
The Serial Ports available are RxD and TxD, which receive and transfer
data according to control signal:
a) SBUF (Serial Port Data Buffer): It holds the data.
b) SCON (Serial Control Register): It manages data
communication.

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c) PCON (Power Control Register): It manages data transfer
rates. It has further 4 programmable modes:
1. Serial Data Mode 0: Shift Register Mode.
2. Serial Data Mode1: Standard UART Mode (Serial
Communication).
3. Serial Data Mode 2: Multiprocessor Mode.
4. Serial Data Mode 3: Multiprocessor Mode.

6. Interrupt Control:
An Interrupt can come from internal/external source; it suspends the
microcontroller for a while. The 2 ways of giving instructions of interrupt
to microcontrollers are:
a) By sending software instructions
b) By sending hardware instructions
 Note: 5 sources of interrupts in 8051 are:
1. Two External Interrupt Sources- Connected through
INT0 and INT1.
2. Two Internal Interrupt Sources- Timer Flag 0, Timer
Flag 1.
3. One Serial Port Interrupt

7. CPU (Central Processing Unit):


It connects system buses to all support.
Arithmetic calculations, Logic calculations, Control Signal Generation.

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3. PIN Diagram:

1. Port 1 (1-8): This is an I/O Port only.


2. Pin 9 (RST): It is to reset the micro-controller to its initial position.
3. Port 3 (10-17): It acts as I/O Port and performs various control
functions.
4. Pin 18-19 (XTAL2, XTAL1): These are used for interfacing with
external crystal for getting the system clock.
5. Pin 20 (GND)
6. Port 2 (21-28): Used for higher order address buses and for I/O
Operations.
7. Pin 29 (PSEN) – Program Store Enable [Flags Used].
8. Pin 30 (ALE) – Address Latch Enable.
9. Pin 31 (EA)- External Access Enable- It is enabling access from
external device or memory interface.
10. Port 0 (32-39): Performs various I/O operations as well as A00-A07
gives the multiplexed address and data bus.

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11. A Controller memory’s Interfacing.

4. 8051 Oscillator & Timings:

 The heart of 8051 is a circuit that generates the clock pulse by


which all internal operations are synchronized. Pin XTAL1, XTAL2
are provided for connecting a resonant network to form an
oscillator. Normally a quartz crystal and capacitor are applied. It
gives maximum frequency of 16MHz to 8051.
 The smallest interval of time required to establish any instruction
causes a machine cycle. A machine cycle is made up of 6 states
therefore a state is the basic time interval for discrete operations
of microcontroller.
 To calculate the time that any particular instruction will take to
execute, we need number of cycles ‘C’ for that instruction.
Time for execution of instruction given by:
𝐶 × 12 𝑑
𝑇(𝑖𝑛𝑠𝑡) =
𝐶𝑟𝑦𝑠𝑡𝑎𝑙 𝐹𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦
 There are 2 ALE pulses per machine cycle. The ALE is mainly for
external memory access and indicates when every byte is fetched;

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therefore, 2 bytes in a single machine cycle can be fetched and
executed in 8051.
 Single byte instructions are not executed in half cycle. However,
single byte throws away the second byte, which is the first byte of
new instruction.

5. Program Counter and Data Pointers:


8051 has 2, 16- bit registers i.e. PC, DPTR.
1. PC (Program Counter): The program instructions are fetched from
location in the memory that are addressed by PC. The program ROM is
from address 0000h to 0FFFh (4k). If external interfacing has to be added
the program counter address from 0000h to FFFFh
 PC is automatically incremented after every instruction
 PC is the only register that does not have internal address.
2. DPTR (Data Pointer): It is made up two 8- bit registers i.e. DPH, DPL. It
is used to furnish memory addresses for external and internal code
access and external data access.

6. A & B CPU Registers:


A stands for Accumulator-
1. It is a part of CPU.
2. No external interfacing can happen without it.
3. No calculations can happen without it.

7. Flags and PSW:


 The Program Status Word (PSW) register is an 8-bit register, also known
as Flag register. It is of 8-bit wide but only 6-bit of it is used. The two unused
bits are user-defined flags. Four of the flags are called conditional flags,
which means that they indicate a condition, which results after an instruction,
is executed. These four are CY (Carry), AC (auxiliary carry), P (parity),
and OV (overflow). The bits RS0 and RS1 are used to change the bank
registers. The following figure shows the program status word register.

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 The PSW Register contains that status bits that reflect the present status of
the CPU.

Bit Symbol Function


7 CY Carry Flag
6 AC Auxillary Carry, used in BCD
5 F0 User Flag 0
4 RS1 Register Bank Select Bit 1
3 RS0 Register Bank Select Bit 0
2 OV Overflow Flag
1 - Reserved
0 P Parity for Accumulator. If A = 1, consider Odd Parity

RS1 RS0 Function

0 0 Register Bank 0

0 1 Register Bank 1

1 0 Register Bank 2

1 1 Register Bank 3

8. Internal Ram Interfacing:


1. 32 bytes 00h to 1Fh make up 32 working registers organised as 4 banks
of 8- bits each. The 4 banks are made up of 8 registers from R0 to R7
having 8- bits each. The bits RS1 and RS0 in PSW determine which bank
is in use. If none of the register bank is selected, then General Purpose
RAM is selected. By default, Bank 0 is selected on Reset.
2. A Bit Addressable area of 16 bytes occupy the RAM from 20h to 2Fh
forming 128 addressable bits. These addressable bits may be specified
by its bit address from 00h to 7Fh.
3. A General Purpose RAM above bit addressable area occupies the
addresses from 30h to 7Fh.

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9. Stack Pointer And Stack:
8- bit Stack Pointer is used to hold an internal RAM address called as TOP of
Stack. The address held in the stack points the location in the internal RAM,
where last byte of data was stored.

10. Internal ROM:


It occupies addresses from 0000h to 0FFFh, address higher than 0FFFh will
fetch the code bytes from external program memory.

11. Ports:
The major feature of microcontroller is versatility built into the O/I structure that
connects 8051 to the outside world. Flexibility of the usage of 40 pins on DIP
(Dual Inline Processor) is another important feature. The functions a pin
performs at any given instant depends firstly on what is physically connected to
it and then on what software commands are used to program the pin. Therefore,
in DIP mode 8051 is capable of yielding 64- bit operation.
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1. Port 0:

1. It may serve as Input or Output or for external memory interfacing when


used together with bi-directional low order addresses and data bus.
When Port 0 is to be used as input, a logic 1 must be written to the
corresponding Port 0 latch by the program. This turns off both
transistors at the output and the pin goes to high impedance state called
as flow.
2. When Port 0 is used as an output, the pi latches which are at 0 logic will
turn on the FET which is grounding the port. All the latches are
programmed to 1 logic and will flow until supply is given through
external pull up registers.
3. When Port 0 is used as an address bus to the external memory, the
internal control signals switch the address lines to the gates of FET. A
logic 1 will appear on upper FET turning lower FET off. With the help of
ALE pulse, the bus is available for data operation from external ports.

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2. Port 1:

1. No Dual Function performed and therefore the output latch is connected


directly to the gate of lower FET.
2. When used as input logic 1 is given to the latch.
3. When used as output logic 0 is given to the latch.

3. Port 2:

1. It may be used as I/O port, similar to port 1. The alternate use Port
2 is to supply higher order address byte in conjunction with Port 0
and a lower order address byte to the external memory.

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4. Port 3:

1. It is an I/O Port similar to Port 1. The I/O function can be


programmed under the control of various Special Function
Register or latch.
2. Note: Each Pin of Port 3 may be individually programmed for I/O
Function or for Special Alternate Function.

12. SFR (Special Function Registers):


In 8051, the operation that do not use 128 bytes RAM address i.e. from 00h to
7Fh are done by specific internal Register called SFR. These have address
usually from 80h to FFh. SFR’s are named in certain opcodes by their functional
name and begin with O Failure to use this numeric convention will result in an
assembler error when programmed.
S.No. Name Function Internal RAM Address
[Hex]
1 A Accumulator OE0
2 B Arithmetic OF0
3 DPH Additional External Memory 83
4 DPL Additional External Memory 82
5 IE Interrupt Enable Control OA8

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S.No. Name Function Internal RAM Address
[Hex]
6 IP Interrupt Priority OB8
7 P0 I/O Port Latch 80
8 P1 I/O Port Latch 90
9 P2 I/O Port Latch A0
10 P3 I/O Port Latch OB0
11 PCON Power Control 87
12 PSW Program Status Word OD0
13 SCON Serial Port Control 98
14 SBUF Serial Port Data Buffer 99
15 SP Stack Pointer 81
16 TMOD Timer 1 Counter Mode Control 89
17 TCON Timer 1 Counter Control 88

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