Memoria de Pic 18f Family

Section 7.
Memory Organization
HIGHLIGHTS
This section of the manual contains the following major topics:
7.1 Introduction .................................................................................................................... 7-2
7.2 Program Memory ........................................................................................................... 7-3
7.3 Program Counter (PC) ................................................................................................... 7-6
7.4 Lookup Tables................................................................................................................ 7-9
7.5 Stack ............................................................................................................................ 7-12
7.6 Data Memory Organization.......................................................................................... 7-13
7.7 Return Address Stack .................................................................................................. 7-17
7.8 Initialization .................................................................................................................. 7-23
7.9 Design Tips .................................................................................................................. 7-24
7.10 Related Application Notes............................................................................................ 7-25
7.11 Revision History ........................................................................................................... 7-26
PIC18C Reference Manual

DS39507A-page 7-2 2000 Microchip Technology Inc.
7.1 Introduction
There are two memory blocks in the memory map; program memory and data memory. Each
block has its own bus, so that access to each block can occur during the same instruction cycle.
The data memory can further be broken down into General Purpose RAM and the Special Function
Registers (SFRs). The operation of the SFRs that control the “core” are described here. The
SFRs used to control the peripheral modules are described in the section discussing each individual
peripheral module.
In addition, there are other registers used that are neither part of the program nor data memory
spaces. These registers are not directly addressable and include:
• return address stack
• fast return stack
Table 7-1 shows the program memory space used depending on the memory allocated, and
Table 7-2 shows the data memory space used.
Table 7-1: PIC18CXXX Program
Memory Ranges
Table 7-2: PIC18CXXX Data
Memory Ranges
Program
Memory
Program Memory
Address Range
Data Memory Banks
1K x 8 0000h - 3FFh 64 0, 15
2K x 8 0000h - 7FFh 128 0, 15
4K x 8 0000h - FFFh 256 0, 15
8K x 8 0000h - 1FFFh 512 0-1, 15
12K x 8 0000h - 2FFFh 640 0-2, 15
16K x 8 0000h - 3FFFh 768 0-2, 15
24K x 8 0000h - 5FFFh 1024 0-3, 15
32K x 8 0000h - 7FFFh 1280 0-4, 15
48K x 8 0000h - BFFFh 1536 0-5,15
64K x 8 0000h - FFFFh 1792 0-6, 15
96K x 8 0000h - 17FFFh 2048 0-7, 15
128K x 8 0000h - 1FFFFh 2304 0-8, 15
160K x 8 0000h - 27FFFh 2560 0-9, 15
192K x 8 0000h - 2FFFFh 2816 0-10, 15
256K x 8 0000h - 3FFFFh 3072 0-11, 15
384K x 8 0000h - 5FFFFh 3328 0-12, 15
512K x 8 0000h - 7FFFFh 3584 0-13,15
768K x 8 0000h - BFFFFh 3840 0-14,15
1024K x 8 0000h - FFFFFh 3968 0-15
1536K x 8 0000h - 17FFFFh
2048K x 8 0000h - 1FFFFFh
2000 Microchip Technology Inc. DS39507A-page 7-3
Section 7. Memory
Memory
7
7.2 Program Memory
Enhanced MCU devices have a 21-bit program counter capable of addressing 2 Mbytes
(1Mwords) of program memory space. The program memory contains instructions for execution
and data tables for storing fixed data. Data tables may be written once using table write instructions
and read as required, using the table read instructions.
The program space is implemented as a single contiguous block. The reset vector is at address
000000h, the high priority interrupt vector is at address 000008h, and the low priority interrupt
vector is at address 000018h (Figure 7-1).
CALL and GOTO instructions can address any location in the memory map, while the BRA and
RCALL instructions have a limited program memory reach (+1024, -1023 program memory word
locations). To allow the CALL and GOTO instructions to contain the entire address, it requires that
these instructions use 2 program memory words (2 word instruction).
Instructions are also available to move information between the data memory and the program
memory areas. These are called table operations. Table operations work with byte entities. This
is discussed in detail in the “Table Read/Table Write” section.
Figure 7-1: Program Memory Map and Stack for PIC18CXXX
PC<20:0>
Stack Level 1
Stack Level 31
Reset Vector
Low Priority Interrupt Vector
CALL,BSUB,RETURN
RETFIE,RETLW
21
0000h
0018h
On-chip
High Priority Interrupt Vector 0008h
User Memory Space
External/Unimplemented
1FFFFFh
200000h
Program Memory
(Read as ’0’ in
microcontroller mode)
Program Memory

7.2.1 Reset Vector
On any Enhanced MCU device, a reset forces the Program Counter (PC) to address 0h. This is
known as the “Reset Vector Address”, since this is the address that program execution will
branch to when a device reset occurs.
Any reset will also clear the contents of the PCLATU and PCLATH registers.
7.2.2 Interrupt Vectors
Two interrupt vectors are implemented; one for interrupts programmed as high priority and the
other for the interrupts programmed as low priority. The vector addresses are 08h for high priority
interrupts and 18h for low priority interrupts. If the interrupt priority is not used, all interrupts are
treated as high priority.
When an interrupt is acknowledged, the PC is forced to address 0008h or 0018h. This is known
as the “Interrupt Vector Address”. When the PC is forced to the interrupt vector, the PCLATU and
PCLATH registers are not modified. Once in the service interrupt routine (ISR), before any write
to the PC, the PCLATH register should be written with the value that will specify the desired location
in program memory. Before the PCLATH register is modified by the Interrupt Service Routine
(ISR), the contents of the PCLATH may need to be saved so it can be restored before returning
from the ISR.
7.2.3 Calibration Information
Some devices have calibration information stored in their program memory. This information is
programmed by Microchip when the device is under final test. The use of these values allows the
application to achieve better results. The calibration information is typically at the end of program
memory. These bytes can be accessed with the table read instructions.
Note: For windowed devices, write down all calibration values BEFORE erasing. This
allows the device’s calibration values to be restored when the device is re-programmed.
When possible, writing the values on the package is recommended.
Section 7. Memory
Memory
7
7.2.4 Instructions in Program Memory
The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes
in program memory. The least significant byte of an instruction word is always stored in a program
memory location with an even address (LSb = ’0’). Figure 7-2 shows an example of how
instruction words are stored in the program memory. To maintain alignment with instruction
boundaries, the PC increments in steps of 2 and the LSb will always read ’0’.
The CALL and GOTO instructions have an absolute program memory address embedded into the
instruction. Since instructions are always stored on word boundaries, the data contained in the
instruction is a word address. The word address is written to PC<20:1>, which accesses the
desired byte address in program memory. Instruction #2 in Figure 7-2 shows how the instruction
"GOTO 000006h’ is encoded in the program memory. Program branch instructions which encode
a relative address offset operate in the same manner. The offset value stored in a branch instruction
represents the number of single word instructions that the PC will be offset by. The “Instruction
Set” section provides further details of the instruction set.
Figure 7-2: Instructions in Program Memory
Word Address
High Byte Low Byte ↓
Program Memory
Byte Locations →
000000h
000002h
000004h
000006h
Instruction 1: MOVLW 055h 0Fh 55h 000008h
Instruction 2: GOTO 000006h EFh 03h 00000Ah
F0h 00h 00000Ch
Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh
F4h 56h 000010h
000012h
000014h

7.3 Program Counter (PC)
The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC
is 21-bits wide and addresses each byte (rather than words) in the program memory. The low
byte is called the PCL register (PC<7:0>). This register is readable and writable. The high byte
is called the PCH register (PC<15:8>). This register is not directly readable or writable. Updates
to the PCH register may be performed through the PCLATH register.
The upper byte is called the PCU register (PC<20:16>). The PCU register is not directly readable
or writable. Updates to the PCU register may be performed through the PCLATU register. The
PC structure is PCU<4:0>:PCH<7:0>:PCL<7:0> and is equivalent to PC<20:0>.
Figure 7-3 shows the interaction of the PCU, PCH, and PCL registers with the PCLATU and
PCLATH registers.
Figure 7-3: Program Counter Structure
The low byte of the PC (PCL<7:0>) is mapped in the data memory. PCL is readable and writable
just as is any other register. PCU and PCH are the upper and high bytes of the PC respectively,
and are not directly addressable. Registers PCLATU<4:0> (PC upper latch) and PCLATH<7:0>
(PC high latch) are used as holding latches for the high bytes of the PCU and PCH, and are
mapped into data memory. The user can read and write PCH through PCLATH and PCU through
PCLATU. Any time PCL is read, the current contents of PCH and PCU are transferred to PCLATH
and PCLATU, respectively. Any time PCL is written to, the contents of PCLATH and PCLATU are
transferred to PCH and PCU, respectively.
The PC addresses bytes rather than words in the program memory. Because the PC must
access the instructions in program memory on an even byte boundary, the LSb of the PC is a
forced '0' and the PC increments by two for each instruction. The LSb bit of the PCL is readable
but not writable. Any write to the LSb is ignored.
Figure 7-4 shows the four situations for the loading of the PC. Situation 1 shows how the PC is
loaded on a write to PCL (PCLATH<4:0> →PCH). Situation 2 shows how the PC is loaded during
a GOTO instruction (PCLATH<4:3> →PCH). Situation 4 shows how the PC is loaded during a
CALL instruction (PCLATH<4:3> →PCH), with the PC loaded (PUSHed) onto the Top of Stack.
Situation 6 shows how the PC is loaded during one of the return instructions where the PC is
loaded (POPed) from the Top of Stack.
PC
21 16 15 8 7 0
PCLATU PCLATH
PCU PCH PCL
23 20
Reserved. Maintain these bits cleared.
Note: The values in PCLATU and PCLATH do not always reflect the current value in PCU
and PCH. When needing to modify the current Program Counter (PC) value, first
read the PCL register to update the values in the PCLATU and PCLATH registers.
Section 7. Memory
Memory
7
Figure 7-4: Loading of PC In Different Situations
PC
ALU Result
8
PCL
Situation 1 - Instruction with PCL as destination
Situation 2 - GOTO Instruction
PCLATU PCLATH
20 PCU 16 15 PCH 8 7 0
PCL
20 15 8 7 0
PCH
16
PCU
91
0
K19:K8
(2nd word
K7:K0
(1st word
of instruction) of instruction)
STACK (21-bits x 31)
Top of STACK
Top of STACK
20 16 15 8 7 1 0
ADDR
Situation 3 - BRA Instruction in Conditional Branch Instruction STACK (21-bits x 31)
Top of STACK
Offset
from
Instruction
0
PCU PCH PCL
Situation 4 - CALL Instruction
20
PCL
20 15 8 7 0
PCH
16
PCU
91
0
K19:K8
(2nd word
K7:K0
(1st word
Top of STACK
of instruction) of instruction)
Note: PCLATU and PCLATH are not updated with the contents of PCH.

Figure 7-4: Loading of PC In Different Situations (Continued)
Situation 6 - RETURN, RETFIE, or RETLW Instruction
PCL
20 15 8 7 0
PCH
16
PLU
91
PCLATU PCLATH
Top of STACK
Situation 5 - RCALL Instruction
20 16 15 8 7 1 0
ADDR
Offset
from
Instruction
0
PCU PCH PCL
Top of STACK
21
Note: PCLATU and PCLATH are not updated with the contents of PCH.
Section 7. Memory
Memory
7
7.3.1 Computed GOTO
A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL).
When doing a table read using a computed GOTO method, care should be exercised if the table
location crosses a PCL memory boundary (each 256 byte block) and the PCH memory boundary
(each 64Kbyte block).
A lookup table can be formed with an ADDWF PCL instruction and a group of RETLW 0xnn
instructions. WREG is loaded with an offset into the table before executing a call to that table.
The first instruction of the called routine is the ADDWF PCL instruction. The next instruction executed
will be one of the RETLW 0xnn instructions that returns the value 0xnn to the calling function.
Since the Program Counter is a byte counter (instead of a word counter), adds to the PCL allow
a table size of 128 entries before the PCLATH needs to be modified.
In this method of storing tables in PIC18CXXX devices, only one data value may be stored in
each instruction location, and room on the return address stack is required. A better method of
storing data in program memory is through the use of table reads and writes. Two bytes of data
can now be stored in each instruction location.
7.4 Lookup Tables
Look-up tables instructions are implemented two ways in the PIC18CXXX devices. The computed
goto is compatible with the PIC16CXXX and PIC17CXXX parts. Code written for those
devices will run on the PIC18CXXX devices with minor modifications.
Table read instructions are implemented on the PIC17CXXX and PIC18CXXX devices. However,
table operations on the PIC18CXXX work differently than on the PIC17CXXX.
7.4.1 Table Reads/Table Writes
Lookup table data may be stored 2 bytes per program word. By using TBLPTR and TABLAT, data
may be retrieved from program memory one byte at a time as required.
Table writes to program memory can be executed as many times as desired. Remember that the
technology of the program memory determines the outcome of the table write. Table writes to
EPROM memory allow the program memory cell to go from a ’1’ state to a ’0’ state, but not the
other direction. FLASH memory allows the cell to go from a ’1’ to a ’0’ and a ’0’ to a ’1’ (though
typically a program memory word or block location is always written).
Note: Since the Program Counter is 21-bits, the uppercase PCLATU register may also
need to be modified when doing computed gotos.
Note: Any write to the Program Counter (PCL) will cause the contents of PCLATU and
PCLATH to be loaded into PCU and PCH, respectively.

Example 7-1: PIC18CXXX Table Lookup
MOVLW BYTE_COUNT ; Load the Byte Count value
MOVWF CNTR ; into CNTR
;
;; MOVLW UPPER(TBL_ADDR) ; Load the Table Address
;; MOVWF TBLPTRU ; (on POR TBLPTRU = 0, so
;; ; loading TBLPTRU is not
;; ; required for conversions)
MOVLW HIGH(TBL_ADDR) ; Load the Table Address
MOVWF TBLPTRH ;
MOVLW LOW(TBL_ADDR) ;
MOVWF TBLPTRL ;
LOOP1 TBLRD*+ ; Read value into TABLAT,
; Increment TBLPTR
MOVFF TABLAT, POSTINC0 ; Copy byte to RAM @ FSR0
; Increment FSR0
DECFSZ CNTR ; Read Byte Count locations
GOTO LOOP1 ; Read next Byte
MOVLW WORD_COUNT ; Load the Word Count value
MOVWF CNTR ; into CNTR
;
MOVLW HIGH(TBL_ADDR) ; Load the Table Address
MOVWF TBLPTRH ;
MOVLW LOW(TBL_ADDR) ;
MOVWF TBLPTRL ;
TABLRD 0, 1, DUMMY ; Dummy read,
; Updates TABLATH
; Increments TBLPTR
LOOP1 TLRD 1, INDF0 ; Read HI byte in TABLATH
TABLRD 0, 1, INDF0 ; Read LO byte in TABLATL,
; update TABLATH:TABLATL,
; and increment TBLPTR
DECFSZ CNTR ; Read Word Count locations
GOTO LOOP1 ; Read next word
Section 7. Memory
Memory
7
CLRF CNTR ;
TABLELP
MOVF CNTR, W ; Place value in
; WREG register
CALL TABLE1
MOVWF INDF
INCF FSR
INCF CNTR
BTFSS CNTR, 3 ; CNTR = 00001000b?
GOTO TABLE_LP
:
:
TABLE1
ADDWF PCL ; Enusure that table does
; not cross 256 byte
; page boundary.
RETLW ’G’
RETLW ’O’
RETLW ’ ’
RETLW ’M’
RETLW ’C’
RETLW ’H’
RETLW ’P’
RETLW ’!’

7.5 Stack
The stack allows a combination of up to 31 program calls and interrupts to occur. The stack contains
the return address from this branch in program execution.
Enhanced MCU devices have an 31-level deep x 21-bit wide hardware stack. The stack space
is not part of either program or data space and the stack pointer is not readable nor writable. The
PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a
branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution.
PCLATH is not modified when the stack is PUSHed or POPed.
After the PC is PUSHed onto the stack 31 times (without POPing any values off the stack), the
32nd PUSH over-writes the value from the 31st PUSH and sets the STKFUL bit while the
STKPTR remains at 11111b. The 33rd PUSH overwrites the 32nd PUSH (and so on) while
STKPTR remains 11111b. When the stack overflow enable bit is enabled a device reset will
occur.
Figure 7-5: Stack Modification
Whenever the program branches, the return address is saved to the stack. Such branches
include CALL, RCALL, or an interrupt. The stack pointer is incremented and PC<20:1> is
PUSHed onto the return stack. PC<0> is always assumed to be 0. When a branch return is executed,
the top of the stack is POPed to the Program Counter and the stack pointer is decremented.
PCLATU and PCLATH are not affected during these branches.
The PC is word incremented by 2 after each instruction fetch during Q1 unless:
• Modified by a GOTO, CALL, RCALL, RETURN, RETLW, RETFIE, or branch instruction
• Modified by an interrupt response
• Due to a write to PCL by an instruction
Skips are equivalent to a forced NOP cycle at the skipped address.
Top of Stack (1)
STACK
STACK POINTER
11111b
00000b
Note1:The stack pointer value does not increment past 11111b.
Section 7. Memory
Memory
7
7.6 Data Memory Organization
Data memory is made up of the Special Function Registers (SFR) area and the General Purpose
Registers (GPR) area. The SFRs are used for control and status of the microcontroller and
peripheral functions, while GPRs are the general area for user data storage and scratch pad
operations.
Each register has a 12-bit address. This allows up to 4096 bytes of data memory. This memory
is partitioned into 16 banks of 256 bytes that contain the General Purpose Registers (GPRs) and
Special Function Registers (SFRs).
The data memory can be banked for both the GPR and SFR areas. Banking requires the use of
BSR Register. Figure 7-6 shows the data memory map organizations, while Table 7-2 shows
which banks will be used depending on the memory size of the devices.
SFRs start at the last location of Bank 15 (0xFFF) and work up. Once the SFR space ends, any
lower locations in that bank may be implemented as GPRs. GPRs start at the first location of
Bank 0 (0h) and work down. Any read of an unimplemented location will read as ’0’s.
The Instruction set and architecture allows operations across all banks. To move values from one
register to another register, the MOVFF instruction can be used. This is a two word / two cycle
instruction.
The entire data memory can be accessed either directly or indirectly. Direct addressing may
require the use of the BSR register. Indirect addressing requires the use of the File Select Registers
(FSRs). Each FSR holds a 12-bit value that can access any location in the Data Memory
map.
To ensure that commonly used registers (SFRs and select GPRs) can be accessed in a single
cycle, regardless of the current BSR values, an Access Bank is implemented. This is explained
in Section 7.6.1.
The GPR area is banked to allow greater than 256 bytes of general purpose RAM to be
addressed. SFRs are for the registers that control the peripheral and core functions.
Figure 7-6: The Data Memory Map and the Access Bank
Bank 0
Bank 1
Bank 14
Bank 15
BSR<3:0> Data Memory Map
= 0000b
= 0001b
= 1110b
= 1111b
00h
FFh
00h
FFh
Access Bank
When a = 0,
the BSR is ignored and this Access
Bank is used.
The first 128 bytes are General Purpose
RAM (from Bank 0).
The second 128 bytes are Special
Function Registers (from Bank 15).
See Section 7.6.1.
When a = 1,
the BSR is used to specify the RAM
location that the instruction uses.
Bank n

7.6.1 Access Bank
The Access Bank is an architectural enhancement that is very useful for C compiler code optimization.
The techniques used by the C compiler may also be useful for programs written in assembly.
This data memory region can be used for:
• Intermediate computational values
• Local variables of subroutines
• Faster context saving/switching of variables
• Common variables
• Faster evaluation/control of SFRs (no banking)
The Access Bank is comprised of the upper portion of Bank 15 (SFRs) and the lower portion of
Bank 0 (GPR). These two sections will be referred to as Access RAM High and Access RAM Low,
respectively. Figure 7-6 indicates the Access RAM areas. The actual size of memory used from
Bank 0 and Bank 15 depends on the specific device. When appropriate, devices will use
128 bytes from Bank 0 (GPR) and 128 bytes from Bank 15 (SFR). In larger devices with more
SFRs, the GPR Access bank size may be reduced to allocate that space to SFRs Access space.
A bit in the instruction word specifies if the operation is to occur in the bank specified by the BSR
register or in the Access Bank. This bit is denoted by the ’a’ bit (for access bit).
When forced in the Access Bank (a = ’0’), the last address in Access RAM Low is followed by the
first address in Access RAM High. Access RAM High maps the Special Function Registers so
that these registers can be accessed without any software overhead. This is useful for testing
status flags, modifying control bits, software stacks, and context saving of registers.
7.6.2 General Purpose Registers (GPR)
Enhanced MCU devices may have banked memory in the GPR area. GPRs are not initialized by
a Power-on Reset and are unchanged on all other resets.
The register file can be accessed either directly, or indirectly, using the File Select Register
(FSR). Some devices have areas that are shared across the data memory banks, so a read/write
to that area will appear as the same location (value), regardless of the current bank. We refer to
this area as the Common RAM.
Data RAM is available for use as GPR registers by all instructions. Most banks of data memory
contain only GPR registers starting with bank 0. The top half of bank 15 (0xF80 to 0xFFF) contains
SFRs.
Each data memory bank has 256 locations and can be addressed using an 8-bit address.
Section 7. Memory
Memory
7
7.6.3 Special Function Registers
The SFRs are used by the CPU and peripheral modules for controlling the desired operation of
the device. These registers are implemented as static RAM.
The SFRs can be classified into two sets; those associated with the “core” function and those
related to the peripheral functions. Those registers related to the “core” are described in this section,
while those related to the operation of the peripheral features are described in the section
of that peripheral feature.
The SFRs are typically distributed among the peripherals whose functions they control.
If the SFRs do not use all the available locations on a particular device, the unused locations will
be unimplemented and read as '0's. In devices that have a high integration of features, some of
the SFRs may be in banks other than bank 15. See Figure 7-7 for addresses for the SFRs. As
new devices are introduced with new SFRs, this register map will be updated. Please refer to the

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Section 7.

PIC18C Reference Manual

PIC18C Reference Manual

PIC18C Reference Manual

PIC18C Reference Manual

PIC18C Reference Manual

PIC18C Reference Manual

PIC18C Reference Manual

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