1444 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO.

10, OCTOBER 2001

A 2-dB Noise Figure 900-MHz Differential

CMOS LNA
Francesco Gatta, Student Member, IEEE, Enrico Sacchi, Member, IEEE, Francesco Svelto, Member, IEEE,
Paolo Vilmercati, and Rinaldo Castello, Fellow, IEEE

Abstract—This paper proposes a new circuit topology for RF

CMOS low noise amplifier (LNA). Since pMOS devices are ap-
proaching the performances of nMOS devices in scaled technolo-
gies, the idea is to realize the input stage shunting an inductively
degenerated nMOS stage with a pMOS one. In this way, due to the
inherent current reuse, the performances can be improved using
the same power consumption. Since the devices of an inductively
degenerated input stage are working in moderate inversion (at least
at moderate power dissipation), prior to the stage optimization an
appropriate moderate inversion model is introduced.
A fully differential 900-MHz 0.35- m CMOS LNA (plus output Fig. 1. Inductively degenerated input stage.
buffer) prototype achieves the following performances: 2-dB noise
figure (NF), 17.5-dB power gain, 6-dBm IIP3 with 8-mA current
consumption from a 2.7-V voltage supply. To the author’s knowl- are in the moderate inversion region of operation. The lack of a
edge, this is the lowest reported NF for a fully differential CMOS well-accepted device model in this region, especially from the
LNA operating at this power consumption level. As an additional
feature, this LNA has a programmable gain. noise standpoint, makes the optimization of the stage difficult.
It is therefore necessary to develop a new noise model valid
Index Terms—CMOS RF, low noise amplifier, moderate inver- also in moderate inversion. An integrated 0.35- m CMOS fully
sion MOS, noise figure.
differential variable gain LNA, based on the new optimization
procedure, has the following performance: 2-dB NF, 6-dBm
I. INTRODUCTION IIP3, and 17.5-dB power gain with 8 mA from 2.7 V. To the
author’s knowledge, this is the lowest reported NF for a fully
I N THIS paper, we propose a variable-gain fully differential
900-MHz CMOS low noise amplifier (LNA), achieving a
2-dB noise figure (NF), while drawing 8 mA. The noise figure
differential CMOS LNA operating at this power consumption
level. Moreover, the IIP3 is limited by the output stage used
for characterization purposes. The core IIP3 is estimated to be
is particularly low, considering that prototypes are packaged and
3 dBm.
that they make use only of on-chip spiral inductors, except for
The paper is organized as follows. Section II presents the
an external one (in series with the gate inductor) used for tuning
input stage basic idea, Section III discusses the device high
purposes. The input stage, which primarily determines the NF,
frequency model in moderate inversion, and Section IV pro-
is made of inductively degenerated nMOS and pMOS pairs,
poses the input stage optimization. The detailed design of the
in shunt configuration, to enable current reuse, thereby saving
900-MHz variable gain LNA is carried out in Section V, while
power. In a 0.35- m CMOS technology, this topology proves
the experimental results performed on an actual prototype are
to be advantageous over the traditional inductively degenerated
reported in Section VI. Finally, Section VII draws the conclu-
nMOS pair. Furthermore, the proposed topology is expected to
sions.
become even more advantageous in further scaled technologies.
This is because the difference in the cutoff frequencies of pMOS
and nMOS devices will tend to decrease while, at the same time, II. INPUT STAGE BASIC IDEA
the noise degradation due to hot electron will be less significant
The requirements set on the input stage of an LNA are: 50-
for p-type devices.
input matching, minimum noise contribution, and maximum
As it will be shown, when the inductively degenerated input
transconductance gain. In addition, the IIP3 of the LNA should
stage is optimized for minimum noise figure, the active devices
be maximized. It has been shown that the optimum topology
that simultaneously fulfills all the above requirements is the
Manuscript received February 2, 2001; revised June 4, 2001. This work has inductively degenerated nMOS input stage, shown in Fig. 1,
been supported by the ESPRIT project CRAFT. in its differential form [1]–[5]. In fact, the series feedback al-
F. Gatta, F. Svelto, P. Vilmercati and R. Castello are with the Dipartimento
di Elettronica, Università degli Studi di Pavia, 27100 Pavia, Italy (e-mail: lows the use of almost noiseless reactive elements to produce a
gattaf@ele.unipv.it; fsvelto@ele.unipv.it; vilmerca@ele.unipv.it; castello@ real input impedance (given by times , where is the
ele.unipv.it). nMOS cutoff frequency) at the carrier frequency (provided
E. Sacchi is with the Studio di Microelettronica, STMicroelectronics, 27100
Pavia, Italy (e-mail: enrico.sacchi@st.com). , where is the gate-to-source
Publisher Item Identifier S 0018-9200(01)08412-8. capacitance of the active devices). This means that the noise is
0018–9200/01$10.00 © 2001 IEEE
GATTA et al.: A 2-dB NOISE FIGURE 900-MHz DIFFERENTIAL CMOS LNA
Fig. 2. Equivalence between p-n input stage and classic nMOS single stage.
contributed, at least to first order, only by the active device. Fur-
thermore, passive voltage amplification at resonance reduces the
noise contributed by the active devices.
The noise analysis of this stage has been presented in [5]
where the optimum device size for minimum noise has been
defined. Such results, however, are numerically correct only if
the MOS devices are always in the strong inversion region of
operation. Actually, for typical current values ( 10 mA) and a
scaled down technology (below 0.5 m), the devices work in
the moderate inversion region at the optimum bias point. As a
consequence, a model valid also in this region is required. The
following important conclusions, derived in [5], are nonethe-
less valid. For a given source resistance and assuming matching
conditions at the carrier frequency, there is an optimum gate
width of the active devices which produces a minimum in the
noise figure. Once the optimum gate width has been chosen,
the only way to reduce the noise figure is to increase the cur-
rent which increases the device transition frequency . The
absolute minimum achievable noise figure corresponds to the
devices working at their peak transition frequency
A similar tradeoff exists between transconductance gain and
biasing current, if the LNA is designed for minimum noise
figure. In fact, the input stage transconductance
matched conditions, neglecting the effect of the gate-to-drain
overlap capacitance, is given by
in which is the source resistance. Assuming, as an example,
a 0.35- m CMOS technology, 900-MHz carrier frequency,
and 4-mA biasing current, from simulations with Philips MM9
Model, the optimum width is about 500 m. The resulting
is 10 GHz, which is far from the peak value (of the order of
38 GHz). This means that an increase, and as a consequence
a transconductance gain increase and noise reduction, can
be achieved if the current consumption is increased. Finally,
since the aspect ratio is set, increasing the current consumption
increases the overdrive voltage which increases the linearity.
Though beneficial for the noise figure, the transconductance
gain, and the linearity, the increase of the current consumption
is in contrast with the requirements of a portable system.
On the other hand, for a given current consumption, the same
goal, i.e., improved gain, noise, and linearity, can be achieved
by shunting a nMOS input stage with a pMOS one, without in-
creasing the current consumption [1]. To understand the concept
behind the new topology, let us consider the classical nMOS
1445
Fig. 3. Small signal equivalent circuit with noise sources.
LNA, shown in Fig. 2(a), and assume to double its biasing cur-
rent, as shown in Fig. 2(b). The input resistance, at resonance, is
kept equal to that of Fig. 2(a), provided . The
circuit of Fig. 2(c), made of two nMOS with half the gate width
connected in parallel and with the same total biasing current, is
equivalent to that of Fig. 2(b). Let us assume, to gain an intu-
itive insight, that pMOS and nMOS devices have the same cutoff
frequency. One nMOS can then be substituted by a pMOS, as
shown in Fig. 2(d), with the following result: the pMOS–nMOS
. input stage achieves the same NF, and the same transconduc-
tance gain of the nMOS-only stage of Fig. 2(b), but with half
the current consumption. The same beneficial effect is obtained
, in on the linearity, since the devices of Fig. 2(d) and Fig. 2(b) have
the same overdrive voltage.
The assumption used in this section is not true, but useful for
an intuitive explanation of the idea. More quantitative conclu-
(1) sions can be derived on the achievable noise and small signal
parameters once the following considerations are taken into ac-
count. First, the cutoff frequencies and the noise coefficients
of pMOS and nMOS devices are not the same. Second, in a
0.35- m CMOS technology, for a typical current level of 4 mA,
and 900-MHz carrier frequency, the nMOS devices of an opti-
mized inductively degenerated input stage are working in mod-
erate inversion. This will be even truer with further scaled tech-
nology. Prior to a new optimization of the input stage, a model
adequate for device operating in moderate inversion will be dis-
cussed.
III. HIGH-FREQUENCY NOISE MODEL
Fig. 3 shows a very simple high-frequency MOS small-signal
equivalent circuit with noise sources. is the gate-to-source
capacitance, is the transconductance, is a non-quasi-
static resistance (producing distributed effects in conjunc-
tion with the gate-to-source capacitance), is the noise power
spectral density in the drain current, is the power spectral
density in the gate current induced by the drain noise current.
1446 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 10, OCTOBER 2001

When the device is biased in strong inversion, the drain noise is

thermal noise and its power spectral density is
(2)
where is the channel conductance for a drain-to-source
voltage equal to zero, while is the thermal noise coefficient,
equal to 2/3 in long channel devices.
Actually, for typical current levels ( 10 mA), the MOS de-
vices of an inductively degenerated input stage are not operating
in strong inversion (i.e., they have mV) [6]. As an
example, for a 0.35- m technology with a current of 4 mA, the Fig. 4. Inductively degenerated nMOS-only input stage with noise sources.
device leaves the strong inversion region for gate widths greater
than 150 m. In the strong inversion region of operation, the cur- Since the drain noise and the gate noise are given by the same
rent is due to drift and the associated noise is thermal, whereas physical phenomena, they are partially correlated, with a corre-
in weak inversion, the current is due to diffusion and the associ- lation coefficient , which we assume to be 0.4 j.
ated noise is primarily shot [7]. The modeling of noise in mod-
erate inversion, intermediate between the two regions, is more IV. INPUT STAGE OPTIMIZATION
difficult. In this section, we will provide expressions, valid in
A. Classical Single-MOS-Type Topology
moderate inversion, for the power spectral densities of the noise
sources, depicted in Fig. 3, in terms of the small-signal param- Once the high-frequency (HF) MOS model has been dis-
eters. The – relation and the small signal parameters are cussed, the optimization of the inductively degenerated input
reported in the Appendix. stage, shown in Fig. 4 with the relevant noise sources, can
We use for the drain noise an exponential expression, which be performed. The results derived in the following apply, at
is fully thermal noise when is much higher than least qualitatively, to an inductively degenerated input stage,
and fully shot noise when is lower than regardless of the type of used device (either nMOS or pMOS).
. Such an expression is given by The noise factor ( ), at the frequency where , ,
and resonate, and assuming ideal inductors (i.e., with no
losses), is given by

(3)
(7)

where is the weak inversion slope factor.

We can substitute the above expression with another formally in which
similar to the one, valid in strong inversion, in which is
substituted with : and (8)

(4) Notice that all the terms in (7) are well defined apart from
and . They are both bias dependent but unfortunately in an un-
where
known way. According to Shaeffer and Lee [5], we will assume
fixed values ( and ) in the entire range.
depends on and on the MOS dimensions, whereas the
ratio of and depends both on the biasing current and on
the MOS dimensions. Assuming a fixed and a given cur-
(5) rent budget, the only remaining variable is the MOS gate width,
which changes and .
Equation (7) has been evaluated as a function of the device
This expression describes well the drain noise at high gate width, using (5), (8), (20)– (22). The resulting NF versus
as well as low . the active devices gate width for an nMOS LNA at 900-MHz
As described in [7], at high frequency, besides the drain noise, frequency with 50- input resistance and 4-mA current con-
an induced gate noise, due to the capacitive coupling of the sumption has been plotted in Fig. 5 (curve a). Curve b shows
channel noise with the gate, is present. The corresponding power the NF, in the same operating conditions, but using the strong
spectral density is given by inversion model in the entire range.
For small gate widths, meaning high overdrives, the two
(6) curves collapse together because the device is actually in
strong inversion and the drain noise is fully thermal noise. For
where is the gate noise coefficient. large gate widths, the drain noise is becoming shot noise: as
GATTA et al.: A 2-dB NOISE FIGURE 900-MHz DIFFERENTIAL CMOS LNA 1447

Fig. 6. NF versus gate width assuming the strong inversion model (dotted
Fig. 5. NF versus gate width assuming the proposed model, valid from strong lines) and the proposed model, valid from strong inversion to weak inversion
inversion to weak inversion (curve a), and the strong inversion model (curve b), (solid line) with the current as a parameter, R = 50
, f = 900 MHz.
in the following conditions: R = 50
, I = 4 mA, f = 900 MHz.

a result the two curves are different and the NF minimum is

obtained for different gate widths. In particular, the minimum
of curve a is higher and sharper than that of curve b. Moreover,
the minimum NF gate width in curve a (equal to 500 m) is
lower than that in curve b (equal to 780 m). These results
are explained as follows: in the moderate inversion region, the
actual drain noise is higher than that estimated on the basis of a
pure thermal noise model. For example, for 800- m width, the
ratio between the actual noise power spectral density and the
thermal noise power spectral density is 1.6. This ratio increases
to 1.9, with the same current, for a 1200- m gate width.
As shown by Shaeffer and Lee [5] for the case of MOS tran-
sistors in strong inversion, the optimum gate width is almost
independent from the biasing current. On the other hand, for the Fig. 7. pMOS–nMOS shunt input stage with noise sources.
general case studied in this paper (i.e., including moderate in-
version), the optimum gate width is a function of the biasing The key point is that the optimum width is inversely propor-
current. This is because the gate width value for which the de- tional to the frequency and almost inversely proportional to the
vice enters the moderate inversion region changes with current. source resistance. Moreover, for the same frequency and source
Fig. 6 shows NF versus , for with the biasing cur- resistance, going from 0.35- m to 0.18- m technology, the op-
rent as a parameter for the two cases: first using the strong in- timum gate width decreases by about 25%. Since the gate length
version model for the entire region, and second using the model is halved, we conclude that using the same current, the overdrive
introduced in this paper. The strong inversion model suggests is further reduced. As a consequence, the model discussed so far
an optimum width almost independent of the biasing current, becomes even more important to achieve a correct sizing.
whereas the actual optimum width changes with the biasing cur-
rent. B. pMOS–nMOS LNA Topology
A compact and useful analytical expression for the optimum
Fig. 7 shows the nMOS shunted pMOS input stage, intro-
width cannot be found. Nonetheless, to gain insight, (7) has been
duced in Section II, with noise sources. The same optimization
computed for different biasing currents, source resistances, and
procedure used for the nMOS input stage can be used in this
technology parameters (belonging to 0.35, 0.25, and 0.18- m
case, assuming again a given current and . However, in this
CMOS processes), and the optimum widths have been evalu-
case not only the device gate width can be changed, but also the
ated. A fitting procedure has been applied to the results, giving
input resistance synthesized by each branch in shunt configura-
the following approximated expression for :
tion with the constraint that the synthesized parallel resistance
is equal to the source resistance . This means that the NF is
(9) a function of four variables with one constraint. The analytical
optimization is easier under the following assumption: the min-
imum noise figure of the shunt configuration is reached when
in which is a constant, dependent on the biasing current the nMOS and pMOS stages are both independently in the min-
and different for pMOS and nMOS devices. imum noise figure condition.
1448 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 10, OCTOBER 2001

With the above assumption, the independent variable is only

one among the nMOS gate width , the pMOS gate width
, the resistance synthesized by the nMOS branch at
resonance, and the resistance synthesized by the pMOS branch
at resonance. Choosing as independent variable ,
is given by

(10)

Equation (9) gives the optimum gate widths for the pMOS and
nMOS input pairs. The quality factors and the transconductance
gains of the nMOS and pMOS stages are as follows:

(11)

(12) Fig. 8. New proposed input stage NF versus R , with R = 50

and R =
100
(I = 4 mA, f = 900 MHz).
(13)
(14)

where and are the n-type (p-type) device

transconductance and input quality factor.
The short circuit noise power spectral density ( and
) are

(15)

and Fig. 9. New proposed input stage NF versus W and W , with optimum R
and I = 4 mA, R = 50
, f = 900 MHz.

imum NF is 1.15 dB. The corresponding parameters values are

, , m and
(16)
m. The result is quite similar to that obtained in Fig. 8,
supporting the original simplifying hypothesis. Fig. 9 shows the
where and . noise figure versus and with in the optimum condi-
The noise factor of the shunted pMOS and nMOS input stage tion. It can be seen that the minimum is relatively broad around
can be calculated as follows: the gate width optimum values.
At the same current level and carrier frequency, the minimum
(17) achievable noise figure with the nMOS-only stage is 1.5 dB
with 50 and 0.94 dB with 100 . For the pMOS-only stage,
For a given value of , , and , the noise figure of the the minimum achievable noise figure is 2.25 dB with 50 and
parallel n and p stage can be computed according to (17) for 1.6 dB with 100 .
each value of . We have seen in Section II, where the basic idea has been in-
Fig. 8 shows the input stage noise figure versus at troduced, that if the cutoff frequencies of the pMOS and nMOS
900-MHz frequency and 4-mA biasing current, for were the same, we would expect the same input referred noise
and . For at 900 MHz, the optimum noise power spectral density with half the current consumption for the
figure corresponds to and , p-n stage. From Fig. 6, the minimum noise of nMOS-only input
while the optimum gate widths are m and stage, with 8-mA biasing current and , is 0.95 dB.
m. The minimum NF is equal to 1.16 dB with This means that, in a 0.35- m technology, the input referred
50 and 0.8 dB with 100 . noise power spectral density of the pMOS–nMOS shunted input
To estimate the validity of the simplified optimization pro- stage is not yet equal but 1.25 times larger than that of a nMOS
cedure of the previous section, a numerical optimization proce- stage operated at twice the current. On the other hand, the new
dure has been carried on, letting all the possible parameters, i.e., topology will become more advantageous as scaling progresses.
, , , vary in an independent way. For , Specifically, for a 0.35- m technology, for 4-mA current con-
4-mA biasing current, 900-MHz frequency, the absolute min- sumption, in the minimum NF conditions, the ratio between
GATTA et al.: A 2-dB NOISE FIGURE 900-MHz DIFFERENTIAL CMOS LNA
Fig. 10. LNA complete schematic.
and is 2.5, while in a 0.18- m process this ratio is 1.8. In
addition the value of for deeply scaled devices is better for the
p-type.
V. LNA IMPLEMENTATION
A. Single-Ended to Differential Comparison
The noise analysis has been carried on referring to a single-
ended circuit. Actually, a fully differential topology is adopted
in the proposed LNA prototype. This is because when used in
a CMOS single-chip receiver, it will be required to reject, as
much as possible, the unwanted signals traveling through the
substrate.
Let us assume that each device of the differential solution is
biased at the same current level as in the single-ended imple-
mentation (i.e., the differential circuit uses twice as much cur-
rent). If is the synthesized input resistance, at resonance,
for the differential case, and for the single-ended one, the
relation between the noise power spectral densities in the two
cases (respectively and ) is
(18)
If the synthesized resistances are equal in the two cases, the
differential topology presents an input noise power twice that
of the single-ended version, with twice the biasing current. If
the synthesized differential resistance is two times the single-
ended resistance, the differential topology has the same input
noise power as the single ended one, but with twice the current
consumption.
B. Variable Gain Stage
Fig. 10 shows the LNA complete schematic. The input resis-
tance is set to 50 . Though a higher value would have been
beneficial for the noise figure, we have chosen 50 to reduce
the LNA sensitivity to external disturbances. The core is made of
1449
the input stage discussed before, the variable gain stage, made of
transistors M5, M6, (M7, M8) and the LC load. The large signal
amplitude range expected requires a variable gain stage. This is
to enhance the signal-to-noise ratio, in the presence of minimum
amplitude signals, while at the same time not saturating the last
stages of the receiver, in the presence of maximum amplitude
signals.
The variable gain feature is realized by a differential pair,
which steers the input stage current signal either to the LC load
or to . In the high gain mode, M5 and M8 are off while
M6 and M7 behave as the common gate of the input cascode
structure. In the zero gain configuration, M6 and M7 are off and
the entire signal is fed to the voltage supply. All intermediate
gain values can, in principle, be set.
VI. LAYOUT ISSUES AND EXPERIMENTAL RESULTS
The LNA of Fig. 10 has been realized in a 0.35- m CMOS
RF technology. The chip microphotograph is shown in Fig. 11.
All the inductors are integrated spiral inductors made using top
metal with the exception of the gate one. The quality factor of
the inductors is 7 at 900 MHz. The gate inductance is 10 nH,
approximately half of which is obtained with an integrated spiral
inductor , the other half being a high external inductor
used to tune the input impedance. and are both equal
to 1.5 nH.
To drive the input port of the 50- Network Analyzer, two
output buffers have been added. Prototypes have been encapsu-
lated in a SO20 plastic package.
A. Layout
A fully differential topology is susceptible to common mode
oscillation, due to the nonideal on-chip ground caused by the
inductance of the bonding. To minimize this effect, the internal
ground uses 4 bonding. A large on-chip capacitor between
and ground has been used. To minimize the contribution of the
1450
Fig. 11. Chip microphotograph.
Fig. 12. S and S : postlayout simulation and measurement.
substrate resistance on the input noise, each input device has
been divided in two parts, each surrounded by substrate con-
tacts. This was necessary since the used process has a high sub-
strate resistivity.
B. Experimental Results
Fig. 12 reports the measurement and postlayout simulation
of the reflection coefficient and power gain
versus frequency. The minimum of the reflection coeffi-
cient is measured at 920 MHz and it is about 10 dB. The little
difference from postlayout simulation ( 11 dB at 940 MHz) is
caused by package parasitic not completely taken into account
during simulations. Notice that the frequency band of the used
baluns is in the range 0.7–1.1 GHz, so the measured resonance
outside this band has no significance. The power gain is mea-
sured in the following measurement conditions: V,
mA, high gain mode. The continuous line is relative to a
postlayout simulation. The measured peak power gain is 17.5 dB
and it is achieved at a frequency (930 MHz) very close to the
one expected from simulations (940 MHz). The difference in
the peak gain amplitude, 17.5 dB versus 21 dB, is possibly due
to an overestimation of the quality factor of the spiral inductors
used in the LC load and to an imperfect on-chip output matching,
with equal to 7.5 dB at 900 MHz, as shown in Fig. 13. In
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 10, OCTOBER 2001
Fig. 13. Measured S and S .
Fig. 14. Noise figure versus frequency: Postlayout simulation and
measurement.
the same figure, the reverse power gain is shown. The very
low measured values (around 40 dB in the band of interest)
proves the effectiveness of the cascode stage to decouple the
output and input stages.
The parameters have been measured while lowering the
supply voltage. Down to 2 V, they do not change appreciably.
On the other hand, with a supply voltage of 1.5 V, the power
gain is reduced to 9 dB.
The variable gain function works correctly. In fact, biasing at
2.5 V the control gain pin, the differential pairs (M5, M6) and
(M7, M8) are balanced, i.e., half of the signal is injected into the
load. A 6-dB gain reduction, in the overall frequency range, is
found.
Noise figure measurements have been performed by means
of an HP 8971B noise figure meter. Losses due to cable be-
tween noise figure meter source and the board are automatically
corrected by the instrument. The measured insertion loss of the
input balun is 0.6 dB. The noise figure values, displayed by the
meter, have been corrected by the same amount.
Fig. 14 shows the measured noise figure and the postlayout
simulated one. The operating conditions are V,
mA, high gain mode. A good agreement is evident. The
GATTA et al.: A 2-dB NOISE FIGURE 900-MHz DIFFERENTIAL CMOS LNA 1451

Fig. 16. Calculated, simulated, and measured NF and voltage gain versus
biasing current.
Fig. 15. Measured noise figure and power gain versus frequency.

minimum measured value is 2.05 dB. Notice that this is the

lowest noise figure value reported to date for a CMOS fully
differential LNA at this low current level. Fig. 15 shows the
power gain and the noise figure on the same plot. As can be
seen, the power gain maximum and the noise figure minimum
are very close in frequency. This is not the case if the LNA is
designed for minimum noise matching using high- external
components.
The voltage gain and the noise figure dependence on the bi-
asing current are shown in Fig. 16. In the same figure, a com-
parison has been done between the measured, calculated, and
simulated NF. The calculated curve takes into account the losses
Fig. 17. Two tones test for third-order intermodulation.
of the integrated inductors and the noise contributed by the cas-
code. For current of 12 and 16 mA, the NF is, respectively, 1.85
VII. CONCLUSION
and 1.65 dB. It is possible to see the good agreement between
the three curves for a large range of currents. Fig. 17 shows the The analysis and optimization of a new proposed LNA input
output signal power, together with the third-order intermodula- stage has been presented. In a 0.35- m CMOS technology, it
tion products. The two tones used in this test are separated by allows to save half current consumption with only 25% increase
1 MHz. The resulting IIP3 is equal to 6 dBm. The output stage, of the input-referred noise power, if compared to the traditional
used to drive the spectrum analyzer, actually limits the measured inductively degenerated input stage. The performances are
nonlinearity. Estimating the IIP3 of the output stage via simu- expected to further improve with scaling. The realized pro-
lations, we can conclude that the IIP3 of the LNA core is given grammable LNA shows the lowest noise figure reported for a
by 3 dBm. CMOS implementation.

(19)

(20)
1452
APPENDIX
The expression, valid in moderate inversion, is
given by (19), shown at the bottom of the previous page [6],
where is the effective mobility coefficient, expressing the
mobility dependence on normal field and is the critical
field. For the 0.35- m technology used, V and
V/m. In saturation, (19) becomes (20), also
shown at the bottom of the previous page.
From (19) and (20), it is possible to derive the transconduc-
tance and the drain-to-source conductance for
. In particular
(21)
(22)
ACKNOWLEDGMENT
The authors would like to thank I. Bietti for his helpful dis-
cussions and his help during measurement setup.
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[5] D. K. Shaeffer and T. H. Lee, “A 1.5-V 1.5-GHz CMOS low noise am-
plifier,” IEEE J. Solid-State Circuits, vol. 32, pp. 745–759, Mar. 1997.
[6] Y. Tsividis, Operation and Modeling of the MOS Transistors. New
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[7] A. Van der Ziel, Noise in Solid State Devices and Circuits. New York:
Wiley, 1990.
Francesco Gatta (S’99) received the Laurea degree
in electrical engineering from the University of Pavia,
Pavia, Italy, in 1998, where he is currently working
toward the Ph.D. degree, sponsored by Mindspeed
Technologies (formerly Conexant Systems).
He was a summer intern at Conexant Systems
from 1998 to 2000, studying CMOS low phase
noise oscillators, UMTS receiver architectures, and
CMOS ring oscillators for SONET192 applications.
His main interests are the analysis and design
of low-power CMOS LNA, CMOS integrated
image-rejection filter, and analysis and implementation of CMOS wireless
receiver for UMTS applications.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 10, OCTOBER 2001
Enrico Sacchi (S’98–M’00) was born in Pavia, Italy,
in 1971. He received the Laurea degree in electrical
engineering and the Ph.D. degree in electronics and
computer science from the University of Pavia, Pavia,
Italy, in 1995 and 1999, respectively. His Ph.D. dis-
sertation was focused on the design, modeling, and
optimization of spiral integrated inductors and on the
design of CMOS low noise amplifiers for wireless ap-
plications.
In March 1999, he joined the Studio di Microelet-
tronica, Pavia, a cooperation between STMicroelec-
tronics and the University of Pavia, where he is involved in the integration of the
analog front-end for wireless applications in BiCMOS and CMOS technology.
In September 2000, he joined the Electrical Engineering and Computer Science
Department, University of California at Berkeley, as a Visiting Industrial Fellow
from STMicroelectronics. His research is focused on the design of a DCS1800
transmitter based on Cartesian feedback linearization technique.
Francesco Svelto (S’94–M’98) received the Laurea
and Ph.D. degrees in electrical engineering from the
University of Pavia, Pavia, Italy, in 1991 and 1995,
respectively.
He held a grant from STMicroelectronics, Pavia,
during 1996–1997, working in CMOS RF design.
During 1997–2000, he was with the University of
Bergamo, Bergamo, Italy, as an Assistant Professor.
Since 2000, he has been with the Electrical En-
gineering Department, University of Pavia, as an
Associate Professor. His research interests are in
CMOS RF design and high-speed analog integrated circuits design.
Dr. Svelto is a member of the Technical Program Committee of the Custom
Integrated Circuits Conference.
Paolo Vilmercati was born in Voghera, Italy, in
1975. He received the Laurea degree in electrical
engineering from the University of Pavia, Pavia, Italy,
in 2000. In his Laurea thesis, he developed the real-
ization of a fully integrated CMOS LNA for mobile
applications, with particular interest in the study of
MOS behavior in the moderate and weak inversion
region of operation from the noise standpoint.
He is currently continuing his military service as a
civil servant.
Rinaldo Castello (S’83–M’84–SM’92–F’99) was
born in Genova, Italy, in 1953. He graduated in
electronic engineering from the University of
Genova, Italy, in 1977. He received the M.S. and the
Ph.D. degrees in 1981 and 1984, respectively, from
the University of California at Berkeley.
From 1983 to 1985, he was a Visiting Assistant
Professor with the Electronics Department of the
University of California at Berkeley, teaching
courses on analog/digital integrated circuit design
and advising several graduate students. In 1987, he
joined the Department of Electronics at the University of Pavia, Pavia, Italy,
as an Associate Professor. In addition to his academic activities, he acts as a
Consultant for STMicroelectronics, Milan, Italy. His research activities are in
the field of integrated circuits for analog/digital interfaces, mainly oriented
toward telecom applications. He was Guest Editor of the July 1992 special
issue of the IEEE JOURNAL OF SOLID-STATE CIRCUITS and Associate Editor for
Europe since 1993.
Dr. Castello has been a member of the Technical Committee of the European
Solid State Circuit Conference (ESSCIRC) since 1987, the International Solid
State Circuit Conference (ISSCC) since 1992, and was Technical Chairman of
the ESSCIRC’91.