VLSI 2017-18 B S Balaji PDF

||Jai Sri Gurudev||
Sri Adichunchanagiri Shikshana Trust (R.)

B.G.S. INSTITUTE OF TECHNOLOGY
Department of Electronics and Communication and Engineering,
BG Nagar – 571448, Nagamangala Taluk,
Mandya District, Karnataka (INDIA).
VLSI LAB MANUAL

(10ECL77)
ACADEMIC YEAR - 2017 -18.
Prepared by
B.S. BALAJI
Assistant Professor, Dept.. ECE,
BGS Institute of Technology.
CONTENTS
PART – A DIGITAL DESIGN
1. Introduction to VLSI 001

2. Introduction to Cadence Digital Design 001
3. Inverter 005
4. Buffer 010
5. Transmission Gate 015
6. Logic Gates 018
7. Flipflops – SR, JK, D, T, MS 025
8. Parallel and Serial adder 049
9. 4 bit Counter (Synchronous and Asynchronous counter) 064
PART – B ANALOG DESIGN
1. Introduction to Cadence analog design lab 084

2. Inverter 134
3. Common Source amplifier 138
4. Common Drain amplifier 142
5. Differential amplifier 146
6. Operational amplifier 150
7. R2R DAC 154
||Jai Sri Gurudev||
Sri Adichunchanagiri Shikshana Trust (R.)
B.G.S. INSTITUTE OF TECHNOLOGY
Department of Electronics and Communication and Engineering,
BG Nagar – 571448, Nagamangala Taluk,
Mandya District, Karnataka (INDIA).
VLSI LABORATORY
PRACTICAL RECORD
(10ECL77)
NAME: ______________________________________________
USN:_________________________________________________
SEM:_______________________ SEC:____________________
IA MARKS:________________ LEC. SIGN:_____________
Name of the Institution: _______________________________________________
Laboratory Certificate
This is to certify that Kumari / Sri __________________________

_____________________ has satisfactorily completed the course of
experiments in practical laboratory ______________________________
_______________________ University ______________________________________
________________ course in the VLSI Laboratory of this college in
the academic year 20___ to 20___.
Date: ____________ Signature of the Teacher

Incharge of the batch
Head of the Department
Name: ___________________________________________
Reg. No. _________________________________________
Examination Centre: __________________________
Date of Practical Examination: ______________

Particulars of the Experiments Performed
INDEX
Serial
Date Experiments Page No. Remarks
no.
Particulars of the Experiments Performed
INDEX
Serial
Date Experiments Page No. Remarks
no.
VLSI LAB 10ECL77, BGSIT B S BALAJI, ASST. PROF, BGSIT
Introduction to VLSI
VLSI stands for “Very Large Scale Integration” circuits. This is the field which involves
packing more and more logic devices into smaller and smaller areas. It is the process of
creating integrated circuits by combining thousands of transistors into a single chip. VLSI
began in the 1970’s, when complex semiconductor and communication technologies were
being developed. The microprocessor is a VLSI device.
A typical digital design flow is as follows: Specification, Architecture, RTL Coding, RTL
Verification, Synthesis, Backend and Tapeout to boundary to the end product. This process is
repeated on the silicon wafer to identical ICs.
Introduction to Cadence Digital Design
Cadence is an Electronic Design Automation (EDA) environment that allows integrating in a

single framework. Different applications and tools (both proprietary and from other vendors),
allowing to support all the stages of IC design and verification form a single environment.
These tools are completely general supporting different fabrication technologies. When a
particular technology is selected, a set of configuration and technology related files are
employed for customizing the Cadence environment. This set of files is commonly referred as
a design kit.
In the Digital design process, the following Cadence tools are used. Simulating the design –
NC Launch – outcome is Simulation waveform. Logical Synthesis – RTL Compiler – Netlist
and SDC files.
NC Launch is a Graphical User Interface (GUI) that helps you to manage a large design
projects and lets you to configure and launch your Cadence Simulation tools – NC Sim.
RTL Compiler is a powerful tool for logic synthesis and analysis for digital designs. It is
fully compatible with all other Cadence tools and especially with Cadence Encounter which
is mainly used for Physical Design Automation.
1
List of Commands
//Directory
1. mkdir TEST – creates a directory (folder) by name – TEST.

2. pwd – Present Working Directory – displays the current working directory.
3. ls – displays the directory contents consisting of directory and files as a list.
4. cd TEST – changes to new directory path and makes TEST as current directory.
5. rmdir TEST – removes the directory TEST.
6. cd .. – changes the directory path and makes previous directory1 as current directory.
7. cd ../.. - changes the directory path and makes previous directory1/directory2 as
current directory.
//Files
1. vi file1.v – creates a new file (file1.v).

2. cp file1.v file2.v – copies the contents of file1.v to file2.v. (press y to confirm it)
3. rm file1.v – removes the file (file1.v).
Please note Directory name does not have extension like TEST but file name has an
extension file1.v.
Experimental procedures for Digital design in VLSI Lab
//Using NC Launch
1. Right click on directory - /Desktop/Digitallab (folder) – open in Terminal.

2. pwd – displays the present working directory – shows the current location in the
directory tree.
3. ls – list all files in the current directory.
4. mkdir student_name – create a directory in your name (student_name).
5. cd student_name – changes the directory path and makes student_name as current
directory.
6. pwd – displays the current working directory - /Desktop/Digitallab/student_name.
7. mkdir inverter – create a directory in the program name like inverter.
8. cd inverter - changes the directory path and makes inverter as current directory.
2
9. pwd – displays current working directory -

/Desktop/Digitallab/student_name/inverter.
10. vi inverter.v – creates a new file and press I to insert or type the program.
11. Press ESC key (to exit from Insert mode) and Type :wq (pressing shift key + : key)
in command mode to save and quit (close) the program.
12. csh – command is used to invoke and runs C shell.
13. source /cad/cshrc – source evaluates a file and indicates the directory path
(/cad/cshrc) containing cshrc file (as a TCL script) consisting to the cadence tools.
14. * Welcome to Cadence tools Suite* (If this line exists then there is no need to enter
12 & 13 commands once again. If terminal window is closed then please repeat 12 &
13 commands).
15. nclaunch –new & - opens a nclaunch tool window.
16. Select MULTIPLE STEP.
17. Create CDS.lib - save and Ok.
18. Select the file (inverter.v) – Tools – Verilog compiler - ok.
19. Select the module (tb.v) in worklib – Tools – Elaborate – ok.
20. Select your snapshot – Tools – Simulation – ok.
21. NC Simvision window – Select testbench (tb) – select the input and output signals,
right click – select – send to waveform window.
22. Waveform window – Run.
23. Check the result and verify it w.r.t truthtable.
//RTL Compiler
1. Go to the directory path (/Desktop/Digitallab/student_name/inverter) and open in

terminal window.
2. Open verilog code (inverter.v) in terminal window.
3. Remove the test bench code (module tb( );) from your code (inverter.v).
4. csh - command is used to invoke and runs C shell.
5. source /cad/cshrc - source evaluates a file and indicates the directory path
(/cad/cshrc) containing cshrc file.
6. *Welcome to Cadence tools Suite* (If this line exists then there is no need to enter
4 & 5 commands once again. If terminal window is closed then please repeat 4 & 5
commands).
7. rc –gui – command invokes the Cadence encounter and RTL compiler tool.
3
8. set_attr lib_search_path /cad/FOUNDRY/digital/180nm/dig/lib

9. set_attr hdl_search_path /Desktop/Digitallab/student_name/inverter
10. set_attr library slow.lib
11. read_hdl -v2001 {inverter.v}
12. elaborate
13. synthesize -to_generic
14. synthesize -to_mapped
15. write_hdl -generic
16. write_hdl -mapped
17. write_hdl> /Desktop/Digitallab/student_name/inverter/inverter_net.v
18. write_sdc> /Desktop/Digitallab/student_name/inverter/inverter_net.sdc
19. gui_show (or)
20. goto the RTL compiler window – File – Update GUI – displays the RTL schematic
design.
4
1. INVERTER
Aim: Write a verilog code for an Inverter circuit and its test bench code for verification,
observe the waveform and synthesize the code.
Objective: To design an inverter in verilog and synthesis the code with RTL compiler.
Tools: NClaunch for compiling and generation of netlist, NC Sim for simulation and RTL
Compiler for Synthesis.
Design Description: Inverter circuit is a Not gate consisting of one input and one output. It
inverts or complements the value applied at the input (a) and the complemented value is
given to output (y). If the input (a) is 1 and the output (y) is 0 (or) vice versa. The input and
output is a bit value i.e., 0 or 1 as shown in truth table.
Applications:
CMOS Inverter is used in digital logic devices for its fast switching operations to change the
voltage from one state to another.
Symbol:
Circuit diagram:
5
Truth table:
Input (a) Output (y)

0 1
1 0
Verilog code:
Verilog Test bench code:
6
Nclaunch tool:
Simulation waveform:
7
RTL Compiler command:
RTL Netlist:
8
RTL Schematic design:
Result: Simulation and RTL Schematic design is done using NClaunch, NCSim and RTL
compiler using Test bench code file and Standard design constraint file generated for an
Inverter is verified based on truth table.
9
2. BUFFER
Aim: Write a verilog code for a Buffer circuit and its test bench code for verification, observe
the waveform and synthesize the code.
Objective: To design a Buffer in verilog and synthesis the code with RTL compiler.
Design Description: a special logic gate called a buffer is manufactured to perform the same
function as two inverters. Its symbol is simply a triangle, with no inverting “bubble” on the
output terminal. Two inverter, or NOT, gates connected in “series” so as to invert, then re-
invert, a binary bit perform the function of a buffer. Buffer gates merely serve the purpose of
signal amplification: taking a “weak” signal source that isn’t capable of sourcing or sinking
much current, and boosting the current capacity of the signal so as to be able to drive a load.
Buffer circuits are symbolized by a triangle symbol with no inverter “bubble.”
Applications:
Buffer is used to provide delays in on chip interconnects to correct timing issues and
synchronise the signals and also to drive the large capacitive loads.
Symbol:
Circuit diagram:
10
Truth table:
Input (a) Output (y)
0 0
1 1
Verilog code:
11
Nclaunch tool:
12
RTL Netlist:
13
compiler using Test bench code file and Standard design constraint file generated for a Buffer
is verified based on truth table.
14
3. TRANSMISSION GATE
Aim: Write a verilog code for a Transmission gate circuit and its test bench code for
verification, observe the waveform and synthesize the code.
Objective: To design a Transmission gate circuit in verilog and simulate the code.
Tools: NClaunch for compiling and generation of netlist, NC Sim for simulation.
Design Description: Transmission gate is a analog switch and is a parallel connection of
nMOS and pMOS with complementary inputs to both MOSFETs (see circuit diagram).
Bidirectional, it carries current in either direction. Depending on the voltage on the gate, the
connection between the input and output is either low-resistance or high-resistance, so that
Ron = 100 Ω or less and Roff > 5 MΩ. This effectively isolates the output from the input.
Whenever both nMOS and pMOS are turned on, any signal '1' or '0' passes equally well
without degradation. The use of transmission gates eliminates undesirable threshold voltage
effects which give rise to loss of logic levels.
Applications: Transmission gates are typically used as building blocks for logic circuitry,
such as a D Latch or D Flip-Flop. As a stand-alone circuit, a transmission gate can isolate a
component or components from live signals during hot insertion or removal. In a security
application, they can selectively block critical signals or data from being transmitted without
proper hardware-controlled authorization.
Symbol:
Circuit diagram:
15
Truth table:
CONTROL INPUT OUTPUT

pMOS (cnt1) nMOS (cnt2) a b
0 0
0 1
1 1
0
1 0 Z
1
Verilog code:
16
Nclaunch tool:
Result: Simulation is done using NClaunch and NCSim using Test bench code file and
Standard design constraint file generated for a Transmission gate is verified based on truth
table.
17
4. LOGIC GATES
Aim: Write a verilog code for all logic gates and its test bench code for verification, observe
the waveform and synthesize the code.
Objective: To design all logic gates in verilog and synthesis the code with RTL compiler.
Design Description:
A logic gate is an elementary building block of a digital circuit. Most logic gates have two
inputs and one output. At any given moment, every terminal is in one of the two binary
conditions low (0) or high (1), represented by different voltage levels. The logic state of a
terminal can, and generally does, change often, as the circuit processes data. In most logic
gates, the low state is approximately zero volts (0 V), while the high state is approximately
five volts positive (+5 V).
There are seven basic logic gates: AND, OR, XOR, NOT, NAND, NOR, and XNOR.
The AND gate is so named because, if 0 is called "false" and 1 is called "true," the gate acts
in the same way as the logical "and" operator. The following illustration and table show the
circuit symbol and logic combinations for an AND gate. (In the symbol, the input terminals
are at left and the output terminal is at right.) The output is "true" when both inputs are "true."
Otherwise, the output is "false."
The OR gate gets its name from the fact that it behaves after the fashion of the logical
inclusive "or." The output is "true" if either or both of the inputs are "true." If both inputs are
"false," then the output is "false."
The XOR ( exclusive-OR ) gate acts in the same way as the logical "either/or." The output is
"true" if either, but not both, of the inputs are "true." The output is "false" if both inputs are
18
"false" or if both inputs are "true." Another way of looking at this circuit is to observe that the
output is 1 if the inputs are different, but 0 if the inputs are the same.
A logical inverter, sometimes called a NOT gate to differentiate it from other types of
electronic inverter devices, has only one input. It reverses the logic state.
The NAND gate operates as an AND gate followed by a NOT gate. It acts in the manner of
the logical operation "and" followed by negation. The output is "false" if both inputs are
"true." Otherwise, the output is "true."
The NOR gate is a combination OR gate followed by an inverter. Its output is "true" if both
inputs are "false." Otherwise, the output is "false."
The XNOR (exclusive-NOR) gate is a combination XOR gate followed by an inverter. Its
output is "true" if the inputs are the same and "false" if the inputs are different.
Applications:
Using combinations of logic gates, complex operations can be performed. In theory, there is
no limit to the number of gates that can be arrayed together in a single device.
But in practice, there is a limit to the number of gates that can be packed into a given physical
space. Arrays of logic gates are found in digital integrated circuits (ICs).
As IC technology advances, the required physical volume for each individual logic gate
decreases and digital devices of the same or smaller size become capable of performing ever-
more-complicated operations at ever-increasing speeds.
19
Symbol & Truth table:
20
Verilog code:
21
Nclaunch tool:
22
RTL Netlist:
23
compiler using Test bench code file and Standard design constraint file generated for all
Logic gates is verified based on truth table.
24
5. FLIPFLOPS – SR, JK, D, T, MS.
Aim: Write a verilog code for all flipflops and its test bench code for verification, observe the
waveform and synthesize the code.
Objective: To design a flipflops in verilog and synthesis the code with RTL compiler.
Design Description: A digital computer needs devices which can store information. A flip
flop is a binary storage device. It can store binary bit either 0 or 1. It has two stable states
HIGH and LOW i.e. 1 and 0. It has the property to remain in one state indefinitely until it is
directed by an input signal to switch over to the other state. It is also called bistable
multivibrator. It is used mainly in three situations such as operations, storage and sequencing.
Flip-flops can be either simple (transparent or asynchronous) or clocked (synchronous); the

transparent ones are commonly called latches. The word latch is mainly used for storage
elements, while clocked devices are described as flip-flops. Flip-flops can be divided into
common types: the SR ("set-reset"), D ("data" or "delay"), T ("toggle"), and JK (Jack &
Kilby) flipflops.
SR flip-flop: The SR flip-flop is a basic building block for other flip-flops. The RS latch
flip-flop required the direct input but no clock. It is very use full to add clock to control
precisely the time at which the flip-flop changes the state of its output.
In the clocked SR flip-flop the appropriate levels applied to their inputs are blocked till the
receipt of a pulse from another source called clock. The flip-flop changes state only when
clock pulse is applied depending upon the inputs.
While the R and S inputs are both low, feedback maintains the Q and Q outputs in a constant
state, with Q the complement of Q. If S (Set) is pulsed high while R (Reset) is held low, then
the Q output is forced high, and stays high when S returns to low; similarly, if R is pulsed
25
high while S is held low, then the Q output is forced low, and stays low when R returns to
low.
The R = S = 1 combination is called a restricted combination or a forbidden or indeterminate

state because, as both NOR gates then output zeros, it breaks the logical equation Q = not Q.
The combination is also inappropriate in circuits where both inputs may go low
simultaneously (i.e. a transition from restricted to keep). The output would lock at either 1 or
0 depending on the propagation time relations between the gates (a race condition).
D flip-flop: The D ﬂip-ﬂop is widely used. It is also known as a "data" or "delay" flip-flop.
The D flip-flop captures the value of the D-input at a definite portion of the clock cycle (such
as the rising edge of the clock). That captured value becomes the Q output. At other times,
the output Q does not change. The D flip-flop can be viewed as a memory cell, a zero-order
hold, or a delay line.
These flip-flops are very useful, as they form the basis for shift registers, which are an
essential part of many electronic devices. The advantage of the D flip-flop over the D-type
"transparent latch" is that the signal on the D input pin is captured the moment the flip-flop is
clocked, and subsequent changes on the D input will be ignored until the next clock event. An
exception is that some flip-flops have a "reset" signal input, which will reset Q (to zero), and
may be either asynchronous or synchronous with the clock.
JK flip-flop: The JK flip-flop augments the behavior of the SR flip-flop (J=Set, K=Reset) by
interpreting the J = K = 1 condition as a "flip" or toggle command. Specifically, the
combination J = 1, K = 0 is a command to set the flip-flop; the combination J = 0, K = 1 is a
command to reset the flip-flop; and the combination J = K = 1 is a command to toggle the
flip-flop, i.e., change its output to the logical complement of its current value. Setting J = K =
0 maintains the current state. To synthesize a D flip-flop, simply set K equal to the
complement of J. Similarly, to synthesize a T flip-flop, set K equal to J. The JK flip-flop is
therefore a universal flip-flop, because it can be configured to work as an SR flip-flop, a D
flip-flop, or a T flip-flop.
T flip-flop: T stands for toggling. It is obtained from JKFF of SRFF by shorting both the
inputs J and K. A method of avoiding the indeterminate state found in the working of SR flip
26
flop is to provide only one input (T input) such, flip-f lop acts as a toggle switch or T Flip-
flop. Toggle means to change in the previous stage i.e. switch to opposite state.
If the T input is high, the T flip-flop changes state ("toggles") whenever the clock input is
strobed. If the T input is low, the flip-flop holds the previous value. When T is held high, the
toggle flip-flop divides the clock frequency by two; that is, if clock frequency is 4 MHz, the
output frequency obtained from the flip-flop will be 2 MHz. This "divide by" feature has
application in various types of digital counters. A T flip-flop can also be built using a JK flip-
flop (J & K pins are connected together and act as T) or a D flip-flop (T input XOR
Qprevious drives the D input).
A disadvantage of the toggle flip flop is that the state of the flip flop after a trigger pulse has
been applied is only known if the previous state is known.
MS JK flip-flop: A master slave flip flop contains two clocked flip flops. The first is called
Master and the second is Slave. When the clock is low the master is active. The output of the
master is set or reset according to the state of the input. As the slave is inactive during this
period its output remains in the previous state. When clock becomes high the output of the
slave flip flop changes because it become active during high clock period. The final output of
master slave flip flop is the output of the slave flip flop. So the output of master slave flip
flop is available at the end of a clock pulse.
Applications:
• Event Detect
• Data Synchronizer
• Data storage
• Data transfer
• Frequency Divider
• Shift Register
• Asynchronous (Ripple) Counter
• Synchronous (Parallel) Counter.
27
Symbol:
Truth table:
28
SR Flip Flop:
Verilog code:
29
Nclaunch tool:
30
RTL Netlist:
31
32
JK Flip flop:
Verilog code:
33
Nclaunch tool:
34
RTL Netlist:
35
36
D Flip flop:
Verilog code:
37
Nclaunch tool:
38
RTL Netlist:
39
40
T Flip flop:
Verilog code:
41
Nclaunch tool:
42
RTL Netlist:
43
44
MS JK Flip flop:
Verilog code:
45
Nclaunch tool:
46
RTL Netlist:
47
compiler using Test bench code file and Standard design constraint file generated for all the
flipflops is verified based on truth table.
48
6. PARALLEL AND SERIAL ADDER
Aim: Write a verilog code for a Parallel and Serial adder circuit and its test bench code for
verification, observe the waveform and synthesize the code.
Objective: To design Parallel and Serial adder in verilog and synthesis the code with RTL
compiler.
Design Description:
Full Adder - The half adder adds two single binary digits A and B. It has two outputs, sum
(S) and carry (C). The carry signal represents an overflow into the next digit of a multi-digit
addition. The value of the sum is 2C + S. The simplest half-adder design, pictured on the
right, incorporates an XOR gate for S and an AND gate for C. With the addition of an OR
gate to combine their carry outputs, two half adders can be combined to make a full adder.
The half-adder adds two inputs bits and generate carry and sum which are the two outputs of
half-adder.
Symbol:
49
Truth table:
Parallel adder or Ripple carry adder:
It is possible to create a logical circuit using multiple full adders to add N-bit numbers. Each
full adder inputs a Cin, which is the Cout of the previous adder. This kind of adder is called a
Parallel adder or ripple-carry adder, since each carry bit "ripples" to the next full adder. Note
that the first (and only the first) full adder may be replaced by a half adder.
The layout of a ripple-carry adder is simple, which allows for fast design time; however, the
ripple-carry adder is relatively slow, since each full adder must wait for the carry bit to be
calculated from the previous full adder. The gate delay can easily be calculated by inspection
of the full adder circuit.
50
Full adder
Verilog code:
51
Nclaunch tool:
52
RTL Netlist:
53
54
Parallel adder
Verilog code:
55
Nclaunch tool:
56
RTL Netlist:
57

Full adder:
58
Parallel adder:
59
Serial Adder
Serial binary addition is done by a flip-flop and a full adder. The flip-flop takes the carry-out
signal on each clock cycle and provides its value as the carry-in signal on the next clock
cycle. After all of the bits of the input operands have arrived, all of the bits of the sum have
come out of the sum output.
Example
Decimal 5+9=14
X=5, Y=9, Sum=14
Binary 0101+1001=1110
Addition of each step
Inputs Outputs
Cin X Y Sum Cout
0 1 1 0 1
1 0 0 1 0
0 1 0 1 0
0 0 1 1 0
*addition starts from lowest
Result=1110 or 14
60
Serial adder
Verilog code:
61
Nclaunch tool:
62
compiler using Test bench code file and Standard design constraint file generated for Parallel
and Serial adder is verified based on truth table.
63
7. 4 BIT COUNTER [SYNCHRONOUS AND

ASYNCHRONOUS COUNTER]
Aim: Write a verilog code for a 4 bit Synchronous and Asynchronous counter and its test
bench code for verification, observe the waveform and synthesize the code.
Objective: To design a 4 bit Synchronous and Asynchronous counter in verilog and synthesis
the code with RTL compiler.
Design Description: In digital logic and computing, a counter is a device which stores (and
sometimes displays) the number of times a particular event or process has occurred, often in
relationship to a clock signal. The most common type is a sequential digital logic circuit with
an input line called the "clock" and multiple output lines. The values on the output lines
represent a number in the binary or BCD number system. Each pulse applied to the clock
input increments or decrements the number in the counter.
A counter circuit is usually constructed of a number of flip-flops connected in cascade.

Counters are a very widely used component in digital circuits, and are manufactured as
separate integrated circuits and also incorporated as parts of larger integrated circuits.
Asynchronous counter
An asynchronous (ripple) counter is a single d-type flip-flop, with its J (data) input fed from
its own inverted output. This circuit can store one bit, and hence can count from zero to one
before it overflows (starts over from 0). This counter will increment once for every clock
cycle and takes two clock cycles to overflow, so every cycle it will alternate between a
transition from 0 to 1 and a transition from 1 to 0.
Ripple counters suffer from unstable outputs as the overflows "ripple" from stage to stage,
but they do find frequent application as dividers for clock signals, where the instantaneous
count is unimportant, but the division ratio overall is (to clarify this, a 1-bit counter is exactly
64
equivalent to a divide by two circuit; the output frequency is exactly half that of the input
when fed with a regular train of clock pulses).
Synchronous counters
In synchronous counters, the clock inputs of all the flip-flops are connected together and are
triggered by the input pulses. Thus, all the flip-flops change state simultaneously (in parallel).
Synchronous counters can also be implemented with hardware finite-state machines, which
are more complex but allow for smoother, more stable transitions.
Decade counters
A decade counter is one that counts in decimal digits, rather than binary. A decade counter
may have each (that is, it may count in binary-coded decimal, as the 7490 integrated circuit
did) or other binary encodings. "A decade counter is a binary counter that is designed to
count to 1010b (decimal 10).
Ring counters
A ring counter is a circular shift register which is initiated such that only one of its flip-flops
is the state one while others are in their zero states.
A ring counter is a shift register (a cascade connection of flip-flops) with the output of the
last one connected to the input of the first, that is, in a ring. Typically, a pattern consisting of
a single bit is circulated so the state repeats every n clock cycles if n flip-flops are used.
Johnson counters
A Johnson counter (or switch-tail ring counter, twisted ring counter, walking ring counter, or
Möbius counter) is a modified ring counter, where the output from the last stage is inverted
and fed back as input to the first stage. The register cycles through a sequence of bit-patterns,
whose length is equal to twice the length of the shift register, continuing indefinitely. These
counters find specialist applications, including those similar to the decade counter, digital-to-
analog conversion, etc. They can be implemented easily using D- or JK-type flip-flops. It is
also known as twisted ring counter.
A twisted ring counter, also called switch-tail ring counter, walking ring counter, Johnson
counter (from using Libaw-Craig code (de) aka Johnson code (de), named after Robert
Royce Johnson - the patent holder) connects the complement of the output of the last shift
register to the input of the first register and circulates a stream of ones followed by zeros
65
around the ring. For example, in a 4-register counter, with initial register values of 0000, the
repeating pattern is: 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000...
Application - Counters are useful for digital clocks and timers, and in oven timers, VCR
clocks, etc.
Symbol:
Circuit diagram:
4 bit Synchronous Counter
4 bit Asynchronous Counter
66
Truth table:
67
Synchronous Counter (Up Counter)

Verilog code:
68
Nclaunch tool:
69
RTL Netlist:
70
71
Synchronous Counter (Down Counter)

Verilog code:
72
Nclaunch tool:
73
RTL Netlist:
74
75
Asynchronous Counter (Up Counter)

Verilog code:
76
Nclaunch tool:
77
RTL Netlist:
78
79
Asynchronous Counter (Down Counter)

Verilog code:
80
Nclaunch tool:
81
RTL Netlist:
82
compiler using Test bench code file and Standard design constraint file generated for a 4 bit
Synchronous and Asynchronous counter is verified based on truth table.
83
Introduction to Cadence Analog design lab

CMOS technology is prevalent in integrated circuit (IC) designs nowadays, due to the
wide availability of highly specified, low cost processes. Cadence is a popular industrial
design environment that provides designers an all-in-one tool to implement each stage of
the IC design and verification flows, as shown in Fig. 1.
The intention of this handout is to introduce new designers to the Cadence design
environment, and to describe all the steps for running the Cadence tools at the
Department of EC&E in the B G S Institute of Technology. A CMOS Inverter is provided
as an example to illustrate the entire design flow. At end of this lab, each designer is
expected to implement each step of the example, and will be assessed according to the
familiarity of the Cadence design environment and the completeness of designing the
example.
Figure 1. Analogue IC design flow and Cadence tools involved.
84
List of Commands
//Directory
1. mkdir TEST – creates a directory (folder) by name – TEST.
2. pwd – Present Working Directory – displays the current working directory.
3. ls – displays the directory contents consisting of directory and files as a list.
4. cd TEST – changes to new directory path and makes TEST as current directory.
5. rmdir TEST – removes the directory TEST.
6. cd .. – changes the directory path and makes previous directory1 as current directory.
7. cd ../.. - changes the directory path and makes previous directory1/directory2 as current
directory.
Replace or Rename TEST with Analoglab as a directory.
//Files
1. vi file1.v – creates a new file (file1.v).
2. cp file1.v file2.v – copies the contents of file1.v to file2.v. (press y to confirm it)
3. rm file1.v – removes the file (file1.v).
Please note Directory name does not have extension like TEST but file name has an
extension file1.v.
Lab getting started:

Login to your system using the username and password.
Right click on the desktop to access the terminal window
In a terminal window, type csh at the command prompt to invoke C shell.
#mkdir analoglab
#cd analoglab
#mkdir student_name
#cd student_name
#csh
#source /cad/cshrc file contains paths to the cadence installation.
#Welcome to Cadence tools suite
#virtuoso &
85
The virtuoso or Command Interface Window (CIW) appears at the bottom of the
screen. Close this (What’s New in IC6.1.6 Overview) window by clicking on <file> and
then <close>.
If the “What’s New…” window appears, close it with the File-Close command.
Keep opened CIW Virtuoso window for the labs.
86
General Procedures
1. Creating a new Library : In CIW Virtuoso window,
Click File-New-Library. New library window will open.
Create your own library by typing some name in the library name field. For example –
mylab1 as library.
Add the created library to the existing library by selecting option “Attach an existing
technology library” and click ok.
In the “Attach Design Library to technology file” form, select gpdk180 from the
cyclic field and click ok
87
Creating a Schematic Cellview:

In the CIW or Library manager, execute File-New-Cellview.
Setup the new file form.
* Click on <tools> and then <library manager> to start the library manager. This came up
automatically in the old system, but not in this one.
* Click on <file> then cursor over to <new> then to <library> and click <library>.
* Then click OK at the bottom. A screen will pop up asking which library to select.
* Select the gpdk180 option by clicking in the list. click on OK.
* Select the new library by clicking on the name – mylab1
You may not get the little pink box. It appears when you leave the cursor there for a
period of time.
88
For practice, the tutorial will now create an inverter, and walk through the steps of
simulating it. First, create the schematic. Click on <file> then cursor over to <new> then
to <cell view>
A small menu <New File> should pop up.
Click ok. A blank schematic editor window appears.
89
3. Adding Components to Schematics:

In the schematic editor window click create-instance-browse. This opens up a
library browser from which you can select the components and the symbol view.
After you complete the add instance form, move your cursor to the schematic window
and click left to place a component. If you place a component with wrong parameter
values, use the Edit-Properties-Objects command to change the parameter. Use
Edit-Move command if you place components in the wrong location. You can rotate
components using Edit-Rotate command.
90
After entering components, click cancel in the Add instance form or press Esc.
Similarly place the required components in the schematic editor window.
4. Adding sources to the schematic:

In the schematic editor window click create-instance-browse. This opens up again a
library browser from which you can select the sources and the symbol view.
91
Select vdd and gnd from the library browser and place it in the schematic editor
window. After placing the sources, click cancel in the Add instance form or press
Esc.
5. Adding Pins to Schematic:

In the schematic editor window click create-pins This opens up again a library
browser from which you can select the pins.
Name the input pin and select the input in the direction field and place it in the
schematic editor window similarly repeat the same steps and place the output pin
Press ESC
6. Adding Wires to a Schematic:

Click the wire (narrow) icon in the schematic window.
In the schematic window, click on a pin of one of your components as the first point
for your wiring. A diamond shape appears over the starting point of this wire.
Follow the prompts at the bottom of the design window and click left on the
destination point for your wire. A wire is routed between the source and destination
points.
Complete the wiring as shown in figure and when done wiring press ESC key in the
schematic window to cancel wiring.
* Click the Check and Save icon in the Schematic editor window.
* Observe the CIW output area for any errors.
92
After the completion of Inverter design. Click on File – check and save. Check the
status in Virtuoso window.
Symbol Creation:
In the schematic window, run Create -Cellview -From Cellview.
The Cellview form appears.as shown below and press ok
93
Verify library name, cell name, and check the To View Name field is set to
symbol, Click ok.
Modify the pin specification.( if necessary for top and bottom pins)
And Click ok.
94
Editing a Symbol:
Select delete option and delete all the rectangles present in the window except pins and
pin names
Set the input and output pins to the required position as shown in the figure
Draw the symbol for the respective circuit by selecting Create-Shape-Line/Circle etc. After
creating the shape press ESC key.
95
Draw the circle using Create-Shape-Circle. After creating the shape press ESC key.
Draw the triangle using Create-Shape-line. After creating the shape press ESC key.
96
Click on Create – Label to add name to the symbol.
After the completion of Inverter symbol. Click on File – check and save. Check the
status in Virtuoso window.
97
After creating symbol, click on the save icon in the symbol editor window to save the
symbol. In the symbol editor, click on File select Close option toclose the symbol view
window and schematic window.
To create the Test circuit:
In the CIW again, click on File – New Cellview and give different name in the cell field
and click ok and select your library in the library field.
98
Again a new schematic editor window will gets open. Click ok. A blank schematic editor
window appears.
In this window click, Create instance browse select your library name and select
inverter and symbol in the corresponding field and press close
Then place the symbol into the schematic editor window
99
Provide the input voltage to the test circuit by selecting Vpulse under analoglib in Library
window using the following steps.
Create-instance–browse–Select analoglib-Vpulse-symbol- close.
Then set the specifications for Vpulse as
Voltage1=0 Period=20n
Voltage2=5 Pulsewidth=10n
Risetime=1n
Falltime=1n
 Click hide and place the symbol near the input terminal in the test circuit. Select
wire option and connect one terminal of Vpulse to the schematic symbol input
terminal and the other terminal to gnd. Then create one output pin as create-
100
pin-enter pin name-set pin direction as output-click ok-place near the output
terminal and connect pin to the output terminal using wire.
 After selecting place them in the appropriate position as shown in the figure.
To create biasing circuit select biasing voltage VDC by following the steps
Create-instance-browse-analoglib-select-VDC-symbol-close.Then set the

properties of Vdc as dc voltage=5, shown below.
Create-instance-browse-analoglib-vdd-close
Create-instance-browse-analoglib-gnd-close
101
In the schematic editor window click create-pins – Vout as output pin.
 Select Gnd and VDD symbol from analoglib library by following the steps Create-
instance-browse-analoglib-Vdd-symbol-closeinstance-browse-analoglib-gnd-symbol-
close.
102
Click the Check and Save icon in the Schematic editor window. Observe the CIW output
area for any errors. Finally the test circuit and biasing circuit is ready for simulation as
shown below.
103
Simulation with Spectre :
In the schematic window, run Launch-ADEL, the following window will appears.
104
In the simulation window click on setup-Model Libraries tab and Click ok.
Click the Analysis icon tab in the ADE-L window and select the Choose
To setup for transient analysis select tran icon, set the StopTime for 100n click at
the moderate or enabled button at the bottom, click Apply and OK.
105
To setup for DC analysis select dc, turn on Save DC Operating Point. Turn on the
Component Parameter. Double Click on the select Component, which takes you to
the schematic window. Select input signal, Vpulse and select component parameter
as DC. Set start time= 0 and stop time = 5 voltages. Click Apply and ok.
Selecting outputs for plotting:
Execute Outputs –To be plotted – Select on Schematic in the simulation window.
Follow the prompt at the bottom of the schematic window, click on the output net,
input net of the design. Press ESC with the cursor in the schematic after selecting it.
106
Execute Simulation-Netlist and Run to start the simulation.
107
Creating a Layout view:

From the schematic window menu run Launch- Layout XL. A startup Option form
appears.
 Select Create New option.
 Check the cell name, View name. Click ok.
108
 Adding Components toLayout:

 Execute Connectivity-Generate-All from Source. Generate Layout window
appears. Click ok, which imports the schematic components into the layout
window automatically.
To rotate a component, select the component and execute Edit-properties. Now select
the degree of rotation.
To move a component, select the component and execute Edit-Move command.

109
Making Interconnection:
 Execute Connectivity-Nets-Show/Hide Selected incomplete nets. The

equivalent operation can be obtained by pressing “Shift + f” key from the
keyboard.
110
 From the layout window execute Create-Shape-Path or Create-Shape-

Rectangle and select the appropriate layers from the LSW window and
Vias for makinginterconnections.
 The blue box is for place and route, and isn't needed at this time. Click on it.
When it selects white, click on <edit> then <delete> . It should go away. After
press the escape key to exit delete mode.
 Now, move the P, and the pins with the Vdd above the P and the ground below the
N. I placed the output pin (Z) to the right of the transistors.
 Now save the design by clicking on the floppy disk symbol in the layout window.
 Click on the magnifying glass icon and if required >> then zoom to fit. You
should now have something like:
111
It highlights the connection in schematic design and layout window.
112
113
It highlights the connection in schematic design and layout window. Input a.
It highlights the connection in schematic design and layout window. output y.
114
Creating Contacts/Vias:
Execute Create-Via to place different contacts as given in the table below.
Connection Contact Type
For Metal1-Poly Metal1-Poly (Gate)
For Metal1-P substrate Metal1-Psub (Gnd)
For Metal1-Nwell Metal1-Nwell (Vdd)
Under via definition, use the red pull down arrow, and select m1_nwell, place vdd! As the net
name. Move to the layout and place the contact above the P transistor.
115
Under via definition, use the red pull down arrow, and select m1_psub, place gnd! As the net
name. Move to the layout and place the contact below the N transistor.
116
 The gate terminal of pmos and nmos are connected using “poly” and input
terminal is connected through via“M1_POLY”.
 The drain terminal of nmos and pmos are connected using “metal1” and the
output terminal is placed.
 The source terminal of pmos is connected to vdd through “metal1” and the
pmosiscoveredbyn-wellandvia“M1_NWELL”is placed near the vdd.
The source terminal of nmos is connected to vss through metal1 and
via“M1_PSUB” is placed near vss.
Save the design by selecting File – Save.
117
It is now time to set up the Assura for DRC and LVS. We will not be using the DIVA
DRC or LVS with this technology. (You will like Assura more as you get used to it).
First, click on <Assura> and then on <Technology> Type in the name of the assura
library as shown below:
118
Running DRC:
Select Assura-Run DRC from Layout Window. The DRC form appears. The
Library and cell name are taken from the current design window, but rule file may
be missing.
Select the technology as gpdk180. This automatically loads the rule file.
Click ok to start DRC. A progress form will appear. You can click on the watch
clock file to see the Log file.
When DRC finishes, a dialog box appears, Click Yes to view the results.
If there are any DRC error exits in the design View Layer Window (VLW) and
Error Layer Window (ELW) appears. Also the errors highlight in the design itself.
Click View – Summary in the ELW to find the details of errors.
• You can refer to rule file also for more information, correct all DRC errors and
Re – run the DRC.
• If there are no errors in the layout then a dialog box appears with No DRC errors
found written in it, Click on close to terminate the DRC run.
click OK. It will take a while. If you get a message:
119
Just click OK. If not, don't worry about it.
You may get some overwrite windows. Eventually, you will get a screen saying there
were no errors, or most likely, an error screen such as:
Each error is explained. If you click on an error, it will show the problem on the layout.
These come from not having a proper N-Well. I'll add a rectangle of N-Well to the layout.
Click <create> then <shape> then <rectangle> On the LSW screen, select Nwell. Click on
one corner, and drag to the other corner. Release the mouse. I moved the contact higher in
the well. You should have:
120
Click the save floppy, then run the DRC again.
121
I still have one error. Select the error, and then click on <Show Error by> and then <Edit
in Place> . The error will show up on the layout. This is my example:
After error correction in the design. Click the save floppy, and then run the DRC again.
122
The DRC is now OK.
123
ASSURA LVS:
• Select Assura-Run LVS from the layout window. The Assura Run LVS
form appears, it will automatically load both the schematic and layout view of
the cell.
• Click OK. The LVS begins and a progress form appears.
 If the schematic and layout matches completely, you will get the form
displaying Schematic and Layout Match.
 If the schematic and Layout do not matches, a form informs that the LS
completed successfully and results form will appear, click YES in the form.
 In the LVS debug form, find the details of mismatches and correct all those
mismatches and Re-Run the LVS.
124
Change the technology to gpdk180, and then click OK.
125
126
You can click yes to see the screens generated. If there were errors, this screen would
help find them.
127
ASSURA RCX:
1. From the layout window execute Assura – Run RCX.
2. Change the Assura Parasitic Extraction form, select Output Type
under Setup tab of theform.
3. In the Extraction tab of the form, choose Extraction type, Cap
coupled mode and specify the reference node for extraction.
4. In the filtering tab of the form, Enter Power Nets as Vdd!, Vss! and
Enter Ground Nets as gnd!
5. Click ok. The RCX progress form appears, in the progress form click
Watch logfile
to see the output log file.
6. When RCX completes, a dialog box appears, shows Assura RCX
Run completed successfully.
7. Open the av_extracted view from the Library manager and view the
parasitic.
128
129
130
131
132
Configuration View:
1. In the CIW or Library manager, execute File-New-Cellview.
2. Click ok in Create New File form. The Hierarchy editor form
opens and a New Configuration form opens in front ofit.
3. ClickUsetemplateatthebottomoftheNewConfigurationformandselectSpe
ctre in the cyclic field and click ok.
4. Change the Top Cell view to schematic and remove the default
entry from the Library Listfield.
5. Click ok. The Hierarchy editor displays the Hierarchy for the design
using table format.
6. Click the Tree View tab. The Design hierarchy changes to Tree
format. Save the currentconfiguration.
7. Close the Hierarchy window, execute File-Closewindow.
To run the circuit without parasites:
1. From the Library manager open cell config view.
2. In the form, turn on the both cyclic buttons to Yes and click ok.
3. Execute Launch-ADE L from the schematic window.
4. Follow the same procedure for running the simulation. Execute Session-
Load state.
5. Click Netlist and Run icon to start the simulation.
6. In the CIW, note the netlisting statistics in the circuit inventory
section. This list includes all nets, design devices, source and loads.
There are no parasitic components.
133
1. INVERTER
Aim : To design an Inverter with given specifications and verify the design as mentioned
below.
Schematic Design – i) DC Analysis, ii) Transient Analysis.
Layout Design – i) DRC & ERC, ii) LVS, iii) RCX.
Specification:
Library name Cell name Properties
gpdk180 pmos W=2u, L=180n
gpdk180 nmos W=2u, L=180n
Pin details:
Pin Names Direction

A Input
Y Output
Inverter Schematic Design:
134
Inverter symbol:
Inverter test_bench Schematic design:
Specifications:

V1=0, V2=5, td=0, tr=tf=1n,
Analoglib Vpulse
ton=10n,T=20n
Analoglib Vdd Vdc=5
135
Analysis:
Transient Analysis: Stop time = 100n, moderate
DC Analysis: Save DC operating point, Component Parameter,

Select the component – Vpulse, Parameter – Vdc,
Start = 0, Stop = 5.
Measuring the Propagation Delay:
1. In the waveform window, select Tools – Calculator.

2. From the functions, select delay, this will open the delay data panel.
3. Place the cursor in the text box for signal1, select the wave button and select the
input waveform from the waveform window.
4. Repeat the same for signal2, select the output form.
5. Set the Threshold value1 and Threshold value2.
6. Execute OK and observe the expression created in the calculator.
7. Click on Evaluate the Buffer icon to perform the calculation. Close Calculator
window.
136
Inverter Layout:
Result: The Schematic design of the Inverter is verified and the LVS, RCX is verified
without any error.
137
2. COMMON SOURCE AMPLIFIER
Aim : To design a Common Source Amplifier with given specifications and verify the
design as mentioned below.
Schematic Design – i) DC Analysis, ii) AC Analysis, iii) Transient Analysis.

Specification:
gpdk180 pmos W=50u, L=1u
gpdk180 nmos W=10u, L=1u
Pin details:
Pin Names Direction

vin, vbias Input
vout Output
vdd, vss Input
Common Source Amplifier Schematic Design:
138
Common Source Amplifier symbol:
Common Source Amplifier test_bench Schematic design:
Specifications:

AC Magnitude = 1, Amplitude = 5m, Frequency = 1K,
Analoglib vsin
offset voltage = 0, DC Voltage = 0.
Analoglib vdd, vbias, vss Vdc = 2.5,Vdc = 2.5, Vdc = -2.5
139
Analysis:
Transient Analysis: Stop time = 5m, Moderate

Select the component – Vsin, Parameter – Vdc,
Start = -5, Stop = 5.
AC Analysis: Frequency, Start = 100, Stop = 100M
140
Common Source Amplifier Layout:
Result: The Schematic design of the Common Source Amplifier is verified and the LVS,
RCX is verified without any error.
141
3. COMMON DRAIN AMPLIFIER
Aim : To design an Common Drain Amplifier with given specifications and verify the

Specification:

Pin details:
Pin Names Direction

vin, vbias Input
vout Output
vdd, vss Input
Common Drain Amplifier Schematic Design:
142
Common Drain Amplifier symbol:
Common Drain Amplifier test_bench Schematic design:
Specifications:

Analoglib vsin
Analoglib vdd, vbias, vss Vdc = 2.5, Vdc = 2.5, Vdc = -2.5
143
Analysis:

144
Common Drain Amplifier Layout:
Result: The Schematic design of the Common Drain Amplifier is verified and the LVS,
RCX is verified without any error.
145
4. DIFFERENTIAL AMPLIFIER
Aim : To design an Differential Amplifier with given specifications and verify the

Specification:
gpdk180 pmos Model name (PM0, PM1); W=15u, L=1u
gpdk180 nmos Model name (NM0, NM1); W=3u, L=1u
gpdk180 nmos Model name (NM2, NM3); W=4.5u, L=1u
Pin details:
Pin Names Direction

Idc, V1, V2 Input
vout Output
vdd, vss Input
Differential Amplifier Schematic Design:
146
Differential Amplifier symbol:
Differential Amplifier test_bench Schematic design:
Specifications:

Analoglib vsin
Analoglib vdd, vss Vdc = 2.5, Vdc = -2.5
Analoglib Idc DC Current = 30u
147
Analysis:

148
Differential Amplifier Layout:
Result: The Schematic design of the Differential Amplifier is verified and the LVS, RCX
is verified without any error.
149
5. OPERATIONAL AMPLIFIER
Aim : To design an Operational Amplifier with given specifications and verify the

Specification:
Studentlib Diff_amplifier Symbol
Studentlib CS_amplifier Symbol
Pin details:
Pin Names Direction

Idc, Vinv, Vnoninv Input
Vo Output
vdd, vss Input
Operational Amplifier Schematic Design:
150
Operational Amplifier symbol:
Operational Amplifier test_bench Schematic design:
Specifications:

AC Magnitude = 1, Amplitude = 5u, Frequency = 1K,
Analoglib vsin
Analoglib gnd
Analoglib Idc DC Current = 30u
151
Analysis:

152
Operational Amplifier Layout:
Result: The Schematic design of the Operational Amplifier is verified and the LVS, RCX
is verified without any error.
153
6. R2R DAC
Aim : To design an R2R DAC with given specifications and verify the design as
mentioned below.
Schematic Design – i) DC Analysis, ii) Transient Analysis.

Specification:
gpdk180 polyres R=2k
gpdk180 polyres R=1k
analoglib Idc Idc=30u
Pin details:
Pin Names Direction

D0, D1, D2, D3 Input
vout Output
vdd, vss Input
R2R DAC Schematic Design:
154
R2R DAC symbol:
R2R DAC test_bench Schematic design:
Specifications:
Library Cell name Properties

For V0 (D0): V1=0, V2=2, Ton(pulse
width)=05n,T(Period)=10n
Analoglib vpulse
155
Analysis:
Transient Analysis: Stop time = 300n
R2R DAC Layout:
Result: The Schematic design of the R2R DAC is verified and the LVS, RCX is verified
without any error.
156

VLSI 2017-18 B S Balaji PDF

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

VLSI 2017-18 B S Balaji PDF

Uploaded by

Copyright:

Available Formats

||Jai Sri Gurudev||

Sri Adichunchanagiri Shikshana Trust (R.)

VLSI LAB MANUAL

ACADEMIC YEAR - 2017 -18.

PART – A DIGITAL DESIGN

1. Introduction to VLSI 001

PART – B ANALOG DESIGN

1. Introduction to Cadence analog design lab 084

This is to certify that Kumari / Sri __________________________

Date: ____________ Signature of the Teacher

Head of the Department

Reg. No. _________________________________________

Examination Centre: __________________________

Date of Practical Examination: ______________

Introduction to Cadence Digital Design

Cadence is an Electronic Design Automation (EDA) environment that allows integrating in a

1. mkdir TEST – creates a directory (folder) by name – TEST.

1. vi file1.v – creates a new file (file1.v).

Experimental procedures for Digital design in VLSI Lab

1. Right click on directory - /Desktop/Digitallab (folder) – open in Terminal.

9. pwd – displays current working directory -

1. Go to the directory path (/Desktop/Digitallab/student_name/inverter) and open in

8. set_attr lib_search_path /cad/FOUNDRY/digital/180nm/dig/lib

Input (a) Output (y)

Verilog Test bench code:

RTL Compiler command:

RTL Schematic design:

Verilog Test bench code:

RTL Compiler command:

RTL Schematic design:

CONTROL INPUT OUTPUT

Verilog Test bench code:

Symbol & Truth table:

Verilog Test bench code:

RTL Compiler command:

RTL Schematic design:

5. FLIPFLOPS – SR, JK, D, T, MS.

Flip-flops can be either simple (transparent or asynchronous) or clocked (synchronous); the

The R = S = 1 combination is called a restricted combination or a forbidden or indeterminate

Verilog Test bench code:

RTL Compiler command:

RTL Schematic design:

Verilog Test bench code:

RTL Compiler command:

RTL Schematic design:

Verilog Test bench code:

RTL Compiler command:

RTL Schematic design:

Verilog Test bench code:

RTL Compiler command:

RTL Schematic design:

Verilog Test bench code:

RTL Compiler command:

RTL Schematic design:

6. PARALLEL AND SERIAL ADDER

Parallel adder or Ripple carry adder:

Verilog Test bench code:

RTL Compiler command:

RTL Schematic design:

Verilog Test bench code:

RTL Compiler command:

RTL Schematic design:

X=5, Y=9, Sum=14