AM57x Sitara™ Processors

Technical Deep Dive

ARM Cortex-A15 Solutions for automation,

HMI, vision, imaging, and other industrial
and high-performance applications
Agenda
• AM57x Silicon Overview

• AM57x Processors

• AM57x Peripherals

• AM57x System Architecture

• AM57x EVMs & Tools

AM57x Silicon Overview

AM57x Sitara Processors

Technical Deep Dive
AM57x Product Family
ARM C66x ARM Video Display PRU-ICSS
Cortex-A15 DSP Cortex-M4 Graphics Accel- Sub-
(MHz) (MHz) (MHz) eration system

AM5728 750 750 213 213

213 PRU-ICSS*
1.5GHz 1.5GHz 3D 3D 2D 1080p Yes
MHz MHz MHz MHz
MHz (Quad Core)

AM5726 750 750 213 213 PRU-ICSS*

1.5GHz 1.5GHz

Software Compatible
MHz MHz MHz MHz (Quad Core)
Pin Compatible

AM5718 750 213 213 PRU-ICSS*

1.5GHz 3D 2D 1080p Yes
MHz MHz MHz (Quad Core)

AM5716 750 213 213 PRU-ICSSU*

1.5GHz
MHz MHz MHz (Quad Core)

AM5716 500 500 213 213 PRU-ICSS*

MHz MHz MHz MHz (Quad Core)

PRU-ICSS can be used for industrial communication protocols such as

Profibus, Profinet RT/IRT, EtherCAT, POWERLINK, Ethernet/IP, and more.**
*PRU-ICSS is configured into two dual-core subsystems.
**Support for premium protocols such as EtherCAT or POWERLINK requires ordering a specific part.
AM572x Cortex®-A15-based Processors
High-Speed Interconnect 28 nm

Video Acceleration
PRU (Quad Core)
+ - * = IVA HD 1080p Video, VPE
ARM
C66x DSP
ARM
Cortex-A15 + - * = Graphics Acceleration Industrial
Cortex-A15 ARM M4 32K/32K L1
32K/32K L1
C66x DSP
288KB L2
3D GPU BB2D Communication
32K/32K L1 ARM M4 32K/32K L1 2x SGX544 GC320
288KB L2 Subsystem (ICSS)
EtherCAT®,PROFINET®,
1MB L2
L2 32KB L1
2MB
w/ECC 64KB RAM Display Subsystem EtherNET/IP™,
PROFIBUS,
3 LCD HDMI 1.4a POWERLINK, SERCOS 3
512KB L3 Shared RAM w/ECC
1080p
Blend/Scale/ Convert
32b DDR3/3L
32b DDR3/3L
w/ ECC Security Acceleration
Video Input Ports 2 AES, 2 SHA2MD5,
2x24b, 2x8b 2x24b, 2x8b 2x16b DES3DES, RNG

System Services
EDMA 13 Mailbox RTC SDMA Secure WDT WDT Spinlock 16 Timer KBD

Serial IO Industrial and Programmable IO Storage IO

2 8 2 GPIO
DCAN McASP PCIe GbE 2-port
switch
5 3 w/1588 3 SD/SDIO
QSPI I2C PWM/CAP/QEP G/MII, SATA
RMII, 1 eMMC/
10 4 RGMII NAND/ SD/SDIO
UART McSPI USB3/2 USB2 NOR

Pin muxing may limit peripheral availability.

Bandwidth may limit simultaneous use of peripherals. Not available in AM5726, except VPE
AM571x Cortex®-A15-based Processors
High-Speed Interconnect 28 nm

Video Acceleration
PRU (Quad Core)
IVA HD 1080p Video, VPE
ARM + - * = Graphics Acceleration Industrial
Cortex-A15 ARM M4 C66x DSP 3D GPU BB2D Communication
32K/32K L1 ARM M4 32K/32K L1 SGX544 GC320
288KB L2 Subsystem (ICSS)
EtherCAT®,PROFINET®,
1MB
1MB L2
L2 32KB L1 Display Subsystem
w/ ECC
w/ECC 64KB RAM EtherNET/IP™,
3 LCD HDMI 1.4a PROFIBUS,
512KB
512KBL3L3Shared RAMw/ECC
Shared RAM w/ ECC 1080p POWERLINK, SERCOS 3
Blend/Scale/ Convert

32b DDR3/3L Camera Port

w/ ECC 2 x CSI2 Security Acceleration
2 AES, 2 SHA2MD5,
Video Input Ports
2x24b, 2x8b DES3DES, RNG

System Services
EDMA 13 Mailbox RTC SDMA Secure WDT WDT Spinlock 16 Timer KBD

Serial IO Industrial and Programmable IO Storage IO

2 8 2 GPIO
DCAN McASP PCIe GbE 2-port
switch
5 3 w/1588 3 SD/SDIO
QSPI I2C PWM/CAP/QEP G/MII, SATA
RMII, 1 eMMC/
10 4 RGMII NAND/ SD/SDIO
UART McSPI USB3/2 USB2 NOR

Pin muxing may limit peripheral availability.

Bandwidth may limit simultaneous use of peripherals. Not available in AM5716, except VPE
AM57x
Package

ABC Package:
23 x 23mm, 0.8 pitch, 760-pin BGA package
AM57x Processors

AM57x Sitara Processors

Technical Deep Dive
Processors and Memory: ARM
Dual (AM572x) / Single (AM571x) ARM Cortex-A15
• Up to 1.5 GHz, r2p2 revision core(s), ARMv7-A instructions set
• Out-of-order instruction dispatch and completion
• Backward-compatible with code for previous ARM processors
• Integrated NEON™ processing engine and VFPv4-compatible
hardware
• Five execution units handle simple instructions, branch instructions,
NEON and floating point instructions, multiply instructions, & load
and store instructions
• AM572x has 2MB L2 memory (no ECC), while AM571x has 1MB L2
with ECC
Cortex-A15 (AM57x) vs Cortex-A9 (AM437x)
Enhancements New Features Key Benefits
• 128-bit (vs 64) data path • Extended physical addressing • Higher single-thread
• 3-inst (vs 2) instruction decode • Virtualization support: performance:
• 8-micro-ops (vs 4) issue – Virtual interrupt controller 3.5 vs 2.5 DMIPS/MHz

• 64-byte (vs 32) cache line – 2nd stage MMU for • 1.4x higher instructions per
Hypervisor control of cycle (IPC) from enhancements
• Dual load/store (vs one or other)
guest OS memory • 1.4x faster floating point
• Improved branch prediction:
– CP15 trapping • 10-15% higher clock in same
– Higher capacity
• Debug/trace support: process due to design
– Support for indirect branches
– Integrated trace • 10-100x faster fully-pipelined
• More out-of-order instructions cache maintenance support
• Physically-indexed/tagged L1 cache – Virtualization support
• Improved system-level support
• Tighter integration with NEON/VFP: • AMBA4 bus supports:
to support new architecture
– Faster interworking with ARM – System coherency needs: Larger memory,
code – MMU coherency virtualization, system
– Dual-issue (vs single) coherency…
• Improved memory performance:
– Tightly-coupled L2 cache to
reduce latency 23 to 14 clocks
– Enhanced auto-prefetch
– More requests buffering
Cortex-A15 offers substantial enhancements and new features to dramatically increase performance
and system-level support.
Processors and Memory: M4, DSP, & L3
Dual (AM572x) / Single (AM571x) ARM Cortex-A15
• Up to 1.5 GHz, r2p2 revision core(s), ARMv7-A instructions set
• Out-of-order instruction dispatch and completion
• Backward-compatible with code for previous ARM processors
• Integrated NEON™ processing engine and VFPv4 compatible hardware
• Five execution units handle simple instructions, branch instructions,
NEON and floating point instructions, multiply instructions, & load and
store instructions AM5728 diagram shown
• AM572x has 2MB L2 memory (no ECC), while AM571x has 1MB L2
with ECC
Dual-ARM Cortex M4s
• Up to 213 MHz, ARMv7-M and Thumb®-2 ISAs w/ ARMv6 SIMD & DSP
extensions
Dual (AM572x) / Single (AM571x) C66x DSPs
• Up to 750MHz, fixed- and floating-point ISA
• Object code compatible with C64x+ and C674x DSPs
• Advanced VLIW architecture w/ two multiplier units and six arithmetic
logic units operating in parallel
L3 Memory with ECC
• AM572x has 2.5MB of L3 memory with ECC
• AM571x has 512 KB of L3 memory with ECC
 Processors and Memory: PRU-ICSS
Programmable Real-Time Unit – Industrial Communication Subsystem (PRU-ICSS) (2)
• Dual 32-bit RISC cores
• 12KB program RAM, 8 KB data RAM per CPU Programming Tools
• 32KB shared RAM •PRU C-compiler for PRU firmware
• Interrupt controller •ARM Linux remoteproc + rpmsg driver
• Fast IO interface •PRU debugger in CCS
• Peripherals:
– One Ethernet MII_RT module with two MII ports *
– One MDIO port *
– One Industrial Ethernet peripheral *
and Industrial Ethernet timer
– 1 x 16550-compatible UART
– 1 x eCAP
• Capable of supporting master and/or slave modes
of protocols such as:
– Profinet, Ethernet IP, Profibus,
Ethercat, Powerlink, and Sercos 3
* Use of these ports is only supported via TI Processor SDK RTOS.
 PRU-ICSS Feature Comparison
AM18x/
AM335x AM437x AM571x AM572x (SR1.1)
Features OMAPL138
PRUSS PRU-ICSS1 PRU-ICSS1 PRU-ICSS0 2 x PRU-ICSS 2 x PRU-ICSS
PRU core version 1 3 3 3 3 3
Number of PRU cores 2 2 2 2 2 2
Max frequency CPU freq / 2 200 MHz 200 MHz 200 MHz 200 MHz 200 MHz
IRAM size (per PRU core) 4 KB 8 KB 12 KB 4 KB 12 KB 12 KB
DRAM size (per PRU core) 512 B 8 KB 8 KB 4 KB 8 KB 8 KB
Shared DRAM size -- 12 KB 32 KB -- 32KB 32KB
Direct; or 16-bit Direct; or 16-bit Direct; or 16-bit
Direct; or 16-bit parallel capture; or parallel capture; or parallel capture; or Direct; or 16-bit
General purpose input
Direct parallel capture; 28-bit shift; or 3ch 28-bit shift; or 3ch 28-bit shift; or 3ch parallel capture; or
(per PRU core)
or 28-bit shift EnDat 2.2; or 9ch EnDat 2.2; or 9ch EnDat 2.2; or 9ch 28-bit shift;
Sigma Delta Sigma Delta Sigma Delta
General purpose output
Direct Direct; or Shift out Direct; or Shift out Direct; or Shift out Direct; or Shift out Direct; or Shift out
(per PRU core)
GPI Pins (PRU0, PRU1) 30, 30 17, 17 13, 0 20, 20 21*, 21 21, 21
GPO Pins (PRU0, PRU1) 32, 32 16, 16 12, 0 20, 20 21*, 21 21, 21
MPY/MAC N Y Y Y Y Y
Scratchpad N Y (3 banks) Y (3 banks) N Y (3 banks) Y (3 banks)
CRC16/32 0 0 2 2 2 0
INTC 1 1 1 1 1 1
Peripherals n/a Y Y Y Y Y
UART 0 1 1 1 1 1
eCAP 0 1 1 not pinned out 1 1
IEP 0 1 1 not pinned out 1 1
MII_RT 0 2 2 not pinned out 2 2
MDIO 0 1 1 not pinned out 1 1
Simultaneous protocols 1 1 2** 2
* PRU-ICSS2 only. PRU-ICSS1 does not pin out the PRU0 core GPIs/GPOs.
** 2nd protocol limited to EnDAT/Profibus/BISS/HIperphase DSL or serial based protocol
AM57x Peripherals

AM57x Sitara Processors

Technical Deep Dive
 Video and Graphics
Video Acceleration
IVA HD 1080p Video, VPE
Graphics Acceleration
3D GPU BB2D
2x SGX544 GC320
AM5728 diagram shown.
Not available in AM57x6, except VPE.
Video Acceleration (same for AM572x and AM571x)
• IVA (image and video accelerator) HD-based video processing
solution. Sometimes this is called HDVICP.
• Up to 1080p60 decode and 1080p30 encode support for MPEG4 and
H.264
• Single-channel encode support (1080p30, D1, and QVGA)
Graphics Acceleration
• Dual (AM572x) / Single (AM571x) Imagination SGX544 3D graphics
engine
– Up to 532 MHz
– API support for OpenGL® ES1.1 & 2.0
– Tile-based architecture reduces access to external memory
• Vivante Corporation GC320 2D graphics accelerator
– API support for OpenWF™, DirectFB, and GDI/DirectDraw™
– Also supports BitBlt, StretchBlt, blending, and transparency
 Display Subsystem
Display Subsystem
• Three LCD outs supporting MIPI DPI 2.0, BT-656, or BT-1120, each
with dedicated overlay manager
• HDMI output supporting up to 1080p with a dedicated overlay
Display Subsystem manager
3 LCD HDMI 1.4a • One graphics, three video, and one write-back pipelines
1080p • Maximum display resolution up to 1920x1200
Blend/Scale/ Convert
NOTE: Simultaneous use of multiple displays will reduce maximum
resolution subject to DDR bandwidth and graphics layers.
Video Input Ports
2x24b, 2x8b 2x24b, 2x8b 2x16b

AM5728 diagram shown.

Not available in AM57x6.
Dual Camera Serial Interface 2 (CSI2)
Display Subsystem
• Three LCD outs supporting MIPI DPI 2.0, BT-656, or BT-1120, each
with dedicated overlay manager
Display Subsystem • HDMI output supporting up to 1080p with a dedicated overlay
3 LCD HDMI 1.4a manager
1080p • One graphics, three video, and one write-back pipelines
Blend/Scale/ Convert
• Maximum display resolution up to 1920x1200
Camera Port NOTE: Simultaneous use of multiple displays will reduce maximum
2 x CSI2 resolution subject to DDR bandwidth and graphics layers
Video Input Ports
2x24b, 2x8b
AM5718 diagram shown.
Not available in AM57x6. Dual-Camera Serial Interface 2 (CSI2) (AM571x)
• Two ports compliant with MIPI CSI-2 1.0, MIPI D-PHY RX 1.0
– Port A: Four data lanes
– Port B: Two data lanes
 Video Input Ports (VIP)
Video Input Ports (VIP)
Each VIP supports 2-input independent stream parser slices
• VIP1 and VIP2 slice can handle two streams
- Port-A: 8/16/24-bit options
- Port-B: 8-bit only
Display Subsystem
• VIP3 slice can handle one stream
3 LCD HDMI 1.4a - Port-A: 8/16-bit options
1080p
Blend/Scale/ Convert NOTE: AM571x only supports VIP1

Video Input Ports

2x24b, 2x8b 2x24b, 2x8b 2x16b

AM5728 diagram shown.

Not available in AM57x6.
AM57x Serial Peripherals
• DCAN (2)
– Support bit rates up to 1Mbit/s and are compliant to CAN2.0B protocol specification

• Multichannel Audio Serial Port Interface (McASP) (8)

– Two instances support 16 channels w/ independent TX/RX clock sync domains
– Six instances support 4 channels w/ shared TX/RX clock sync domains

• QSPI
– Master-only interface primarily intended for fast booting from Serial IO
quad-SPI flash memories 2 8
– Supports single, dual or quad reads. Only single writes are supported. DCAN McASP

• I2C (5) QSPI 5

I2C
– Slave or master configurable
– Two I2C ports support Fast mode (up to 400 Kbps) 10 4
– Three I2C ports support HS mode (up to 3.4 Mbps) UART McSPI

• Universal Asynchronous Receiver Transmitters (UART) (10)

– Baud rates up to 3.6864 Mbps
– One with extended modem control signals (DCD, RI, DTR, DSR)
– One with IrDA

• Multichannel Serial Port Interface (McSPI) (4)

– Function as master or slave
– Each supports up to four external device (four chip selects)
or one external master
Industrial Programmable I/Os: PWMSS & GPIO
• Three PWMSS (Pulse-Width Modulation Subsystems)
– eHRPWM: High Resolution PWM
• 2x PWM outputs with single-/dual-edge symmetric/asymmetric operation
Only ehrpwm[x]A supports the High-Resolution PWM feature
• 1x Trip Zone Input for reacting to external fault conditions
• eHRPWM1 has Time Base Synchronization I/Os (internally daisy-chained to other
modules) Industrial and Programmable IO
– eCAP: Capture 2 GPIO
PCIe GbE 2-port
• 1x Capture Input with 4-event time-stamp registers switch
3 w/1588
• Used for measuring audio sample rate, rotating machinery PWM/CAP/QEP G/MII,
RMII,
speed, position sensor pulses RGMII
USB3/2 USB2
• Can optionally be configured as a single channel PWM output
– eQEP: Quadrature Encoded Pulse
• Used to measure the angular position or motion of a shaft
or axle (for example, volume knob)
• 2x Quadrature Inputs, 1x Index Input, 1x Strobe Input
• GPIOs
– AM572x up to 247 GPIOs; AM571x up to 215 GPIOs
– Divided amongst 8x GPIO modules
(muxed on most LVCMOS device pins)
Industrial Programmable I/Os: PCI Express (PCIe)
PCI Express (PCIe) (2)
– Supports Gen I (2.5GT/s) and Gen II (5GT/s) modes
– AM57x has 2x PCIe lanes* supporting two configurations: PCIE_SS1 Lane 0
1) One Controller with 2 lanes
2) Two Controllers with 1 lane each
* On AM571x, use of Lane 1 is mutually exclusive with
USB SuperSpeed mode
– Supported features:
• Root Complex and Endpoint modes
• Single Function in Endpoint mode USB SS * Lane 1
• Optional traffic mapping through dedicated MMU2
• Single Virtual Channel (VC) and Traffic Class (TC)
– Unsupported features: Control
• Power states L2 (w/Beacon) and D3cold Module
• Built-in hot plug
• Addressing modes other than incremental for bursts
• Outbound transactions involving less than 4 bytes
– Supports the following maximum payload sizes PCIE_SS2
• 128-byte outbound payload size (limited by EDMA)
• 256-byte inbound payload size
Industrial Programmable I/Os: USB
USB (2) (USB 3.0/2.0 x1; USB 2.0 x1)

• Two xHCI USB Controllers with different configurations:

Standard Line Rate PHY
USB Port 1 (USB1) USB 3.0 5Gbps Internal SS (USB3.0) PHY and
Internal HS/FS (USB2.0) PHY
USB Port 2 (USB2) USB 2.0 480Mbps Internal HS/FS PHY

• On AM571x, use of USB SuperSpeed mode is mutually

exclusive with lane of second PCIe.
• All xHCI Controllers support:
– Host or Peripheral mode (Dual-Role-Device (DRD))
– DRVVBUS (Drive-VBUS) output signal to External Charge
Pump for VBUS 5V generation
• No support for the following:
– Full OTG (Software-based Role Switching still possible)
• Attached Detection Protocol (ADP), ACA
– ID pin (if desired, must be implemented by an
external GPIO)
Industrial Programmable I/Os: Ethernet
Ethernet

• Internal Gb Ethernet Switch with 3 ports:

– 2 External Ethernet Ports
– 1 Internal Local Host Port

• External Interface support:

– RMII/MII (10/100Mbps) at 3.3V
– RGMII (10/100/1000*Mbps) at 1.8V/3.3V
– Single MDIO interface for PHY Control

• Clocking:
– MII/RMII: Supports both internal and external
50MHz reference clock
– RGMII: Internal clock reference only

• No support for:
– GMII interface
– 2.5V Signaling

* AM572x errata – Ethernet RGMII2 limited to 10/100 Mbps.

Refer to device errata for impacted silicon revisions.
Storage I/Os: SATA
SATA

• Single Port SATA host controller supporting 1.5-Gbps and 3-Gbps speeds (SATA-1 and SATA-2)

• Supports multiple drives with a port multiplier: command-based switching only (Issuing commands
to only one drive at a time)

• Dedicated sata1_led pin for Activity LED generation Storage IO

• No support for the following: 3 SD/SDIO

SATA
– ATA legacy mode of operation 1 eMMC/
NAND/NOR SD/SDIO
– Cold presence detection for hot-plug operation
– Message signaled interrupts
– Far-end Analog Loopback
– Port Multiplier FIS-based switching
Storage I/Os: eMCC/SD/SDIO
eMMC / SD / SDIO (4)

• Four controllers with different configurations:

Data Bus Primary Support Max Frequency* IO Buffer Type DMA

MMC1 4-bit SD 192 MHz (via DLL) UHS1 Master & Slave
MMC2 8-bit eMMC 192 MHz (via DLL) LVCMOS Master & Slave
MMC3 8-bit SDIO / SD 96 MHz LVCMOS Slave
MMC4 4-bit SDIO / SD 48 MHz LVCMOS Slave
* AM572x errata – MMC1/2/3 write speed limited.
• Full compliance with standards: Refer to device errata for impacted silicon revisions.
– JC64 MMC/eMMC standard specification, v4.5
– SD Physical Layer specification v3.01
– SD part E1 specification v3.00 (SDIO)
– SD card specification Part A2 v3.00

• No support for:
– MMC POW output pin: Must utilize chip level GPIO for this function, if desired.
Storage I/Os: GPMC & ELM
• General Purpose Memory Controller (GPMC) GPMC
– Used for accessing SRAM, NOR, NAND, etc.
– 8/16-bit data at up to 88MHz
– Non-muxed, Address-Data muxed, and
Address-Address-Data muxed modes
– Async mode with read page access
– Sync mode with burst access and wrap
capability
– 8 chip-selects covering 512MB of address
space
• Error Locator Module (ELM)
– Used when interfacing GPMC to a NAND
device
– Provides 4-, 8- or 16-bit error location over a
512-Byte block based on BCH algorithms
– Allows detected errors and their locations in
the NAND block to be retrieved by the
processor when the PAGE_VALID interrupt is
generated
Storage I/Os: EMIF & DMM
• External Memory Interface (EMIF)
Number EMIF ECC Addressable SDRAM size Chip Selects
Controllers
AM572x Dual EMIF1 only Up to 2GB per controller 1 per controller
AM571x Single Yes Up to 4 GB * 2
* if using stacked die package
– 16-/32-bit DDR3/ DDR3L support
– Speeds up to 533MHz (DDR-1066)
– Hardware-leveling support
– Class of Service and burst priority counter
– MPU MA has 128-bit direct path with
optimized latency to each of EMIF0/1

• Dynamic Memory Management (DMM)

– Performs global address translation and
address rotation (tiling) between L3_MAIN
Interconnect and EMIFs
– Performs access interleaving between
EMIFs
System Peripherals
• Enhanced DMA (EDMA)
– Supports two simultaneous read and two simultaneous write physical channels
– Up to 64 programmable logical channels
• Mailbox (13)
– 13 for the MPU, DSP, IPU, and PRU; 1 for IVA
– Number of users, number of messages in the queue
• Real-Time Clock (RTC): RTC-only low power mode not supported
• System DMA (SDMA): Up to 128 hardware requests, 32 prioritizable logical channels, and 256 × 64-
bit FIFO dynamically allocable between active channels
• Watchdog Timer: Free-running 32-bit upward counter
(runs off of 32kHz system clock)
• Spinlock: 256 hardware semaphores between the MPU, DSP, and IPU
• Timer (16): Free-running 32-bit upward counter. Runs off 32KHz or system clock
• Keyboard Controller (KBD): Supports up to 9x9 Keypads

System Services
EDMA 13 Mailbox RTC SDMA Secure WDT WDT Spinlock 16 Timer KBD
AM57x System Architecture

AM57x Sitara Processors

Technical Deep Dive
Pad Configuration Requirements
• In order to guarantee the IO Timings in the AM57x Data Manual over the
lifetime of the device, AM57x software shall implement the proper pad
configuration requirements.

• Pad configuration settings that impact IO timings include:

– Slew Control Settings (default values must be used)
– Virtual IO Timing Modes
– Manual IO Timing Modes

• Proper pad configuration procedure includes:

– IO Isolation: Required to guarantee IO state when changing IO settings
– IO Delay Recalibration: Required to guarantee timings after AVS changes

• The AM57x Data Manual lists the pad configuration requirements to achieve
the various timing modes of operation.

• The TRM Pad Configuration Section provides the details on implementing the
pad configuration requirements.
Virtual IO Timing Modes
• Virtual IO Timing Modes are pre-defined IO timing settings that are coded in the
Device ROM.

• Selection of Virtual Modes is done via the Pad Configuration Registers. This is
described in AM57x TRM section Virtual IO Timing Modes.

• Below is an example of how Virtual IO Timing Modes are defined in the AM57x Data
Manual:
Manual IO Timing Modes
• Manual IO Timing Modes are IO timing settings that must be calculated and
programmed by system software based on seed values in the datasheet.

• Application of Manual IO Timing Modes is done via the CFG_x_IN, CFG_x_OEN, and
CFG_x_OUT registers in the IODELAYCONFIG Module. This is described in the
AM57x TRM section Manual IO Timing Modes.

• Below is an example of how Manual IO Timing Modes seed values are defined in the
AM57x Data Manual:
IO Isolation Mode
• Any changes to the Pad Configuration Registers or IODELAYCONFIG registers
can potentially result in an undesirable state (i.e., output state changes or
output enable changes) on the associated IOs.
• To guarantee IO state, device pins should be placed in Isolation Mode when
making any changes to the Pad Configuration Registers or IODELAYCONFIG
Module Registers.
• Run-time (non-isolated) changes are only supported for MMC.
• See TRM section “Isolation Requirements” for details.
Customer Software Implications
• All I/O timing modes and pinmuxing shall be set by software …
– At boot-time
– While under protection of isolation
– While executing code from OCMCRAM (since DDR cannot be accessed while IOs
are in isolation)
– The Secondary Boot Loaders (just after ROM bootloader) execute from OCMC
RAM. The MLO in the Linux eco-system operates from the OCMC RAM.
– Therefore the MLO/ SBL is the ideal place for pad configurations.

• Run-time changes are needed for MMC where dynamic configurations can
not be avoided. TI has validated this use case.

• IO Delay support is included in the AM57xx Pin Mux Tool (PMT).

NOTE: In order to guarantee the IO timings in the AM57x Data Manual

over the lifetime of the device, AM57x software shall implement the
proper pad configuration requirements.
AM57x Boot
• Booting devices include:

– NOR flash memory or other XIP device – SATA-compatible devices

– NAND flash memories (non-XIP)
– Removable SD card device
– eMMC™ memory device
– 1-bit SPI flash memories (QSPI_1)
– 4-bit (Quad) SPI flash memories (QSPI_4)
• Solid state drives (SSDs)
• Hard-disk drives (HDDs)
– USB: HS USB 2.0 interface
– UART: UART interface

• Initial boot order comes from sysboot pins.

Interrupt & Event Controller Crossbar
• Each core or DMA can only supports a static number of interrupt/event inputs.
• Each core interrupt controller and each DMA event handler is preceded by an Interrupt
Controller or DMA Crossbar mux.
• Crossbar allows any peripheral interrupt/event to be mapped to a core or DMA .
• Mapping of peripheral interrupt/event selections is the same for each crossbar instance to allow
software consistency.

All peripherals Repeated for each IRQ of

each CPU core
(similar for events/DMA)
AM57x EVMs & Tools

AM57x Sitara Processors

Technical Deep Dive
AM57x Development Tools
AM572x Evaluation BeagleBoard-X15 AM57x Industrial
Module (EVM) Development Kit (IDK)

COMING SOON

General Availability Oct ‘15 Late 4Q15 1Q16

Sold and
TI BeagleBoard.org TI
Supported by
AM5728
Processor AM5728 AM5728
AM571x –1Q16
2GB DDR3L 2GB DDR3L 1GB DDR3L
Memory 4GB eMMC 4GB eMMC 32MB QSPI / 16 GB eMMC
micro SD micro SD micro SD
Yes, Capacitive Touch Yes, Capacitive Touch
Display None
Size: 7”, 800 x 480 Size: 10”, 1080p
USB 3.0/2.0, e/mSATA, HDMI,
USB 3.0/2.0, eSATA, HDMI,
2x Gb Ethernet, Audio in/out, Full ICSS access (x4), ADC,
Key Features 2x Gb Ethernet, Audio in/out,
ECC DDR support, HDMI, Camera
WiLink8 connector, Camera,
& Peripheral Expansion
PCIe & Peripheral Expansion
Software Linux, Android*, TI-RTOS** Linux, TI-RTOS** TI-RTOS, RT Linux***

*Supplied via third party: would not ship with kit

**Available via download: target 4Q15
*** Available via download: target 1Q16
 AM572x Evaluation Module (EVM)
7” LCD Display
• Processor board based on (WVGA - 800x480)
BeagleBoard-X15 Power LED Capacitive touch screen User buttons
– Sitara™ AM5728 processor
– TPS659037 power management
– 2GB DDR3L
– 4GB eMMC
– Micro SD card
– 3x USB 3.0 HUB
– USB 2.0 (micro)
– Full size HDMI connector
– eSATA connector
– 2Gb Ethernet ports
– Audio input/output
– 20-pin ARM JTAG
Processor board
• Included accessories Plugs in via expansion
– Quick Start Guide connectors in the back
– HDMI cable Bottom side of LCD board
– USB-to-Serial debug cable Camera board miniPCIe connector
3Mp sensor mSATA connector
– Micro SD card with Processor SDK WiLink™ 8 connector
*Power supply not included
AM572x Power Solutions
TPS659037 is the Power Management IC (PMIC) that shall be used for the Device
designs. TI requires use of this PMIC for the following reasons:
• TI has validated its use with the device.
• Board level margins – including transient response and output accuracy – are analyzed and
optimized for the entire system.
• Support for power sequencing requirements (refer to Section 5.8 Power Supply Sequences in the
AM57x datasheet)
• Support for Adaptive Voltage Scaling (AVS) Class 0 requirements, including TI provided software

TPS659037 Power TPS659037 configured for TPS659037 configured for

Supply the AM572x EVM the AM572x IDK

SMPS1/2 vdd_mpu vdd_mpu

SMPS3 DDR Memory DDR Memory

vdd_dspeve, vdd_gpu,
vdd_dspeve
SMPS4/5 vdd_iva

SMPS6 vdd vdd_gpu

SW configuration after boot vdd

SMPS7

SMPS8 vdds18v vdd_iva

SW configuration after boot 3.3V vddshvx

SMPS9
AM571x Power Solutions
TPS65916 or TPS659037 is the Power Management IC (PMIC) that shall be used for the
Device designs.

TPS659037 TPS659037 configured for the TPS65916 Power Generic TPS65916 configuration
Power Supply AM571x IDK Supply for AM571x

SMPS1/2 vdd_mpu SMPS1 vdd_mpu

SMPS3 DDR Memory SMPS2 vdd

SMPS4/5 vdd_dsp SMPS3 vdd_dsp, vdd_gpu, vdd_iva

SMPS6 vdd_gpu SMPS4 vdds18v

SMPS7 vdd SMPS5 DDR Memory

SMPS8 vdd_iva

SMPS9 3.3V
Thermal Considerations
• Thermal management ensures that every silicon device on the board works within its allowable
operating junction temperature. Failure to maintain a junction temperature within the range
specified reduces operating lifetime, reliability, and performance.

• The product design cycle should include thermal analysis to verify the operating junction
temperature of the device is within functional limits. If the temperature is too high, component-
or system-level thermal enhancements are required to dissipate the heat from the system.
AM572/1x Layout Compatibility
• AM572x & AM571x are designed as layout compatible solutions.

• AM572/1x Compatibility Guide application note walks through differences:

– Feature differences – Hardware considerations
– Pin compatibility – Software impact
– PMIC compatibility

• Example differences:
– Same multiplexings for all common features
– Features/signals removed or added in AM571x
– New added pin muxings in AM571x
– IVA/DSP must run at same OPP when AM571x populated
(unless special population hooks)
– Some special powers swap, must treat them the same
(same filtering/handling)
For More Information

• For information about AM57x: www.ti.com/product/am5728

www.ti.com/product/am5718

• For more training related to Sitara and AM57x: www.ti.com/sitaratraining

• For questions about this training, refer to the E2E Sitara Processors Forum:
https://e2e.ti.com/support/arm/sitara_arm