Professional Documents
Culture Documents
1200AP100 ONSemiconductor
1200AP100 ONSemiconductor
PWM Current−Mode
Controller for Universal
Off−Line Supplies Featuring
Low Standby Power
Housed in SOIC−8 or PDIP−8 package, the NCP1200A enhances
http://onsemi.com
the previous NCP1200 series by offering a reduced optocoupler
current together with an increased drive capability. Due to its novel
concept, the circuit allows the implementation of complete off−line MINIATURE PWM
AC−DC adapters, battery charger or a SMPS where standby power is a CONTROLLER FOR HIGH
key parameter.
www.DataSheet4U.com
POWER AC−DC WALL
With an internal structure operating at a fixed 40 kHz, 60 kHz or
100 kHz, the controller supplies itself from the high−voltage rail, ADAPTERS AND OFFLINE
avoiding the need of an auxiliary winding. This feature naturally eases BATTERY CHARGERS
the designer task in battery charger applications. Finally,
current−mode control provides an excellent audio−susceptibility and
MARKING
inherent pulse−by−pulse control.
DIAGRAMS
When the current setpoint falls below a given value, e.g. the output
power demand diminishes, the IC automatically enters the so−called 8
skip cycle mode and provides excellent efficiency at light loads. SOIC−8
200Ay
8 D SUFFIX
Because this occurs at a user adjustable low peak current, no acoustic ALYW
1 CASE 751
noise takes place.
1
The NCP1200A features an efficient protective circuitry which, in
presence of an overcurrent condition, disables the output pulses while 8
the device enters a safe burst mode, trying to restart. Once the default
has gone, the device auto−recovers. PDIP−8 1200APxxx
P SUFFIX AWL
8 CASE 626 YYWW
Features 1
1
• Pb−Free Packages are Available
• No Auxiliary Winding Operation
xxx = Specific Device Code
• Auto−Recovery Internal Output Short−Circuit Protection (40, 60 or 100)
• Extremely Low No−Load Standby Power y = Specific Device Code
• Current−Mode Control with Skip−Cycle Capability A
(4 for 40, 6 for 60, 1 for 100)
= Assembly Location
• Internal Temperature Shutdown WL, L = Wafer Lot
• Internal Leading Edge Blanking Y, YY = Year
• 250 mA Peak Current Capability
W, WW = Work Week
FB 2 7 NC
Typical Applications
• AC−DC Adapters for Portable Devices CS 3 6 VCC
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
* VOUT
+
+
NCP1200A
Adj HV
1 8
FB
2 7
EMI CS VCC
3 6
FILTER GND Drv
4 5
UNIVERSAL
INPUT +
www.DataSheet4U.com
3 CS Current sense input This pin senses the primary current and routes it to the internal comparator
via an L.E.B.
http://onsemi.com
2
NCP1200A
Adj HV
1 8
HV CURRENT
SOURCE
80 k SKIP CYCLE
FB 1.2 V COMPARATOR NC
+
2 − UVLO HIGH AND LOW 7
INTERNAL VCC INTERNAL REGULATOR
24 k
www.DataSheet4U.com
CURRENT
Q FLIP−FLOP
SENSE VCC
DCmax = 80%
250 ns 40−60−100 kHz SET Q
3 6
L.E.B. CLOCK
RESET
20 k 57 k +
−
GROUND Drv
VREF
4 + 25 k 1V ±250 mA 5
− 5V
OVERLOAD?
FAULT DURATION
MAXIMUM RATINGS
Rating Symbol Value Unit
Power Supply Voltage VCC 16 V
Thermal Resistance Junction−to−Air, PDIP−8 Version RJA 100 °C/W
Thermal Resistance Junction−to−Air, SOIC Version RJA 178 °C/W
http://onsemi.com
3
NCP1200A
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = 0°C to +125°C, Max TJ = 150°C,
VCC = 11 V unless otherwise noted.)
Characteristic Symbol Pin Min Typ Max Unit
Internal IC Consumption, 1.0 nF Output Load on Pin 5, FSW = 40 kHz ICC2 6 − 1.2 1.4 mA
(Note 2)
Internal IC Consumption, 1.0 nF Output Load on Pin 5, FSW = 60 kHz ICC2 6 − 1.4 1.6 mA
(Note 2)
www.DataSheet4U.com
Internal IC Consumption, 1.0 nF Output Load on Pin 5, FSW = 100 kHz ICC2 6 − 1.9 2.2 mA
(Note 2)
Drive Output
Output Voltage Rise−Time @ CL = 1.0 nF, 10−90% of Output Signal Tr 5 − 67 − ns
Output Voltage Fall−Time @ CL = 1.0 nF, 10−90% of Output Signal Tf 5 − 25 − ns
Source Resistance ROH 5 27 40 61
Sink Resistance ROL 5 5.0 10 21
http://onsemi.com
4
NCP1200A
TYPICAL CHARACTERISTICS
70 12.5
60 12.3
40 11.9
30 11.7
20 11.5
10 11.3
0 11.1
www.DataSheet4U.com−25 0 25 50 75 100 125 −25 0 25 50 75 100 125
Figure 3. HV Pin Leakage Current vs. Temperature Figure 4. VCC(off) vs. Temperature
10.2 900
10.1 850
ICC1 (A)
9.9 750
60 kHz
9.8 700
40 kHz
9.7 650
9.6 600
−25 0 25 50 75 100 125 −25 0 25 50 75 100 125
2.10 110
100 kHz
100 kHz 104
1.90 98
92
1.70 86
ICC2 (mA)
FSW (kHz)
80
1.50 74
60 kHz
68
1.30 62 60 kHz
40 kHz 56
1.10 50
40 kHz
44
0.90 38
−25 0 25 50 75 100 125 −25 0 25 50 75 100 125
http://onsemi.com
5
NCP1200A
TYPICAL CHARACTERISTICS
5.50 490
460
5.45
430
5.40 400
VCC LATCHOFF
ICC3 (A)
5.35 370
340
5.30
310
5.25 280
250
5.20
220
5.15 190
www.DataSheet4U.com −25 0 25 50 75 100 125 −25 0 25 50 75 100 125
Figure 9. VCC Latchoff vs. Temperature Figure 10. ICC3 vs. Temperature
60 1.00
30
0.88
20
Sink 0.84
10
0 0.80
−25 0 25 50 75 100 125 −25 0 25 50 75 100 125
Figure 11. Drive and Source Resistance vs. Figure 12. Current Sense Limit vs. Temperature
Temperature
1.40 87
1.35
85
1.30
83
DUTY MAX (%)
1.25
VSKIP (V)
81
1.20
79
1.15
1.10 77
1.05 75
1.00 73
−25 0 25 50 75 100 125 −25 0 25 50 75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 13. VSKIP vs. Temperature Figure 14. Max Duty Cycle vs. Temperature
http://onsemi.com
6
NCP1200A
APPLICATION INFORMATION
http://onsemi.com
7
NCP1200A
HV
mains
Cbulk 1 8
2 7
3 6
4 5
Figure 16. A simple diode naturally reduces the average voltage on pin 8
Skipping Cycle Mode To better understand how this skip cycle mode takes place,
www.DataSheet4U.com
The NCP1200A automatically skips switching cycles a look at the operation mode versus the FB level
when the output power demand drops below a given level. immediately gives the necessary insight:
This is accomplished by monitoring the FB pin. In normal
operation, pin 2 imposes a peak current accordingly to the FB
load value. If the load demand decreases, the internal loop 4.2 V, FB Pin Open
asks for less peak current. When this setpoint reaches a
3.2 V, Upper
determined level, the IC prevents the current from NORMAL CURRENT Dynamic Range
decreasing further down and starts to blank the output MODE OPERATION
pulses: the IC enters the so−called skip cycle mode, also
named controlled burst operation. The power transfer now
1V
depends upon the width of the pulse bunches (Figure 18). SKIP CYCLE OPERATION
Suppose we have the following component values: IP(min) = 333 mV/RSENSE
Power P1
Power P2
Power P3
http://onsemi.com
8
NCP1200A
MAX PEAK
300 M CURRENT
100 M
www.DataSheet4U.com
Figure 19. The Skip Cycle Takes Place at Low Peak Currents which Guaranties Noise−Free
Operation
We recommend a pin 1 operation between 400 mV and 1.3 disappeared. This option can easily be accomplished
V that will fix the skip peak current level between 120 mV through a single NPN bipolar transistor wired between FB
/ RSENSE and 390 mV / RSENSE. and ground. By pulling FB below the Adj pin 1 level, the
output pulses are disabled as long as FB is pulled below
Non−Latching Shutdown pin 1. As soon as FB is relaxed, the IC resumes its operation.
In some cases, it might be desirable to shut off the part Figure 20 depicts the application example:
temporarily and authorize its restart once the default has
1 8
2 7
3 6
ON/OFF Q1
4 5
Figure 20. Another Way of Shutting Down the IC without a Definitive Latchoff State
http://onsemi.com
9
NCP1200A
http://onsemi.com
10
NCP1200A
VCC REGULATION
OCCURS
HERE
12 V
LATCHOFF
10 V PHASE
5.4 V
TIME
Drv
DRIVER DRIVER
PULSES PULSES
www.DataSheet4U.com TIME
INTERNAL
FAULT FLAG
FAULT IS
RELAXED
TIME
STARTUP PHASE FAULT OCCURS HERE
Figure 21. If the fault is relaxed during the VCC natural fall down sequence, the IC automatically resumes.
If the fault still persists when VCC reached UVLOL, then the controller cuts everything off until recovery.
When this level crosses 5.4 V typical, the controller enters in either simulating or measuring in the lab how much time
a new startup phase by turning the current source on: VCC the system takes to reach the regulation at full load. Let’s
rises toward 12 V and again delivers output pulses at the suppose that this time corresponds to 6 ms. Therefore a VCC
UVLOH crossing point. If the fault condition has been fall time of 10 ms could be well appropriated in order to not
removed before UVLOL approaches, then the IC continues trigger the overload detection circuitry. If the corresponding
its normal operation. Otherwise, a new fault cycle takes IC consumption, including the MOSFET drive, establishes
place. Figure 21 shows the evolution of the signals in at 1.8 mA for instance, we can calculate the required
presence of a fault. t V C
capacitor using the following formula: i , with
Calculating the VCC Capacitor V = 2 V. Then for a wanted t of 10 ms, C equals 9 F or
As the above section describes, the fall down sequence 22 F for a standard value. When an overload condition
depends upon the VCC level: how long does it take for the occurs, the IC blocks its internal circuitry and its
VCC line to go from 12 V to 10 V? The required time depends consumption drops to 350 A typical. This happens at
on the startup sequence of your system, i.e. when you first VCC = 10 V and it remains stuck until VCC reaches 5.4 V: we
apply the power to the IC. The corresponding transient fault are in latchoff phase. Again, using the calculated 22 F and
duration due to the output capacitor charging must be less 350 A current consumption, this latchoff phase lasts:
than the time needed to discharge from 12 V to 10 V, 296 ms.
otherwise the supply will not properly start. The test consists
http://onsemi.com
11
NCP1200A
Protecting the Controller Against Negative Spikes fed by its VCC capacitor and keeps activating the MOSFET
As with any controller built upon a CMOS technology, it ON and OFF with a peak current limited by Rsense.
is the designer’s duty to avoid the presence of negative Unfortunately, if the quality coefficient Q of the resonating
spikes on sensitive pins. Negative signals have the bad habit network formed by Lp and Cbulk is low (e.g. the MOSFET
to forward bias the controller substrate and induce erratic Rdson + Rsense are small), conditions are met to make the
behaviors. Sometimes, the injection can be so strong that circuit resonate and thus negatively bias the controller. Since
internal parasitic SCRs are triggered, engendering we are talking about ms pulses, the amount of injected
irremediable damages to the IC if they are a low impedance charge (Q = I x t) immediately latches the controller which
path is offered between VCC and GND. If the current sense brutally discharges its VCC capacitor. If this VCC capacitor
pin is often the seat of such spurious signals, the is of sufficient value, its stored energy damages the
high−voltage pin can also be the source of problems in controller. Figure 22 depicts a typical negative shot
certain circumstances. During the turn−off sequence, e.g. occurring on the HV pin where the brutal VCC discharge
when the user unplugs the power supply, the controller is still testifies for latchup.
www.DataSheet4U.com
Figure 22. A negative spike takes place on the Bulk capacitor at the switch−off sequence
Simple and inexpensive cures exist to prevent from Another option (Figure 24) consists in wiring a diode from
internal parasitic SCR activation. One of them consists in VCC to the bulk capacitor to force VCC to reach UVLOlow
inserting a resistor in series with the high−voltage pin to sooner and thus stops the switching activity before the bulk
keep the negative current to the lowest when the bulk capacitor gets deeply discharged. For security reasons, two
becomes negative (Figure 23). Please note that the negative diodes can be connected in series.
spike is clamped to –2 x Vf due to the diode bridge. Please
refer to AND8069/D for power dissipation calculations.
3
Rbulk
> 4.7 k
2 3
1 8 1 8 D3
+ +
Cbulk 2 7 Cbulk 2 7 1N4007
3 6 3 6
1 + 1 +
4 5 CVCC 4 5 CVCC
Figure 23. A simple resistor in series avoids any Figure 24. or a diode forces VCC to reach
latchup in the controller UVLOlow sooner
http://onsemi.com
12
NCP1200A
ORDERING INFORMATION
Device Type Marking Package Shipping†
NCP1200AP40 1200AP40 PDIP−8 50 Units / Rail
NCP1200AP40G 1200AP40 PDIP−8 50 Units / Rail
FSW = 40 kHz
(Pb−Free)
NCP1200AD40R2 200A4 SOIC−8 2500 Units /Reel
NCP1200AP60 1200AP60 PDIP−8 50 Units / Rail
NCP1200AP60G 1200AP60 PDIP−8 50 Units / Rail
(Pb−Free)
FSW = 60 kHz
NCP1200AD60R2 200A6 SOIC−8 2500 Units /Reel
NCP1200AD60R2G 200A6 SOIC−8 2500 Units /Reel
(Pb−Free)
www.DataSheet4U.com
NCP1200AP100 1200AP100 PDIP−8 50 Units / Rail
NCP1200AP100G 1200AP100 PDIP−8 50 Units / Rail
(Pb−Free)
FSW = 100 kHz
NCP1200AD100R2 200A1 SOIC−8 2500 Units / Reel
NCP1200AD100R2G 200A1 SOIC−8 2500 Units / Reel
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
13
NCP1200A
PACKAGE DIMENSIONS
SOIC−8
D SUFFIX
CASE 751−07
ISSUE AC
−X− NOTES:
1. DIMENSIONING AND TOLERANCING PER
A ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
8 5
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
B S 0.25 (0.010) M Y M 5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
1 PROTRUSION SHALL BE 0.127 (0.005) TOTAL
4 IN EXCESS OF THE D DIMENSION AT
−Y− K MAXIMUM MATERIAL CONDITION.
www.DataSheet4U.com 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
G
MILLIMETERS INCHES
C N X 45 DIM MIN MAX MIN MAX
A 4.80 5.00 0.189 0.197
SEATING
PLANE B 3.80 4.00 0.150 0.157
−Z− C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
0.10 (0.004) G 1.27 BSC 0.050 BSC
H M J H 0.10 0.25 0.004 0.010
D J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050
M 0 8 0 8
0.25 (0.010) M Z Y S X S
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
SOLDERING FOOTPRINT*
1.52
0.060
7.0 4.0
0.275 0.155
0.6 1.270
0.024 0.050
http://onsemi.com
14
NCP1200A
PACKAGE DIMENSIONS
PDIP−8
P SUFFIX
CASE 626−05
ISSUE L
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
8 5 FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
−B− 3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
1 4
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 9.40 10.16 0.370 0.400
F B 6.10 6.60 0.240 0.260
w w w . D a t a S h e e t 4 U . c o m C 3.94 4.45 0.155 0.175
NOTE 2 −A− D 0.38 0.51 0.015 0.020
L F 1.02 1.78 0.040 0.070
G 2.54 BSC 0.100 BSC
H 0.76 1.27 0.030 0.050
J 0.20 0.30 0.008 0.012
C K 2.92 3.43 0.115 0.135
L 7.62 BSC 0.300 BSC
M −−− 10 −−− 10
−T− J N 0.76 1.01 0.030 0.040
SEATING N
PLANE
M
D K
H G
0.13 (0.005) M T A M B M
http://onsemi.com
15
NCP1200A
www.DataSheet4U.com
The product described herein (NCP1200A), may be covered by the following U.S. patents: 6,271,735, 6,362,067, 6,385,060, 6,429,709, 6,587,357. There
may be other patents pending.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
http://onsemi.com NCP1200A/D
16