Microprocessor & Interfacing

(8086 family microprocessors)

Jimmy Mathew
Asst. Professor (Sr.),
School of Computing Science & Engineering (SCSE),
VIT University, India
Email: jimmym@vit.ac.in / Room: SJT 313 A08
 8086 MAX mode

MP & I/F Module 1 JMW VIT-U 2

 8086 MAX mode
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Maximum mode – Multiprocessor operations

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There may be more than one Microprocessors

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Low in MN/MX pin

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Processor drives the status signals S2-S0

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Bus controller chip (IC 8288)– Derives control signal using
status information

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Bus controller inputs: CLK, S2, S1, S0

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Bus controller outputs: ALE, DEN, DT/R, MRDC, MWTC,
IORC, IOWC
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8086 max mode

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 8086 MAX mode

S2, S1, S0 (MAX mode)

– Status lines, indicate current status of processor

• [000] - Interrupt acknowledge

• [001] - Read I/O port

• [010] - Write I/O port

• [011] - Halt

• [100] - Code access

• [101] - Read memory

• [110] - Write memory

• [111] - Passive
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 8086 MAX mode
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Memory read timing in maximum mode :

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 8086 MAX mode
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Memory write timing in maximum mode :

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 8086 MAX mode
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RQ/GT timings in maximum mode :

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 Numeric Coprocessor 8087
– 8087 takes control of system bus by the following RQ/GT
sequence

– 8087 sends out a low going pulse on its RQ/GT pin of one
clock pulse duration

– 8087 waits for the grant pulse from the host (8086)

– Once granted, 8087 proceeds with bus operation (memory

read or memory write operations)

– After completion, another low going pulse is sent out by

8087 on its RQ/GT pin, to let 8086 to take back the bus

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