Microprocessor & Interfacing

(8086 family microprocessors)

Jimmy Mathew
Asst. Professor Sr.,
School of Computing Science & Engineering (SCSE),
VIT University, Vellore, India
Email: jimmym@vit.ac.in / Room: SJT 313 A 08
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 8086 pin details
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Available clock rates: 5 MHz, 8 MHz, 10 MHz

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40 pins

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Ceramic Dual-In-Line package (CERDIP)

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Two modes of operations:

– 1. Minimum mode (Uniprocessor mode)

– 2. Maximum mode (Multiprocessor mode)

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Signal categories :

– 1. Common signals (in MIN & MAX modes):

• GND, AD15-AD0, A19/S6 - A16/S3, NMI, INTR, CLK, RESET,

READY, TEST, RD, MN/MX, BHE/S7, VCC

– 2. Special signals in MIN mode:

• INTA, ALE, DEN, DT/R, M/IO, WR, HLDA, HOLD

– 3. Special signals in MAX mode:

• QS1-QS0, S2-S0, LOCK, RQ/GT1 - RQ/GT0

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AD15 - AD0

– Address lines / Data lines

– Time multiplexed

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A19/S6 - A16/S3

– Address lines / Status lines

– Time multiplexed

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– S4:S3 – Indicate current active segments (E:S:C:D)

– S5 – Shows status of interrupt enable flag

– S6 – Always logical low

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•BHE/S7

– BHE – Bus High Enable (Active low)

– Indicates transfer of data over D15 – D8 lines

– Used to select odd address memory or peripherals

– S7 – Not used

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•RD

– Read signal (Active low)

– It indicates peripherals that the processor is performing

memory or I/O read operations

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READY

– Used as acknowledgement from slow devices

– Indicates completion of data transfer

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INTR

– Level triggered interrupt request

– Sampled at every last clock of each instruction

– In case of any interrupts, the processor enters interrupt

acknowledge cycle

– Enabled or disabled by interrupt flag (IF)

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TEST

– Used after WAIT instruction

– The processor waits until the TEST signal goes low

– When TEST signal goes low, the execution continues

– Active low

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NMI

– Non-Maskable Interrupt, edge triggered

– Low to High transition initiates interrupt

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RESET

– Stops current execution of processor abruptly

– Forces processor to restart the processing from first

address onwards

– Active high, must be active for at least 4 clock cycles

– Restarts the execution when RESET line returns low

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CLK

– Clock input (5 MHz, 8 MHz, 10 MHz)

– Provides basic timings for processor operations

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VCC

– Voltage supply, +5V DC

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GND

– Ground, 0V DC

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MN/MX

– The logic level at this pin decides whether the processor

is to operate in either minimum (single processor) mode
or maximum (multiprocessor) mode

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M/IO

– Memory operation or I/O operation, output

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INTA

– Interrupt acknowledge, output

– When it goes low, it indicates that

the processor has accepted the interrupt

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ALE

– Address Latch Enable, output

– Informs a valid address is present in address/data lines

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DT/R

– Indicates data transmit or receive, output

– Direction of data flow

– High – Processor transmits data out

– Low – Processor receives data

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DEN

– Data enable, out

– Indicates valid data available at data lines

– To enable or disable bidirectional buffers

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HOLD

– Hold request

– When high, indicates microprocessor that another master

is requesting bus access

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HLDA

– Hold acknowledgement

– The processor is given bus access to the requested master

– The processor halts its operations

– The processor proceeds when HOLD becomes low

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S2, S1, S0 (MAX mode)

– Status lines, indicate current status of processor

• [000] - Interrupt acknowledge

• [001] - Read I/O port

• [010] - Write I/O port

• [011] - Halt

• [100] - Code access

• [101] - Read memory

• [110] - Write memory

• [111] - Passive
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LOCK

– When low, indicates that other masters will be prevented

from requesting a bus access

– Used with LOCK instruction

– Used when processor executes critical instructions

– Unlocks after completion of instructions

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QS1 – QS0

– Queue status lines, provides information about status of

code pre-fetch queue

• [00] - No operation

• [01] - First byte of opcode from queue

• [10] - Empty queue

• [11] - Subsequent byte from the queue

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RQ/GT0 - RQ/GT1

– Request / Grant lines

– Used by other bus masters to force the processor to

release bus access at the end of the current bus cycle

– Used in maximum mode

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