5cbdb While Arrow MLB K18 PDF

8 7 6 5 4 3 2 1
CK
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD
REV ECN DESCRIPTION OF REVISION
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DATE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
SCHEM,WHITE_ARROW,MLB,K18 <REV> <ECN> <ECO_DESCRIPTION> <ECODATE>
02/01/10
D (.csa) Date (.csa) Date (.csa) Date
D
Page 1
Contents Sync MASTER
Page 50
Contents Sync 06/29/2009
Page 100
Contents Sync 06/15/2009
1 46 91
TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_HEAD
Table of Contents MASTER SMC Support K18_SENSORS CPU Constraints K17_REF

2 06/30/2009 51 06/23/2009 101 06/15/2009
2 47 92
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
System Block Diagram K17_REF LPC+SPI Debug Connector K17_MLB Memory Constraints K17_REF
3 06/30/2009 52 06/18/2009 102 06/15/2009
3 48 93
Power Block Diagram K17_REF K18 SMBus Connections K18_SENSORS PCH Constraints 1 K17_REF
4 MASTER 53 06/29/2009 103 06/15/2009
4 49 94
Revision History MASTER Current & Voltage Sensing K18_SENSORS PCH Constraints 2 K17_REF
5 05/28/2009 54 07/02/2009 104 06/15/2009
5 50 95
BOM Configuration K17_REF Current Sensing K18_SENSORS Ethernet Constraints K17_REF

7 MASTER 55 06/18/2009 105 06/15/2009
6 51 96
Functional / ICT Test MASTER Thermal Sensors K18_SENSORS FireWire Constraints K17_REF
8 MASTER 56 05/29/2009 106 06/15/2009
7 52 97
Power Aliases MASTER Fan Connectors K19_MLB SMC Constraints K17_REF

TABLE_TABLEOFCONTENTS_ITEM
9 06/11/2009 TABLE_TABLEOFCONTENTS_ITEM
57 05/29/2009 TABLE_TABLEOFCONTENTS_ITEM
107 06/15/2009
8 10
Signal Aliases K17_REF
06/15/2009 TABLE_TABLEOFCONTENTS_ITEM
53 58
WELLSPRING 1 K19_MLB
98 108
GPU (GT216) CONSTRAINTS K17_REF
06/15/2009
9 11
CPU DMI/PEG/FDI/RSVD K17_REF
54 59
WELLSPRING 2 K19_MLB
99 109
Project Specific Constraints K17_REF
06/15/2009
10 12
CPU Clock/Misc/JTAG K17_REF
55 60
Sudden Motion Sensor (SMS) K19_MLB
100 132
PCB Rule Definitions K17_REF
06/15/2009
11 13
CPU DDR3 Interfaces K17_REF
56 61
DEBUG SENSORS AND ADC K18_SENSORS
101 BluRay Decrypter Card Connector K17_REF
12 14
CPU Power (1 of 2) K17_REF
57 62
SPI ROM K17_REF
09/21/2009
13 15
CPU Power (2 of 2) K17_REF
58 63
AUDIO: CODEC/REGULATOR K18_AUDIO
07/29/2009
14 16
CPU Grounds K17_REF
59 65
AUDIO: LINE INPUT FILTER K18_AUDIO
07/29/2009
15 17
CPU Non-GFX Decoupling (1 of 2) K17_REF
60 66
AUDIO: HEADPHONE FILTER K18_AUDIO
07/29/2009
16 CPU Non-GFX Decoupling (2 of 2) K17_REF 61 AUDIO: SPEAKER AMP K18_AUDIO
C
17 18
19
PCH SATA/PCIE/CLK/LPC/SPI K17_REF
08/24/2009
06/15/2009
62 67
68
AUDIO: JACKS K18_AUDIO
07/29/2009
07/29/2009
C
18 20
PCH DMI/FDI/Graphics K17_REF
63 69
AUDIO: JACK TRANSLATORS K18_AUDIO
06/30/2009
19 21
PCH PCI/FlashCache/USB K18_MLB
64 70
DC-In & Battery Connectors K18_POWER
06/30/2009
20 22
PCH MISC K17_REF
65 72
PBus Supply & Battery Charger K18_POWER
07/13/2009
21 23
PCH Power K17_REF
06/15/2009
66 73
5V / 3.3V Power Supply K18_POWER
07/14/2009
22 67
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
PCH Grounds K17_REF 1.5V DDR3 Supply K18_POWER

24 06/15/2009 74 06/29/2009
23 68
PCH Non-GFX Decoupling K17_REF CPU IMVP VCore Regulator K18_POWER

25 06/15/2009 75 07/08/2009
24 69
CPU/PCH GFX Decoupling K17_REF GFX IMVP VCore Regulator K18_POWER

26 06/15/2009 76 07/14/2009
25 70
eXtended Debug Port (XDP) K17_REF CPUVTT (1.05V) Power Supply K18_POWER
27 06/23/2009 77 06/29/2009
26 71
Clock (CK505) K17_MLB Misc Power Supplies K18_POWER

28 06/15/2009 78 06/10/2009
27 72
Chipset Support K17_REF Power FETs K18_POWER

29 MASTER 79 06/15/2009
28 73
DDR3 SO-DIMM Connector A MASTER Power Control K17_REF

30 MASTER 80 06/15/2009
29 74
DDR3 Byte/Bit Swaps MASTER NV GT216 PCI-E K17_REF

31 MASTER TABLE_TABLEOFCONTENTS_ITEM
81 06/15/2009
30 32
DDR3 SO-DIMM Connector B MASTER
75 82
NV GT216 CORE/FB POWER K17_REF
06/15/2009
31 33
CPU Memory S3 Support K17_REF
76 84
NV GT216 FRAME BUFFER I/F K17_REF
06/15/2009
32 34
FSB/DDR3/FRAMEBUF Vref Margining K17_REF
77 85
GDDR3 Frame Buffer A (Top) K17_REF
06/15/2009
33 35
X16/ALS/CAMERA CONNECTOR K18_COMMS
78 86
GDDR3 Frame Buffer B (Top) K17_REF
06/15/2009
B TABLE_TABLEOFCONTENTS_ITEM
34 36
SecureDigital Card Reader T27_REF
79 87
NV GT216 GPIO/MIO/MISC K17_REF
06/15/2009 B
35 37
USB HUB 1 K18_MLB
80 88
GT216 GPIOS & STRAPS K17_REF
06/15/2009
36 39
USB HUB 2 K23F
81 89
NV GT216 VIDEO INTERFACES K17_REF
07/14/2009
37 40
Ethernet PHY (Caesar II/IV) T27_REF
82 90
GPU (GT216) CORE SUPPLY K18_POWER
05/29/2009
38 41
Ethernet Connector K17_REF
83 93
LVDS Display Connector K19_MLB
06/15/2009
39 42
FireWire LLC/PHY (FW643) K19_MLB
84 94
Muxed Graphics Support K17_REF
06/15/2009
40 43
FireWire Port Power K19_MLB
85 95
DisplayPort Connector K17_REF
06/26/2009
41 45
FireWire Ports K19_MLB
86 96
1V8 / 1V55 FB Power Supply K18_POWER
06/15/2009
42 46
SATA Connectors T27_REF
87 97
Graphics MUX (GMUX) K17_REF
07/29/2009
43 48
External USB Connectors K17_REF
05/29/2009
88 98
LCD BACKLIGHT DRIVER K18_BKLT
05/29/2009
44 89
Front Flex Support K19_MLB LCD Backlight Support K19_MLB

49 06/15/2009 99 06/10/2009
45 90
SMC K17_REF
Misc Power Supplies K18_POWER
Schematic / PCB #’s

ALIASES RESOLVED DRAWING TITLE
SCHEM,WHITE_ARROW,MLB,K18
DRAWING NUMBER
<SCH_NUM> D
SIZE
A
Apple Inc. REVISION

PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION R
<E4LABEL>
051-8504 1 SCHEM,WHITE_ARROW,MLB,K18 SCH CRITICAL NOTICE OF PROPRIETARY PROPERTY: BRANCH
820-2850 1 PCBF,WHITE_ARROW,MLB,K18 PCB CRITICAL

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
<BRANCH>
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
DRAWING
TITLE=MLB
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
1 OF 132
ABBREV=DRAWING III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
LAST_MODIFIED=Mon Feb 1 10:13:48 2010 IV ALL RIGHTS RESERVED 1 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U2600
U8000 INTEL CPU
PRAPHICS 2.X GHZ XDP CONN
PG 25
NV GT216 ARRANDALE
PG 9
PG 73 J2900
2 UDIMMs
DDR3-1067/1333MHZ
DIMM
D PG 28,30
J6950
D
DC/BATT POWER SUPPLY
PG 63
GPIO FDI DMI RTC

PG 20 PG 18 PG 18 PG 17 U4900
TEMP SENSOR
U2700 CLOCK
CK505 Misc PG 44
CLK
PG 20
U6100
P8 26 BUFFER POWER PGSENSE
44
SPI
PG 17 Boot ROM J5650,5660
J4500
SPI FAN CONN AND CONTROL
SATA PG 56 PG 51
PG 17
Conn
HD 1.05V/3GHZ.
P8 40 INTEL U4900
B,0 BSB ADC Fan Ser
J5100
SATA IBEX PEAK-MPCH SMC Prt LPC Conn
J4501
SATA PG 17 LPC Port80,serial
C Conn
1.05V/3GHZ.
PG 17
PG 44
PG 46 C
ODD U1800
P8 40
J9000
PWR
DISPLAY PORT
DP OUT CTRL
CONN
PG 84 RGB OUT
J3401 J5713 J3401 J3401 J4600,J4610,4720
0 1 2 3 4 5 6 7 8 9 10 11 12 13
HDMI OUT
Bluetooth TRACKPAD/ IR CAMERA EXTERNAL
U9600 KEYBOARD USB
DVI OUT Connectors
GMUX PG 33 PG 52 PG 33 PG 33
PG 41
(UP TO 14 DEVICES)
XP2-5 LVDS OUT
PG 85 TMDS OUT
USB
PG 19
PG 18
PCI
PG 19
J9400
LVDS PCI-E
B CONN PG 19 B
SMB
PG 71 JTAG SMB
PG 17
PG 17
CONN
PCI-E HDA PG 47
PEG DIMM’s
(UP TO 16 LINES)
PG 17
PG 17 PG 17
U6200
Audio
Codec
PG 57
U6500 U6610,6620,6630,6640,6650
U4100 U3900 J3500
A FW643 GB
E-NET
EXPRESSCARD Line In HEADPHONE Line Out Speaker
SYNC_MASTER=K17_REF SYNC_DATE=06/30/2009 A
CONN Amp Amp Amp Amps PAGE TITLE
BCM5764M
PG 37
PG 35 PG 34
PG 59 PG 60 System Block Diagram
DRAWING NUMBER SIZE
Apple Inc. <SCH_NUM> D

J3400 J4310 J4000 REVISION
R
Mini PCI-E E-NET E-NET J6780,6781,6782,6700,6750

<E4LABEL>
NOTICE OF PROPRIETARY PROPERTY: BRANCH
AirPort Conn Conn Audio
<BRANCH>
PG 28 Conns THE POSESSOR AGREES TO THE FOLLOWING: PAGE
PG 39 PG 36
PG 61 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
2 OF 132
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 2 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
K17 POWER SYSTEM ARCHITECTURE SMC PWRGD

NCP303LSN SMC_RESET_L
PPDCIN_G3H_OR_PBUS_R U5000
R6905
(PAGE 45)
ENABLE SMC AVREF SUPPLY
3.425V G3HOT
LT3470A PP3V42_G3H PP3V3_S5_AVREF_SMC
SMC_PBUS_VSENSE VIN
U6990 VR5020 VOUT
J6900 F7040 V Q5315
(PAGE 63) (PAGE 45)
SMC_TPAD_RST_L
D
D F6905
R7020
PPBUS_G3H
SMC_ONOFF_L
6A FUSE U5001
AC
ADAPTER
DCIN(16.5V)
A U7000 PPVBAT_G3H_CHGR_REG V SMC_GPU_VSENSE R7640
IN
SMC_DCIN_ISENSE
VIN
ISL6259HRTZ
VOUT
F7041
8A FUSE
PP5V_S3_GPUVCORE
VDD
VIN
GPU VCORE
VOUT A PPVCORE_GPU PP5V_S0_CPUVTTS0
VIN
1.05V
VOUT
A PPCPUVTT_S0
SMC_CPU_FSB_ISENSE
PBUS SUPPLY/ U5410 TPS51513
ISL6263C U7600
BATTERY CHARGER R7050 A VR_ON
U8900
PGOOD
SMC_GPU_ISENSE
CPUVTTS0_EN
EN
PGOOD
CPUVTTS0_PGOOD
SMC_BATT_ISENSE GPUVCORE_EN GPUVCORE_PGOOD (PAGE 69)

(PAGE 64) (PAGE 81)
SMC_CPU_VSENSE
J6950
Q7055 R5388 V
PPVBATT_G3H_CONN PPVBAT_G3H_CHGR_R SMC_CPU_HI_ISENSE CPU VCORE
A PPVCORE_S0_CPU
(6 TO 8.4V)
A VIN
VOUT IBEX PEAK MPM_PWRBTN_L
PWRBTN#
2S4P
ISL9522 SMC_CPU_ISENSE SYS_RERST#

CPUIMVP_VR_ON U7400
CHGR_BGATE VR_ON RSMRST#
PGOOD CPUIMVP_GOOD
ACPRESENT
(PAGE 67)
PM_PCH_PWRGD
PS_PWRGD PLT_RERST_L
PLTRST#
U1800 CPU_PWRGD
C GMUX PB16B EG_RAIL1_EN P1V1GPU_EN
PROCPWRGD
PM_MEM_PWRGD
C
DRAMPWROK
U5440
EG_RAIL2_EN P3V3GPU_EN PP5V_S3_DDRREG U2850 (PAGE 17~22)
PB17A SMC_CPU_DDR_VSENSE
U9600
PB17B
EG_RAIL3_EN GPUVCORE_EN
R7350
XP2-5 PB18A
EG_RAIL4_EN P1V8_S0GPU_EN
DDRREG_EN 1.5V
VIN VLDOIN
SMC_DDR_ISENSE
V
(PAGE 86)
PL32A PM_ALL_GPU_PGOOD
P1V1GPU_EN
EN1 VIN
VOUT1
PP1V1_S0GPU
DDRVTT_EN
S5
S3 0.75V
VOUT1
PPDDR_S3_REG
A PP1V5_S3
1.103V(L/H) R5413 VOUT2 PPVTT_S0_DDR_LDO SM_DRAMPWROK

CPU
SMC P1V8FB_EN
EN2
1.8V(R/H)
VOUT2
A PP1V8_S0GPU
SMC_GPU_1V8_ISENSE
TPS51116
U7300 PGOOD
DDRREG_PGOOD U1000 VCCCPUPWRGD
(PAGE 66)
U4900 ISL6236 POK1 P1V1GPU_PGOOD RESET*
(PAGE 9~14)
RC P3V3S5_EN U9500 P1V8FB_PGOOD Q7860 Q7850
P60 POK2 SLG5AP020 PP1V5_S0
DELAY (PAGE 85) PP5V_S0_FET P1V5DDR_EN VOUT
SMC_PM_G2_EN ON PP1V2_GMUX_FET
(PAGE 44) U7801
VIN P5VS0_EN P1V2GMUX_EN

P5VS3_EN VOUT1
PP5V_S3
IBEX_PEAK_M EN1 5V
(L/H) PM_ALL_GPU_PGOOD
PP3V3_S5 PP3V3_S5
PM_SLP_S5_L P3V3S5_EN VIN U7980
SLP_S5#(E4) EN2 3.3V
VOUT2
P1V2ENET_EN
EN
ISL8009B PP1V2_ENET SMC
Q9806 (R/H) U7760 VOUT
B RC P5VS3_EN TPS51980
Q7870 (PAGE 70)
ALL_SYS_PWRGD
PWRGD(P12)
SMC_ADAPTER_EN
(P64)
B
U7201 PP3V3_S0_GPU
DELAY
(PAGE 65) RSMRST_PWRGD RSMRST_IN(P13) PM_RSMRST_L
RSMRST_OUT(P15)
PGOOD1 PGOOD2
RC DDRREG_EN BKLT_PLT_RST_L P1V5_EXP_S0_EN VIN PP1V5_EXP_S0 SMC_ONOFF_L 99ms DLY
P3V3S5_PGOOD EN ISL8009B PWR_BUTTON(P90) IMVP_VR_ON
DELAY && VIN P3V3GPU_EN
U7710 OUT IMVP_VR_ON(P16)
U1800 LCD_BKLT_EN APP001 (PAGE 70)

P5VS3_PGOOD Q7810 PM_SYSRST_L
P3V3S3_EN SYSRST(PA2)
BKLT_EN U9700 PPVOUT_S0_LCDBKLT PP3V3_S3
ENA VOUT Q7922 PP3V3_ENET
PP3V3_S0_PWRCTL
PM_PWRBTN_L
P17(BTN_OUT)
PM_SLP_S4_L (PAGE 87) P1V8S0_PGOOD
SLP_S4#(H7) PM_SLP_S5_L
P3V3S3_EN SLP_S5_L(P95)
PM_SLP_S3_L&&WOL_EN||SMC_ADAPTER_EN P5VS3_PGOOD SMC_RESET_L
Q4260 Q7830 PM_SLP_S4_L RES*
SLP_S4_L(P94)
PM_SLP_S3_L PFWBOOST S0PGOOD_PWROK PM_SLP_S3_L
SLP_S3#(P12) LTC1872 PP3V3_S0_FET SLP_S3_L(P93)
VIN VOUT VIN PP1V8_S0
U7790 P1V8_S0_EN ISL8014
VOUT
(PAGE 17~22) (PAGE 70) EN U4900
U7720 P1V8S0_PGOOD PP3V3_S0 (PAGE 44)
P3V3S0_EN
(PAGE 70) PGOOD
SMC_ADAPTER_EN&&PM_SLP_S3_L Q3810
SMC_GFX_VSENSE VCC
R7978 Q4291 PP1V5_S0 U7971
PM_SLP_S3_L_R
R7540
GFXIMVP_ISENSE
V PP3V3_FW_FET
ADJ1
ISL88042IRTEZ
RST*
VIN PP1V05_S0
A RC P1V8S0_EN GFX_VR_ENVR_ON
1.05V AUX
TPS51981
VOUT A PPVCORE_S0_GFX FW_PWR_EN
ADJ2
(PAGE 72)
P5VS0_EN TRST = 200mS
DELAY PAGE TITLE
U7500
RC P1V2GMUX_EN
(PAGE 68)
Power Block Diagram
DRAWING NUMBER SIZE
DELAY
P3V3S0_EN
GFX_DPRSLPVR Apple Inc. <SCH_NUM> D
DPRSLPVR GFXIMVP_PGOOD REVISION
RC CPUVTTS0_EN PGOOD R
DELAY
<E4LABEL>
PBUSVSENS_EN NOTICE OF PROPRIETARY PROPERTY: BRANCH
RC P1V5DDR_EN THE INFORMATION CONTAINED HEREIN IS THE

<BRANCH>
DELAY I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
3 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PROTO:
D D
C C
B B
A SYNC_MASTER=MASTER SYNC_DATE=MASTER A
PAGE TITLE
Revision History
DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
4 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BOM Variants Alternate Parts TABLE_ALT_HEAD
TABLE_BOMGROUP_HEAD
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

BOM NUMBER BOM NAME BOM OPTIONS PART NUMBER
TABLE_BOMGROUP_ITEM TABLE_ALT_ITEM
639-0952 PCBA,2.0G,512SAM_VRAM,K18 K18_COMMON,CPU_2_4GHZ,FB_256_SAMSUNG,K18_PVT,EEEE_DCJ7 138S0603 138S0602 ALL Murata alt to Samsung

639-0953 PCBA,2.0G,512HYN_VRAM,K18 K18_COMMON,CPU_2_4GHZ,FB_256_HYNIX,K18_PVT,EEEE_DCJ8 157S0058 157S0055 ALL Delta alt to TDK Magnetics
639-0954 PCBA,2.13G,512SAM_VRAM,K18 K18_COMMON,CPU_2_53GHZ,FB_512_SAMSUNG,K18_PVT,EEEE_DCJ9 152S0896 152S0518 ALL MAG LAYERS ALT TO CYNTEC
639-0955 PCBA,2.13G,512HYN_VRAM,K18 K18_COMMON,CPU_2_53GHZ,FB_512_HYNIX,K18_PVT,EEEE_DCJC 155S0457 155S0329 ALL MAG LAYERS ALT TO MURATA
639-0956 PCBA,2.4G,512SAM_VRAM,K18 K18_COMMON,CPU_2_66GHZ,FB_512_SAMSUNG,K18_PVT,EEEE_DCJD 333S0506 333S0535 ALL Hynix 900M alt to 1000M
D 639-0957 PCBA,2.4G,512HYN_VRAM,K18 K18_COMMON,CPU_2_66GHZ,FB_512_HYNIX,K18_PVT,EEEE_DCJF

TABLE_BOMGROUP_ITEM
516S0805 516S0806 ALL Molex alt to Foxconn
TABLE_ALT_ITEM
D
085-1404 K18 DEVELOPMENT BOM 152S1102 152S1088 ALL Mag layer alt to Vishay
TABLE_ALT_ITEM
353S2805 353S2603 ALL Fairchild wafer option

TABLE_ALT_ITEM
333S0542 333S0507 ALL Samsung I die alt to H

TABLE_ALT_ITEM
128S0264 128S0257 ALL Sanyo alt to Kemet
K18 BOM GROUPS TABLE_BOMGROUP_HEAD

128S0303 128S0282 ALL Panasonic alt to Sanyo
TABLE_ALT_ITEM
TABLE_ALT_ITEM
BOM GROUP BOM OPTIONS 337S3808 337S3839 ALL A02 alt to A03 GPU
K18_COMMON ALTERNATE,COMMON,K18_COMMON1,K18_COMMON2,K18_PROGPARTS,USBHUB_2061,RDRV:8515A2,DCI 128S0305 128S0294 ALL 6.3V alt to 11V Sanyo

TABLE_BOMGROUP_ITEM
K18_COMMON1 BATT_3S,BCM5764M,GL137,CPUPOC_IMAX_40_50,CPUMEM_S0,SMC_EXCARD_NOT,SMC_DEBUG_YES,HUB1_2NONREM,HUB2_3NONREM
TABLE_BOMGROUP_ITEM
K18_COMMON2 GMUXPLL_3V3,GPU_SS_INT,MIKEY,GPUVID_0P90V,DPMUX_EN_PLD,DP_CA_DET_EG_PLD,DP_ESD,VFRQ_SLPS3,SMC_OSC_YES,RAIL_MON
TABLE_BOMGROUP_ITEM
K18_PVT BMON_PROD,VREFMRGN_NOT,XDP,XDP_NORMAL,XDP_CPU_BPM
TABLE_BOMGROUP_ITEM
K18_PROGPARTS GMUX_PROG,BOOTROM_PROG,SMC_PROG,TPAD_PROG
TABLE_BOMGROUP_HEAD
BOM GROUP BOM OPTIONS

TABLE_BOMGROUP_ITEM
FB_256_SAMSUNG VRAM4,VRAM_256_SAMSUNG,FB1V55
TABLE_BOMGROUP_ITEM
FB_256_HYNIX VRAM4,VRAM_256_HYNIX,FB1V55
TABLE_BOMGROUP_ITEM
FB_512_SAMSUNG VRAM4,VRAM_512_SAMSUNG,FB1V35
TABLE_BOMGROUP_ITEM
FB_512_HYNIX VRAM4,VRAM_512_HYNIX,FB1V35
C C
Bar Code Labels / EEE #’s

PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE:DCJ7] CRITICAL EEEE_DCJ7
826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE:DCJC] CRITICAL EEEE_DCJC
826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE:DCJD] CRITICAL EEEE_DCJD
826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE:DCJF] CRITICAL EEEE_DCJF
B
Module Parts B
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
337S3848 1 ARD,SLBPE,PRQ,2.66G,35W,C2,3M,BGA U1000 CRITICAL CPU_2_66GHZ
337S3847 1 ARD,SLBPF,PRQ,2.53G,35W,C2,3M,BGA U1000 CRITICAL CPU_2_53GHZ
337S3846 1 ARD,SLBNA,PRQ,2.4G,35W,C2,4M,BGA U1000 CRITICAL CPU_2_4GHZ
337S3849 1 IC,PCH,IBEX PEAK-M,SLGZS,PRQ,B3,BGA U1800 CRITICAL
337S3839 1 IC,GPU,NV GT216 LP++,969BGA,40NM,A03 U8000 CRITICAL
343S0493 1 IC,ASIC,BCM5764M,ENET CONTROLLER,8x8,64 QFN U3900 CRITICAL BCM5764M
341S2731 1 IC,1MBIT,SPI FLASH,K17/K18 U3990 CRITICAL
338S0753 1 IC,FW643-E2,1394B PHY/OHCI LINK/PCI-E,12 U4100 CRITICAL
338S0563 1 IC,SMC,HS8/2117,9MMX9MM,TLP U4900 CRITICAL SMC_BLANK
341T0233 1 IC,SMC,K18 U4900 CRITICAL SMC_PROG
335S0610 1 IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP U6100 CRITICAL BOOTROM_BLANK
341S2562 1 IC,EFI ROM,DEVELOPMENT,K18 U6100 CRITICAL BOOTROM_PROG
341S2384 1 IR,ENCORE II, CY7C63833-LFXC U4800 CRITICAL

341S2616 1 IC,PSOC +W/USB,56PIN,MLF,K18 U5701 CRITICAL TPAD_PROG
336S0025 1 IC,XP2-5,HF,CPLD,BLANK U9600 CRITICAL GMUX_5K_BLANK
341S2566 1 IC,CPLD,LATTICE,132CSBGA,K18 U9600 CRITICAL GMUX_PROG

A 333S0507 4 IC,SGRAM,GDDR3,16MX32,1000MHZ,136 FBGA U8400,U8450,U8500,U8550 CRITICAL VRAM_256_SAMSUNG SYNC_MASTER=K17_REF SYNC_DATE=05/28/2009 A
PAGE TITLE
333S0483 4 IC,SDRAM,GDDR3,16MX32,900MHZ,136 FBGA U8400,U8450,U8500,U8550 CRITICAL VRAM_256_HYNIX
BOM Configuration
333S0533 4 IC,SGRAM,GDDR3,32MX32,1000MHZ,136 FBGA U8400,U8450,U8500,U8550 CRITICAL VRAM_512_SAMSUNG DRAWING NUMBER SIZE
333S0535 4 IC,SDRAM,GDDR3,32MX32,1000MHZ,136 FBGA U8400,U8450,U8500,U8550 CRITICAL VRAM_512_HYNIX Apple Inc. <SCH_NUM> D

REVISION
R
<E4LABEL>
Development BOM NOTICE OF PROPRIETARY PROPERTY:
BRANCH
<BRANCH>
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION THE POSESSOR AGREES TO THE FOLLOWING: PAGE
085-1404 1 K18 MLB DEVELOPMENT DEVEL CRITICAL DEVEL_BOM

5 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
J5713 (KEY BOARD CONN) 73 87 101
TRUE PP3V3_S3
FUNC_TEST
I720 TRUE BKLT_EN
ICT Test Points NC NO_TESTs
Functional Test Points USB PORTS I1103
TRUE PP3V42_G3H
35 36 48 50
6 7 8 17 20
31 32 33 34
53 54 55 72
88
I722 TRUE TP_ISSP_SCLK_P1_1 8 53

NO_TEST
TRUE NC_SMC_FAN_3_TACH 45 46
I1038 TRUE PP5V_S3_RTUSB_A_F 43
I1102
TRUE WS_KBD1
6
7 17 21 23 CPU NO_TESTs I1297
NC_SMC_FAN_3_CTL 45 46
I724 TRUE TP_ISSP_SDATA_P1_0 8 53
43 45 46 47
I1104 5348 49 53 64 I761 TRUE
J5650 (LEFT FAN CONN) I1039 TRUE USB2_LT1_N 43 99 65 66 73
I1105 TRUE WS_KBD2 53 I723 TRUE LCD_BKLT_PWM 87 88 NO_TEST I762 TRUE NC_SMC_FAN_2_TACH 45 46
FUNC_TEST I1040 TRUE USB2_LT1_P 43 99
3 TPs I1107 TRUE WS_KBD3 53 I725 TRUE LPCPLUS_GPIO 20 47 I763 TRUE NC_SMC_FAN_2_CTL 45 46
TRUE PP5V_S0 70 72 86 88
6 7 23 42 47 per Fan TRUE GND 9 TP_CPU_RSVD<65..62> TRUE NC_TP_CPU_RSVD<65..62>
52 54 68 69
I1106 TRUE WS_KBD4 53 I726 TRUE LPCPLUS_RESET_L 27 47 87 94 MAKE_BASE=TRUE I764 TRUE NC_FW2_TPBP 39 41
TRUE FAN_LT_PWM 52 I1108 TRUE WS_KBD5 53 I727 TRUE LPC_AD<0..3> 17 45 47 87 94 9 TP_CPU_RSVD<58..45> TRUE NC_TP_CPU_RSVD<58..45> I765 TRUE NC_FW2_TPBN 39 41
LPC_CLK33M_LPCPLUS 27 47 94 MAKE_BASE=TRUE
TRUE FAN_LT_TACH 52 I1042 TRUE PP5V_S3_RTUSB_B_F 43 I1109 TRUE WS_KBD6 53 I729 TRUE I767 TRUE NC_FW2_TPBIAS 39 41
LPC_FRAME_L TP_CPU_RSVD<43..32> TRUE NC_TP_CPU_RSVD<43..32> 9
I1043 TRUE USB_LT2_N 43 99 I1110 TRUE WS_KBD7 53 I728 TRUE 17 45 47 87 94 MAKE_BASE=TRUE I766 TRUE NC_FW2_TPAP 39 41
J5660 (RIGHT FAN CONN) USB_LT2_P
I1044 TRUE 43 99 I1111 TRUE WS_KBD8 53 I730 TRUE LPC_PWRDWN_L 18 45 47 9 TP_CPU_RSVD<27..26> TRUE NC_TP_CPU_RSVD<27..26> I769 TRUE NC_FW2_TPAN 39 41
MAKE_BASE=TRUE
TRUE FAN_RT_PWM 52 TRUE GND I1112 TRUE WS_KBD9 53 I732 TRUE LPC_SERIRQ 17 45 47 I768 TRUE NC_FW0_TPBP 39 41 96
9 TP_CPU_RSVD<24..15> TRUE NC_TP_CPU_RSVD<24..15>
D TRUE
TRUE
FAN_RT_TACH
GND
52
5 TPs
I1113
I1114
TRUE WS_KBD10
TRUE WS_KBD11
53
53
I731 TRUE
I734 TRUE
PM_CLKRUN_L
PM_SYSRST_L
18 45 47
18 27 45 9 TP_CPU_RSVD<2..1>
MAKE_BASE=TRUE
TRUE NC_TP_CPU_RSVD<2..1>
I770
I772
TRUE
TRUE
NC_FW0_TPBN
NC_FW0_TPAP
39 41 96
39 41 96
D
per Fan TRUE WS_KBD12 SMC_MD1
MAKE_BASE=TRUE
NC_ESTARLDO_EN 45 46
I1115 53 I733 TRUE 45 47
TP_CPU_RSVD_NCTF<8..5> NC_TP_CPU_RSVD_NCTF<8..5> I771 TRUE
TRUE 9
I1117 TRUE WS_KBD13 53 I735 TRUE SMC_NMI 45 47 MAKE_BASE=TRUE I774 TRUE NC_ALS_GAIN 45 46
J6780 (MIC CONN) TRUE WS_KBD14 TRUE SMC_ONOFF_L

I1116
TRUE WS_KBD15_CAP
53
SMC_RESET_L
45 46 53
NC NO_TESTs 39 6 NC_FW643_AVREG TRUE NC_FW643_AVREG 6 39
I1118 53 I737 TRUE 45 46 47 65
NC_FW643_TDI MAKE_BASE=TRUE
NC_FW643_TDI
NO_TEST 39 6 TRUE 6 39
I557 TRUE BI_MIC_N 62 63 I1119 TRUE WS_KBD16_NUM 53 I739 TRUE SMC_RX_L 43 45 46 47 MAKE_BASE=TRUE
SMC_TCK 18 6 NC_CRT_IG_BLUE TRUE NC_CRT_IG_BLUE 6 18
TRUE BI_MIC_SHIELD 62 63 J3401 & J3402 (AIRPORT/BT/CAMERA CONN) I1120 TRUE WS_KBD17 53 I738 TRUE 45 46 47 MAKE_BASE=TRUE 18 6 NC_DP_IG_C_HPD TRUE NC_DP_IG_C_HPD 6 18
I558
SMC_TDI 18 6 NC_CRT_IG_GREEN TRUE NC_CRT_IG_GREEN 6 18 MAKE_BASE=TRUE
TRUE BI_MIC_P 62 63 I1051 TRUE PCIE_AP_D2R_P 17 33 94 I1122 TRUE WS_KBD18 53 I740 TRUE 45 46 47 MAKE_BASE=TRUE 18 6 NC_DP_IG_C_CTRL_CLK TRUE NC_DP_IG_C_CTRL_CLK 6 18
I559
18 6 NC_CRT_IG_RED TRUE NC_CRT_IG_RED 6 18 MAKE_BASE=TRUE
I1050 TRUE PCIE_AP_D2R_N 17 33 94 I1121 TRUE WS_KBD19 53 I741 TRUE SMC_TDO 45 46 47 MAKE_BASE=TRUE 18 6 NC_DP_IG_C_CTRL_DATA TRUE NC_DP_IG_C_CTRL_DATA 6 18
MAKE_BASE=TRUE
I1053 TRUE PCIE_AP_R2D_P 33 94 I1123 TRUE WS_KBD20 53 I742 TRUE SMC_TMS 45 46 47 TP_DP_IG_C_MLP<3..0> TRUE NC_DP_IG_C_MLP<3..0> 18
18 6 NC_CRT_IG_DDC_CLK TRUE NC_CRT_IG_DDC_CLK 6 18 MAKE_BASE=TRUE
I1052 TRUE PCIE_AP_R2D_N 33 94 I1124 TRUE WS_KBD21 53 I743 TRUE SMC_TRST_L 45 47
NC_CRT_IG_DDC_DATA MAKE_BASE=TRUE
NC_CRT_IG_DDC_DATA
TP_DP_IG_C_MLN<3..0> TRUE NC_DP_IG_C_MLN<3..0> 18
18 6 TRUE 6 18 MAKE_BASE=TRUE
I1054 TRUE PCIE_CLK100M_AP_CONN_P 33 99 I1125 TRUE WS_KBD22 53 I744 TRUE SMC_TX_L 43 45 46 47 MAKE_BASE=TRUE 18 6 NC_DP_IG_C_AUXP TRUE NC_DP_IG_C_AUXP 6 18
MAKE_BASE=TRUE
I1056 TRUE PCIE_CLK100M_AP_CONN_N 33
I1127 TRUE WS_KBD23 53 I751 TRUE SPIROM_USE_MLB 20 47 57 18 6 NC_DP_IG_C_AUXN TRUE NC_DP_IG_C_AUXN 6 18
99
18 6 NC_CRT_IG_HSYNC TRUE NC_CRT_IG_HSYNC 6 18 MAKE_BASE=TRUE
I1055 TRUE AP_CLKREQ_Q_L 33 I1126 TRUE WS_KBD_ONOFF_L 53 I752 TRUE SPI_ALT_CLK 47 MAKE_BASE=TRUE
18 6 NC_CRT_IG_VSYNC TRUE NC_CRT_IG_VSYNC 6 18 18 6 NC_DP_IG_D_HPD TRUE NC_DP_IG_D_HPD 6 18
I1058 TRUE PCIE_WAKE_L 18 27 33 I1128 TRUE WS_LEFT_SHIFT_KBD 53 I760 TRUE SPI_ALT_CS_L 47 MAKE_BASE=TRUE
NC_DP_IG_D_CTRL_CLK MAKE_BASE=TRUE
NC_DP_IG_D_CTRL_CLK
18 6 TRUE 6 18
I1057 TRUE AP_RESET_CONN_L 33 I1129 TRUE WS_LEFT_OPTION_KBD 53 I756 TRUE SPI_ALT_MISO 47
NC_LVDS_IG_CTRL_CLK NC_LVDS_IG_CTRL_CLK NC_DP_IG_D_CTRL_DATA MAKE_BASE=TRUE
NC_DP_IG_D_CTRL_DATA
18 6 TRUE 6 18 18 6 TRUE 6 18
I1059 TRUE PP3V3_WLAN 33 I1130 TRUE WS_CONTROL_KBD 53 I1292 TRUE SPI_ALT_MOSI 47 MAKE_BASE=TRUE MAKE_BASE=TRUE
18 6 NC_LVDS_IG_CTRL_DATA TRUE NC_LVDS_IG_CTRL_DATA 6 18 TP_DP_IG_D_MLP<3..0> TRUE NC_DP_IG_D_MLP<3..0> 18
I1061 TRUE PP5V_S3_ALSCAMERA_F 33 I1288 TRUE SYS_LED_ANODE_R 42
NC_PCH_LVDS_VBG MAKE_BASE=TRUE
NC_PCH_LVDS_VBG TP_DP_IG_D_MLN<3..0> MAKE_BASE=TRUE
NC_DP_IG_D_MLN<3..0>
18 6 TRUE 6 18 TRUE 18
J6781 & J6782 (SPEAKERS CONN) I1060 TRUE SMBUS_SMC_A_S3_SDA 6 33 45 48 54 97 J6950 (BIL CABLE CONN) MAKE_BASE=TRUE
NC_DP_IG_D_AUXP MAKE_BASE=TRUE
NC_DP_IG_D_AUXP
18 6 TRUE 6 18
SPKRCONN_L_OUT_P I1063 TRUE SMBUS_SMC_A_S3_SCL 6 33 45 48 54 97 NC_DP_IG_D_AUXN MAKE_BASE=TRUE

NC_DP_IG_D_AUXN
I989 TRUE 61 62 99 18 6 TRUE 6 18
I1062 TRUE USB_CAMERA_CONN_P 33 93 17 6 NC_HDA_SDIN1 TRUE NC_HDA_SDIN1 6 17 MAKE_BASE=TRUE
I990 TRUE SPKRCONN_L_OUT_N 61 62 99
I1150 TRUE PP5V_S3_IR_R 42 MAKE_BASE=TRUE
SPKRCONN_R_OUT_P I1064 TRUE USB_CAMERA_CONN_N 33 93 17 6 NC_HDA_SDIN2 TRUE NC_HDA_SDIN2 6 17
I992 TRUE 61 62 99
I1149 TRUE SMC_LID_R 64 MAKE_BASE=TRUE 18 6 NC_SDVO_TVCLKINN TRUE NC_SDVO_TVCLKINN 6 18
SPKRCONN_R_OUT_N I1066 TRUE CONN_USB2_BT_P 33 99 17 6 NC_HDA_SDIN3 TRUE NC_HDA_SDIN3 6 17 MAKE_BASE=TRUE

I991 TRUE 61 62 99
I1151 TRUE IR_RX_OUT 42 44 MAKE_BASE=TRUE 18 6 NC_SDVO_TVCLKINP TRUE NC_SDVO_TVCLKINP 6 18
SPKRCONN_S_OUT_P I1065 TRUE CONN_USB2_BT_N 33 99 MAKE_BASE=TRUE

I994 TRUE 61 62 99
I1152 TRUE SYS_LED_ANODE 42 46
NC_SDVO_STALLN NC_SDVO_STALLN
18 6 TRUE
I993 TRUE SPKRCONN_S_OUT_N 61 62 99 J3500 (SD CARD CONN) GNDTRUE
NCNO_TEST
NO_TESTs 18 6 NC_SDVO_STALLP MAKE_BASE=TRUE
TRUE NC_SDVO_STALLP
6 18
6 18
C J9000 (LVDS CONN)

TRUE SD_D<7..0> 34
TP_PCI_AD<31..0>
TP_PCI_C_BE_L<3..0>
TRUE
MAKE_BASE=TRUE
TRUE
NC_PCI_AD<31..0> 19
NC_PCI_C_BE_L<3..0> 19
18 6 NC_SDVO_INTN
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
NC_SDVO_INTN 6 18
C
I1452
MAKE_BASE=TRUE 18 6 NC_SDVO_INTP TRUE NC_SDVO_INTP 6 18
I1451 TRUE SD_CMD 34 19 6 NC_PCI_GNT3_L TRUE NC_PCI_GNT3_L 6 19 MAKE_BASE=TRUE
MAKE_BASE=TRUE
I995 TRUE PP3V3_SW_LCD 83 TRUE SD_CLK 34 19 6 NC_PCI_GNT2_L TRUE NC_PCI_GNT2_L 6 19
84 85 87 88 99 I1453
MAKE_BASE=TRUE NC_GPU_BUFRST_L TRUE NC_GPU_BUFRST_L 6 74
I996 TRUE PP3V3_S0 50 51 52 54 58 62 63 68 69 72
6 7 17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48 I1454 TRUE SD_CD_L 34 37 POWER RAILS 19 6 NC_PCI_GNT1_L TRUE
MAKE_BASE=TRUE
NC_PCI_GNT1_L 6 19
74 6
80 79 TP_GPU_GSTATE<0> MAKE_BASE=TRUE
TRUE NC_GPU_GSTATE<0>
I997 TRUE PPVOUT_S0_LCDBKLT 73 80 83 2 TP needed TRUE SD_WP 34 37 FUNC_TEST 19 6 NC_PCI_GNT0_L TRUE NC_PCI_GNT0_L 6 19 MAKE_BASE=TRUE
I1455
MAKE_BASE=TRUE 80 TP_GPU_GSTATE<1> TRUE NC_GPU_GSTATE<1>
I998 TRUE LVDS_DDC_CLK 83 84 19 6 NC_PCI_PAR TRUE NC_PCI_PAR 6 19 MAKE_BASE=TRUE
TRUE GND 2 TPs TRUE PM_SLP_S3_L 18 31 45 73 85 MAKE_BASE=TRUE 80 79 TP_GPU_MIOA_D<9..0> TRUE NC_GPU_MIOA_D<9..0>
I1000 TRUE LVDS_DDC_DATA 83 84
I640
19 6 NC_PCI_RESET_L TRUE NC_PCI_RESET_L 6 19 MAKE_BASE=TRUE
TRUE PP0V75_S0_DDRVTT 7 28 30 31 67 MAKE_BASE=TRUE 80 79 TP_GPU_MIOA_DE TRUE NC_GPU_MIOA_DE
I1001 TRUE LVDS_CONN_A_DATA_P<0> 83 84 98 I602
19 6 NC_PCI_PME_L TRUE NC_PCI_PME_L 6 19 MAKE_BASE=TRUE
TRUE PP18V5_S3 6 54 MAKE_BASE=TRUE
I1002 TRUE LVDS_CONN_A_DATA_N<0> 83 84 98 I603
19 6 NC_PCI_CLK33M_OUT3 TRUE NC_PCI_CLK33M_OUT3 6 19
TRUE PP1V05_S0 7 10 12 13 15 17 18 20 21 23 24 MAKE_BASE=TRUE
I1004 TRUE LVDS_CONN_A_DATA_P<1> 83 84 98 I604 25 26 40 70 73 86
TRUE PP1V05_S0GPU 7 74 76 79 81 86 19 6 NC_PCH_NV_RCOMP TRUE NC_PCH_NV_RCOMP 6 19
MAKE_BASE=TRUE 6 NC_LVDS_EG_BKL_PWM TRUE NC_LVDS_EG_BKL_PWM 6
TRUE PP1V05_S5 7 17 71 TP_NV_DQ<15..0> TRUE NC_NV_DQ<15..0> 19 MAKE_BASE=TRUE
I1005 TRUE LVDS_CONN_A_DATA_P<2> 83 84 98 I607
MAKE_BASE=TRUE 93 18 8 TP_LVDS_IG_B_CLKN TRUE NC_LVDS_IG_B_CLKN
TRUE PP1V0_FW_FWPHY 7 39 40 TP_NV_DQS<1..0> TRUE NC_NV_DQS<1..0> 19 MAKE_BASE=TRUE
MAKE_BASE=TRUE 93 18 8 TP_LVDS_IG_B_CLKP TRUE NC_LVDS_IG_B_CLKP
I610 TRUE PP1V2_ENET 7 37 71 72 MAKE_BASE=TRUE
I1006 TRUE LVDS_CONN_A_CLK_F_P 83 98 TP_NV_CE_L<3..0> TRUE NC_NV_CE_L<3..0> 19 18 8 TP_LVDS_IG_BKL_PWM TRUE NC_LVDS_IG_BKL_PWM
TRUE PP1V2_S0 7 72 87 MAKE_BASE=TRUE MAKE_BASE=TRUE
I1009 TRUE LVDS_CONN_A_CLK_F_N 83 98 I612
TRUE PP1V5_S3 7 28 30 31 67 72 19 6 NC_NV_ALE TRUE NC_NV_ALE 6 19
I1008 TRUE LVDS_CONN_B_DATA_P<0> 83 84 98 I611
PP1V5_S3RS0 MAKE_BASE=TRUE 6 NC_SMC_BS_ALRT_L TRUE NC_SMC_BS_ALRT_L 6
TRUE 7 13 16 31 42 72 73 99 19 6 NC_NV_CLE TRUE NC_NV_CLE 6 19 MAKE_BASE=TRUE
I1010 TRUE LVDS_CONN_B_DATA_N<0> 83 84 98 I613
PP1V8R1V55_S0GPU_ISNS MAKE_BASE=TRUE
TRUE 7 8 50 56 75 76 77 78
19 6 NC_NV_RB_L TRUE NC_NV_RB_L 6 19 20 6 NC_PCH_SST TRUE NC_PCH_SST 6 20
I1011 TRUE LVDS_CONN_B_DATA_P<1> 83 84 98 J5800 (IPD FLEX CONN) I600
MAKE_BASE=TRUE MAKE_BASE=TRUE
TRUE PP1V8R1V55_S0GPU_ISNS_R 7 50 86 TP_NV_WR_RE_L<1..0> TRUE NC_NV_WR_RE_L<1..0> 19 20 6 NC_PCH_NC1 TRUE NC_PCH_NC1 6 20
TRUE PP1V8_GPUIFPX 7 72 81 TP_NV_WE_CK_L<1..0> TRUE NC_NV_WE_CK_L<1..0> 19 20 6 NC_PCH_NC2 TRUE NC_PCH_NC2 6 20
I1014 TRUE LVDS_CONN_B_DATA_P<2> 83 84 98 I1086 TRUE PP18V5_S3 6 54
I624
TRUE PP1V8_S0 7 12 16 21 23 24 58 71 72 87 NC_PCH_NC3 TRUE NC_PCH_NC3
17 6 NC_PCIE_CLK100M_PE4N TRUE NC_PCIE_CLK100M_PE4N 6 1720 6
MAKE_BASE=TRUE 6 20
TRUE PP3V3_ENET 7 27 37 73 MAKE_BASE=TRUE NC_PCH_NC4 TRUE NC_PCH_NC4

I1015 TRUE LVDS_CONN_B_CLK_F_P 83 98 I1273 TRUE Z2_CS_L 53 54
I620
17 6 NC_PCIE_CLK100M_PE4P TRUE NC_PCIE_CLK100M_PE4P 6 1720 6
MAKE_BASE=TRUE 6 20
TRUE PP3V3_FW_FWPHY 7 39 40 41 MAKE_BASE=TRUE NC_PCH_NC5 TRUE NC_PCH_NC5

I1016 TRUE LVDS_CONN_B_CLK_F_N 83 98 I1089 TRUE Z2_DEBUG3 53 54
I621 83 84 85 87 88 99 17 6 NC_PCIE_CLK100M_PE5N TRUE NC_PCIE_CLK100M_PE5N 6 1720 6
MAKE_BASE=TRUE 6 20
TRUE PP3V3_S0 50 51 52 54 58 62 63 68 69 72
6 7 17 18 19 20 21 23 24 25 26 MAKE_BASE=TRUE NC_PCH_TP19 TRUE NC_PCH_TP19
I1017 TRUE LED_RETURN_1 83 88 I1088 TRUE Z2_MISO 53 54
I618 27 28 30 34 37 40 42 46 47 48 17 6 NC_PCIE_CLK100M_PE5P TRUE NC_PCIE_CLK100M_PE5P 6 1720 6
MAKE_BASE=TRUE 6 20
TRUE PP3V3_S0GPU 7 72 74 79 80 81 82 84
73 80
MAKE_BASE=TRUE NC_PCH_TP18 TRUE NC_PCH_TP18
TRUE LED_RETURN_2 I1090 TRUE Z2_BOOST_EN I617
NC_PCIE_CLK100M_PE6N TRUE NC_PCIE_CLK100M_PE6N 6 2020 6
MAKE_BASE=TRUE 6 20
TRUE PP3V3_S3
I1018 83 88 54 20 6
6 7 8 17 20 31 32 33 34 35 36 48 50 53 54 MAKE_BASE=TRUE NC_PCH_TP17 TRUE NC_PCH_TP17
NC_PCIE_CLK100M_PE6P 6 2020 6 6 20
B I1019
I1020
TRUE
TRUE
LED_RETURN_3
LED_RETURN_4
83 88
83 88
I1464
I1098
TRUE
TRUE
Z2_SCLK
Z2_CLKIN
53 54
53 54
I615
I616 TRUE PP3V3_S5

55 72 73 87 101
7 17 18 19 20 21 23 27 31 35 57
66 71 72 73 83 85 99
20 6
20 6
NC_PCIE_CLK100M_PE6P
NC_PCIE_CLK100M_PE7N
TRUE
MAKE_BASE=TRUE
TRUE NC_PCIE_CLK100M_PE7N 6 2020 6 NC_PCH_TP16
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
NC_PCH_TP16 6 20 B
TRUE PP3V3_S5_AVREF_SMC 45 46 MAKE_BASE=TRUE NC_PCH_TP15 TRUE NC_PCH_TP15
I1022 TRUE LED_RETURN_5 83 88 I1097 TRUE Z2_KEY_ACT_L 53 54
I614
20 6 NC_PCIE_CLK100M_PE7P TRUE NC_PCIE_CLK100M_PE7P 6 2020 6
MAKE_BASE=TRUE 6 20
TRUE PP3V42_G3H 6 7 17 21 23 43 45 46 47 48 49 MAKE_BASE=TRUE 20 6 NC_PCH_TP14 TRUE NC_PCH_TP14 6 20

I1021 TRUE LED_RETURN_6 83 88 I1095 TRUE Z2_RESET 53 54
I627 53 64 65 66 73 53 6 NC_PSOC_P1_3 TRUE NC_PSOC_P1_3 6 53 MAKE_BASE=TRUE
TRUE PP5V_S0 6 7 23 42 47 52 54 68 69 70 72 MAKE_BASE=TRUE 20 6 NC_PCH_TP13 TRUE NC_PCH_TP13 6 20
TRUE GND I1096 TRUE PSOC_F_CS_L 53 54
I626 86 88 17 6 NC_SATA_C_D2RN TRUE NC_SATA_C_D2RN 6 17 MAKE_BASE=TRUE
4 TPs TRUE PP5V_S3 7 31 33 42 43 44 46 54 56 58 61 66 67 72 MAKE_BASE=TRUE 20 6 NC_PCH_TP12 TRUE NC_PCH_TP12 6 20
I1092 TRUE PICKB_L 53 54
I639 82 101 17 6 NC_SATA_C_D2RP TRUE NC_SATA_C_D2RP 6 17 MAKE_BASE=TRUE
TRUE PP5V_S5 7 23 66 72 MAKE_BASE=TRUE 20 6 NC_PCH_TP11 TRUE NC_PCH_TP11 6 20
I1093 TRUE PSOC_MISO 53 54
I638
17 6 NC_SATA_C_R2D_CN TRUE NC_SATA_C_R2D_CN 6 17 MAKE_BASE=TRUE
TRUE PPBUS_G3H 7 40 49 65 66 67 69 70 82 86 89 MAKE_BASE=TRUE 20 6 NC_PCH_TP10 TRUE NC_PCH_TP10 6 20
J4500 (SATA ODD CONN) I1094 TRUE PSOC_MOSI 53 54
I637
17 6 NC_SATA_C_R2D_CP TRUE NC_SATA_C_R2D_CP 6 17 MAKE_BASE=TRUE
3 TPs TRUE PPDCIN_G3H 7 64 65 MAKE_BASE=TRUE 20 6 NC_PCH_TP9 TRUE NC_PCH_TP9 6 20
I1099 TRUE PSOC_SCLK 53 54
I636
17 6 NC_SATA_D_D2RN TRUE NC_SATA_D_D2RN 6 17 MAKE_BASE=TRUE
I1024 TRUE PP5V_SW_ODD 42 56 TRUE PPVCORE_GPU 7 49 75 82 MAKE_BASE=TRUE 20 6 NC_PCH_TP8 TRUE NC_PCH_TP8 6 20
I1100 TRUE SMBUS_SMC_A_S3_SCL 6 33 45 48 54 97
I709
17 6 NC_SATA_D_D2RP TRUE NC_SATA_D_D2RP 6 17 MAKE_BASE=TRUE
I1026 TRUE SMC_ODD_DETECT 42 45 I714 TRUE PPVCORE_S0_CPU 7 12 15 49 68 MAKE_BASE=TRUE 20 6 NC_PCH_TP7 TRUE NC_PCH_TP7 6 20
I1101 TRUE SMBUS_SMC_A_S3_SDA 6 33 45 48 54 97 17 6 NC_SATA_D_R2D_CN TRUE NC_SATA_D_R2D_CN 6 17 MAKE_BASE=TRUE
I1025 TRUE SATA_ODD_D2R_C_P 42 93 I1156 TRUE PPVCORE_S0_GFX 7 13 24 49 69 MAKE_BASE=TRUE 20 6 NC_PCH_TP6 TRUE NC_PCH_TP6 6 20
17 6 NC_SATA_D_R2D_CP TRUE NC_SATA_D_R2D_CP 6 17 MAKE_BASE=TRUE
I1028 TRUE SATA_ODD_D2R_C_N 42 93 I1160 TRUE PPVP_FW 7 40 41 MAKE_BASE=TRUE 20 6 NC_PCH_TP5 TRUE NC_PCH_TP5 6 20
J6900 (DC POWER CONN) 17 6 NC_SATA_SSD2_D2RN TRUE NC_SATA_SSD2_D2RN 6 17 MAKE_BASE=TRUE
I1027 TRUE SATA_ODD_R2D_P 42 93 I1161 TRUE PPVTTDDR_S3 7 32 67 MAKE_BASE=TRUE 20 6 NC_PCH_TP4 TRUE NC_PCH_TP4 6 20
I1131 TRUE ADAPTER_SENSE NC_SATA_SSD2_D2RP NC_SATA_SSD2_D2RP 6 17
64 17 6 TRUE MAKE_BASE=TRUE
I1029 TRUE SATA_ODD_R2D_N 42 93 MAKE_BASE=TRUE 20 6 NC_PCH_TP3 TRUE NC_PCH_TP3 6 20
I1132 TRUE PP18V5_DCIN_FUSE NC_SATA_SSD2_R2D_CN NC_SATA_SSD2_R2D_CN 6 17
64 17 6 TRUE MAKE_BASE=TRUE
TRUE GND MAKE_BASE=TRUE 20 6 NC_PCH_TP2 TRUE NC_PCH_TP2 6 20
5 TPs 17 6 NC_SATA_SSD2_R2D_CP TRUE NC_SATA_SSD2_R2D_CP 6 17 MAKE_BASE=TRUE
TRUE GND MAKE_BASE=TRUE 20 6 NC_PCH_TP1 TRUE
MAKE_BASE=TRUE
NC_PCH_TP1 6 20
J4501 (SATA HDD CONN) TRUE PCH_VSS_NCTF<15> 20 94

J6950 (MAIN BATT CONN) TRUE PCH_VSS_NCTF<1> 20 94 I1443
46 45 TP_SMC_P41 TRUE NC_SMC_P41 I1436
TRUE PCH_VSS_NCTF<17> 20 94
I1032 TRUE PP5V_S0_HDD_FLT 42 I1134 TRUE PPVBAT_G3H_CONN 64 65 MAKE_BASE=TRUE TRUE PCH_VSS_NCTF<2> 20 94 I1444
I1437
TRUE PCH_VSS_NCTF<19> 6 20 94
I1031 TRUE SATA_HDD_R2D_P 42 93 I1136 TRUE SMBUS_SMC_BSA_SCL 6 45 48 64 65 97 NC NO_TESTs
NO_TEST I1438 TRUE PCH_VSS_NCTF<5> 20 94 I1445
TRUE PCH_VSS_NCTF<19> 6 20 94
I1033 TRUE SATA_HDD_R2D_N 42 93 I1135 TRUE SMBUS_SMC_BSA_SDA 6 45 48 64 65 97 I1439 TRUE PCH_VSS_NCTF<7> I1446
17 6 NC_PCIE_PE5_D2RN TRUE NC_PCIE_PE5_D2RN 6 17 TRUE PCH_VSS_NCTF<21> 20 94
I1035 TRUE SATA_HDD_D2R_C_N 42 93 I1137 TRUE NC_SMC_BS_ALRT_L 6 MAKE_BASE=TRUE TRUE PCH_VSS_NCTF<9> 20 94 I1447
17 6 NC_PCIE_PE5_D2RP TRUE NC_PCIE_PE5_D2RP 6 17
I1440
I1448 TRUE PCH_VSS_NCTF<25> 20 94
I1034 TRUE SATA_HDD_D2R_C_P 42 93 MAKE_BASE=TRUE TRUE PCH_VSS_NCTF<11> 20 94
17 6 NC_PCIE_PE5_R2D_CN TRUE NC_PCIE_PE5_R2D_CN 6 17
I1441
TRUE PCH_VSS_NCTF<27> 20 94
MAKE_BASE=TRUE TRUE PCH_VSS_NCTF<12> 20 94 I1449
TRUE GND TRUE GND 17 6 NC_PCIE_PE5_R2D_CP TRUE NC_PCIE_PE5_R2D_CP 6 17
I1442
I1450 TRUE PCH_VSS_NCTF<29> 20 94
MAKE_BASE=TRUE
NC_PCIE_PE6_D2RN NC_PCIE_PE6_D2RN
A J5815 (KBD BACKLIGHT CONN)
J6995 (BAT LED CONN) 73
17 6
17 6 NC_PCIE_PE6_D2RP
TRUE
TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_PCIE_PE6_D2RP
6 17
6 17 SYNC_MASTER=MASTER SYNC_DATE=MASTER A
I1145 TRUE KBDLED_ANODE 54
64 65 66
17 6 NC_PCIE_PE6_R2D_CN TRUE NC_PCIE_PE6_R2D_CN 6 17
PAGE TITLE
PP3V42_G3H 48 49 53
I1146 TRUE SMC_KDBLED_PRESENT_L 54 I1140 TRUE

I1142 TRUE SMBUS_SMC_BSA_SDA
6 7 17 21 23 43
45 46 47 17 6
6 45 48 64 65 97
NC_PCIE_PE6_R2D_CP TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_PCIE_PE6_R2D_CP 6 17 Functional / ICT Test
DRAWING NUMBER SIZE
TRUE GND TRUE SMBUS_SMC_BSA_SCL NC_PCIE_PE7_D2RN TRUE NC_PCIE_PE7_D2RN
I1141
TRUE SMC_BIL_BUTTON_L
6 45 48 64 17 6
65 97
45 46 64 17 6 NC_PCIE_PE7_D2RP TRUE
MAKE_BASE=TRUE
NC_PCIE_PE7_D2RP
6 17
6 17 Apple Inc. <SCH_NUM> D

I1143
MAKE_BASE=TRUE REVISION
17 6 NC_PCIE_PE7_R2D_CN TRUE NC_PCIE_PE7_R2D_CN 6 17 17 6 NC_CLINK_CLK TRUE NC_CLINK_CLK 6 17 R
FUNC_TEST 17 6 NC_PCIE_PE7_R2D_CP TRUE

MAKE_BASE=TRUE
NC_PCIE_PE7_R2D_CP 6 17 17 6 NC_CLINK_DATA MAKE_BASE=TRUE
TRUE NC_CLINK_DATA 6 17 <E4LABEL>
TRUE GND MAKE_BASE=TRUE MAKE_BASE=TRUE NOTICE OF PROPRIETARY PROPERTY: BRANCH
TRUE GND NC_CLINK_RESET_L TRUE NC_CLINK_RESET_L 6 17
17 6 NC_PCIE_PE8_D2RN TRUE
MAKE_BASE=TRUE
NC_PCIE_PE8_D2RN 6 17
17 6
MAKE_BASE=TRUE THE INFORMATION CONTAINED HEREIN IS THE
<BRANCH>
TRUE GND 17 6 NC_PCIE_PE8_D2RP TRUE NC_PCIE_PE8_D2RP 6 17 17 6 NC_PCIE_CLK100M_PEBN TRUE NC_PCIE_CLK100M_PEBN 6 17 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
6 TPs 17 6 NC_PCIE_PE8_R2D_CN TRUE
MAKE_BASE=TRUE
NC_PCIE_PE8_R2D_CN 6 17 17 6 NC_PCIE_CLK100M_PEBP TRUE
MAKE_BASE=TRUE
NC_PCIE_CLK100M_PEBP 6 17 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
7 OF 132
17 6 NC_PCIE_PE8_R2D_CP TRUE NC_PCIE_PE8_R2D_CP 6 17
MAKE_BASE=TRUE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
"G3Hot" (Always-Present) Rails 3.3V Rails 1.8V/1.5V/1.2V/1.05V Rails "FW" (FireWire) Rails
89 86 82
66 65 49 40 7 6 PPBUS_G3H PPBUS_G3H 99 85 83
20 19 18 17 7 6 PP3V3_S5 PP3V3_S5 6 7 17 18 19 20 21 23 27 31 35
70 69 67 MIN_LINE_WIDTH=0.6 mm 73 72 71 66 57 35 31 27 23 21 MIN_LINE_WIDTH=0.6 MM 57 66 71 72 73 83 85 99
MIN_NECK_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 MM 41 40 7 6 PPVP_FW PPVP_FW 6 7 40 41
VOLTAGE=12.8V VOLTAGE=3.3V MIN_LINE_WIDTH=0.4 MM
MAKE_BASE=TRUE MAKE_BASE=TRUE MIN_NECK_WIDTH=0.2 MM
87 72 71 58 24 23 21
73 83 85 99 16 12 7 6
PP1V8_S0 PP1V8_S0 6 7 12 16 21 23 24 58 71 72 87 VOLTAGE=12.8V
PPBUS_G3H 6 7 40 49 65 66 67 69 70 82 86 PP3V3_S5 6 7 17 18 19 20 21 23 MIN_LINE_WIDTH=0.5 MM MAKE_BASE=TRUE
PPBUS_G3H
89
PP3V3_S5
27 31 35 57 66 71 72 2A max supply MIN_NECK_WIDTH=0.2 MM PPVP_FW
6 7 40 49 65 66 67 69 70 82 86 6 7 17 18 19 20 21 23 27 31 35 VOLTAGE=1.8V 6 7 40 41
PPBUS_G3H
89
6 7 40 49 65 66 67 69 70 82 86 PP3V3_S5
57 66 71 72 73 83 85 99
6 7 17 18 19 20 21 23 27 31 35
MAKE_BASE=TRUE PPVP_FW 6 7 40 41
89 57 66 71 72 73 83 85 99 PP1V8_S0 6 7 12 16 21 23 24 58 71 72 87
PPBUS_G3H 6 7 40 49 65 66 67 69 70 82 86 PP3V3_S5 6 7 17 18 19 20 21 23 27 31 35
89 57 66 71 72 73 83 85 99 PP1V8_S0 6 7 12 16 21 23 24 58
PPBUS_G3H 6 7 40 49 65 66 67 69 70 82 86 PP3V3_S5 6 7 17 18 19 20 21 23 27 31 35 71 72 87 41 40 39 7 6 PP3V3_FW_FWPHY PP3V3_FW_FWPHY 6 7 39 40 41
89 57 66 71 72 73 83 85 99 PP1V8_S0 6 7 12 16 21 23 24 58 71 72 87 MIN_LINE_WIDTH=0.4 MM
PPBUS_G3H 6 7 40 49 65 66 67 69 70 82 86 PP3V3_S5 6 7 17 18 19 20 21 23 27 31 35 MIN_NECK_WIDTH=0.2 MM
89 57 66 71 72 73 83 85 99 PP1V8_S0 6 7 12 16 21 23 24 58 71 72 87 VOLTAGE=3.3V
PPBUS_G3H 6 7 40 49 65 66 67 69 70 82 86 PP3V3_S5 6 7 17 18 19 20 21 23 27 31 35 MAKE_BASE=TRUE
89 57 66 71 72 73 83 85 99 PP1V8_S0 6 7 12 16 21 23 24 58 71 72 87
PPBUS_G3H 6 7 40 49 65 66 67 69 70 82 86 PP3V3_S5 6 7 17 18 19 20 21 23 27 31 35 PP3V3_FW_FWPHY 6 7 39 40 41
D PPBUS_G3H
89
6 7 40 49 65 66 67 69 70 82 86
89
PP3V3_S5
57 66 71 72 73 83 85 99
6 7 17 18 19 20 21 23 27 31
57 66 71 72 73 83 85 99
35
PP1V8_S0
PP1V8_S0
6 7 12 16 21 23 24 58 71 72 87
6 7 12 16 21 23 24 58 71 72 87
PP3V3_FW_FWPHY 6 7 39 40 41 D
PP3V3_S5 6 7 17 18 19 20 21 23 27 31 35
68 49 7 PPBUS_CPU_IMVP_ISNS PPBUS_CPU_IMVP_ISNS 7 49 68 57 66 71 72 73 83 85 99 40 39 7 6 PP1V0_FW_FWPHY PP1V0_FW_FWPHY 6 7 39 40
MIN_LINE_WIDTH=0.4 mm PP3V3_S5 99
6 7 17 18 19 20 21 23 27 31 35 MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.25 mm 57 66 71 72 73 83 85 MIN_NECK_WIDTH=0.2 MM
VOLTAGE=12.8V PP3V3_S5 83 85 99
6 7 17 18 19 20 21 23 VOLTAGE=1.0V
MAKE_BASE=TRUE 27 31 35 57 66 71 72 73 PP1V5_S3 PP1V5_S3 6 7 28 30 31 67 72 MAKE_BASE=TRUE
PP3V3_S5 6 7 17 18 19 20 21 23 27 31 35 MIN_LINE_WIDTH=0.2 mm
PPBUS_CPU_IMVP_ISNS 7 49 68 57 66 71 72 73 83 85 99 MIN_NECK_WIDTH=0.17 mm PP1V0_FW_FWPHY 6 7 39 40
PP3V3_S5 6 7 17 18 19 20 21 23 27 31 35 VOLTAGE=1.5V
57 66 71 72 73 83 85 99 MAKE_BASE=TRUE
PP3V3_S5 6 7 17 18 19 20 21 23 27 31 35
57 66 71 72 73 83 85 99 PP1V5_S3
65 64 7 6 PPDCIN_G3H PPDCIN_G3H
MIN_LINE_WIDTH=0.6 MM
6 7 64 65 PP3V3_S5 6 7 17 18 19 20 21 23 27 31 35
57 66 71 72 73 83 85 99 PP1V5_S3
6 7 28 30 31 67 72
6 7 28 30 31 67 72
"GPU" Rails
MIN_NECK_WIDTH=0.25 MM PP3V3_S5 6 7 17 18 19 20 21 23 27 31 35 84 82 81 80 79 74 72 7 6 PP3V3_S0GPU PP3V3_S0GPU 6 7 72 74 79 80 81 82 84
VOLTAGE=18.5V 57 66 71 72 73 83 85 99 PP1V5_S3 6 7 28 30 31 67 72 MIN_LINE_WIDTH=0.3 MM
MAKE_BASE=TRUE MIN_NECK_WIDTH=0.10MM
PP1V5_S3 6 7 28 30 31 67 72 VOLTAGE=3.3V
PPDCIN_G3H 6 7 64 65 MAKE_BASE=TRUE
PP1V5_S3 6 7 28 30 31 67 72
73
PP3V3_S0GPU 6 7 72 74 79 80 81 82 84
53 49 48
43 23 21 17 7 6 PP3V42_G3H PP3V42_G3H 6 7 17 21 23 43 45 46 47 48 49 PP3V3_S0GPU 6 7 72 74 79 80 81 82 84
47 46 45 MIN_LINE_WIDTH=0.3 MM 53 64 65 66 73
66 65 64
MIN_NECK_WIDTH=0.2 MM 53 50 48 36 35 34 33 32 31 20 17 8 7 6 PP3V3_S3 PP3V3_S3 6 7 8 17 20 31 32 33 34 35 36 48 50 53 54 PP3V3_S0GPU 6 7 72 74 79 80 81
VOLTAGE=3.42V 101 87 73 72 55 54 MIN_LINE_WIDTH=0.50MM 55 72 73 87 101 82 84
MAKE_BASE=TRUE MIN_NECK_WIDTH=0.20MM PP3V3_S0GPU 6 7 72 74 79 80 81 82 84
VOLTAGE=3.3V
PP3V42_G3H 6 7 17 21 23 43 45 46 47 48 49 MAKE_BASE=TRUE PP3V3_S0GPU 6 7 72 74 79 80 81 82 84
53 64 65 66 73
PP3V42_G3H 6 7 17 21 23 43 45 46 47 48 49
53 64 65 66 73
PP3V3_S3 6 7 8 17 20 31 32 33 34 35 36 48 50 53 54
55 72 73 87 101
PP3V42_G3H 6 7 17 21 23 43 45 46 47 48 49 PP3V3_S3 81 72 7 6 PP1V8_GPUIFPX PP1V8_GPUIFPX 6 7 72 81
53 64 65 66 73
PP3V3_S3 99 73 72 42 31 16 13 7 6 PP1V5_S3RS0 PP1V5_S3RS0 6 7 13 16 31 42 72 73 99 MIN_LINE_WIDTH=0.6 MM
PP3V42_G3H 6 7 17 21 23 43 45 46 47 48 49 6 7 8 17 20 31 32 33 34 35 36 48 50 53 54 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.15 MM
53 64 65 66 73 55 72 73 87 101 MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.8V
PP3V42_G3H 6 7 17 21 23 43 45 46 47 48 49 PP3V3_S3 6 7 8 17 20 31 32 33 34 35 36 48 50 53 54 VOLTAGE=1.5V MAKE_BASE=TRUE
53 64 65 66 73 55 72 73 87 101 MAKE_BASE=TRUE
PP3V42_G3H 6 7 17 21 23 43 45 46 47 48 49 PP3V3_S3 6 7 8 17 20 31 32 33 34 35 36 48 50 53 54 PP1V8_GPUIFPX 6 7 72 81
53 64 65 66 73 55 72 73 87 101 PP1V5_S3RS0 6 7 13 16 31 42 72 73 99
PP3V42_G3H 6 7 17 21 23 43 45 46 47 48 49 PP3V3_S3 6 7 8 17 20 31 32 33 34 35 36 48 50 53 54
53 64 65 66 73 55 72 73 87 101 PP1V5_S3RS0 6 7 13 16 31 42 72 73 99
PP3V42_G3H 6 7 17 21 23 43 45 46 47 48 49 PP3V3_S3 6 7 8 17 20 31 32 33 34 35 36 48 50 53 54 78 77 76 75 56 50 8 7 6 PP1V8R1V55_S0GPU_ISNS PP1V8R1V55_S0GPU_ISNS 6 7 8 50 56 75 76
53 64 65 66 73 55 72 73 87 101 PP1V5_S3RS0 6 7 13 16 31 42 72 73 99 MIN_LINE_WIDTH=0.6 MM 77 78
PP3V42_G3H 6 7 17 21 23 43 45 46 47 48 49 PP3V3_S3 6 7 8 17 20 31 32 33 34 35 36 48 50 53 54 MIN_NECK_WIDTH=0.2 MM
53 64 65 66 73 55 72 73 87 101 PP1V5_S3RS0 6 7 13 16 31 42 72 73 99 VOLTAGE=1.8V
PP3V42_G3H 6 7 17 21 23 43 45 46 47 48 49 PP3V3_S3 6 7 8 17 20 31 32 33 34 35 36 48 50 53 54 MAKE_BASE=TRUE
53 64 65 66 73 55 72 73 87 101
PP3V42_G3H 6 7 17 21 23 43 45 46 47 48 49
53 64 65 66 73
PP3V3_S3 6 7 8 17 20 31 32 33 34 35 36 48 50 53 54
55 72 73 87 101
PP1V8R1V55_S0GPU_ISNS 6 7 8 50 56 75 76
77 78
PP3V42_G3H PP3V3_S3 PP1V8R1V55_S0GPU_ISNS
C PP3V42_G3H
6 7 17 21 23 43 45 46 47 48 49
53 64 65 66 73
6 7 17 21 23 43 45 46 47 48 49
53 64 65 66 73
PP3V3_S3
6 7 8 17 20 31 32 33 34 35 36 48 50 53 54
55 72 73 87 101
6 7 8
55 72
17
73
20
31 32
87
101
33 34 35 36 48 50 53 54 PP1V8R1V55_S0GPU_ISNS
6 7 8 50 56 75 76
77 78
6 7 8 50 56 75 76
77 78
C
PP3V42_G3H 6 7 17 21 23 43 45 46 47 48 49 PP3V3_S3 6 7 8 17 20
53
31 32
54 55 72 73 87 101
33 34 PP1V8R1V55_S0GPU_ISNS 6 7 8 50 56 75 76
53 64 65 66 73 35 36 48 50
67 32 7 6 PPVTTDDR_S3 PPVTTDDR_S3 6 7 32 67 77 78
PP3V3_S3 6 7 8 17 20 31 32 33 34 35 36 48 50 53 54 MIN_LINE_WIDTH=0.3 MM
55 72 73 87 101 MIN_NECK_WIDTH=0.2 MM
PP3V3_S3 6 7 8 17 20 31 32 33 34 35 36 48 50 53 54 VOLTAGE=0.75V 86 50 7 6 PP1V8R1V55_S0GPU_ISNS_R PP1V8R1V55_S0GPU_ISNS_R 6 7 50 86
55 72 73 87 101 MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6 MM
PP3V3_S3 6 7 8 17 20 31 32 33 34 35 36 48 50 53 54 MIN_NECK_WIDTH=0.2 MM
55 72 73 87 101 VOLTAGE=1.8V
5V Rails 67 31 30 28 7 6 PP0V75_S0_DDRVTT PP0V75_S0_DDRVTT 6 7 28 30 31 67
MAKE_BASE=TRUE
72 66 23 7 6 PP5V_S5 PP5V_S5 6 7 23 66 72 MIN_LINE_WIDTH=2 mm PP1V8R1V55_S0GPU_ISNS_R 6 7 50 86
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.17 mm
MIN_NECK_WIDTH=0.2 MM 69 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6 PP3V3_S0 PP3V3_S0 50 51 52 54 58 62 63 68 69 72
6 7 17 18 19 20 21 23 24 25 26 VOLTAGE=0.75V
VOLTAGE=5V 47 46 42 40 37 34 30 28 27 26
99 88 87 85 84 83 80 73 72
MIN_LINE_WIDTH=0.5 MM 27 28 30 34 37 40 42 46 47 48
73 80 83 84 85 87 88 99
MAKE_BASE=TRUE
MAKE_BASE=TRUE MIN_NECK_WIDTH=0.20MM PP1V05_S0GPU
VOLTAGE=3.3V PP0V75_S0_DDRVTT 6 7 86 81 79 76 74 7 6 PP1V05_S0GPU 6 7 74 76 79 81 86
PP5V_S5 6 7 23 66 72 MAKE_BASE=TRUE 73 80 83 84 85 87 88 99 28 30 31 67 MIN_LINE_WIDTH=0.6 MM
50 51 52 54 58 62 63 68 69 72 PP0V75_S0_DDRVTT 6 7 28 30 31 67 MIN_NECK_WIDTH=0.2 MM
PP5V_S5 6 7 23 66 72 PP3V3_S0 27 28 30 34 37 40 42 46 47 48
6 7 17 18 19 20 21 23 24 25 26 VOLTAGE=1.05V
PP0V75_S0_DDRVTT 6 7 28 30 31 67 MAKE_BASE=TRUE
PP5V_S5 6 7 23 66 72 PP3V3_S0 50 51 52 54 58 62 63 68 69 72
6 7 17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48 PP1V05_S0GPU 6 7 74 76 79 81 86
PP3V3_S0 73 80 83 84 85 87 88 99
PP1V05_S0GPU 6 7 74 76 79 81 86
PP3V3_S0
72 67 66 61 58
42 33 31 7 6 PP5V_S3 PP5V_S3 6 7 31 33 42 43 44 46 54 56 58 61 66 67 PP1V05_S0GPU 6 7 74 76 79 81 86
56 54 46 44 43 MIN_LINE_WIDTH=0.5 mm 72 82 101 PP3V3_S0 50 51 52 54 58 62 63 68 69 72
6 7 17 18 19 20 21 23 24 25 26
101 82
MIN_NECK_WIDTH=0.2 mm 27 28 30 34 37 40 42 46 47 48 PP1V05_S0GPU 6 7 74 76 79 81 86
VOLTAGE=5V PP3V3_S0 73 80 83 84 85 87 88 99
6 27 28
MAKE_BASE=TRUE 7 17 18 19 20 21 23 24 25 26 PP1V05_S0GPU 6 7 74 76 79 81 86
PP3V3_S0 30 34 37 40 42 46 47
48 50 51 52 54 58 62
63 68 69 87 72 7 6 PP1V2_S0 PP1V2_S0 6 7 72 87 PP1V05_S0GPU 6 7 74 76 79 81 86
PP5V_S3 6 7 31 33 42 43 44 46 54 56 58 61 66 67 PP3V3_S0 72 73 80 MIN_LINE_WIDTH=0.6 MM
72 82 101 83 84 85 87 88 99
MIN_NECK_WIDTH=0.09 MM PP1V05_S0GPU 6 7 74 76 79 81 86
PP5V_S3 6 7 31 33 42 43 44 46 54 56 58 61 66 67 PP3V3_S0 50 51 52 54 58 62 63 68 69 72
6 7 17 18 19 20 21 23 24 25 26 VOLTAGE=1.2V
72 82 101 27 28 30 34 37 40 42 46 47 48 MAKE_BASE=TRUE PP1V05_S0GPU 6 7 74 76 79 81 86
PP5V_S3 6 7 31 33 42 43 44 46 54 56 58 61 66 67 PP3V3_S0 73 80 83 84 85 87 88 99
6 27 28
PP5V_S3 72 82 101 7 17 18 19 20 21 23 24 25 26
8830 34 37 40 42 46 47 48 50 PP1V2_S0 6 7 72 87 PP1V05_S0GPU 6 7 74 76 79 81 86
6 7 31 33 42 43 44 46 54 56 58 61 66 67
72 82 101
PP3V3_S0 6351 52 54 58 62 63 68 69 72
4273 80 83 84 85 87 88 99
PP5V_S3 6 7 31 33 42 43 44 46 54 56 58 61 66 67 PP3V3_S0 28
6 7 17 18 19 20 21 23
72 82 101 24 25 26 27 71 17 7 6 PP1V05_S5 PP1V05_S5 6 7 17 71 82 75 49 7 6 PPVCORE_GPU PPVCORE_GPU 6 7 49 75 82
PP5V_S3 6 7 31 33 42 43 44 46 54 56 58 61 66 67 PP3V3_S0 30 34 37 40
46 47 48 50 51 52 54 58 62 69 MIN_LINE_WIDTH=0.4 MM MIN_LINE_WIDTH=0.6 MM
72 82 101 68 69 72 73 80 83 84 85 87 MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM
PP5V_S3 6 7 31 33 42 43 44 46 54 56 58 61 66 67 PP3V3_S0 996 7 17 18 19 20 21 23 24 47
3026 27 28 30 34 37 40 42 46
25 VOLTAGE=1.05V VOLTAGE=1.0V
72 82 101 MAKE_BASE=TRUE MAKE_BASE=TRUE
PP5V_S3 6 7 31 33 42 43 44 46 54 56 58 61 66 67 PP3V3_S0 1748 50 51 52 54 58 62 63 68
6 72 73 80 83 84 85 87 88 99
72 82 101 7 PP1V05_S5 6 7 17 71 PPVCORE_GPU 6 7 49 75 82
PP5V_S3 6 7 31 33 42 43 44 46 54 56 58 61 66 67 PP3V3_S0 18 19 20 21 23 24 25 26 27 28
B PP5V_S3
72 82 101
6 7 31 33 42 43 44 46 54 56 58 61 66 67
72 82 101
PP3V3_S0
34 37 40 42 46 47 48 50 51
52 54 58 62 63 68 69 72 73
80 83 84 85 87 88 99
21 20 18 17 15 13 12 10 7 6 PP1V05_S0 PP1V05_S0 6 7 10 12 13 15 17 18 20 21 23
B
PP5V_S3 6 7 31 33 42 43 44 46 54 56 58 61 66 67 PP3V3_S0 86 73 70 40 26 25 24 23 MIN_LINE_WIDTH=0.6 MM 24 25 26 40 70 73 86
PP5V_S3
72 82 101
PP3V3_S0 ? mA MIN_NECK_WIDTH=0.2 MM
6 7 31 33 42 43 44 46 54 56 58 61 66 67 VOLTAGE=1.05V
72 82 101 MAKE_BASE=TRUE
PP5V_S3 6 7 31 33 42 43 44 46 54 56 58 61 66 67
72 82 101
PP3V3_S0 50 51 52 54 58 62 63 68 69 72
6 7 17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48 PP1V05_S0 26 40 70 73 86
6 7 10 12 13 15 17
Chipset "VCore" Rails
PP5V_S3 6 7 31 33 42 43 44 46 54 56 58 61 66 67 PP3V3_S0 73 80 83 84 85 87 88 99 18 20 21 23 24 25 PPVCORE_S0_CPU PPVCORE_S0_CPU 6 7 12 15 49
72 82 101 PP1V05_S0 6 7 10 12 13 15 17 18 20 21 23 MIN_LINE_WIDTH=0.6 MM 68
PP5V_S3 6 7 31 33 42 43 44 46 54 56 58 61 66 67 PP3V3_S0 50 51 52 54 58 62 63 68 69 72
6 7 17 18 19 20 21 23 24 25 26 24 25 26 40 70 73 86 MIN_NECK_WIDTH=0.25 MM
72 82 101 27 28 30 34 37 40 42 46 47 48 PP1V05_S0 6 7 10 12 13 15 17 18 20 21 23 VOLTAGE=1.25V
PP3V3_S0 73 80 83 84 85 87 88 99
6 27 28 24 25 26 40 70 73 86 MAKE_BASE=TRUE
7 17 18 19 20 21 23 24 25 26 PP1V05_S0 6 7 10 12 13 15 17 18 20 21 23
PP3V3_S0 30 34 37 40 42 46 47 48 50
8051 52 54 58 62 63 68 69 72
24 25 26 40 70 73 86 PPVCORE_S0_CPU 6 7 12 15 49
PP5V_S0 5073 80 83 84 85 87 88 99
PP1V05_S0 6 7 10 12 13 15 17 18 20 21 23 68
88 86 72
47 42 23 7 6 PP5V_S0 6 7 23 42 47 52 54 68 69 70 72 PP3V3_S0 6 7 17 18 19 20 21 23 24 25 26 24 25 26 40 70 73 86
70 69 68 54 52 MIN_LINE_WIDTH=0.6 mm 86 88 27 28 30 34 37 40 42 46 47 48 PP1V05_S0
MIN_NECK_WIDTH=0.2 mm PP3V3_S0 51 52 54 58 62 63 68 69 72 73
83 84 85 87 88 99 69 49 24 13 7 6 PPVCORE_S0_GFX PPVCORE_S0_GFX 6 7 13 24 49
VOLTAGE=5V PP1V05_S0 6 7 10 12 13 15 17 18 20 21 23 MIN_LINE_WIDTH=0.6 MM 69
MAKE_BASE=TRUE PP3V3_S0 24 25 26 40 70 73 86 MIN_NECK_WIDTH=0.2 MM
PP1V05_S0 6 7 10 12 13 15 17 18 20 21 23 VOLTAGE=1.05V
PP5V_S0 6 7 23 42 47 52 54 68 69 70 72 PP3V3_S0 50 51 52 54 58 62 63 68 69 72
6 7 17 18 19 20 21 23 24 25 26 24 25 26 40 70 73 86 MAKE_BASE=TRUE
86 88 27 28 30 34 37 40 42 46 47 48 PP1V05_S0 6 7 10 12 13 15 17 18 20 21 23
PP5V_S0 6 7 23 42 47 52 54 68 69 70 72 PP3V3_S0 73 80 83 84 85 87 88 99
6 27 28 24 25 26 40 70 73 86 PPVCORE_S0_GFX 6 7 13 24 49
86 88 197 17 18 19 20 21 23 24 25 26 PP1V05_S0 6 7 10 12 13 15 17 18 20 21 23 69
PP5V_S0 6 7 23 42 47 52 54 68 69 70 72 PP3V3_S0 1730 34 37 40 42 46 47 48 50
6 51 52 54 58 62 63 68 69 72 24 25 26 40 70 73 86
86 88 7 73 80 83 84 85 87 88 99 PP1V05_S0 6 7 10 12 13 15 17
PP5V_S0 6 7 23 42 47 52 54 68 69 70 72 PP3V3_S0 18
20 21 23 24 25 26 27 28 30
18 20 21 16 12 7 PPVCORE_S0_CPU_VCAP0 PPVCORE_S0_CPU_VCAP0 7 12 16
86 88 34 37 40 42 46 47 48 50 51 PP1V05_S0 23 24 25
266 40 70 73 86 MIN_LINE_WIDTH=0.6 MM
PP5V_S0 6 7 23 42 47 52 54 68 69 70 72 PP3V3_S0 52 54 58 62 63 68 69 72 7 MIN_NECK_WIDTH=0.25 MM
86 88 73 80 83 84 85 87 88 99
PP1V05_S0 1010 12 13 15 17 18 20 21 23
6 24 25 26 40 70 73 86 VOLTAGE=1.25V
PP5V_S0 6 7 23 42 47 52 54 68 69 70 72 PP3V3_S0 50 51 52 54 58 62 63 68 69 72
6 7 17 18 19 20 21 23 24 25 26 7 26 40 MAKE_BASE=TRUE
86 88 27 28 30 34 37 40 42 46 47 48 PP1V05_S0 12 13 15 17 18 20 21 23 24 25
706 73 86
PP5V_S0 6 7 23 42 47 52 54 68 69 70 72 PP3V3_S0 73 80 83 84 85 87 88 99
6 27 28 7
86 88 197 17 18 19 20 21 23 24 25 26 PP1V05_S0 1010 12
6 13 15 16 12 7 PPVCORE_S0_CPU_VCAP1 PPVCORE_S0_CPU_VCAP1 7 12 16
PP5V_S0 6 7 23 42 47 52 54 68 69 70 72 PP3V3_S0 1730 34 37 40 42 46 47 48 50
6 51 52 54 58 62 63 68 69 72 7 17 18 20 21 23 24 25 26 MIN_LINE_WIDTH=0.6 MM
86 88 7 73 80 83 84 85 87 88 99 PP1V05_S0 1240 70 73 86
13 40 70 73 86 MIN_NECK_WIDTH=0.25 MM
PP5V_S0 6 7 23 42 47 52 54 68 69 70 72 PP3V3_S0 18
20 21 23 24 25 26 27 28 30 15 17 18 20 21 23 24 25 26 VOLTAGE=1.25V
86 88 34 37 40 42 46 47 48 50 51 PP1V05_S0 6 7 10 12 13 15 17 18 20 21 23 MAKE_BASE=TRUE
PP5V_S0 6 7 23 42 47 52 54 68 69 70 72 PP3V3_S0 52 54 58 62 63 68 69 72 24 25 26 40 70 73 86
86 88 73 80 83 84 85 87 88 99
PP1V05_S0
PP5V_S0 6 7 23 42 47 52 54 68 69 70 72 PP3V3_S0 50 51 52 54 58 62 63 68 69 72
6 7 17 18 19 20 21 23 24 25 26 24 13 7 PPVCORE_S0_CPU_VCAP2 PPVCORE_S0_CPU_VCAP2 7 13 24
86 88 27 28 30 34 37 40 42 46 47 48 PP1V05_S0 6 7 10 12 13 15 17 18 20 21 23 MIN_LINE_WIDTH=0.6 MM
PP5V_S0 6 7 23 42 47 52 54 68 69 70 72 PP3V3_S0 73 80 83 84 85 87 88 99
6 27 28
197 17 18 19 20 21 23 24 25 26
24 25 26 40 70 73 86 MIN_NECK_WIDTH=0.25 MM
86 88 VOLTAGE=1.25V
PP5V_S0 6 7 23 42 47 52 54 68 69 70 72
86 88
PP3V3_S0 1730 34 37 40 42 46 47 48 50
6 51 52 54 58 62 63 68 69 72
7 73 80 83 84 85 87 88 99
MAKE_BASE=TRUE
PP3V3_S0 18
PP3V3_S0
20 21 23 24 25 26 27 28 30
34 37 40 42 46 47 48 50 51 ENET Rails
A PP3V3_S0
52 54 58 62 63 68 69 72
73 80 83 84 85 87 88 99
50 51 52 73 37 27 7 6 PP3V3_ENET
6 7 17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
PP3V3_ENET
MIN_NECK_WIDTH=0.2 MM
6 7 27 37 73
SYNC_MASTER=MASTER SYNC_DATE=MASTER A
PP3V3_S0 54 58 62 63 68 69 72 73 80 83
VOLTAGE=3.3V PAGE TITLE
84 85 87 88 99
PP3V3_S0 50 51 52 54 58 62 63 68 69 72
6 7 17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
MAKE_BASE=TRUE
PP3V3_ENET 6 7 27 37 73
Power Aliases
PP3V3_S0 73 80 83 84 85 87 88 99
58 62 63 68 69 72 73 80 83 84
DRAWING NUMBER SIZE
PP3V3_S0 28 30 34 37 40 42 46 47 48 50
6 7 17 18 19 20 21 23 24
25 26 27 72 71 37 7 6 PP1V2_ENET PP1V2_ENET 6 7 37 71 72 Apple Inc. <SCH_NUM> D
51 52 54
85 87 88 99 MIN_LINE_WIDTH=0.6 MM REVISION
MIN_NECK_WIDTH=0.2 MM R
VOLTAGE=1.2V
MAKE_BASE=TRUE
<E4LABEL>
PP1V2_ENET 6 7 37 71 72 THE INFORMATION CONTAINED HEREIN IS THE
<BRANCH>
PP1V2_ENET 6 7 37 71 72 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
8 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ZT0984 Thermal Module Holes Fan Holes
STDOFF-4.5OD.98H-1.1-3.48-TH ZT0981 ZT0930 CPU signals
1 STDOFF-4.5OD.98H-1.1-3.48-TH STDOFF-4.5OD.98H-1.1-3.48-TH
1 1
ZT0987 91 15 12 CPU_VID<0..6>
MAKE_BASE=TRUE
CPUIMVP_VID<0..6> 68 91 12 8 TP_CPU_VTT_SELECT
MAKE_BASE=TRUE
TP_CPU_VTT_SELECT 8 12 91
STDOFF-4.5OD.98H-1.1-3.48-TH ZT0985 ZT0988
STDOFF-4.5OD.98H-1.1-3.48-TH STDOFF-4.5OD.98H-1.1-3.48-TH 91 13 GFX_VID<0..6> GFXIMVP_VID<0..6> 69
1 MAKE_BASE=TRUE
1 1 67 31 8 MEMVTT_EN MEMVTT_EN 8 31 67
MAKE_BASE=TRUE
ZT0980
STDOFF-4.5OD.98H-1.1-3.48-TH ZT0986 ZT0989
1 STDOFF-4.5OD.98H-1.1-3.48-TH STDOFF-4.5OD.98H-1.1-3.48-TH GPU signals
1 1 91 74 9 PEG_D2R_P<15..0> =PEG_D2R_P<0..15>
D MAKE_BASE=TRUE
PEG_D2R_N<15..0> =PEG_D2R_N<0..15>
D
ZT0991 91 74
MAKE_BASE=TRUE
9
STDOFF-4.5OD.98H-1.1-3.48-TH 91 74 9 PEG_R2D_C_P<15..0> =PEG_R2D_C_P<0..15>

MAKE_BASE=TRUE
1
91 74 PEG_R2D_C_N<15..0> =PEG_R2D_C_N<0..15> 9
MAKE_BASE=TRUE
ZT0915 Frame Holes
3R2P5 ** PEG LANES REVERSED. ARD STRAP REQ’D. **
1 GND
GMUX ALIASES
ZT0940 R0902
3R2P5
Left Speaker Holes 87 86 82 73 8 PM_ALL_GPU_PGOOD PM_ALL_GPU_PGOOD 8 73 82 86 87 91 25 9 CPU_CFG<3> 1
3.0K 2 93 18 8 6 TP_LVDS_IG_B_CLKP
MAKE_BASE=TRUE
TP_LVDS_IG_B_CLKP 6 8 18 93
MAKE_BASE=TRUE
1 GND 5%
ZT0934 TP_LVDS_MUX_SEL_EG TP_LVDS_MUX_SEL_EG 8 87
1/16W
MF-LF
93 18 8 6 TP_LVDS_IG_B_CLKN
MAKE_BASE=TRUE
TP_LVDS_IG_B_CLKN 6 8 18 93
ZT0950 STDOFF-4.0OD3.0H-TH 87 8
MAKE_BASE=TRUE 402
TH 1 87 74 8 EG_RESET_L EG_RESET_L 8 74 87 18 8 6 TP_LVDS_IG_BKL_PWM TP_LVDS_IG_BKL_PWM 6 8 18
1 GND MAKE_BASE=TRUE MAKE_BASE=TRUE
SL-3.1X2.7-6CIR-NSP LVDS_IG_BKL_ON LVDS_IG_BKL_ON 8 18 87
ZT0935 87 18 8
MAKE_BASE=TRUE 79 8 NC_GPU_XTALOUT
MAKE_BASE=TRUE NO_TEST=TRUE
NC_GPU_XTALOUT 8 79
ZT0960 STDOFF-4.0OD3.0H-TH 87 18 8 LVDS_IG_PANEL_PWR LVDS_IG_PANEL_PWR 8 18 87
NC_LVDS_IG_A_DATAP<3> NC_LVDS_IG_A_DATAP<3>
3R2P5 1
MAKE_BASE=TRUE 93 18 8
8 18 93
1 GND 89 87 8 LCD_BKLT_EN LCD_BKLT_EN 8 87 89
MAKE_BASE=TRUE 93 18 8 NC_LVDS_IG_A_DATAN<3> NC_LVDS_IG_A_DATAN<3> 8 18 93
MAKE_BASE=TRUE
ZT0990 93 84 DP_IG_ML_P<3..0> DP_IG_B_ML_P<3..0> 18
NO_TEST=TRUE
3R2P5 MAKE_BASE=TRUE
1 GND 93 84 DP_IG_ML_N<3..0> DP_IG_B_ML_N<3..0> 18 93 18 8 NC_LVDS_IG_B_DATAP<3> NC_LVDS_IG_B_DATAP<3> 8 18 93
MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
87 74 8 PEX_CLKREQ_L PEX_CLKREQ_L 8 74 87
MAKE_BASE=TRUE 93 84 18 8 DP_IG_AUX_CH_P DP_IG_AUX_CH_P 8 18 84 93 18 8 NC_LVDS_IG_B_DATAN<3> NC_LVDS_IG_B_DATAN<3> 8 18 93
MAKE_BASE=TRUE 93 MAKE_BASE=TRUE NO_TEST=TRUE
87 17 8 PEG_CLKREQ_L PEG_CLKREQ_L 8 17 87
MAKE_BASE=TRUE 93 84 18 8 DP_IG_AUX_CH_N DP_IG_AUX_CH_N 8 18 84 93
MAKE_BASE=TRUE
Keyboard / IPD Conn Protect 35 8 NC_USB_HUB1_OCS4 NC_USB_HUB1_OCS4 8 35
73 71 8 PM_ENET_EN PM_ENET_EN 8 71 73 84 80 18 8 DP_IG_DDC_CLK DP_IG_DDC_CLK 8 18 80 84 MAKE_BASE=TRUE
ZT0952 NC_USB_HUB2_OCS3 NC_USB_HUB2_OCS3
C
C Tall EMI pogo pins
4.0OD1.85H-M1.6X0.35 84 80 18 8 DP_IG_DDC_DATA
MAKE_BASE=TRUE
DP_IG_DDC_DATA 8 18 80 84
36 8
MAKE_BASE=TRUE
8 36
1 84 18 8 DP_IG_HPD DP_IG_HPD 8 18 84 93 36 34 8 USB_SDCARD_P USB_SDCARD_P 8 34 36 93

SH0902 40 20 8 FW_PLUG_DET_L FW_PLUG_DET_L 8 20 40 93 36 34 8 USB_SDCARD_N USB_SDCARD_N 8 34 36 93
2.0DIA-TALL-EMI-MLB-M97-M98
ZT0953 MAKE_BASE=TRUE MAKE_BASE=TRUE
SH0900 4.0OD1.85H-M1.6X0.35
SM 40 39 8 FW643_WAKE_L FW643_WAKE_L 8 39 40
2.0DIA-TALL-EMI-MLB-M97-M98 1 MAKE_BASE=TRUE 54 53 50 48 36 35 34 33 32 31 20 17 7 6 PP3V3_S3
1 101 87 73 72 55
SM
45 8 TP_SMC_EXCARD_PWR_EN TP_SMC_EXCARD_PWR_EN 8 45 R09031 1
R0904
1 MAKE_BASE=TRUE
SH0903 NC_SATA_EXTA_D2R_N NC_SATA_EXTA_D2R_N
10K 10K
17 8 8 17 5% 5%
2.0DIA-TALL-EMI-MLB-M97-M98 MAKE_BASE=TRUE NO_TEST=TRUE 1/16W 1/16W
SM SH0916 17 8 NC_SATA_EXTA_D2R_P NC_SATA_EXTA_D2R_P 8 17
MF-LF
402 2
MF-LF
2 402
1 2.0DIA-TALL-EMI-MLB-M97-M98 MAKE_BASE=TRUE NO_TEST=TRUE
USB_EXTC_N 35 93
SM 17 8 NC_SATA_EXTA_R2D_C_N NC_SATA_EXTA_R2D_C_N 8 17
MAKE_BASE=TRUE NO_TEST=TRUE USB_EXTC_P 35 93
1
SH0904 17 8 NC_SATA_EXTA_R2D_C_P NC_SATA_EXTA_R2D_C_P 8 17
2.0DIA-TALL-EMI-MLB-M97-M98 NC_PCIE_EXCARD_D2R_N NC_PCIE_EXCARD_D2R_N
17 8 8 17
SM MAKE_BASE=TRUE NO_TEST=TRUE
1 17 8 NC_PCIE_EXCARD_D2R_P NC_PCIE_EXCARD_D2R_P 8 17
17 8 NC_PCIE_EXCARD_R2D_C_N NC_PCIE_EXCARD_R2D_C_N 8 17
17 8 NC_PCIE_EXCARD_R2D_C_P NC_PCIE_EXCARD_R2D_C_P 8 17
MAKE_BASE=TRUE NO_TEST=TRUE R0900
NC_PCIE_CLK100M_EXCARD_N NC_PCIE_CLK100M_EXCARD_N
PP1V8R1V55_S0GPU_ISNS1 10
8 17 94
94 17 8
MAKE_BASE=TRUE NO_TEST=TRUE 78 77 76 75 56 50 7 6 2 GPU_FB_A_VREF_DIV 8 32 77
MAKE_BASE=TRUE
94 17 8 NC_PCIE_CLK100M_EXCARD_P NC_PCIE_CLK100M_EXCARD_P 8 17 94 1%
MAKE_BASE=TRUE NO_TEST=TRUE 1/16W
MF-LF GPU_FB_A_VREF_DIV 8 32 77
Short (IO Row) EMI pogo pins 402
SH0911 53 8 6 TP_ISSP_SCLK_P1_1 TP_ISSP_SCLK_P1_1 6 8 53

R0901
MAKE_BASE=TRUE 10 GPU_FB_B_VREF_DIV
B SH0910
1.4DIA-SHORT-EMI-MLB-M97-M98
SM 53 8 6 TP_ISSP_SDATA_P1_0
MAKE_BASE=TRUE
TP_ISSP_SDATA_P1_0 6 8 53
1
1%
2
MAKE_BASE=TRUE
8 32 78
B
1.4DIA-SHORT-EMI-MLB-M97-M98 1/16W GPU_FB_B_VREF_DIV 8 32 78
1 MF-LF
SM GND 402
1 GND
SH0913 GND
1.4DIA-SHORT-EMI-MLB-M97-M98 GND
SH0912 SM
1.4DIA-SHORT-EMI-MLB-M97-M98 1
SM GND
1
SH0917
1.4DIA-SHORT-EMI-MLB-M97-M98
SH0901 SM
1.4DIA-SHORT-EMI-MLB-M97-M98 1
SM
1
Digital Ground
SH0914
1.4DIA-SHORT-EMI-MLB-M97-M98 GND
SM MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.095 mm
VOLTAGE=0V
1 GND_CHASSIS_AUDIO_JACK 62
A SYNC_MASTER=K17_REF SYNC_DATE=06/11/2009 A
PAGE TITLE
Signal Aliases
DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
9 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT OMIT
U1000 U1000
ARRANDALE ARRANDALE
BGA BGA
(SYM 1 OF 11) (SYM 5 OF 11)
91 18 DMI_S2N_N<0> F7 DMI_RX0* PEG_ICOMPI B12 91 CPU_PEG_COMP RSVD32 W66 NC_TP_CPU_RSVD<32> 6

IN
91 18 DMI_S2N_N<1> J8 DMI_RX1* PEG_ICOMPO A13 RSVD33 W64 NC_TP_CPU_RSVD<33> 6
IN
91 18 DMI_S2N_N<2> K8 DMI_RX2* PEG_RCOMPO D12
IN
J4 B11 RSVD34 AC69 NC_TP_CPU_RSVD<34> 6
91 18 DMI_S2N_N<3> DMI_RX3* PEG_RBIAS 91 CPU_PEG_RBIAS
D 91 18
IN
IN DMI_S2N_P<0> F9 DMI_RX0 G40

RSVD35 AC71 NC_TP_CPU_RSVD<35> 6
D
J6 PEG_RX0* =PEG_D2R_N<0> IN 8 R10121 1
R1010 RSVD36 AA71 NC_TP_CPU_RSVD<36> 6
91 18 DMI_S2N_P<1> DMI_RX1 G38
IN
K9 PEG_RX1* =PEG_D2R_N<1> IN 8 750 49.9 RSVD37 AA69 NC_TP_CPU_RSVD<37> 6
91 18 IN DMI_S2N_P<2> DMI_RX2 H34 1% 1%
J2 PEG_RX2* =PEG_D2R_N<2> 8 1/16W 1/16W
RSVD38 R66
DMI_S2N_P<3> IN NC_TP_CPU_RSVD<38>
91 18 IN DMI_RX3 P34 MF-LF MF-LF 6
PEG_RX3* =PEG_D2R_N<3> 8 402 2 2 402 RSVD39 R64
IN NC_TP_CPU_RSVD<39>
PEG_RX4* G28 =PEG_D2R_N<4> 6
DMI
IN 8
91 18 DMI_N2S_N<0> H17 DMI_TX0*
OUT H25
K15 PEG_RX5* =PEG_D2R_N<5> IN 8 RSVD_NCTF3 BT5 NC_TP_CPU_RSVD<40> 6
91 18 OUT DMI_N2S_N<1> DMI_TX1* H24 AL4
J13 PEG_RX6* =PEG_D2R_N<6> IN 8 91 25 IN CPU_CFG<0> CFG0 (IPU) RSVD_NCTF4 BR5 NC_TP_CPU_RSVD<41> 6
91 18 OUT DMI_N2S_N<2> DMI_TX2* D29 AM2
F10 PEG_RX7* =PEG_D2R_N<7> 8 91 25 CPU_CFG<1> CFG1 (IPU)
91 18 OUT DMI_N2S_N<3> DMI_TX3* B26
IN IN
AK1 RSVD_NCTF2 BV6 NC_TP_CPU_RSVD<42> 6
PEG_RX8* =PEG_D2R_N<8> 8 91 25 CPU_CFG<2> CFG2 (IPU)
G17 D26
IN IN
AK2 RSVD_NCTF1 BV8 NC_TP_CPU_RSVD<43> 6
91 18 OUT DMI_N2S_P<0> DMI_TX0 PEG_RX9* =PEG_D2R_N<9> IN 8 Embedded DisplayPort 91 25 8 IN CPU_CFG<3> CFG3 (IPU)
91 18 DMI_N2S_P<1> M15 DMI_TX1 PEG_RX10* B23 =PEG_D2R_N<10> 8 (eDP) pins 91 25 CPU_CFG<4> AK4 CFG4 (IPU) RSVD45 AV69 TP_CPU_RSVD<45> 6
OUT IN IN
91 18 DMI_N2S_P<2> G13 DMI_TX2 PEG_RX11* D22 =PEG_D2R_N<11> 8 (Auburndale only): 91 25 CPU_CFG<5> AJ2 CFG5 (IPU) RSVD46 AK71 TP_CPU_RSVD<46> 6
OUT IN IN
91 18 DMI_N2S_P<3> J11 DMI_TX3 PEG_RX12* A20 =PEG_D2R_N<12> 8 91 25 CPU_CFG<6> AT2 CFG6 (IPU) RSVD47 AN69 TP_CPU_RSVD<47> 6
OUT IN IN
PEG_RX13* D19 =PEG_D2R_N<13> 8 eDP_AUX# 91 25 CPU_CFG<7> AG7 CFG7 (IPU) RSVD48 AP66 TP_CPU_RSVD<48> 6
IN IN
PEG_RX14* A17 =PEG_D2R_N<14> 8 91 25 CPU_CFG<8> AF4 CFG8 (IPU) RSVD49 AH66 TP_CPU_RSVD<49> 6
IN IN
PEG_RX15* B14 =PEG_D2R_N<15> 8 91 25 CPU_CFG<9> AG2 CFG9 (IPU) RSVD50 AK66 TP_CPU_RSVD<50> 6
IN IN
91 18 FDI_DATA_N<0> L2 FDI_TX0* 91 25 CPU_CFG<10> AH1 CFG10 (IPU) RSVD51 AR71 TP_CPU_RSVD<51> 6
OUT
PEG_RX0 F40 PEG_D2R_P<15> 8 74 91
IN
FDI_DATA_N<1> N7 IN CPU_CFG<11> AC2 AM66 TP_CPU_RSVD<52>
91 18 OUT FDI_TX1* J38 PEG_D2R_P<14> 91 25 IN CFG11 (IPU) RSVD52 6
M4 PEG_RX1 IN 8 74 91
AC4 AK69
91 18 OUT FDI_DATA_N<2> FDI_TX2* G34 91 25 IN CPU_CFG<12> CFG12 (IPU) RSVD53 TP_CPU_RSVD<53> 6
P1 PEG_RX2 PEG_D2R_P<13> IN 8 74 91
AE2 AU71
91 18 OUT FDI_DATA_N<3> FDI_TX3* M34 91 25 IN CPU_CFG<13> CFG13 (IPU) RSVD54 TP_CPU_RSVD<54> 6
N10 PEG_RX3 PEG_D2R_P<12> IN 8 74 91 AD1 AT70
91 18 OUT FDI_DATA_N<4> FDI_TX4* J28 91 25 IN CPU_CFG<14> CFG14 (IPU) RSVD55 TP_CPU_RSVD<55> 6
R7 PEG_RX4 PEG_D2R_P<11> IN 8 74 91 AF8 AR69
91 18 OUT FDI_DATA_N<5> FDI_TX5* G25 91 25 IN CPU_CFG<15> CFG15 (IPU) RSVD56 TP_CPU_RSVD<56> 6
PEG_RX5 PEG_D2R_P<10>
RESERVED
U7 IN 8 74 91 AF6
FDI_DATA_N<6> CPU_CFG<16> (IPU) AU69 TP_CPU_RSVD<57>
FLEXIBLE DISPLAY INTERFACE

91 18 OUT FDI_TX6* K24 91 25 IN CFG16 RSVD57 6
W8 PEG_RX6 PEG_D2R_P<9> IN 8 74 91 AB7 AT67
91 18 OUT FDI_DATA_N<7> FDI_TX7* B28 91 25 IN CPU_CFG<17> CFG17 (IPU) RSVD58 TP_CPU_RSVD<58> 6
PEG_RX7 PEG_D2R_P<8> IN 8 74 91
91 18 FDI_DATA_P<0> K1 FDI_TX0 PEG_RX8 A27 PEG_D2R_P<7> 8 74 91 TP_CPU_RSVD_TP0 AU1 RSVD_TP0 RSVD_TP2 AP2 TP_CPU_RSVD<2> 6
OUT IN
NOTE: HPD must be inverted
C 91 18
91 18
OUT FDI_DATA_P<1>
FDI_DATA_P<2>
N5
N2
FDI_TX1
FDI_TX2
PEG_RX9
PEG_RX10
B25
A24
PEG_D2R_P<6>
PEG_D2R_P<5>
IN 8 74 91
8 74 91
and level-shifted for 6 TP_CPU_RSVD<15> T4 RSVD15
RSVD_TP1 AN7 TP_CPU_RSVD<1> 6 C
OUT IN T2
R2 B21 Auburndale (1.05V). 6 TP_CPU_RSVD<16> RSVD16 RSVD62 AV4 CPU_THERMD_P BI 51 99
91 18 OUT FDI_DATA_P<3> FDI_TX3 PEG_RX11 PEG_D2R_P<4> IN 8 74 91
N9 B19 U1 RSVD63 AU2 CPU_THERMD_N BI 51 99
91 18 OUT FDI_DATA_P<4> FDI_TX4 PEG_RX12 PEG_D2R_P<3> IN 8 74 91 eDP_HPD# 6 TP_CPU_RSVD<17> RSVD17
91 18 FDI_DATA_P<5> R8 FDI_TX5 PEG_RX13 B18 PEG_D2R_P<2> 8 74 91 eDP_AUX 6 TP_CPU_RSVD<18> V2 RSVD18 RSVD64 BE69 TP_CPU_RSVD<64> 6
OUT IN
PCI EXPRESS -- GRAPHICS
91 18 FDI_DATA_P<6> U6 FDI_TX6 PEG_RX14 B16 PEG_D2R_P<1> 8 74 91 RSVD65 BE71 TP_CPU_RSVD<65>

OUT IN
6 TP_CPU_RSVD<19> AV71 RSVD19
6
91 18 FDI_DATA_P<7> W10 FDI_TX7 PEG_RX15 D15 PEG_D2R_P<0> 8 74 91

OUT IN
6 TP_CPU_RSVD<20> AW70 RSVD20 DC_TEST_BV71 BV71 CPU_TEST_BV71_BV69
DC_TEST_BV69 BV69
91 18 FDI_FSYNC<0> AC7 FDI_FSYNC0 PEG_TX0* N40 =PEG_R2D_C_N<0> 8 6 TP_CPU_RSVD<21> AY69 RSVD21
IN OUT
DC_TEST_BV68 BV68 TP_CPU_TEST_BV68
91 18 FDI_FSYNC<1> AC9 FDI_FSYNC1 PEG_TX1* L38 =PEG_R2D_C_N<1> 8 6 TP_CPU_RSVD<22> BB69 RSVD22
IN OUT
DC_TEST_BV5 BV5 TP_CPU_TEST_BV5
PEG_TX2* M32 =PEG_R2D_C_N<2> 8
FDI_INT AB5 OUT TP_CPU_RSVD<23> D8 BV3 CPU_TEST_BV3_BT3
91 18 IN FDI_INT D40 6 RSVD23 DC_TEST_BV3
PEG_TX3* =PEG_R2D_C_N<3> OUT 8 B7 BV1
AA1 A38 6 TP_CPU_RSVD<24> RSVD24 DC_TEST_BV1 CPU_TEST_BV1_BT1
91 18 IN FDI_LSYNC<0> FDI_LSYNC0 PEG_TX4* =PEG_R2D_C_N<4> OUT 8 BT71
AB2 G32 A10 DC_TEST_BT71 CPU_TEST_BT71_BT69
91 18 IN FDI_LSYNC<1> FDI_LSYNC1 PEG_TX5* =PEG_R2D_C_N<5> OUT 8 6 TP_CPU_RSVD<26> RSVD26 BT69
B33 B9 DC_TEST_BT69
PEG_TX6* =PEG_R2D_C_N<6> OUT 8 6 TP_CPU_RSVD<27> RSVD27 BT3
B35 DC_TEST_BT3
PEG_TX7* =PEG_R2D_C_N<7> OUT 8 C5 BT1
L30 6 NC_TP_CPU_RSVD_NCTF<7> RSVD_NCTF7 DC_TEST_BT1
PEG_TX8* =PEG_R2D_C_N<8> OUT 8 A6 BR71
A31 6 NC_TP_CPU_RSVD_NCTF<8> RSVD_NCTF8 DC_TEST_BR71 TP_CPU_TEST_BR71
PEG_TX9* =PEG_R2D_C_N<9> OUT 8 BR1
B32 E3 DC_TEST_BR1 TP_CPU_TEST_BR1
PEG_TX10* =PEG_R2D_C_N<10> OUT 8 6 NC_TP_CPU_RSVD_NCTF<6> RSVD_NCTF6 E71
L28 F1 DC_TEST_E71 TP_CPU_TEST_E71
PEG_TX11* =PEG_R2D_C_N<11> OUT 8 6 NC_TP_CPU_RSVD_NCTF<5> RSVD_NCTF5 E1
N26 DC_TEST_E1 TP_CPU_TEST_E1
PEG_TX12* =PEG_R2D_C_N<12> OUT 8 eDP_TX#<3> C71
M24 DC_TEST_C71 CPU_TEST_C71_A71
G21 DC_TEST_C69 CPU_TEST_C69_A69
J20 DC_TEST_C3 TP_CPU_TEST_C3
PEG_TX15* =PEG_R2D_C_N<15> OUT 8 eDP_TX#<0> A71
DC_TEST_A71
PEG_TX0 L40 PEG_R2D_C_P<15> 8 74 91 DC_TEST_A69 A69
OUT
PEG_TX1 N38 PEG_R2D_C_P<14> 8 74 91 DC_TEST_A68 A68 TP_CPU_TEST_A68
B PEG_TX2 N32
B39
PEG_R2D_C_P<13>
OUT
OUT 8 74 91 DC_TEST_A5 A5 TP_CPU_TEST_A5 B
PEG_TX3 PEG_R2D_C_P<12> OUT 8 74 91
PEG_TX4 B37 PEG_R2D_C_P<11> 8 74 91

OUT
PEG_TX5 H32 PEG_R2D_C_P<10> 8 74 91
OUT
PEG_TX6 A34 PEG_R2D_C_P<9> 8 74 91
OUT
PEG_TX7 D36 PEG_R2D_C_P<8> 8 74 91
OUT
J30 PEG_R2D_C_P<7> CFG0: PCIe Configuration Select 1 = Single PEG 0 = Bifurcation Enabled
PEG_TX8 OUT 8 74 91
B30 PEG_R2D_C_P<6> CFG3: PCIe Lane Reversal 1 = Normal Operation 0 = Lanes Reversed
PEG_TX9 OUT 8 74 91
D33 PEG_R2D_C_P<5> CFG4: Display Port Presence 1 = eDP Disabled 0 = Embedded Display Port Enabled
PEG_TX10 OUT 8 74 91
PEG_TX11 N28 PEG_R2D_C_P<4> 8 74 91

OUT
PEG_TX12 M25 PEG_R2D_C_P<3> OUT 8 74 91 eDP_TX<3> WF: RSVD nets with arrows have offpage marks on CRB schematic.
PEG_TX13 N24 PEG_R2D_C_P<2> eDP_TX<2>
PEG_TX14 F21 PEG_R2D_C_P<1>
OUT
OUT
8 74 91
8 74 91 eDP_TX<1>
WF: RSVD nets with red wires have 0-ohm resistors to GND in CRB schematic.
PEG_TX15 L20 PEG_R2D_C_P<0> 8 74 91 eDP_TX<0>
OUT
PAGE TITLE
CPU DMI/PEG/FDI/RSVD
DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
10 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
21 20 18 17 15 13 12 10 7 6 PP1V05_S0
86 73 70 40 26 25 24 23
NO STUFF OMIT
D
1
R1100
49.9
R11011
68
R11021
68
1
R1103
1K U1000
R11501
10K
1
R1151
10K
D
1% 5% 5% 5% 5% 5%
1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
ARRANDALE 1/16W
MF-LF
1/16W
MF-LF
BGA
2 402 402 2 402 2 2 402 402 2 2 402
(SYM 2 OF 11)
91 CPU_COMP3 AD71 COMP3 BCLK AK7 FSB_CLK133M_CPU_P 20 91
IN
91 CPU_COMP2 AC70 COMP2 BCLK* AK8 FSB_CLK133M_CPU_N 20 91
IN
91 CPU_COMP1 AD69 COMP1
AE66 BCLK_ITP K71 FSB_CLK133M_ITP_P OUT 25 91
MISC
91 CPU_COMP0 COMP0
BCLK_ITP* J70 FSB_CLK133M_ITP_N OUT 25 91
R11101 R11121 M71 PEG_CLK L21 PCIE_CLK100M_CPU_P IN 17 91

TP_CPU_SKTOCC_L
CLOCKS
PROC_DETECT
20 49.9 PEG_CLK* J21 PCIE_CLK100M_CPU_N IN 17 91
1% 1% (GND)
1/16W 1/16W
MF-LF MF-LF DPLL_REF_SSCLK Y2 GFX_CLK120M_DPLLSS_P IN 17 93
402 2 402 2 N61
91 CPU_CATERR_L CATERR* DPLL_REF_SSCLK* W4 GFX_CLK120M_DPLLSS_N IN 17 93
1
R1111 1
R1113 N19 SM_DRAMRST* BJ12 CPU_MEM_RESET_L OUT 31
91 20 BI CPU_PECI PECI
THERMAL
20 49.9
1% 1% SM_RCOMP0 BV33 91 CPU_SM_RCOMP0
DDR3
MISC
1/16W 1/16W
MF-LF MF-LF N67 SM_RCOMP1 BP39 91 CPU_SM_RCOMP1
2 402 2 402 91 68 46 BI CPU_PROCHOT_L PROCHOT*
SM_RCOMP2 BV40 91 CPU_SM_RCOMP2
N17 PM_EXT_TS0* AV66 PM_EXT_TS_L<0> IN 46 91
91 46 20 PM_THRMTRIP_L THERMTRIP* R11601 R11621
OUT
PM_EXT_TS1* AV64 PM_EXT_TS_L<1> IN 46 91
130 100
1% 1%
1/16W 1/16W
N70 PRDY* U71 XDP_PRDY_L OUT 25 91 MF-LF MF-LF
91 25 FSB_CPURST_L RESET_OBS* 402 2 402 2
OUT
(IPU) PREQ* U69 XDP_PREQ_L IN 25 91
M17 (IPU) TCK T67 XDP_TCK IN 25 91

91 18 BI PM_SYNC PM_SYNC 1
R1161
(IPU) TMS N65 XDP_TMS
C 21 20 18 17 15 13 12 10 7 6PP1V05_S0
86 73 70 40 26 25 24 23 (IPU) TRST* P69 XDP_TRST_L
IN
IN
25 91
25 91
24.9
1%
1/16W
C
AM7 VCCPWRGOOD_1 MF-LF
1
R1120 (IPU) TDI T69 JTAG_CPU_TDI IN 25
2 402
JTAG & MBP

(IPD)
PWR MANAGEMENT
1K TDO T71 JTAG_GMCH_TDO OUT 25
5% Y67
1/16W 91 25 20 IN CPU_PWRGD VCCPWRGOOD_0
MF-LF (IPU) TDI_M P71 JTAG_GMCH_TDI IN 25
2 402 (IPD)
TDO_M T70 JTAG_CPU_TDO OUT 25
91 31 18 PM_MEM_PWRGD AM5 SM_DRAMPWROK W71

IN XDP_DBRESET_L
DBR* OUT 25 27 91
(IPD)
(IPU) BPM0* J69 XDP_BPM_L<0> 25 91
CPUVTTS0_PGOOD H15 OUT
91 70 IN VTTPWRGOOD J67
(IPU) BPM1* XDP_BPM_L<1> OUT 25 91
(IPD) J62 XDP_BPM_L<2>
(IPU) BPM2* OUT 25 91
91 25 XDP_CPUPWRGD Y70 TAPPWRGOOD (IPU) BPM3* K65 XDP_BPM_L<3> 25 91

OUT OUT
(IPU) K62 XDP_BPM_L<4>
R1125 BPM4*
J64
OUT 25 91
1.5K 2 G3 (IPU) BPM5* XDP_BPM_L<5> OUT 25 91

27 IN PLT_RST_BUF_L 1 PLT_RESET_LS1V1_L RSTIN* K69
(IPU) BPM6* XDP_BPM_L<6> OUT 25 91
1%
1/16W (IPU) BPM7* M69 XDP_BPM_L<7> 25 91
OUT
MF-LF
402 R11261
750 1
1%
1/16W
R1170
MF-LF 51
402 2 5%
1/16W
MF-LF
402 2
B B
PAGE TITLE
CPU Clock/Misc/JTAG
DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
11 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT OMIT
U1000 U1000
ARRANDALE ARRANDALE
BGA BGA
(SYM 3 OF 11) (SYM 4 OF 11)
92 29 MEM_A_DQ<0> AT8 SA_DQ0 SA_CK0 BM34 MEM_A_CLK_P<0> 28 92 92 29 MEM_B_DQ<0> BA2 SB_DQ0 SB_CK0 BU33 MEM_B_CLK_P<0> 30 92
BI OUT BI OUT
92 29 MEM_A_DQ<1> AT6 SA_DQ1 SA_CK0* BP35 MEM_A_CLK_N<0> 28 92 92 29 MEM_B_DQ<1> AW2 SB_DQ1 SB_CK0* BV34 MEM_B_CLK_N<0> 30 92
BI OUT BI OUT
92 29 MEM_A_DQ<2> BB5 SA_DQ2 92 29 MEM_B_DQ<2> BD1 SB_DQ2
D 92 29
BI
BI MEM_A_DQ<3> BB9
AV7
SA_DQ3
SA_CKE0 BF20 MEM_A_CKE<0> OUT 28 92
92 29
BI
BI MEM_B_DQ<3> BE4
AY1
SB_DQ3
SB_CKE0 BT26 MEM_B_CKE<0> OUT 30 92
D
92 29 MEM_A_DQ<4> SA_DQ4 92 29 MEM_B_DQ<4> SB_DQ4
BI
AV6 SA_CK1 BK36 MEM_A_CLK_P<1> OUT 28 92
BI
BC2 SB_CK1 BV38 MEM_B_CLK_P<1> OUT 30 92
92 29 BI MEM_A_DQ<5> SA_DQ5 92 29 BI MEM_B_DQ<5> SB_DQ5
BE6 SA_CK1* BH36 MEM_A_CLK_N<1> OUT 28 92
BF2 SB_CK1* BU39 MEM_B_CLK_N<1> OUT 30 92
92 29 BI MEM_A_DQ<6> SA_DQ6 92 29 BI MEM_B_DQ<6> SB_DQ6
92 29 MEM_A_DQ<7> BE8 SA_DQ7 SA_CKE1 BK24 MEM_A_CKE<1> 28 92 92 29 MEM_B_DQ<7> BH2 SB_DQ7 SB_CKE1 BT24 MEM_B_CKE<1> 30 92
BI OUT BI OUT
92 29 MEM_A_DQ<8> BF11 SA_DQ8 92 29 MEM_B_DQ<8> BG4 SB_DQ8
BI BI
92 29 MEM_A_DQ<9> BE11 SA_DQ9 SA_CS0* BH40 MEM_A_CS_L<0> 28 92 92 29 MEM_B_DQ<9> BG1 SB_DQ9 SB_CS0* BP46 MEM_B_CS_L<0> 30 92
BI OUT BI OUT
92 29 MEM_A_DQ<10> BK5 SA_DQ10 SA_CS1* BJ47 MEM_A_CS_L<1> 28 92 92 29 MEM_B_DQ<10> BR6 SB_DQ10 SB_CS1* BT43 MEM_B_CS_L<1> 30 92
BI OUT BI OUT
92 29 MEM_A_DQ<11> BH13 SA_DQ11 92 29 MEM_B_DQ<11> BR8 SB_DQ11
BI BI
92 29 MEM_A_DQ<12> BF9 SA_DQ12 SA_ODT0 BF43 MEM_A_ODT<0> 28 92 92 29 MEM_B_DQ<12> BJ4 SB_DQ12 SB_ODT0 BV45 MEM_B_ODT<0> 30 92
BI OUT BI OUT
92 29 MEM_A_DQ<13> BF6 SA_DQ13 SA_ODT1 BL47 MEM_A_ODT<1> 28 92 92 29 MEM_B_DQ<13> BK2 SB_DQ13 SB_ODT1 BU49 MEM_B_ODT<1> 30 92
BI OUT BI OUT
92 29 MEM_A_DQ<14> BK7 SA_DQ14 92 29 MEM_B_DQ<14> BU9 SB_DQ14
BI BI
92 29 MEM_A_DQ<15> BN8 SA_DQ15 SA_DM0 BB10 MEM_A_DM<0> 28 29 92 92 29 MEM_B_DQ<15> BV10 SB_DQ15 SB_DM0 BB4 MEM_B_DM<0> 29 30 92
BI OUT BI OUT
92 29 MEM_A_DQ<16> BN11 SA_DQ16 SA_DM1 BJ10 MEM_A_DM<1> 29 92 92 29 MEM_B_DQ<16> BR10 SB_DQ16 SB_DM1 BL4 MEM_B_DM<1> 29 92
BI OUT BI OUT
92 29 MEM_A_DQ<17> BN9 SA_DQ17 SA_DM2 BM15 MEM_A_DM<2> 29 92 92 29 MEM_B_DQ<17> BT12 SB_DQ17 SB_DM2 BT13 MEM_B_DM<2> 29 92
BI OUT BI OUT
92 29 MEM_A_DQ<18> BG17 SA_DQ18 SA_DM3 BN24 MEM_A_DM<3> 29 92 92 29 MEM_B_DQ<18> BT15 SB_DQ18 SB_DM3 BP22 MEM_B_DM<3> 29 92
BI OUT BI OUT
92 29 MEM_A_DQ<19> BK15 SA_DQ19 SA_DM4 BG44 MEM_A_DM<4> 29 92 92 29 MEM_B_DQ<19> BV15 SB_DQ19 SB_DM4 BV47 MEM_B_DM<4> 29 92
BI OUT BI OUT
92 29 MEM_A_DQ<20> BK9 SA_DQ20 SA_DM5 BG53 MEM_A_DM<5> 29 92 92 29 MEM_B_DQ<20> BV12 SB_DQ20 SB_DM5 BV57 MEM_B_DM<5> 29 92
BI OUT BI OUT
92 29 MEM_A_DQ<21> BG15 SA_DQ21 SA_DM6 BN62 MEM_A_DM<6> 29 92 92 29 MEM_B_DQ<21> BP12 SB_DQ21 SB_DM6 BU65 MEM_B_DM<6> 29 92
BI OUT BI OUT
92 29 MEM_A_DQ<22> BH17 SA_DQ22 SA_DM7 BH59 MEM_A_DM<7> 29 92 92 29 MEM_B_DQ<22> BV17 SB_DQ22 SB_DM7 BF67 MEM_B_DM<7> 29 92
BI OUT BI OUT
MEM_A_DQ<23> BK17 SA_DQ23 MEM_B_DQ<23> BU16 SB_DQ23
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY B

92 29 BI 92 29 BI
92 29 MEM_A_DQ<24> BN20 SA_DQ24 SA_DQS0* AY5 MEM_A_DQS_N<0> 28 29 92 92 29 MEM_B_DQ<24> BP15 SB_DQ24 SB_DQS0* BE2 MEM_B_DQS_N<0> 29 30 92
BI BI BI BI
92 29 MEM_A_DQ<25> BN17 SA_DQ25 SA_DQS1* BJ7 MEM_A_DQS_N<1> 29 92 92 29 MEM_B_DQ<25> BU19 SB_DQ25 SB_DQS1* BM3 MEM_B_DQS_N<1> 29 92
BI BI BI BI
92 29 MEM_A_DQ<26> BK25 SA_DQ26 SA_DQS2* BN13 MEM_A_DQS_N<2> 29 92 92 29 MEM_B_DQ<26> BV22 SB_DQ26 SB_DQS2* BU12 MEM_B_DQS_N<2> 29 92
BI BI BI BI
92 29 MEM_A_DQ<27> BH25 SA_DQ27 SA_DQS3* BL21 MEM_A_DQS_N<3> 29 92 92 29 MEM_B_DQ<27> BT22 SB_DQ27 SB_DQS3* BT19 MEM_B_DQS_N<3> 29 92
BI BI BI BI
92 29 MEM_A_DQ<28> BJ20 SA_DQ28 SA_DQS4* BH44 MEM_A_DQS_N<4> 29 92 92 29 MEM_B_DQ<28> BP19 SB_DQ28 SB_DQS4* BT52 MEM_B_DQS_N<4> 29 92
BI BI BI BI
MEM_A_DQ<29> BH21 BK51 MEM_A_DQS_N<5> MEM_B_DQ<29> BV19 BV55 MEM_B_DQS_N<5>
C 92 29
92 29
BI
BI MEM_A_DQ<30> BG24
SA_DQ29
SA_DQ30
SA_DQS5*
SA_DQS6* BP58 MEM_A_DQS_N<6>
BI
BI
29 92
29 92
92 29
92 29
BI
BI MEM_B_DQ<30> BV20
SB_DQ29
SB_DQ30
SB_DQS5*
SB_DQS6* BU63 MEM_B_DQS_N<6>
BI
BI
29 92
29 92
C
92 29 MEM_A_DQ<31> BG25 SA_DQ31 SA_DQS7* BE62 MEM_A_DQS_N<7> 29 92 92 29 MEM_B_DQ<31> BT20 SB_DQ31 SB_DQS7* BG69 MEM_B_DQS_N<7> 29 92
BI BI BI BI
92 29 MEM_A_DQ<32> BJ40 SA_DQ32 92 29 MEM_B_DQ<32> BT48 SB_DQ32
BI BI
92 29 MEM_A_DQ<33> BM43 SA_DQ33 SA_DQS0 AY7 MEM_A_DQS_P<0> 28 29 92 92 29 MEM_B_DQ<33> BV48 SB_DQ33 SB_DQS0 BD4 MEM_B_DQS_P<0> 29 30 92
BI BI BI BI
92 29 MEM_A_DQ<34> BF47 SA_DQ34 SA_DQS1 BJ5 MEM_A_DQS_P<1> 29 92 92 29 MEM_B_DQ<34> BV50 SB_DQ34 SB_DQS1 BN4 MEM_B_DQS_P<1> 29 92
BI BI BI BI
92 29 MEM_A_DQ<35> BF48 SA_DQ35 SA_DQS2 BL13 MEM_A_DQS_P<2> 29 92 92 29 MEM_B_DQ<35> BP49 SB_DQ35 SB_DQS2 BV13 MEM_B_DQS_P<2> 29 92
BI BI BI BI
92 29 MEM_A_DQ<36> BN40 SA_DQ36 SA_DQS3 BN21 MEM_A_DQS_P<3> 29 92 92 29 MEM_B_DQ<36> BT47 SB_DQ36 SB_DQS3 BT17 MEM_B_DQS_P<3> 29 92
BI BI BI BI
92 29 28 MEM_A_DQ<37> BH43 SA_DQ37 SA_DQS4 BK44 MEM_A_DQS_P<4> 29 92 92 30 29 MEM_B_DQ<37> BV52 SB_DQ37 SB_DQS4 BT50 MEM_B_DQS_P<4> 29 92
BI BI BI BI
92 29 MEM_A_DQ<38> BN44 SA_DQ38 SA_DQS5 BH51 MEM_A_DQS_P<5> 29 92 92 29 MEM_B_DQ<38> BV54 SB_DQ38 SB_DQS5 BU56 MEM_B_DQS_P<5> 29 92
BI BI BI BI
92 29 MEM_A_DQ<39> BN47 SA_DQ39 SA_DQS6 BM60 MEM_A_DQS_P<6> 29 92 92 29 MEM_B_DQ<39> BT54 SB_DQ39 SB_DQS6 BV62 MEM_B_DQS_P<6> 29 92
BI BI BI BI
92 29 MEM_A_DQ<40> BN48 SA_DQ40 SA_DQS7 BE64 MEM_A_DQS_P<7> 29 92 92 29 MEM_B_DQ<40> BP53 SB_DQ40 SB_DQS7 BJ69 MEM_B_DQS_P<7> 29 92
BI BI BI BI
92 29 MEM_A_DQ<41> BN51 SA_DQ41 92 29 MEM_B_DQ<41> BU53 SB_DQ41
BI BI
92 29 MEM_A_DQ<42> BH53 SA_DQ42 SA_MA0 BT36 MEM_A_A<0> 28 92 92 29 MEM_B_DQ<42> BT59 SB_DQ42 SB_MA0 BT34 MEM_B_A<0> 30 92
BI OUT BI OUT
92 29 MEM_A_DQ<43> BJ55 SA_DQ43 SA_MA1 BP33 MEM_A_A<1> 28 92 92 29 MEM_B_DQ<43> BT57 SB_DQ43 SB_MA1 BP30 MEM_B_A<1> 30 92
BI OUT BI OUT
92 29 MEM_A_DQ<44> BH48 SA_DQ44 SA_MA2 BV36 MEM_A_A<2> 28 92 92 29 MEM_B_DQ<44> BP56 SB_DQ44 SB_MA2 BV29 MEM_B_A<2> 30 92
BI OUT BI OUT
92 29 MEM_A_DQ<45> BJ48 SA_DQ45 SA_MA3 BG34 MEM_A_A<3> 28 92 92 29 MEM_B_DQ<45> BT55 SB_DQ45 SB_MA3 BU30 MEM_B_A<3> 30 92
BI OUT BI OUT
92 29 MEM_A_DQ<46> BM53 SA_DQ46 SA_MA4 BG32 MEM_A_A<4> 28 92 92 29 MEM_B_DQ<46> BU60 SB_DQ46 SB_MA4 BV31 MEM_B_A<4> 30 92
BI OUT BI OUT
92 29 MEM_A_DQ<47> BN55 SA_DQ47 SA_MA5 BN32 MEM_A_A<5> 28 92 92 29 MEM_B_DQ<47> BV59 SB_DQ47 SB_MA5 BT33 MEM_B_A<5> 30 92
BI OUT BI OUT
92 29 MEM_A_DQ<48> BF55 SA_DQ48 SA_MA6 BK32 MEM_A_A<6> 28 92 92 29 MEM_B_DQ<48> BV61 SB_DQ48 SB_MA6 BT31 MEM_B_A<6> 30 92
BI OUT BI OUT
92 29 MEM_A_DQ<49> BN57 SA_DQ49 SA_MA7 BJ30 MEM_A_A<7> 28 92 92 29 MEM_B_DQ<49> BP60 SB_DQ49 SB_MA7 BP26 MEM_B_A<7> 30 92
BI OUT BI OUT
92 29 MEM_A_DQ<50> BN65 SA_DQ50 SA_MA8 BN30 MEM_A_A<8> 28 92 92 29 MEM_B_DQ<50> BR66 SB_DQ50 SB_MA8 BV27 MEM_B_A<8> 30 92
BI OUT BI OUT
92 29 MEM_A_DQ<51> BJ61 SA_DQ51 SA_MA9 BF28 MEM_A_A<9> 28 92 92 29 MEM_B_DQ<51> BR64 SB_DQ51 SB_MA9 BT27 MEM_B_A<9> 30 92
BI OUT BI OUT
92 29 MEM_A_DQ<52> BF57 SA_DQ52 SA_MA10 BH34 MEM_A_A<10> 28 92 92 29 MEM_B_DQ<52> BR62 SB_DQ52 SB_MA10 BU42 MEM_B_A<10> 30 92
BI OUT BI OUT
92 29 MEM_A_DQ<53> BJ57 SA_DQ53 SA_MA11 BH30 MEM_A_A<11> 28 92 92 29 MEM_B_DQ<53> BT61 SB_DQ53 SB_MA11 BU26 MEM_B_A<11> 30 92
BI OUT BI OUT
92 29 MEM_A_DQ<54> BK64 SA_DQ54 SA_MA12 BJ28 MEM_A_A<12> 28 92 92 29 MEM_B_DQ<54> BN68 SB_DQ54 SB_MA12 BT29 MEM_B_A<12> 30 92
BI OUT BI OUT
92 29 MEM_A_DQ<55> BK61 SA_DQ55 SA_MA13 BF40 MEM_A_A<13> 28 92 92 29 MEM_B_DQ<55> BL69 SB_DQ55 SB_MA13 BT45 MEM_B_A<13> 30 92
B 92 29
BI
BI MEM_A_DQ<56> BJ63
BF64
SA_DQ56 SA_MA14 BN28
BN25
MEM_A_A<14>
OUT
OUT 28 92 92 29
BI
BI MEM_B_DQ<56> BJ71
BF70
SB_DQ56 SB_MA14 BV26
BU23
MEM_B_A<14>
OUT
OUT 30 92 B
92 29 BI MEM_A_DQ<57> SA_DQ57 SA_MA15 MEM_A_A<15> OUT 28 92 92 29 BI MEM_B_DQ<57> SB_DQ57 SB_MA15 MEM_B_A<15> OUT 30 92
92 29 MEM_A_DQ<58> BB64 SA_DQ58 92 29 MEM_B_DQ<58> BG71 SB_DQ58

BI BI
92 29 MEM_A_DQ<59> BB66 SA_DQ59 92 29 MEM_B_DQ<59> BC67 SB_DQ59
BI BI
92 29 MEM_A_DQ<60> BJ66 SA_DQ60 92 29 MEM_B_DQ<60> BK70 SB_DQ60
BI BI
92 29 MEM_A_DQ<61> BF65 SA_DQ61 92 29 MEM_B_DQ<61> BK67 SB_DQ61
BI BI
92 29 MEM_A_DQ<62> AY64 SA_DQ62 92 29 MEM_B_DQ<62> BD71 SB_DQ62
BI BI
92 29 MEM_A_DQ<63> BC70 SA_DQ63 92 29 MEM_B_DQ<63> BD69 SB_DQ63
BI BI
92 28 MEM_A_BA<0> BT38 SA_BS0 92 30 MEM_B_BA<0> BV43 SB_BS0

OUT OUT
92 28 MEM_A_BA<1> BH38 SA_BS1 92 30 MEM_B_BA<1> BV41 SB_BS1
OUT OUT
92 28 MEM_A_BA<2> BF21 SA_BS2 92 30 MEM_B_BA<2> BV24 SB_BS2
OUT OUT
92 28 MEM_A_CAS_L BK43 SA_CAS* 92 30 MEM_B_CAS_L BU46 SB_CAS*

OUT OUT
92 28 MEM_A_RAS_L BL38 SA_RAS* 92 30 MEM_B_RAS_L BT40 SB_RAS*
OUT OUT
92 28 MEM_A_WE_L BF38 SA_WE* 92 30 MEM_B_WE_L BT41 SB_WE*
OUT OUT
PAGE TITLE
CPU DDR3 Interfaces

DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
12 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT OMIT
U1000 U1000
ARRANDALE ARRANDALE
BGA BGA
16 7 PPVCORE_S0_CPU_VCAP0 (SYM 8 OF 11) PPVCORE_S0_CPU 6 7 12 15 49 68
(SYM 6 OF 11)
BD55 VCAP0_1 VCC_1 AF57 PP1V05_S0 6 7 10 12 13 15 17 18 20 21 23
NOTE: VCAP0 is sourced by CPU BD51 AF55 CPU_PSI_L F68 BF60 24 25 26 40 70 73 86
VCAP0_2 VCC_2 91 68 15 OUT PSI* VTT0_1 Arrandale: 1.05V
Do not connect to power supply, BD48 AF53 BF59
VCAP0_3 VCC_3
CPU_VID<0> A61 VTT0_2 Clarksfield: 1.1V
but provide bypass caps on PCB. BB55 AF51 91 15 8 OUT VID0 BD60
VCAP0_4 VCC_4
CPU_VID<1> D61 VTT0_3 (Controlled by VTT_SELECT pin)
91 15 8 VID1
D
BB51 VCAP0_5 VCC_5 AF50 OUT
CPU_VID<2> D62 VTT0_4 BD59
D
CPU VIDS
BB48 AF48 91 15 8 OUT VID2 BB60
VCAP0_6 VCC_6 A62 VTT0_5
AY57 AF46 91 15 8 OUT CPU_VID<3> VID3 BB59
VCAP0_7 VCC_7 B63 VTT0_6
AY53 AF44 91 15 8 OUT CPU_VID<4> VID4 AY60
VCAP0_8 VCC_8 D64 VTT0_7
AY50 AF42 91 15 8 OUT CPU_VID<5> VID5 AW60
VCAP0_9 VCC_9 D66 VTT0_8
AW57 AF41 91 15 8 OUT CPU_VID<6> VID6 AW35
VCAP0_10 VCC_10 VTT0_9
AW53 VCAP0_11 VCC_11 AD55 91 8 TP_CPU_VTT_SELECT AN1 VTT_SELECT1 VTT0_10 AW33
OUT
AW50 VCAP0_12 VCC_12 AD51 VTT0_11 AW14
91 68 15 PM_DPRSLPVR F66 PROC_DPRSLPVR
AU55 AD48 OUT AW12
AU51 AD44 21 20 18 17 15 13 12 10 7 6 PP1V05_S0 AU60
VCAP0_14 VCC_14 86 73 70 40 26 25 24 23
PPVCORE_S0_CPU VTT_SELECT: 1 = 1.05V, 0 = 1.1V VTT0_13
AU48 AD41 68 49 15 12 7 6
VCAP0_15 VCC_15 VTT0_14 AU59
AR55 VCAP0_16 VCC_16 AB55 VTT0_15 AU12
AR51 VCAP0_17 VCC_17 AB51 R13001 1
R1305 VTT0_16 AR60
AR48 AB48 100 10 AR59
VCAP0_18 VCC_18 1% 1% VTT0_17
AN57 AB44 1/16W 1/16W AR12
VCAP0_19 VCC_19 MF-LF MF-LF A41 VTT0_18
AN53 AB41 402 2 2 402 91 68 50 IN CPUIMVP_IMON ISENSE AN60
VCAP0_20 VCC_20 PLACE_NEAR=U1000.F64:25.4MM VTT0_19
SENSE LINES
AN50 VCAP0_21 POWER VCC_21 AA55 91 68 OUT
PLACE_NEAR=U1000.N13:25.4MM
CPU_VCCSENSE_P F64 VCC_SENSE VTT0_20 AN59
AL57 VCAP0_22 VCC_22 AA51 91 68 CPU_VCCSENSE_N F63 VSS_SENSE VTT0_21 AN35
OUT
AL53 VCAP0_23 VCC_23 AA48 VTT0_22 AN33
91 70 CPU_VTTSENSE_P N13 VTT_SENSE
AL50 AA44 OUT AN17
VCAP0_24 VCC_24 R12 VTT0_23
AK57 AA41 91 70 OUT CPU_VTTSENSE_N VSS_SENSE_VTT AN15
AK53 W55 PLACE_NEAR=U1000.F63:25.4MM PLACE_NEAR=U1000.R12:25.4MM AN14
AK50 VCAP0_27 VCC_27 W51 R13011 1
R1306 VTT0_26 AN12
W48 100 10 AM10
VCC_28 1% 1% VTT0_27
W44 1/16W 1/16W AL60
VCC_29 MF-LF MF-LF VTT0_28
W41 402 2 2 402 AL59
POWER
VCC_30 VTT0_29
U55 87 72 71 58 24 23 21 16 7 6 PP1V8_S0 AL17
CPU CORE SUPPLY VCC_31 W39 VTT0_30
C 16 7 PPVCORE_S0_CPU_VCAP1 VCC_32 U51
U48
W37
VCCPLL1
VCCPLL2
VTT0_31 AL15
AL14
C
1.8V
BD44 VCC_33 U37 VTT0_32
VCAP1_1 U44 VCCPLL3 AL12
NOTE: VCAP1 is sourced by CPU BD41 VCC_34 R39 VTT0_33
VCAP1_2 U41 VCCPLL4 AK35
Do not connect to power supply, BD37 VCC_35 R37 VTT0_34
VCAP1_3 R55 VCCPLL5 AK33
but provide bypass caps on PCB. BB44 VCC_36 VTT0_35
VCAP1_4 R51 AF39
BB41 VCC_37 VTT0_36
VCAP1_5 R48 AF37
BB37 VCC_38 16 PP1V5_S3_CPU_VCCDDR_CLK VTT0_37
1.1V RAIL POWER

VCAP1_6 R44 BB14 AF35
AY46 VCC_39 MIN_LINE_WIDTH=0.4mm VDDQ_CK1 VTT0_38
VCAP1_7 R41 BB12 AF33
AY42 VCC_40 MIN_NECK_WIDTH=0.2mm VDDQ_CK2 VTT0_39
VCAP1_8 P60 AF32
AY39 VCC_41 VOLTAGE=1.5V VTT0_40
VCAP1_9 N55 AF30
AW46 VCC_42 VTT0_41
VCAP1_10 N51 AD39
AW42 VCC_43 VTT0_42
VCAP1_11 N48 AD37
AW39 VCC_44 VTT0_43
VCAP1_12 N44 AD35
AU44 VCC_45 VTT0_44
VCAP1_13 N42 AD33
AU41 VCC_46 VTT0_45
VCAP1_14 M60 AD32
AU37 VCC_47 VTT0_46
VCAP1_15 M51 AD30
AR44 VCC_48 VTT0_47
VCAP1_16 M44 W35
AR41 VCC_49 VTT0_48
VCAP1_17 L55 W33
AR37 VCC_50 VTT0_49
VCAP1_18 K60 W32
AN46 VCC_51 VTT0_50
VCAP1_19 K51 W30
AN42 VCC_52 VTT0_51
VCAP1_20 K44 W28
AN39 VCC_53 VTT0_52
VCAP1_21 J55 W26
AL46 VCC_54 VTT0_53
VCAP1_22 H60 W24
AL42 VCC_55 VTT0_54
VCAP1_23 H51 W23
AL39 VCC_56 VTT0_55
VCAP1_24 H44 U35
AK46 VCC_57 VTT0_56
VCAP1_25 G60 U33
B AK42
AK39
VCAP1_26
VCC_58
VCC_59 G55
VTT0_57
VTT0_58 U32 B
VCAP1_27 G51 U30
VCC_60 VTT0_59
VCC_61 G44 VTT0_60 U28
VCC_62 F55 VTT0_61 U26
VCC_63 E60 VTT0_62 U24
VCC_64 E57 VTT0_63 U23
VCC_65 E53 VTT0_64 R35
VCC_66 E50 VTT0_65 R33
VCC_67 E46 VTT0_66 R32
VCC_68 E42 VTT0_67 R30
VCC_69 D59 VTT0_68 R28
VCC_70 D57 VTT0_69 R26
VCC_71 D55 VTT0_70 R24
VCC_72 D54 VTT0_71 R23
VCC_73 D52 VTT0_72 AY10
VCC_74 D50 VTT0_73 AN9
VCC_75 D48
VCC_76 D47
VCC_77 D45
VCC_78 D43
VCC_79 B60
VCC_80 B56
VCC_81 B53
VCC_82 B49
VCC_83 B46
A VCC_84
VCC_85
B42
A57 SYNC_MASTER=K17_REF SYNC_DATE=06/15/2009 A
PAGE TITLE
A54
VCC_86
VCC_87 A50 CPU Power (1 of 2)
A47 DRAWING NUMBER SIZE
VCC_88
VCC_89 A43 Apple Inc. <SCH_NUM> D
REVISION
R
<E4LABEL>
<BRANCH>
13 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT 69 49 24 13 7 6 PPVCORE_S0_GFX
U1000 R14001
ARRANDALE 100
BGA 1%
(SYM 7 OF 11) 1/16W
MF-LF
402 2
D 69 49 24 13 7 6 PPVCORE_S0_GFX
AN32 VAXG_SENSE AF12 GFX_VSENSE_P PLACE_NEAR=U1000.AF12:25.4MM D
SENSE
LINES
VAXG1 OUT 69 91
AN30 VAXG2 VSSAXG_SENSE AF10 GFX_VSENSE_N 69 91
OUT
AN28 VAXG3 PLACE_NEAR=U1000.AF10:25.4MM
AN26
AN24
VAXG4 R14011
VAXG5 100
AN23 AF71 1%
VAXG6 GFX_VID0 GFX_VID<0> OUT 8 91 1/16W
AN21 AG67 MF-LF
VAXG7 GFX_VID1 GFX_VID<1> OUT 8 91 402 2
AN19 VAXG8 GFX_VID2 AG70 GFX_VID<2> 8 91
OUT
AL32 AH71
GRAPHICS VIDS
VAXG9 GFX_VID3 GFX_VID<3> OUT 8 91
AL30 VAXG10 GFX_VID4 AN71 GFX_VID<4> 8 91
OUT
AL28 VAXG11 GFX_VID5 AM67 GFX_VID<5> 8 91
OUT
AL26 VAXG12 GFX_VID6 AM70 GFX_VID<6> 8 91
OUT
AL24 VAXG13
AL23 GFX_VR_EN AH69 GFX_VR_EN OUT 69 91
VAXG14
AL21 VAXG15 GFX_DPRSLPVR AL71 GFX_DPRSLPVR 69 91
OUT 1
AL19 VAXG16 R1405
AK14 GFX_IMON AL69 GFXIMVP_IMON IN 69 91 4.7K
VAXG17 5%
AK12 1/16W
VAXG18 MF-LF
GRAPHICS
AJ10 402 2
VAXG19
AH14 PP1V5_S3RS0 6 7 16 31 42 72 73 99
VAXG20 BU40
AH12 VDDQ1
VAXG21 BU35
AF28 VDDQ2
VAXG22 BU28
AF26 VDDQ3
VAXG23 BN38
AF24 VDDQ4
VAXG24 BM25
AF23 VDDQ5
VAXG25 BL30
AF21 VDDQ6
VAXG26 BJ38
C AF19
AF17
VAXG27
VAXG28
VDDQ7
VDDQ8 BH32 C
VDDQ9 BH28
AF15 VAXG29
VDDQ10 BG43
AF14 VAXG30
VDDQ11 BF16
AD28 VAXG31
VDDQ12 BF15
AD26 VAXG32
VDDQ13 BD35
AD24 VAXG33
VDDQ14 BD33
AD23 VAXG34
VDDQ15 BD32
AD21 VAXG35
VDDQ16 BD30
AD19
DDR3 -1.5 V RAILS

VAXG36 BD28
AD17 VDDQ17
VAXG37 BD26
VDDQ18
VDDQ19 BD24
VDDQ20 BD23
21 20 18 17 15 13 12 10 7 6 PP1V05_S0 BD21
86 73 70 40 26 25 24 23
W21 VDDQ21
VTT1_1 BD19
W19 VDDQ22
VTT1_2 BD17
U21 VDDQ23
VTT1_3 BD15
U19 VDDQ24
PEG & DMI

VTT1_4 BB35
U17 VDDQ25
VTT1_5 BB33
U15 VDDQ26
VTT1_6
POWER
VDDQ27 BB32
U14 VTT1_7
VDDQ28 BB30
U12 VTT1_8
VDDQ29 BB28
R21 VTT1_9
VDDQ30 BB26
R19 VTT1_10
VDDQ31 BB24
R17 VTT1_11
VDDQ32 BB23
VDDQ33 BB21
B 24 7 PPVCORE_S0_CPU_VCAP2 VDDQ34 BB19
BB17
B
AK62 VDDQ35
VCAP2_1 BB15
NOTE: VCAP2 is sourced by CPU AK60 VDDQ36
VCAP2_2
Do not connect to power supply, AK59 VCAP2_3
but provide bypass caps on PCB. AH60 VCAP2_4
AH59 PP1V1R1V05_S0_CPU_VTT0_DDR 15
VCAP2_5 AW32
AF60 VTT0_DDR
VCAP2_6 AW30
AF59 VTT0_DDR1
VCAP2_7 AW28
AD60 VTT0_DDR2
VCAP2_8 AW26
AD59 VTT0_DDR3
VCAP2_9 AW24
AB60 VTT0_DDR4
VCAP2_10 AW23
AB59 VTT0_DDR5
VCAP2_11 AW21
AA60 VTT0_DDR6
VCAP2_12 AW19
AA59 VTT0_DDR7
VCAP2_13 AW17
W60 VTT0_DDR8
VCAP2_14 AW15
W59 VTT0_DDR9
VCAP2_15 PP1V05_S0 6 7 10 12 13 15 17 18 20 21 23
24 25 26 40 70 73 86
U60 VCAP2_16 VTT1_12 AD15
U59 VCAP2_17 VTT1_13 AD14
R60 VCAP2_18 VTT1_14 AD12
R59 VCAP2_19 VTT1_15 AB12
VTT1_16 AA12
VTT1_17 W17
VTT1_18 W15
VTT1_19 W14
VTT1_20 W12
A VTT1_21 R15
PAGE TITLE
CPU Power (2 of 2)
DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
14 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT OMIT OMIT
U1000 U1000 U1000

ARRANDALE ARRANDALE ARRANDALE
BGA BGA BGA
(SYM 9 OF 11) (SYM 10 OF 11) (SYM 11 OF 11)
BU62 VSS1 VSS76 AY62 AR19 VSS151 VSS226 BN71 AA28 VSS301 VSS367 K6
BU58 VSS2 VSS77 AY59 AR17 VSS152 VSS227 E68 AA26 VSS302 VSS368 K4
D BU55
BU51
VSS3 VSS78 AY55
AY51
AR15
AR14
VSS153 VSS228 AH28
AH41
AA24
AA23
VSS303 VSS369 J65
J57
D
VSS4 VSS79 VSS154 VSS229 VSS304 VSS370
BU48 VSS5 VSS80 AY48 AR4 VSS155 VSS230 A66 AA21 VSS305 VSS371 J48
BU44 VSS6 VSS81 AY44 AR1 VSS156 VSS231 AH26 AA19 VSS306 VSS372 J47
BU37 VSS7 VSS82 AY41 AP70 VSS157 VSS232 BN1 AA17 VSS307 VSS373 J40
BU32 VSS8 VSS83 AY37 AP64 VSS158 VSS233 A64 AA15 VSS308 VSS374 J9
BU25 VSS9 VSS84 AY35 AN62 VSS159 VSS234 AH24 AA14 VSS309 VSS375 H53
BU21 VSS10 VSS85 AY33 AN55 VSS160 VSS235 AH39 AA4 VSS310 VSS376 H43
BU18 VSS11 VSS86 AY32 AN51 VSS161 VSS236 E5 W69 VSS311 VSS377 H36
BU14 VSS12 VSS87 AY30 AN48 VSS162 VSS237 AH23 W62 VSS312 VSS378 H1
BU11 VSS13 VSS88 AY28 AN44 VSS163 VSS238 C68 W57 VSS313 VSS379 G70
BU7 VSS14 VSS89 AY26 AN41 VSS164 VSS239 AH21 W53 VSS314 VSS380 G57
BP42 VSS15 VSS90 AY24 AN37 VSS165 VSS240 AH19 W50 VSS315 VSS381 G53
BN64 VSS16 VSS91 AY23 AN5 VSS166 VSS241 AH17 W46 VSS316 VSS382 G48
BN6 VSS17 VSS92 AY21 AN4 VSS167 VSS242 AH15 W42 VSS317 VSS383 G47
BM70 VSS18 VSS93 AY19 AM64 VSS168 VSS243 AH4 W6 VSS318 VSS384 G43
BM51 VSS19 VSS94 AY17 AM8 VSS169 VSS244 AG64 W1 VSS319 VSS385 G30
BM44 VSS20 VSS95 AY15 AL62 VSS170 VSS245 AG9 V70 VSS320 VSS386 G24
BM32 VSS21 VSS96 AY14 AL55 VSS171 VSS246 AG6 U64 VSS321 VSS387 G20
BM24 VSS22 VSS97 AY12 AL51 VSS172 VSS247 AF69 U62 VSS322 VSS388 G15
BM17 VSS23 VSS98 AY8 AL48 VSS173 VSS248 AF62 U57 VSS323 VSS389 F61
BL57 VSS24 VSS99 AY4 AL44 VSS174 VSS249 AF1 U53 VSS324 VSS390 F48
BL55 VSS25 VSS100 AW67 AL41 VSS175 VSS250 AE70 U50 VSS325 VSS391 F47
BL48 VSS26 VSS101 AW62 AL37 VSS176 VSS251 AE64 U46 VSS326 VSS392 F28
BL40 VSS27 VSS102 AW59 AL35 VSS177 VSS252 AD62 U42 VSS327 VSS393 F20
BL28 VSS28 VSS103 AW55 AL33 VSS178 VSS253 AD57 U39 VSS328 VSS394 F4
BL20 AW51 AL1 AD53 U9 E37
C BK63
VSS29
VSS30
VSS104
VSS105 AW48 AK70
VSS179
VSS180
VSS254
VSS255 AD50 U4
VSS329
VSS330
VSS395
VSS396 E33 C
BK60 VSS31 VSS106 AW44 AK64 VSS181 VSS256 AD46 T1 VSS331 VSS397 E30
BK53 VSS32 VSS107 AW41 AK55 VSS182 VSS257 AD42 R70 VSS332 VSS398 E16
BK34 VSS33 VSS108 AW37 AK51 VSS183 VSS258 AD4 R62 VSS333 VSS399 E12
BK10 VSS34 VSS109 AV9 AK48 VSS184 VSS259 AC67 R57 VSS334 VSS400 D41
BJ64 VSS35 VSS110 AV1 AK44 VSS185 VSS260 AC64 R53 VSS335 VSS401 D38
BJ21 VSS36 VSS111 AU70 AK41 VSS186 VSS261 AC10 R50 VSS336 VSS402 D34
BH70 VSS39 VSS114 AU53 AK30 VSS189 VSS264 AB70 R5 VSS339 VSS405 D24
BH57 VSS40 VSS115 AU50 AK28 VSS190 VSS265 AB62 P4 VSS340 VSS406 D20
BH55 VSS41 VSS116 AU46 AK26 VSS191 VSS266 AB57 N63 VSS341 VSS407 D17
BH15 VSS45 VSS120 AU33 AK19 VSS195 VSS270 AB42 N46 VSS345 VSS411 B65
BG51 VSS46 VSS121 AU32 AK17 VSS196 VSS271 AB39 N30 VSS346 VSS412 B62
BG36 VSS47 VSS122 AU30 AK15 VSS197 VSS272 AB37 N21 VSS347 VSS413 B58
BF62 VSS48 VSS123 AU28 AJ70 VSS198 VSS273 AB35 N15 VSS348 VSS414 B55
BF30 VSS49 VSS124 AU26 AH62 VSS199 VSS274 AB33 M53 VSS349 VSS415 B51
BE70 VSS52 VSS127 AU21 AH53 VSS202 VSS277 AB28 M1 VSS352 VSS418 A59
BE65 VSS53 VSS128 AU19 BV66 VSS203 VSS278 AB26 L70 VSS353 VSS419 A55
BE9 VSS54 VSS129 AU17 AH51 VSS204 VSS279 AB24 L57 VSS354 VSS420 A52
BE1 VSS55 VSS130 AU15 BV64 VSS205 VSS280 AB23 L48 VSS355 VSS421 A48
B BD57
BD53
VSS56 VSS131 AU14
AU4
AH50
BT68
VSS206 VSS281 AB21
AB19
L47
L13
VSS356 VSS422 A45
A40
B
VSS57 VSS132 VSS207 VSS282 VSS357 VSS423
BD50 VSS58 VSS133 AT64 AH48 VSS208 VSS283 AB17 K64 VSS358 VSS424 A36
BD46 VSS59 VSS134 AT10 BR69 VSS209 VSS284 AB15 K53 VSS359 VSS425 A33
BD42 VSS60 VSS135 AR62 BL71 VSS210 VSS285 AB14 K43 VSS360 VSS426 A29
BD39 VSS61 VSS136 AR57 AH46 VSS211 VSS286 AB9 K36 VSS361 VSS427 A26
BD14 VSS62 VSS137 AR53 BL1 VSS212 VSS287 AA66 K34 VSS362 VSS428 A22
BB71 VSS63 VSS138 AR50 AH37 VSS213 VSS288 AA64 K32 VSS363 VSS429 A19
BB62 VSS64 VSS139 AR46 BR68 VSS214 VSS289 AA62 K25 VSS364 VSS430 A15
BB57 VSS65 VSS140 AR42 R14 VSS215 VSS290 AA57 K17 VSS365 VSS431 A12
BB53 VSS66 VSS141 AR39 AH35 VSS216 VSS291 AA53 K11 VSS366 VSS432 A8
BB50 VSS67 VSS142 AR35 AH44 VSS217 VSS292 AA50 VSS433 B40
BB46 VSS68 VSS143 AR33 H71 VSS218 VSS293 AA46
BB42 VSS69 VSS144 AR32 AH33 VSS219 VSS294 AA42
BB39 VSS70 VSS145 AR30 BR3 VSS220 VSS295 AA39
BB7 VSS71 VSS146 AR28 F71 VSS221 VSS296 AA37
BB1 VSS72 VSS147 AR26 AH32 VSS222 VSS297 AA35
BA70 VSS73 VSS148 AR24 AH42 VSS223 VSS298 AA33
AY71 VSS74 VSS149 AR23 E69 VSS224 VSS299 AA32
AY66 VSS75 VSS150 AR21 AH30 VSS225 VSS300 AA30
PAGE TITLE
CPU Grounds
DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
15 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU VCore HF and Bulk Decoupling CPU Power On Configuration (POC) Straps
4x 470uF 4.5mOhm, 3x 62uF B2, 10x 22uF 0603, 25x 1uF 0402
Intel recommends all option straps should be provided in layout
PLACEMENT_NOTE (C1600-C1624):
68 49 12 7 6 PPVCORE_S0_CPU
Place on bottom side of U1000.. 21 20 18 17 15 13 12 10 7 6 PP1V05_S0
86 73 70 40 26 25 24 23
CPUPOC4U NO STUFF NO STUFF

1 C1600 1 C1601 1 C1602 1 C1603 1 C1604 1 C1605 1 C1606 1 C1607 1 C1608 1 C1609 1 C1610 1 C1611 1 C1612
1UF
10%
1UF
10%
1UF
10%
1UF
10%
1UF
10%
1UF
10%
1UF
10%
1UF
10%
1UF
10%
1UF
10%
1UF
10%
1UF
10%
1UF
10%
R16001 R16021 R16041 R16061 R16081
1K 1K 1K 1K 1K
2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 5% 5% 5% 5% 5%
402 402 402 402 402 402 402 402 402 402 402 402 402 1/16W 1/16W 1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF MF-LF MF-LF
D 402 2 402 2 402 2 402 2 402 2

D
CPUPOC3U CPUPOC5U
1 1 1 1
R1601 R1603 R1605 R1607
1K 1K 1K 1K
1 C1613 1 C1614 1 C1615 1 C1616 1 C1617 1 C1618 1 C1619 1 C1620 1 C1621 1 C1622 1 C1623 1 C1624 5%
1/16W
5%
1/16W
5%
1/16W
5%
1/16W
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF MF-LF MF-LF MF-LF MF-LF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 16V 2 16V 2 16V 2 16V 2 16V 2 16V 2 16V 2 16V 2 16V 2 16V 2 16V 2 16V 2 402 2 402 2 402 2 402
X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
402 402 402 402 402 402 402 402 402 402 402 402 CPU_VID<0>
91 12 8 OUT
91 12 8 OUT CPU_VID<1>
PLACEMENT_NOTE (C1625-C1634): CPU_VID<3>
91 12 8 OUT
Place near U1000 on bottom side. 91 12 8 OUT CPU_VID<4>
NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF CPU_VID<6>
1 C1625 1 C1626 1 C1627 1 C1628 1 C1629 1 C1630 1 C1631 1 C1632 1 C1634 1 C1691 1 C1692 1 C1693 1 C1694 1 C1698 91 12 8 OUT
PM_DPRSLPVR
22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 91 68 12 OUT
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 91 68 12 CPU_PSI_L
OUT
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
603 603 603 603 603 603 603 603 603 603 603 603 603 603 NO STUFF NO STUFF CPUPOC4D
R16101 R16121 R16141 R16161 R16181
1K 1K 1K 1K 1K
5% 5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W 1/16W
PLACEMENT_NOTE (C1635-C1648): MF-LF MF-LF MF-LF MF-LF MF-LF
402 2 402 2 402 2 402 2 402 2
Place near inductors on bottom side.
NO STUFF CPUPOC3D CPUPOC5D NO STUFF
1 1 1 1
NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF R1611 R1613 R1615 R1617
1 C1635 1 C1636 1 C1637 1 C1638 1 C1640 1 C1641 1 C1642 1 C1643 1 C1644 1 C1645 1 C1646 1 C1648 5%
1K
5%
1K 1K
5%
1K
5%
22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 1/16W 1/16W 1/16W 1/16W
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% MF-LF MF-LF MF-LF MF-LF
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
6.3V
2 X5R-CERM
6.3V
2 X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 402 2 402 2 402 2 402
603 603 603 603 603 603 603 603 603 603 603 603
C C
VID[2:0] = Reserved (111)
VID[5:3] = GPU Gain Setting (See below)
NO STUFF NO STUFF VID[6] = Reserved (0)
1 1 1 1 1 1 1 1 1
C1649 C1650 C1651 C1652 C16A0 C16A1 C16A2 C16A3 C16A4 DPRSLPVR = 1 - IMVP-6.5 compliant controller
470UF-4MOHM 470UF-4MOHM 470UF-4MOHM 470UF-4MOHM 62UF 62UF 62UF 62UF 62UF PSI# = Reserved (0)
20% 20% 20% 20% 20% 20% 20% 20% 20%
3 2 2.0V 3 2 2.0V 3 2 2.0V 3 2 2.0V 2 11V 2 11V 2 11V 2 11V 2 11V
POLY-TANT POLY-TANT POLY-TANT POLY-TANT ELEC ELEC ELEC ELEC ELEC TABLE_BOMGROUP_HEAD
D2T-SM D2T-SM D2T-SM D2T-SM CASE-B2 CASE-B2 CASE-B2 CASE-B2 CASE-B2 BOM GROUP IMAX @ 900mV CPU Gain Setting BOM OPTIONS Equivalent Gain
TABLE_BOMGROUP_ITEM
CPUPOC_IMAX_DIS 000 CPUPOC3D,CPUPOC4D,CPUPOC5D

TABLE_BOMGROUP_ITEM
CPUPOC_IMAX_0_20 20A 001 CPUPOC3D,CPUPOC4D,CPUPOC5U 45
VTT (CPU Uncore) DECOUPLING CPUPOC_IMAX_20_30

CPUPOC_IMAX_30_40
30A
40A
010
011
CPUPOC3D,CPUPOC4U,CPUPOC5D
CPUPOC3D,CPUPOC4U,CPUPOC5U
30
22.5
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
3x 330uF 6 mOhm, 4x 22uF 0805, 7x 10uF 0603, 24x 1uF 0402 TABLE_BOMGROUP_ITEM
CPUPOC_IMAX_40_50 50A 100 CPUPOC3U,CPUPOC4D,CPUPOC5D 18

PLACEMENT_NOTE (C1653-C1656): TABLE_BOMGROUP_ITEM
86 73 70 40 26 25
15 13 12 10 7 6 PP1V05_S0 CPUPOC_IMAX_50_60 60A 101 CPUPOC3U,CPUPOC4D,CPUPOC5U 15
24 23 21 20 18 17 Place on bottom side of U1000. TABLE_BOMGROUP_ITEM
CPUPOC_IMAX_60_70 70A 110 CPUPOC3U,CPUPOC4U,CPUPOC5D 12.857

TABLE_BOMGROUP_ITEM
1 C1653 1 C1654 1 C1655 1 C1656 CPUPOC_IMAX_70_90 90A 111 CPUPOC3U,CPUPOC4U,CPUPOC5U 10

22UF 22UF 22UF 22UF
20% 20% 20% 20%
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM NOTE: BOM Configurations should not call out CPUPOCnU/D BOMOPTIONs directly.
603 603 603 603
Instead call out appropriate BOM GROUP defined in tables above.
B Place on bottom side of U1000.. B
1 C1657 1 C1658 1 C1659 1 C1660 1 C1661 1 C1662 1 C1663
10UF 10UF 10UF 10UF 10UF 10UF 10UF
20%
2 6.3V
X5R
603
20%
2 6.3V
X5R
603
20%
2 6.3V
X5R
603
20%
2 6.3V
X5R
603
20%
2 6.3V
X5R
603
20%
2 6.3V
X5R
603
20%
2 6.3V
X5R
603
VTT0_DDR DECOUPLING
3x 1uF 0402
PLACEMENT_NOTE (C1664-C1687): L1695
30-OHM-5A Place on bottom side of U1000. PP1V1R1V05_S0_CPU_VTT0_DDR 13
Place on bottom side of U1000. 1 2 MIN_LINE_WIDTH=0.4 mm
0603
VOLTAGE=1.1V
1 C1664 1 C1665 1 C1666 1 C1667 1 C1668 1 C1669 1 C1670 1 C1671 1 C1672 1 C1673 1 C1674 1 C1675 1 C1695 1 C1696 1 C1697
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
10V
2 X5R 10V
2 X5R 10V
2 X5R 10V
2 X5R 10V
2 X5R 10V
2 X5R 10V
2 X5R 10V
2 X5R 10V
2 X5R 10V
2 X5R 10V
2 X5R 10V
2 X5R 10V
2 X5R 10V
2 X5R 10V
2 X5R
402 402 402 402 402 402 402 402 402 402 402 402 402 402 402
1 C1676 1 C1677 1 C1678 1 C1679 1 C1680 1 C1681 1 C1682 1 C1683 1 C1684 1 C1685 1 C1686 1 C1687
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R
402 402 402 402 402 402 402 402 402 402 402 402
PAGE TITLE
CPU Non-GFX Decoupling (1 of 2)

DRAWING NUMBER SIZE
1
C1688 1
C1689 1
C1690 Apple Inc. <SCH_NUM> D
330UF 330UF 330UF REVISION
20% 20% 20% R
3 2 2.0V
POLY-TANT
3 2 2.0V
POLY-TANT
3 2 2.0V
POLY-TANT
<E4LABEL>
D2T-SM2 D2T-SM2 D2T-SM2 NOTICE OF PROPRIETARY PROPERTY: BRANCH
<BRANCH>
16 OF 132
Design recommendations from Calpella Small Form Factor Design Guide Rev 1.5 (doc #407364) table 2-34 and Calpella Small Form Factor Schematic Check List Rev 1.1 (doc #395914) table 3.26.
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VCAP0 (CPU BSC Package) DECOUPLING
12x 1uF 0402
12 7 PPVCORE_S0_CPU_VCAP0 Place on bottom side of U1000.
1 C1700 1 C1701 1 C1702 1 C1703 1 C1704 1 C1705 1 C1706 1 C1707 1 C1708 1 C1709 1 C1710 1 C1711
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R
402 402 402 402 402 402 402 402 402 402 402 402
D D

12x 1uF 0402
12 7 PPVCORE_S0_CPU_VCAP1 Place on bottom side of U1000.
1 C1712 1 C1713 1 C1714 1 C1715 1 C1716 1 C1717 1 C1718 1 C1719 1 C1720 1 C1721 1 C1722 1 C1723
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
402 402 402 402 402 402 402 402 402 402 402 402
Memory (CPU VCCDDR) DECOUPLING

5x 1uF 0402
42 31 16 13 7 6
99 73 72
PP1V5_S3RS0 NOTE: 3x 330uF 6 mOhm caps to be shared between CPU and SO-DIMMs. DG recommends 2x 22uF at SO_DIMM not provided. Decoupling caps at SO-DIMMs on CSA 29 and CSA 31.
C 1 C1724
1UF
1 C1725
1UF
1 C1726
1UF
1 C1727
1UF
1 C1728
1UF
C
10% 10% 10% 10% 10%
2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R
402 402 402 402 402
NOTE: 19x 1uF 0402 caps per Apple SI for CMD and CNTRL lines.
1 C1735 1 C1736 1 C1737 1 C1738 1 C1739 1 C1740 1 C1741 1 C1742 1 C1743 1 C1744 1 C1745 1 C1746 1 C1747 1 C1748 1 C1749 1 C1750 1 C1751 1 C1752 1 C1753
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
10V
2 X5R 2 10V 10V
2 X5R 2 10V 2 10V 2 10V 10V
2 X5R 2 10V 10V
2 X5R 2 10V 10V
2 X5R 10V
2 X5R 2 10V 10V
2 X5R 2 10V 2 10V 2 10V 10V
2 X5R 10V
2 X5R
X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402
1
C1729
330UF
20%
3 2 2.0V
POLY-TANT
D2T-SM2
B B
PLL (CPU VCCSFR) DECOUPLING
1x 22uF 0805, 1x 4.7uF 0603
24 23 21 12 7 6 PP1V8_S0
87 72 71 58
1 C1732 1 C1733
22uF 4.7UF
20% 10%
2 6.3V
CERM-X5R 2 6.3V
X5R-CERM
805 603
DDR Clock (CPU VDDQ_CK) DECOUPLING

1x 1uF 0402
L1734
42 31 16 13 7 6 PP1V5_S3RS0 30-OHM-5A PP1V5_S3_CPU_VCCDDR_CLK 12
99 73 72
1 2
0603
1 C1734
A 1UF
10%
2 10V
X5R PAGE TITLE
402
CPU Non-GFX Decoupling (2 of 2)
DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
Design recommendations from Calpella Small Form Factor Design Guide Rev 1.5 (doc #407364) table 2-34 and Calpella Small Form F I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
17 OF 132
actor Schematic Check List Rev 1.1 (doc #395914) table 3.26. III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
21 20 18 17 15 13 12 10 7 6 PP1V05_S0
86 73 70 40 26 25 24 23
50 48
25 24 23 21 20 19 18 17 7 6 PP3V3_S0 21 20 18 17 15 13 12 10 7 6 PP1V05_S0
47 46 42 40 37 34 30 28 27 26 86 73 70 40 26 25 24 23
72 69 68 63 62 58 54 52 51
99 88 87 85 84 83 80 73
1
R1820 R18301 R18901
10K 37.4 90.9
5% 1% 1%
1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF
2 402 402 2 402 2
27 IN PCH_CLK32K_RTCX1 B13 RTCX1 OMIT FWH0/LAD0 D33 LPC_AD<0> BI 6 45 47 87 94 94 37 IN PCIE_ENET_D2R_N BG30 PERN1 OMIT SMBALERT*/GPIO11 B9 SMC_WAKE_SCI_L IN 17 45
(IPU)
27 OUT PCH_CLK32K_RTCX2 D13 RTCX2
U1800 FWH1/LAD1 B33 LPC_AD<1> BI 6 45 47 87 94 94 37 IN PCIE_ENET_D2R_P BJ30 PERP1 U1800 SMBCLK H14 SMBUS_PCH_CLK 94
25 26 28 30 32
D IBEX_PEAK_M
FCBGA
FWH2/LAD2
FWH3/LAD3
C32
A32
LPC_AD<2>
LPC_AD<3>
BI
BI
6 45 47 87 94
6 45 47 87 94
94 37
94 37
OUT
OUT
PCIE_ENET_R2D_C_N
PCIE_ENET_R2D_C_P
BF29
BH29
PETN1
PETP1
IBEX_PEAK_M
FCBGA
SMBDATA C8 SMBUS_PCH_DATA
OUT
BI
42 47 48 63 88
25 26 28 30 32 42
47 48 63 88 94
D
17 RTC_RESET_L C14 RTCRST* (1 OF 10) (2 OF 10)
FWH4/LFRAME* C34 LPC_FRAME_L OUT 6 45 47 87 94 94 33 6 IN PCIE_AP_D2R_N AW30 PERN2 SML0ALERT*/GPIO60 J14 PCH_SML0ALERT_L 17
17 PCH_SRTCRST_L D17 SRTCRST* 94 33 6 IN PCIE_AP_D2R_P BA30 PERP2

(IPU) LDRQ0* A34 TP_LPC_DREQ0_L C6 SML_PCH_0_CLK
RTC
LPC
SML0CLK OUT 48 94
PCIE_AP_R2D_C_N BC30 PETN2
SMBUS
94 33 OUT
17 PCH_INTRUDER_L A16 INTRUDER* LDRQ1*/GPIO23 F34 TP_LPC_DREQ1_L SML0DATA G8 SML_PCH_0_DATA BI 48 94
94 33 OUT PCIE_AP_R2D_C_P BD30 PETP2
17 PCH_INTVRMEN_L A14 INTVRMEN SERIRQ AB9 LPC_SERIRQ BI 6 45 47
94 39 IN PCIE_FW_D2R_N AU30 PERN3 SML1ALERT*/GPIO74 M14 PCH_SML1ALERT_L 17
94 39 IN PCIE_FW_D2R_P AT30 PERP3

AK7 HDD SML1CLK/GPIO58 E10 SML_PCH_1_CLK OUT 48 94
94 17 HDA_BIT_CLK_R A30 HDA_BCLK (IPD) SATA0RXN SATA_HDD_D2R_N IN 42 93 94 39 OUT PCIE_FW_R2D_C_N AU32 PETN3
SML1DATA/GPIO75 G12 SML_PCH_1_DATA BI 48 94
SATA0RXP AK6 SATA_HDD_D2R_P IN 42 93 94 39 OUT PCIE_FW_R2D_C_P AV32 PETP3
HDA_SYNC_R D29 HDA_SYNC (IPD) SATA0TXN AK11 SATA_HDD_R2D_C_N
C-LINK
94 17 OUT 42 93
8 IN NC_PCIE_EXCARD_D2R_N BA32 PERN4
SATA0TXP AK9 SATA_HDD_R2D_C_P OUT 42 93 (IPU) CL_CLK1 T13 NC_CLINK_CLK 6
8 IN NC_PCIE_EXCARD_D2R_P BB32 PERP4
17 PCH_SPKR P1 SPKR (IPD) ODD
SATA1RXN AH6 SATA_ODD_D2R_N IN 42 93 8 OUT NC_PCIE_EXCARD_R2D_C_N BD32 PETN4 (IPU) CL_DATA1 T11 NC_CLINK_DATA 6
AH5 SATA_ODD_D2R_P NC_PCIE_EXCARD_R2D_C_P BE32
IHDA
SATA1RXP IN 42 93 8 OUT PETP4
94 17 HDA_RST_R_L C30 HDA_RST* (IPD) CL_RST1* T9 NC_CLINK_RESET_L 6
SATA1TXN AH9 SATA_ODD_R2D_C_N OUT 42 93
6 NC_PCIE_PE5_D2RN BF33 PERN5
SATA1TXP AH8 SATA_ODD_R2D_C_P OUT 42 93
94 58 IN HDA_SDIN0 G30 HDA_SDIN0 (IPD) 6 NC_PCIE_PE5_D2RP BH33 PERP5
AF11 Unused PEG_A_CLKRQ*/GPIO47 H1 PEG_CLKREQ_L
some IbexPeak SKUs

IN 8 17 87
6 NC_HDA_SDIN1 F30 HDA_SDIN1 (IPD) SATA2RXN NC_SATA_C_D2RN 6 6 NC_PCIE_PE5_R2D_CN BG32 PETN5
Not available on
6 NC_HDA_SDIN2 E32 HDA_SDIN2 (IPD) SATA2RXP AF9 NC_SATA_C_D2RP 6 6 NC_PCIE_PE5_R2D_CP BJ32 PETP5
CLKOUT_PEG_A_N AD43 PEG_CLK100M_N
PEG
OUT 74 94
6 NC_HDA_SDIN3 F32 HDA_SDIN3 (IPD) SATA2TXN AF7 NC_SATA_C_R2D_CN 6
6 NC_PCIE_PE6_D2RN BA34 PERN6 CLKOUT_PEG_A_P AD45 PEG_CLK100M_P OUT 74 94
SATA2TXP AF6 NC_SATA_C_R2D_CP 6
6 NC_PCIE_PE6_D2RP AW34 PERP6
94 17 HDA_SDOUT_R B29 HDA_SDO (IPD) Unused NC_SATA_D_D2RN
SATA3RXN AH3 6 6 NC_PCIE_PE6_R2D_CN BC34 PETN6
CLKOUT_DMI_N AN4 PCIE_CLK100M_CPU_N OUT 10 91
(IPU/NO) SATA3RXP AH1 NC_SATA_D_D2RP 6 6 NC_PCIE_PE6_R2D_CP BD34 PETP6
45 17 IN SPI_DESCRIPTOR_OVERRIDE_L H32 HDA_DOCK_EN*/GPIO33 CLKOUT_DMI_P AN2 PCIE_CLK100M_CPU_P OUT 10 91
SATA3TXN AF3 NC_SATA_D_R2D_CN 6
SATA
37 17 IN ENET_ENERGY_DET J30 HDA_DOCK_RST*/GPIO13 6 NC_PCIE_PE7_D2RN AT34 PERN7
SATA3TXP AF1 NC_SATA_D_R2D_CP 6
6 NC_PCIE_PE7_D2RP AU34 PERP7
SSD CLKOUT_DP_N/CLKOUT_BCLK1_N AT1 GFX_CLK120M_DPLLSS_N
C C
PCI-E*
OUT 10 93
SATA4RXN AD9 NC_SATA_SSD2_D2RN NC_PCIE_PE7_R2D_CN AU36 PETN7
support FIS-based
IN 6 6
JTAG_PCH_TCK M3 JTAG_TCK (IPU) CLKOUT_DP_P/CLKOUT_BCLK1_P AT3 GFX_CLK120M_DPLLSS_P
Only ports 4 & 5
port multipliers
25 17 IN OUT 10 93
SATA4RXP AD8 NC_SATA_SSD2_D2RP IN 6 6 NC_PCIE_PE7_R2D_CP AV36 PETP7
25 17 IN JTAG_PCH_TMS K3 JTAG_TMS (IPU)
JTAG SATA4TXN AD6 NC_SATA_SSD2_R2D_CN OUT 6
6 NC_PCIE_PE8_D2RN BG34 PERN8
SATA4TXP AD5 NC_SATA_SSD2_R2D_CP OUT 6 CLKIN_DMI_N AW24 PCIE_CLK100M_PCH_N IN 26 93
25 17 IN JTAG_PCH_TDI K1 JTAG_TDI (IPU) 6 NC_PCIE_PE8_D2RP BJ34 PERP8
eSATA CLKIN_DMI_P BA24 PCIE_CLK100M_PCH_P IN 26 93
SATA5RXN AD3 NC_SATA_EXTA_D2R_N IN 8 6 NC_PCIE_PE8_R2D_CN BG36 PETN8
25 17 OUT JTAG_PCH_TDO J2 JTAG_TDO
SATA5RXP AD1 NC_SATA_EXTA_D2R_P IN 8 6 NC_PCIE_PE8_R2D_CP BJ36 PETP8
TP_JTAG_PCH_TRST_L J4 JTAG_RST* (IPU) SATA5TXN AB3 NC_SATA_EXTA_R2D_C_N OUT 8 CLKIN_BCLK_N AP3 FSB_CLK133M_PCH_N IN 26 93
SATA5TXP AB1 NC_SATA_EXTA_R2D_C_P OUT PCIE_CLK100M_ENET_N AK48 CLKOUT_PCIE0N CLKIN_BCLK_P AP1 FSB_CLK133M_PCH_P
FROM CLK BUFFER

8 94 37 OUT IN 26 93
94 37 OUT PCIE_CLK100M_ENET_P AK47 CLKOUT_PCIE0P

94 47 OUT SPI_CLK_R BA2 SPI_CLK
SATAICOMPO AF16 93 PCH_SATAICOMP
37 17 IN ENET_CLKREQ_L P9 PCIECLKRQ0*/GPIO73 CLKIN_DOT_96N F18 PCH_CLK96M_DOT_N IN 26 93
94 47 OUT SPI_CS0_R_L AV3 SPI_CS0* SATAICOMPI AF15
CLKIN_DOT_96P E18 PCH_CLK96M_DOT_P
SPI
IN 26 93
94 33 OUT PCIE_CLK100M_AP_N AM43 CLKOUT_PCIE1N
TP_SPI_CS1_L AY3 SPI_CS1*
(IPU) SATALED* T3 TP_PCH_SATALED_L 94 33 OUT PCIE_CLK100M_AP_P AM45 CLKOUT_PCIE1P
94 47 OUT SPI_MOSI_R AY1 SPI_MOSI (IPD) CLKIN_SATA_N/CKSSCD_N AH13 PCH_CLK100M_SATA_N IN 26 93
SATA0GP/GPIO21 Y9 SATARDRVR_A_EN OUT 17 25 42 33 25 17 IN AP_CLKREQ_L U4 PCIECLKRQ1*/GPIO18
CLKIN_SATA_P/CKSSCD_P AH12 PCH_CLK100M_SATA_P IN 26 93
94 47 IN SPI_MISO AV1 SPI_MISO (IPU) SATA1GP/GPIO19 V1 SATARDRVR_B_EN OUT 17 25
94 39 OUT PCIE_CLK100M_FW_N AM47 CLKOUT_PCIE2N
94 39 OUT PCIE_CLK100M_FW_P AM48 CLKOUT_PCIE2P
REFCLK14IN P41 PCH_CLK14P3M_REFCLK IN 26 93
40 25 17 IN FW_CLKREQ_L N4 PCIECLKRQ2*/GPIO20
94 8 OUT NC_PCIE_CLK100M_EXCARD_N AH42 CLKOUT_PCIE3N CLKIN_PCILOOPBACK J42 PCH_CLK33M_PCIIN IN 27 93
94 8 OUT NC_PCIE_CLK100M_EXCARD_P AH41 CLKOUT_PCIE3P

73 66 65
45 43 23 21 7 6 PP3V42_G3H 71 7 6 PP1V05_S5
64 53 49 48 47 46 17 IN EXCARD_CLKREQ_L A8 PCIECLKRQ3*/GPIO25 XTAL25_IN AH51 PCH_CLK25M_XTALIN IN 27
XTAL25_OUT AH53 PCH_CLK25M_XTALOUT OUT 27

XDP_PCH XDP_PCH XDP_PCH 6 NC_PCIE_CLK100M_PE4N AM51 CLKOUT_PCIE4N
R18021 1
R1803 R18251 R18261 1
R1827 6 NC_PCIE_CLK100M_PE4P AM53 CLKOUT_PCIE4P
20K 20K 51 51 51 XCLK_RCOMP AF38 PCH_XCLK_RCOMP
B 5%
1/16W
MF-LF
5%
1/16W
MF-LF
5%
1/16W
MF-LF
5%
1/16W
MF-LF
5%
1/16W
MF-LF
17 PCH_PE4_CLKREQ_L M9 PCIECLKRQ4*/GPIO26
B
402 2 2 402 402 2 402 2 2 402 6 NC_PCIE_CLK100M_PE5N AJ50 CLKOUT_PCIE5N
CLKOUTFLEX0/GPIO64 T45 BRCRYPT_RESET 17 101
6 NC_PCIE_CLK100M_PE5P AJ52 CLKOUT_PCIE5P (IPD)
JTAG_PCH_TMS Default: 0V
CLOCK
17 25
FLEX
R18001 1
R1801 JTAG_PCH_TDI 17 25 101 17 OUT BRCRYPT_PWR_EN H6 PCIECLKRQ5*/GPIO44 CLKOUTFLEX1/GPIO65 P43 ARB_DETECT 17
(IPD)
330K 1M JTAG_PCH_TDO 17 25 Default: 24.576 MHz (unsupported)
5% 5% 6 NC_PCIE_CLK100M_PEBN AK53 CLKOUT_PEG_B_N
1/16W 1/16W JTAG_PCH_TCK 17 25 CLKOUTFLEX2/GPIO66 T42 MLB_RAM_SIZE 17
MF-LF MF-LF RTC_RESET_L 17 6 NC_PCIE_CLK100M_PEBP AK51 CLKOUT_PEG_B_P (IPD)
402 2 2 402 PCH_SRTCRST_L Default: 14.31818 MHz
17
R18281 17 PCH_PEB_CLKREQ_L P13 PEG_B_CLKRQ*/GPIO56 CLKOUTFLEX3/GPIO67 N50 MLB_RAM_VENDOR 17
PCH_INTRUDER_L 17 (IPD)
51 PP3V3_S5 6 7 18 19 20 21 23 27 31 35 57 Default: 48 MHz
PCH_INTVRMEN_L 17 5% 66 71 72 73 83 85 99
1/16W PP3V3_S3 101
6 7 8 20 31 32 33 34 35 36 48 50 53 54 55
MF-LF
PP3V3_S0 50 51 52 54 58 62 63 68 69 72
72 73 87 All 4 CLKOUTFLEX outputs support
402 2
C1802 1 1 C1803 6 7 17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
73 80 83 84 85 87 88 99
33.333 MHz and 14.31818 MHz,
1UF 1UF
10%
10V
10%
10V
R1899 2.2K 1 2 PCH_SPKR 17
CLKOUTFLEX3 also supports 48 MHz.
X5R 2 2 X5R 5% 1/16W MF-LF 402
402 402 R1815 10K 1 2 SPI_DESCRIPTOR_OVERRIDE_L 17 45
5% 1/16W MF-LF 402
R1816 10K 1 2 ENET_ENERGY_DET 17 37
5% 1/16W MF-LF 402
R1840 10K 1 2 SATARDRVR_A_EN 17 25 42
R1841 10K 1 5% 1/16W MF-LF 402

2 SATARDRVR_B_EN 17 25
5% 1/16W MF-LF 402
R1850 10K 1 2 ENET_CLKREQ_L 17 37
R1810 R1851 10K 1 2 5% 1/16W MF-LF 402
AP_CLKREQ_L 17 25 33
33 R1852 10K 1 5% 1/16W MF-LF 402
94 17 HDA_BIT_CLK_R 1 2 HDA_BIT_CLK OUT 58 94 2 FW_CLKREQ_L 17 25 40
R1853 10K 1 5% 1/16W MF-LF 402
5% 2 EXCARD_CLKREQ_L 17
1/16W 5% 1/16W MF-LF 402
MF-LF
402 R1811 R1854 10K 1 2 PCH_PE4_CLKREQ_L 17
R1855 10K 1 5% 1/16W MF-LF 402

33 2 PCH_PEB_CLKREQ_L 17
HDA_SYNC_R 1 2 HDA_SYNC
A 94 17
5%
1/16W
OUT 58 94
R1860 100K 1 2
5%
5%
1/16W MF-LF
1/16W MF-LF 402

402
BRCRYPT_PWR_EN 17 101 SYNC_MASTER=K17_REF SYNC_DATE=08/24/2009 A
PAGE TITLE
R1812 MF-LF
R1870 10K 1 SMC_WAKE_SCI_L
94 17 HDA_RST_R_L 1
33 2
402
HDA_RST_L OUT 58 94 R1871 10K 1
2
2 5% 1/16W MF-LF 402
PCH_SML0ALERT_L
17 45
17
PCH SATA/PCIE/CLK/LPC/SPI
R1872 10K 1 5% 1/16W MF-LF 402 DRAWING NUMBER SIZE
5% 2 PCH_SML1ALERT_L
1/16W 5% 1/16W MF-LF 402
17

MF-LF
402 R1813 R1880 10K 1 2 PEG_CLKREQ_L 8 17 87 REVISION
33 5% 1/16W MF-LF 402 R
94 17 HDA_SDOUT_R 1 2 HDA_SDOUT OUT 58 94
R1895 10K 1 2 BRCRYPT_RESET 17 101
<E4LABEL>
5%
1/16W R1896 10K 1 2
5% 1/16W MF-LF 402
ARB_DETECT NOTICE OF PROPRIETARY PROPERTY: BRANCH
MF-LF
402 R1897 10K 1 2 5% 1/16W MF-LF 402
MLB_RAM_SIZE
17
17
<BRANCH>
R1898 10K 1 5% 1/16W MF-LF 402 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
2 MLB_RAM_VENDOR
5% 1/16W MF-LF 402
17
18 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PP3V3_S5 6 7 17 18 19 20 21 23 27 31 35
57 66 71 72 73 83 85 99
PP1V05_S0 6 7 10 12 13 15 17 20 21 23 24
25 26 40 70 73 86
R19051 1
R1900
10K 49.9
1% 1%
1/16W 1/16W
MF-LF MF-LF
402 2 2 402
91 9 IN DMI_N2S_N<0> BC24 DMI0RXN OMIT FDI_RXN0 BA18 FDI_DATA_N<0> IN 9 91 87 8 OUT LVDS_IG_BKL_ON T48 L_BKLTEN OMIT SDVO_TVCLKINN BJ46 NC_SDVO_TVCLKINN 6
91 9 IN DMI_N2S_N<1> BJ22 DMI1RXN U1800 FDI_RXN1 BH17 FDI_DATA_N<1> IN 9 91 87 8 OUT LVDS_IG_PANEL_PWR T47 L_VDD_EN U1800 SDVO_TVCLKINP BG46 NC_SDVO_TVCLKINP 6
D 91 9
91 9
IN
IN
DMI_N2S_N<2>
DMI_N2S_N<3>
AW20
BJ20
DMI2RXN
DMI3RXN
IBEX_PEAK_M
FCBGA
FDI_RXN2
FDI_RXN3
BD16
BJ16
FDI_DATA_N<2>
FDI_DATA_N<3>
IN
IN
9 91
9 91
8 6 OUT TP_LVDS_IG_BKL_PWM Y48 L_BKLTCTL IBEX_PEAK_M
FCBGA
SDVO_STALLN BJ48 NC_SDVO_STALLN 6 D
SDVO_STALLP BG48 NC_SDVO_STALLP 6
(3 OF 10) FDI_RXN4 BA16 FDI_DATA_N<4> IN 9 91 84 OUT LVDS_IG_DDC_CLK AB48 L_DDC_CLK (4 OF 10)
91 9 IN DMI_N2S_P<0> BD24 DMI0RXP
FDI_RXN5 BE14 FDI_DATA_N<5> IN 9 91 84 BI LVDS_IG_DDC_DATA Y45 L_DDC_DATA SDVO_INTN BF45 NC_SDVO_INTN 6
91 9 IN DMI_N2S_P<1> BG22 DMI1RXP
FDI_RXN6 BA14 FDI_DATA_N<6> IN 9 91 SDVO_INTP BH45 NC_SDVO_INTP 6
91 9 IN DMI_N2S_P<2> BA20 DMI2RXP 6 NC_LVDS_IG_CTRL_CLK AB46 L_CTRL_CLK
FDI_RXN7 BC12 FDI_DATA_N<7> IN 9 91
91 9 IN DMI_N2S_P<3> BG20 DMI3RXP 6 NC_LVDS_IG_CTRL_DATA V48 L_CTRL_DATA (IPD)
(IPD) SDVO_CTRLCLK T51 DP_IG_DDC_CLK OUT 8 80 84
FDI_RXP0 BB18 FDI_DATA_P<0> IN 9 91
(IPD) SDVO_CTRLDATA T53 DP_IG_DDC_DATA BI 8 80 84
91 9 OUT DMI_S2N_N<0> BE22 DMI0TXN FDI_RXP1 BF17 FDI_DATA_P<1> IN 9 91 PCH_LVDS_IBG AP39 LVD_IBG
91 9 OUT DMI_S2N_N<1> BF21 DMI1TXN FDI_RXP2 BC16 FDI_DATA_P<2> IN 9 91 6 NC_PCH_LVDS_VBG AP41 LVD_VBG DDPB_AUXN BG44 DP_IG_AUX_CH_N BI 8 84 93
91 9 OUT DMI_S2N_N<2> BD20 DMI2TXN FDI_RXP3 BG16 FDI_DATA_P<3> IN 9 91

1
R1950 DDPB_AUXP BJ44 DP_IG_AUX_CH_P BI 8 84 93
91 9 OUT DMI_S2N_N<3> BE18 DMI3TXN FDI_RXP4 AW16 FDI_DATA_P<4> IN 9 91 2.37K AT43 LVD_VREFH DDPB_HPD AU38 DP_IG_HPD IN 8 84
DMI
FDI
1%
FDI_RXP5 BD14 FDI_DATA_P<5> IN 9 91 1/16W AT42 LVD_VREFL
91 9 OUT DMI_S2N_P<0> BD22 DMI0TXP MF-LF DDPB_0N BD42 DP_IG_B_ML_N<0> OUT 8
FDI_RXP6 BB14 FDI_DATA_P<6> IN 9 91
2 402
91 9 OUT DMI_S2N_P<1> BH21 DMI1TXP DDPB_0P BC42 DP_IG_B_ML_P<0> OUT 8
FDI_RXP7 BD12 FDI_DATA_P<7> IN 9 91 93 87 OUT LVDS_IG_A_CLK_N AV53 LVDSA_CLK*
91 9 OUT DMI_S2N_P<2> BC20 DMI2TXP DDPB_1N BJ42 DP_IG_B_ML_N<1> OUT 8
93 87 OUT LVDS_IG_A_CLK_P AV51 LVDSA_CLK
91 9 OUT DMI_S2N_P<3> BD18 DMI3TXP DDPB_1P BG42 DP_IG_B_ML_P<1> OUT 8
FDI_INT BJ14 FDI_INT OUT 9 91
LVDS_IG_A_DATA_N<0> DP_IG_B_ML_N<2>
DIGITAL DISPLAY INTERFACE

93 87 OUT BB47 LVDSA_DATA0* DDPB_2N BB40 OUT 8
FDI_FSYNC0 BF13 FDI_FSYNC<0> OUT 9 91 93 87 OUT LVDS_IG_A_DATA_N<1> BA52 LVDSA_DATA1* DDPB_2P BA40 DP_IG_B_ML_P<2> OUT 8
LVDS
FDI_FSYNC1 BH13 FDI_FSYNC<1> OUT 9 91 93 87 OUT LVDS_IG_A_DATA_N<2> AY48 LVDSA_DATA2* DDPB_3N AW38 DP_IG_B_ML_N<3> OUT 8
93 8 OUT NC_LVDS_IG_A_DATAN<3> AV47 LVDSA_DATA3* DDPB_3P BA38 DP_IG_B_ML_P<3> OUT 8

PCH_DMI_COMP BH25 DMI_ZCOMP FDI_LSYNC0 BJ12 FDI_LSYNC<0> OUT 9 91
BF25 DMI_IRCOMP FDI_LSYNC1 BG14 FDI_LSYNC<1> OUT 9 91 93 87 OUT LVDS_IG_A_DATA_P<0> BB48 LVDSA_DATA0 (IPU)
DDPC_CTRLCLK Y49 NC_DP_IG_C_CTRL_CLK 6
93 87 OUT LVDS_IG_A_DATA_P<1> BA50 LVDSA_DATA1
DDPC_CTRLDATA AB49 NC_DP_IG_C_CTRL_DATA 6
LVDS_IG_A_DATA_P<2> AY49 LVDSA_DATA2 (IPD)
SYSTEM POWER
93 87 OUT
45 27 6 IN PM_SYSRST_L T6 SYS_RESET* WAKE* J12 PCIE_WAKE_L IN 6 18 27 33
NC_LVDS_IG_A_DATAP<3> AV48 BE44 NC_DP_IG_C_AUXN
MANAGEMENT
93 8 OUT LVDSA_DATA3 DDPC_AUXN 6
27 IN PM_PCH_PWRGD M6 SYS_PWROK CLKRUN*/GPIO32 Y1 PM_CLKRUN_L BI 6 18 45 47 DDPC_AUXP BD44 NC_DP_IG_C_AUXP 6
93 8 6 OUT TP_LVDS_IG_B_CLKN AP48 LVDSB_CLK* DDPC_HPD AV40 NC_DP_IG_C_HPD 6

B17 PWROK LPC_PWRDWN_L OUT 6 18 45 47
TP_LVDS_IG_B_CLKP
C K5 MEPWROK SUS_STAT*/GPIO61 P8
MAKE_BASE=TRUE
LPC_PWRDWN_L 6 18 45 47
93 8 6
93 87
OUT
LVDS_IG_B_DATA_N<0>
AP47
AY53
LVDSB_CLK
LVDSB_DATA0*
DDPC_0N
DDPC_0P
BE40
BD40
NC_DP_IG_C_MLN<0>
NC_DP_IG_C_MLP<0>
6
6
C
OUT
PCH_LAN_RST_L A10 LAN_RST* SUSCLK/GPIO62 F3 PM_CLK32K_SUSCLK OUT 46 94 93 87 OUT LVDS_IG_B_DATA_N<1> AT49 LVDSB_DATA1* DDPC_1N BF41 NC_DP_IG_C_MLN<1> 6
93 87 OUT LVDS_IG_B_DATA_N<2> AU52 LVDSB_DATA2* DDPC_1P BH41 NC_DP_IG_C_MLP<1> 6

91 31 10 OUT PM_MEM_PWRGD D9 DRAMPWROK SLP_S5*/GPIO63 E4 PM_SLP_S5_L OUT 45 46
93 8 OUT NC_LVDS_IG_B_DATAN<3> AT53 LVDSB_DATA3* DDPC_2N BD38 NC_DP_IG_C_MLN<2> 6
45 18 IN PM_RSMRST_L C16 RSMRST* SLP_S4* H7 PM_SLP_S4_L OUT 31 43 45 46 72 73 DDPC_2P BC38 NC_DP_IG_C_MLP<2> 6

93 87 OUT LVDS_IG_B_DATA_P<0> AY51 LVDSB_DATA0
DDPC_3N BB36 NC_DP_IG_C_MLN<3> 6
18 OUT PM_SUS_PWR_ACK M1 SUS_PWR_ACK/GPIO30 SLP_S3* P12 PM_SLP_S3_L OUT 6 31 45 73 85 93 87 OUT LVDS_IG_B_DATA_P<1> AT48 LVDSB_DATA1
DDPC_3P BA36 NC_DP_IG_C_MLP<3> 6
93 87 OUT LVDS_IG_B_DATA_P<2> AU50 LVDSB_DATA2
45 25 IN PM_PWRBTN_L P5 PWRBTN* (IPU) SLP_M* K8 TP_PM_SLP_M_L
93 8 OUT NC_LVDS_IG_B_DATAP<3> AT51 LVDSB_DATA3 (IPU)
DDPD_CTRLCLK U50 NC_DP_IG_D_CTRL_CLK 6
73 46 45 IN SMC_ADAPTER_EN P7 ACPRESENT/GPIO31 TP23 N2 TP_PM_SLP_DSW_L
DDPD_CTRLDATA U52 NC_DP_IG_D_CTRL_DATA 6
(IPD)
45 18 IN PM_BATLOW_L A6 BATLOW*/GPIO72 PMSYNCH BJ10 PM_SYNC BI 10 91 6 NC_CRT_IG_BLUE AA52 CRT_BLUE
DDPD_AUXN BC46 NC_DP_IG_D_AUXN 6
6 NC_CRT_IG_GREEN AB53 CRT_GREEN
PCH_RI_L F14 RI* SLP_LAN* F6 TP_SLP_LAN_L DDPD_AUXP BD46 NC_DP_IG_D_AUXP 6
6 NC_CRT_IG_RED AD53 CRT_RED
DDPD_HPD AT38 NC_DP_IG_D_HPD 6
1
R1906 NC_CRT_IG_DDC_CLK NC_DP_IG_D_MLN<0>
CRT
6 V51 CRT_DDC_CLK DDPD_0N BJ40 6
10K
5% 6 NC_CRT_IG_DDC_DATA V53 CRT_DDC_DATA DDPD_0P BG40 NC_DP_IG_D_MLP<0> 6
1/16W
MF-LF DDPD_1N BJ38 NC_DP_IG_D_MLN<1> 6
2 402 6 NC_CRT_IG_HSYNC Y53 CRT_HSYNC DDPD_1P BG38 NC_DP_IG_D_MLP<1> 6
6 NC_CRT_IG_VSYNC Y51 CRT_VSYNC DDPD_2N BF37 NC_DP_IG_D_MLN<2> 6

72 69 68 63 62 58 54 52 51 50
26 25 24 23 21 20 19 17 7 6 PP3V3_S0 DDPD_2P BH37 NC_DP_IG_D_MLP<2> 6
48 47 46 42 40 37 34 30 28 27
99 88 87 85 84 83 80 73 PCH_DAC_IREF AD48 DAC_IREF DDPD_3N BE36 NC_DP_IG_D_MLN<3> 6
AB51 CRT_IRTN DDPD_3P BD36 NC_DP_IG_D_MLP<3> 6
R19201 1
R1921 1
R1951
10K 10K 1K
5% 5% 5%
1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF
B 402 2 2 402 2 402
0.5% recommended, Intel okay
B
PM_SUS_PWR_ACK 18
PM_CLKRUN_L with 5% when CRTDAC not used.

6 18 45 47
PM_RSMRST_L 18 45
1
R1925
10K
5%
1/16W
MF-LF
402 2
31 27 23 21 20 19 18 17 7 6 PP3V3_S5
99 85 83 73 72 71 66 57 35
R19301 1
R1931
10K 10K
5% 5%
1/16W 1/16W
MF-LF MF-LF
402 2 2 402
PM_BATLOW_L 18 45
PCIE_WAKE_L 6 18 27 33
PAGE TITLE
PCH DMI/FDI/Graphics
DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
19 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
6 NC_PCI_AD<0> H40 AD0 OMIT NV_CE0* AY9 NC_NV_CE_L<0> 6
6 NC_PCI_AD<1> N34 AD1 U1800 NV_CE1* BD1 NC_NV_CE_L<1> 6
D 6
6
NC_PCI_AD<2>
NC_PCI_AD<3>
C44
A38
AD2
AD3
IBEX_PEAK_M
FCBGA
NV_CE2*
NV_CE3*
AP15
BD8
NC_NV_CE_L<2>
NC_NV_CE_L<3>
6
6
D
6 NC_PCI_AD<4> C36 AD4 (5 OF 10)
NV_DQS0 AV9 NC_NV_DQS<0> 6
6 NC_PCI_AD<5> J34 AD5
NV_DQS1 BG8 NC_NV_DQS<1> 6
6 NC_PCI_AD<6> A40 AD6
6 NC_PCI_AD<7> D45 AD7 NV_DQ0/NV_IO0 AP7 NC_NV_DQ<0> 6
6 NC_PCI_AD<8> E36 AD8 NV_DQ1/NV_IO1 AP6 NC_NV_DQ<1> 6
6 NC_PCI_AD<9> H48 AD9 NV_DQ2/NV_IO2 AT6 NC_NV_DQ<2> 6
6 NC_PCI_AD<10> E40 AD10 NV_DQ3/NV_IO3 AT9 NC_NV_DQ<3> 6
6 NC_PCI_AD<11> C40 AD11 NV_DQ4/NV_IO4 BB1 NC_NV_DQ<4> 6
NVRAM
6 NC_PCI_AD<12> M48 AD12 NV_DQ5/NV_IO5 AV6 NC_NV_DQ<5> 6
6 NC_PCI_AD<13> M45 AD13 NV_DQ6/NV_IO6 BB3 NC_NV_DQ<6> 6
6 NC_PCI_AD<14> F53 AD14 NV_DQ7/NV_IO7 BA4 NC_NV_DQ<7> 6
6 NC_PCI_AD<15> M40 AD15 NV_DQ8/NV_IO8 BE4 NC_NV_DQ<8> 6
6 NC_PCI_AD<16> M43 AD16 NV_DQ9/NV_IO9 BB6 NC_NV_DQ<9> 6
6 NC_PCI_AD<17> J36 AD17 NV_DQ10/NV_IO10 BD6 NC_NV_DQ<10> 6
6 NC_PCI_AD<18> K48 AD18 NV_DQ11/NV_IO11 BB7 NC_NV_DQ<11> 6
6 NC_PCI_AD<19> F40 AD19 NV_DQ12/NV_IO12 BC8 NC_NV_DQ<12> 6
6 NC_PCI_AD<20> C42 AD20 NV_DQ13/NV_IO13 BJ8 NC_NV_DQ<13> 6
6 NC_PCI_AD<21> K46 AD21 NV_DQ14/NV_IO14 BJ6 NC_NV_DQ<14> 6
6 NC_PCI_AD<22> M51 AD22 NV_DQ15/NV_IO15 BG6 NC_NV_DQ<15> 6

(IPD) NV_ALE BD3 NC_NV_ALE 6
6 NC_PCI_AD<24> K51 AD24
(IPD) NV_CLE AY6 NC_NV_CLE 6
6 NC_PCI_AD<25> L34 AD25
6 NC_PCI_AD<26> F42 AD26 NV_RCOMP AU2 NC_PCH_NV_RCOMP 6

(IPU) NV_RB* AV7 NC_NV_RB_L 6
6 NC_PCI_AD<28> G46 AD28
C 6
6
NC_PCI_AD<29>
NC_PCI_AD<30>
F44
M47
AD29
AD30
NV_WR0_RE*
NV_WR1_RE*
AY8
AY5
NC_NV_WR_RE_L<0>
NC_NV_WR_RE_L<1>
6
6
C
6 NC_PCI_AD<31> H36 AD31
NV_WE_CK0* AV11 NC_NV_WE_CK_L<0> 6
6 NC_PCI_C_BE_L<0> J50 C/BE0* NV_WE_CK1* BF5 NC_NV_WE_CK_L<1> 6
6 NC_PCI_C_BE_L<1> G42 C/BE1*

6 NC_PCI_C_BE_L<2> H47 C/BE2*
USBP0N H18 USB_HUB1_UP_N BI 35 93
72 69 68 63 62 58 54 52 51 50
26 25 24 23 21 20 18 17 7 6 PP3V3_S0 6 NC_PCI_C_BE_L<3> G34 C/BE3* External Hub 1
USB_HUB1_UP_P
NOTE: Internal pull-downs on all USB pins

48 47 46 42 40 37 34 30 28 27
99 88 87 85 84 83 80 73 USBP0P J18 BI 35 93
R2010
(DPD)
10K 1 2 PCI_INTA_L G38 PIRQA* USBP1N A18 NC_USB_1N
5% 1/16W MF-LF 402
R2011 10K 1 2 PCI_INTB_L H51 PIRQB* USBP1P C18 NC_USB_1P
R2012 10K 5% 1/16W MF-LF 402
1 2 PCI_INTC_L USB_BRCRYPT_N
PCI
B37 PIRQC* USBP2N N20 BI 93 101
R2013 10K 1 2
5% 1/16W MF-LF 402
PCI_INTD_L USB_BRCRYPT_P T57
A44 PIRQD* USBP2P P20 BI 93 101
5% 1/16W MF-LF 402
USBP3N J20 NC_USB_3N
R2014 10K 1 2 PCI_REQ0_L
EHCI1
F51 REQ0*
5% 1/16W MF-LF 402 USBP3P L20 NC_USB_3P
87 19 OUT JTAG_GMUX_TMS A46 REQ1*/GPIO50
USBP4N F20 NC_USB_4N
87 19 OUT JTAG_GMUX_TDI B45 REQ2*/GPIO52
USBP4P G20 NC_USB_4P
19 PCI_REQ3_L M53 REQ3*/GPIO54
USBP5N A20 NC_USB_5N
6 NC_PCI_GNT0_L F48 GNT0* (IPU) USBP5P C20 NC_USB_5P
6 NC_PCI_GNT1_L K45 GNT1*/GPIO51 USBP6N M22 NC_USB_6N
6 NC_PCI_GNT2_L F36 GNT2*/GPIO53 USBP6P N22 NC_USB_6P
6 NC_PCI_GNT3_L H53 GNT3*/GPIO55 USBP7N B21 NC_USB_7N
USBP7P D21 NC_USB_7P
19 PCH_GPIO2 B41 PIRQE*/GPIO2
USBP8N H22 USB_HUB2_UP_N BI 36 93
63 19 IN AUD_IP_PERIPHERAL_DET K53 PIRQF*/GPIO3 External Hub 2
USBP8P J22 USB_HUB2_UP_P BI 36 93
MIKEY_MIC_LOAD_DET A36 PIRQG*/GPIO4
(DPD)
19 IN
USBP9N E22 NC_USB_9N
63 19 AUD_I2C_INT_L A48 PIRQH*/GPIO5
USB
IN NC_USB_9P
USBP9P F22
PP3V3_S5 85 99
6 7 17 18 19 20 21 23 27
B 6 NC_PCI_RESET_L K6 PCIRST* USBP10N A22 NC_USB_10N 31 35 57 66 71 72 73 83

B
EHCI2
USBP10P C22 NC_USB_10P
R2020 10K 1 2 PCI_SERR_L E44 SERR*
G24 NC_USB_11N
R2021 10K 5% 1/16W MF-LF 402 USBP11N
1 2 PCI_PERR_L E50 PERR* 1
R2061 1
R2064 1
R2066
5% 1/16W MF-LF 402 USBP11P H24 NC_USB_11P
R2022 10K 10K 10K 10K
1 2 PCI_IRDY_L A42 IRDY* USBP12N L24 NC_USB_12N 5% 5% 5%
5% 1/16W MF-LF 402 1/16W 1/16W 1/16W
6 NC_PCI_PAR H44 PAR USBP12P M24 NC_USB_12P MF-LF MF-LF MF-LF
R2023 10K 1 2 PCI_DEVSEL_L F46 DEVSEL* USBP13N A24 NC_USB_13N 2 402 2 402 2 402
R2024 10K 5% 1/16W MF-LF 402
1 2 PCI_FRAME_L C46 FRAME* USBP13P C24 NC_USB_13P
5% 1/16W MF-LF 402
R2025 10K 1 2 PCI_PLOCK_L D49 PLOCK* R20601 R20621 R20651
5% 1/16W MF-LF 402 USBRBIAS* B25 93 PCH_USB_RBIAS 10K 10K 10K
R2026 10K 1 2 PCI_STOP_L D41 STOP* USBRBIAS D25
5%
1/16W
5%
1/16W
5%
1/16W
R2027 10K 5% 1/16W MF-LF 402 MF-LF MF-LF MF-LF
1 2 PCI_TRDY_L C48 TRDY* 402 2 402 2 402 2
5% 1/16W MF-LF 402
6 NC_PCI_PME_L M7 PME* (IPU) OC0*/GPIO59 N16 PCH_GPIO59 IN 19 25
OC1*/GPIO40 J16 USB_HUB_SOFT_RESET_L 25 35

40 31 27 OUT PLT_RESET_L D5 PLTRST*
OC2*/GPIO41 F16 PCH_GPIO41 25
94 27 OUT LPC_CLK33M_SMC_R N52 CLKOUT_PCI0 OC3*/GPIO42 L16 PCH_GPIO42 25
27 OUT LPC_CLK33M_LPCPLUS_R P53 CLKOUT_PCI1 OC4*/GPIO43 E14 PCH_GPIO43 25
27 LPC_CLK33M_GMUX_R P46 CLKOUT_PCI2 OC5*/GPIO9 G16 PCH_GPIO9 25
6 NC_PCI_CLK33M_OUT3 P51 CLKOUT_PCI3 OC6*/GPIO10 F12 PCH_GPIO10 25 46
27 OUT PCH_CLK33M_PCIOUT P48 CLKOUT_PCI4 OC7*/GPIO14 T15 PM_LATRIGGER_L IN 19 25
R20701
22.6
1%
1/16W
MF-LF
R2030 10K 1 2 JTAG_GMUX_TMS 19 87
402 2
A R2031
R2032
10K
10K
1
1
2
2
5%
5%
1/16W MF-LF 402
1/16W MF-LF 402
JTAG_GMUX_TDI
PCI_REQ3_L
19 87
19
SYNC_MASTER=K18_MLB SYNC_DATE=10/07/2009 A
5% 1/16W MF-LF 402 PAGE TITLE
R2035 10K 1 2
5% 1/16W MF-LF 402
PCH_GPIO2 19 PCH PCI/FlashCache/USB
R2036 10K 1 2 AUD_IP_PERIPHERAL_DET 19 63 DRAWING NUMBER SIZE
5% 1/16W MF-LF 402
R2037 10K 1 2 MIKEY_MIC_LOAD_DET 19 <SCH_NUM> D
R2038 10K 1 2 5% 1/16W MF-LF 402
AUD_I2C_INT_L 19 63
Apple Inc. REVISION
5% 1/16W MF-LF 402 R
<E4LABEL>
31 27 23 21 20 19 18 17 7 6 PP3V3_S5 NOTICE OF PROPRIETARY PROPERTY: BRANCH
99 85 83 73 72 71 66 57 35
R2080 10K 1 2 PCH_GPIO59 19 25 THE INFORMATION CONTAINED HEREIN IS THE <BRANCH>
R2081 10K 5% 1/16W MF-LF 402 PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
1 2 PM_LATRIGGER_L 19 25 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
5% 1/16W MF-LF 402 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
20 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
IPU* = Only on TACH function. PP3V3_S0 50 51 52 54 58 62 63 68 69 72

6 7 17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
73 80 83 84 85 87 88 99
46 45 25 20 IN SMC_IG_THROTTLE_L Y3 BMBUSY*/GPIO0 OMIT CLKOUT_PCIE6N AH45 NC_PCIE_CLK100M_PE6N 6
U1800 CLKOUT_PCIE6P AH46 NC_PCIE_CLK100M_PE6P 6

40 20 8 FW_PLUG_DET_L C38 TACH1/GPIO1 (IPU*) R21501 1
R2155
D 87 20
IN
IN GMUX_INT D37 TACH2/GPIO6 (IPU*)

IBEX_PEAK_M
FCBGA CLKOUT_PCIE7N AF48 NC_PCIE_CLK100M_PE7N 6
10K
5%
10K
5%
D
1/16W 1/16W
(6 OF 10) CLKOUT_PCIE7P AF47 NC_PCIE_CLK100M_PE7P 6 MF-LF MF-LF
45 20 IN SMC_RUNTIME_SCI_L J32 TACH3/GPIO7 (IPU*) 402 2 2 402
20 PCH_FCIM_EN_L F10 GPIO8 (IPU) MISC A20GATE U2 PCH_A20GATE

37 20 OUT ENET_LOW_PWR K9 LAN_PHY_PWR_CTRL/GPIO12
CLKOUT_BCLK0_N/CLKOUT_PCIE8N AM3 FSB_CLK133M_CPU_N OUT 10 91
20 PCH_GPIO15 T7 GPIO15 (IPD)
CLKOUT_BCLK0_P/CLKOUT_PCIE8P AM1 FSB_CLK133M_CPU_P OUT 10 91
63 25 20 OUT AUD_IPHS_SWITCH_EN AA2 SATA4GP/GPIO16

PP1V05_S0 6 7 10 12 13 15 17 18 21 23 24
PECI BG10 CPU_PECI BI 10 91 25 26 40 70 73 86
47 20 6 BI LPCPLUS_GPIO F38 TACH0/GPIO17 (IPU*)
CPU
1
42 20 OUT ODD_PWR_EN_L Y7 SCLOCK/GPIO22 RCIN* T1 PCH_RCIN_L R2160
56
5%
20 PCH_GPIO24 H10 MEM_LED/GPIO24 1/16W
PROCPWRGD BE10 CPU_PWRGD OUT 10 25 91 MF-LF
20 PCH_VRM_EN AB12 GPIO27 R2161 2 402
56
THRMTRIP* BD10 PCH_THRMTRIP_L 1 2 PM_THRMTRIP_L IN 10 46 91
31 25 OUT ISOLATE_CPU_MEM_L V13 GPIO28 (IPU)
5%
GPIO
1/16W
TP_PCH_STP_PCI_L M11 STP_PCI*/GPIO34 MF-LF
TP1 BA22 NC_PCH_TP1 6 402
20 OUT MXM_GOOD V6 SATACLKREQ*/GPIO35
TP2 AW22 NC_PCH_TP2 6
34 25 20 OUT SDCARD_RESET AB7 SATA2GP/GPIO36
87 25 20 OUT JTAG_GMUX_TCK AB13 SATA3GP/GPIO37 TP3 BB22 NC_PCH_TP3 6
87 20 IN JTAG_GMUX_TDO V3 SLOAD/GPIO38
TP4 AY45 NC_PCH_TP4 6 (DPL_B_MON1_N)
20 PCH_GPIO39 P3 SDATAOUT0/GPIO39
TP5 AY46 NC_PCH_TP5 6 (DPL_B_MON1_P)
WOL_EN
C 73 20
73 33 20
OUT
AP_PWR_EN
H3
F1
PCIECLKRQ6*/GPIO45
PCIECLKRQ7*/GPIO46 TP6 AV43 NC_PCH_TP6 6 (DPL_B_MON2_N)

C
OUT
40 20 OUT FW_PWR_EN AB6 SDATAOUT1/GPIO48

TP7 AV45 NC_PCH_TP7 6 (DPL_B_MON2_P)
25 20 OUT ME_TEMP_ALERT_L AA4 SATA5GP/GPIO49
TP8 AF13 NC_PCH_TP8 6 (SATA_OB_ANA)
57 47 20 6 BI SPIROM_USE_MLB F8 GPIO57
TP9 M18 NC_PCH_TP9 6
94 6 PCH_VSS_NCTF<1> A4 VSS_NCTF1
94 6 PCH_VSS_NCTF<2> A49 VSS_NCTF2 TP10 N18 NC_PCH_TP10 6
A5 VSS_NCTF3
A50 VSS_NCTF4 TP11 AJ24 NC_PCH_TP11 6
94 6 PCH_VSS_NCTF<5> A52 VSS_NCTF5
RSVD
A53 VSS_NCTF6 TP12 AK41 NC_PCH_TP12 6 (XCKPLL_MON1_N)
94 TP_PCH_VSS_NCTF<7> B2 VSS_NCTF7
B4 VSS_NCTF8 TP13 AK42 NC_PCH_TP13 6 (XCKPLL_MON1_P)
94 6 PCH_VSS_NCTF<9> B52 VSS_NCTF9
B53 VSS_NCTF10 TP14 M32 NC_PCH_TP14 6
94 6 PCH_VSS_NCTF<11> BE1 VSS_NCTF11

94 6 PCH_VSS_NCTF<12> BE53 VSS_NCTF12 TP15 N32 NC_PCH_TP15 6
BF1 VSS_NCTF13
BF53 VSS_NCTF14 TP16 M30 NC_PCH_TP16 6
NCTF
94 6 PCH_VSS_NCTF<15> BH1 VSS_NCTF15
BH2 VSS_NCTF16 TP17 N30 NC_PCH_TP17 6
94 6 PCH_VSS_NCTF<17> BH52 VSS_NCTF17

BH53 VSS_NCTF18 TP18 H12 NC_PCH_TP18 6
B 94 6 PCH_VSS_NCTF<19> BJ1
BJ2
VSS_NCTF19
VSS_NCTF20 TP19 AA23 NC_PCH_TP19 6
B
94 6 PCH_VSS_NCTF<21> BJ4 VSS_NCTF21
94 PCH_VSS_NCTF<22> BJ49 VSS_NCTF22
NC_1 AB45 NC_PCH_NC1 6
PP3V3_S5 6 7 17 18 19 21 23 27 31 35 57 BJ5 VSS_NCTF23
66 71 72 73 83 85 99 NC_2 AB38 NC_PCH_NC2 6
PP3V3_S3 101
6 7 8 17 31 32 33 34 35 36 48 50 53 54 55 BJ50 VSS_NCTF24
72 73 87 NC_3 AB42 NC_PCH_NC3 6
PP3V3_S0 50 51 52 54 58 62 63 68 69 72
6 7 17 18 19 20 21 23 24 25 26 94 6 PCH_VSS_NCTF<25> BJ52 VSS_NCTF25
27 28 30 34 37 40 42 46 47 48
73 80 83 84 85 87 88 99
NC_4 AB41 NC_PCH_NC4 6
BJ53 VSS_NCTF26
NC_5 T39 NC_PCH_NC5
R2110 10K 1 2 SMC_IG_THROTTLE_L 20 25 45 46 94 6 PCH_VSS_NCTF<27> D1 VSS_NCTF27
6
5% 1/16W MF-LF 402

R2111 10K 1 2 FW_PLUG_DET_L 8 20 40 D2 VSS_NCTF28
5% 1/16W MF-LF 402
R2112 20K 94 6 PCH_VSS_NCTF<29> D53 VSS_NCTF29 (IPD) INIT3_3V* P6 TP_PCH_INIT3V3_L
1 2 GMUX_INT 20 87
5% 1/16W MF-LF 402 E1 VSS_NCTF30
R2113 10K 1 2 SMC_RUNTIME_SCI_L 20 45 E53 VSS_NCTF31 TP24 C10 NC_PCH_SST 6
R2114 10K 5% 1/16W MF-LF 402
1 2 PCH_FCIM_EN_L 20
R2115 2.2K 1 2
5% 1/16W MF-LF 402
ENET_LOW_PWR 20 37
5% 1/16W MF-LF 402
R2116 10K 1 2 PCH_GPIO15 20
5% 1/16W MF-LF 402
R2120 10K 1 2 AUD_IPHS_SWITCH_EN 20 25 63
R2121 10K 5% 1/16W MF-LF 402
1 2 LPCPLUS_GPIO 6 20 47
5% 1/16W MF-LF 402
R2122 10K 1 2 ODD_PWR_EN_L 20 42
5% 1/16W MF-LF 402
R2123 10K 1 2 PCH_GPIO24 20
5% 1/16W MF-LF 402
R2124 10K 1 2 PCH_VRM_EN 20
5% 1/16W MF-LF 402
R2130 10K 1 2 MXM_GOOD 20

R2131 10K 5% 1/16W MF-LF 402
1 2 SDCARD_RESET
A R2132 10K 1 2 5%
5%
1/16W MF-LF 402
1/16W MF-LF 402
JTAG_GMUX_TCK
20 25 34
20 25 87 SYNC_MASTER=K17_REF SYNC_DATE=06/15/2009 A
PAGE TITLE
R2133 10K JTAG_GMUX_TDO
R2134 10K
1
1
2
2 5% 1/16W MF-LF 402
PCH_GPIO39
20 87
20
PCH MISC
5% 1/16W MF-LF 402 DRAWING NUMBER SIZE
R2135 10K 1 2 WOL_EN 20 73 <SCH_NUM> D
5% 1/16W MF-LF 402 Apple Inc.
R2136 10K 1 2 AP_PWR_EN 20 33 73 R
REVISION
5% 1/16W MF-LF 402 <E4LABEL>
R2137 10K 1 2 FW_PWR_EN 20 40 NOTICE OF PROPRIETARY PROPERTY: BRANCH
R2138 10K 5% 1/16W MF-LF 402
1 2
5% 1/16W MF-LF 402
ME_TEMP_ALERT_L 20 25 THE INFORMATION CONTAINED HEREIN IS THE
<BRANCH>
R2139 100K 1 2 SPIROM_USE_MLB THE POSESSOR AGREES TO THE FOLLOWING: PAGE
5% 1/16W MF-LF 402
6 20 47 57
21 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT OMIT
U1800 U1800
IBEX_PEAK_M IBEX_PEAK_M
FCBGA FCBGA
23 PP1V05_S0_PCH_VCCA_CLK (10 OF 10) PP1V05_S0 6 7 10 12 13 15 17 18 20 21 23 21 20 18 17 15 13 12 10 7 6 PP1V05_S0 (7 OF 10) PP3V3_S0_PCH_VCCA_DAC 24
D 52 mA AP51 VCCACLK1 VCCIO5 V24 3062 mA (VCCIO[1-56] total)

24 25 26 40 70 73 86 86 73 70 40 26 25 24 23
1432 mA AB24 VCCCORE1 VCCADAC1 AE50 69 mA D
AP53 VCCACLK2 VCCIO6 V26 AB26 VCCCORE2 VCCADAC2 AE52
USB
CRT
VCCIO7 Y24 AB28 VCCCORE3
GND VSSA_DAC1 AF53
VCCIO8 Y26 AD26 VCCCORE4
320 mA S0, 67 mA M-on AF23 VCCLAN1 VSSA_DAC2 AF51
VCC CORE
AD28 VCCCORE5
AF24 VCCLAN2 PP3V3_S5 6 7 17 18 19 20 21 23 27 31 35
57 66 71 72 73 83 85 99 AF26 VCCCORE6
VCCSUS3_3_1 V28 163 mA S0, 65 mA S3-S5
PCH output, for decoupling only AF28 VCCCORE7
PPVOUT_S5_PCH_DCPSUSBYP VCCSUS3_3_2 U28 (VCCSUS3_3[1-32] total)
Y20 DCPSUSBYP AF30 VCCCORE8
CLOCK AND MISCELLANEOUS

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V VCCSUS3_3_3 U26
AF31 VCCCORE9
73 70 40 26 25 24
PP1V05_S0 VCCSUS3_3_4 U24
1 C2200 15 13 12 10 7 6
23 21 20 18 17
86
1849 mA S0, 700 mA M-on AD38 VCCME1 VCCSUS3_3_5 P28
AH26 VCCCORE10
0.1UF AH28 VCCCORE11 PP3V3_S0 50 51 52 54 58 62 63 68 69 72
6 7 17 18 19 20 21 23 24 25 26
20% (VCCME[1-16] total) AD39 VCCME2 VCCSUS3_3_6 P26 27 28 30 34 37 40 42 46 47 48
2 10V
LVDS
CERM AH30 VCCCORE12 VCCALVDS AH38 < 1 mA 73 80 83 84 85 87 88 99
402 AD41 VCCME3 VCCSUS3_3_7 N28

AH31 VCCCORE13
AF43 VCCME4 VCCSUS3_3_8 N26 VSSA_LVDS AH39
AJ30 VCCCORE14
PLACE_NEAR=U1800.Y20:2.54MM AF41 VCCME5 VCCSUS3_3_9 M28
AJ31 VCCCORE15 PP1V8_S0_PCH_VCCTX_LVDS 24
AF42 VCCME6 VCCSUS3_3_10 M26
V39 L28 PP1V05_S0 VCCTX_LVDS1 AP43 59 mA
VCCME7 VCCSUS3_3_11 21 20 18 17 15 13 12 10 7 6
86 73 70 40 26 25 24 23 VCCTX_LVDS2 AP45
V41 VCCME8 VCCSUS3_3_12 L26 3062 mA (VCCIO[1-56] total) AK24 VCCIO24
VCCTX_LVDS3 AT46
V42 VCCME9 VCCSUS3_3_13 J28
23 PP1V05_S0_PCH_VCCAPLL_EXP VCCTX_LVDS4 AT45
Y39 VCCME10 VCCSUS3_3_14 J26
40 mA (if GPIO27 is low) BJ24 VCCAPLLEXP
Y41 VCCME11 VCCSUS3_3_15 H28
Y42 VCCME12 VCCSUS3_3_16 H26 21 20 18 17 15 13 12 10 7 6 PP1V05_S0
86 73 70 40 26 25 24 23
VCCSUS3_3_17 G28 3062 mA AN20 VCCIO25
PCH output, for decoupling only
PPVOUT_G3_PCH_DCPRTC V9
VCCSUS3_3_18 G26 (VCCIO[1-56] total) AN22 VCCIO26
DCPRTC
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=X.XV VCCSUS3_3_19 F28 AN23 VCCIO27
HVCMOS
23 21 16 12 7 6 PP1V8_S0 VCCSUS3_3_20 F26 AN24 VCCIO28 PP3V3_S0 50 51 52 54 58 62 63 68 69 72
6 7 17 18 19 20 21 23 24 25 26
1 C2210 87 72 71 58 24
164 mA (VCCVRM[1-4] total) AU24 VCCVRM3 VCCSUS3_3_21 E28 AN26 VCCIO29 VCC3_3_2 AB34 357 mA
27 28 30 34 37 40 42 46 47 48
73 80 83 84 85 87 88 99
0.1UF
C 20%
10V
2 CERM 24 PP1V05_S0_PCH_VCCADPLLA VCCSUS3_3_22
VCCSUS3_3_23
E26
C28
AN28
BJ26
VCCIO30
VCCIO31
VCC3_3_3
VCC3_3_4
AB35
AD35
(VCC3_3[1-14] total) C
402 68 mA BB51 VCCADPLLA1
VCCSUS3_3_24 C26 BJ28 VCCIO32
PLACE_NEAR=U1800.V9:2.54MM BB53 VCCADPLLA2
VCCSUS3_3_25 B27 AT26 VCCIO33
PP1V05_S0_PCH_VCCADPLLB
24 VCCSUS3_3_26 A28 AT28 VCCIO34
69 mA BD51 VCCADPLLB1 VCCSUS3_3_27 A26 AU26 VCCIO35
3062 mA (VCCIO[1-56] total) BD53 VCCADPLLB2 VCCSUS3_3_28 U23 AU28 VCCIO36
PCI-E*
26 25 24 23
13 12 10 7 6 PP1V05_S0 AV26 VCCIO37
21 20 18 17 15
86 73 70 40
PP1V05_S0 6 7 10 12 13 15 17 18 20 21 23 PP1V8_S0 6 7 12 16 21 23 24 58 71 72 87
R2225 AH23 VCCIO21 VCCIO56 V23 3062 mA (VCCIO[1-56] total)
24 25 26 40 70 73 86 AV28 VCCIO38
VCCVRM2 AT24 164 mA (VCCVRM[1-4] total)
0.2 AW26 VCCIO39
DMI
1 2 PP1V05_S0_PCH_VCCIO_SSC_FLT AJ35 VCCIO22
MIN_LINE_WIDTH=0.2 mm PP5V_S5_PCH_V5REFSUS 23 AW28 VCCIO40 PP1V05_S0 6 7 10 12 13 15 17 18 20 21 23
1% MIN_NECK_WIDTH=0.1 mm AH35 VCCIO23 24 25 26 40 70 73 86
1/6W
MF
C2225 1 VOLTAGE=1.05V V5REF_SUS F24 < 1 mA S0-S5 BA26 VCCIO41 VCCDMI1 AT16 61 mA (1.1V)
402-HF 4.7UF BA28 VCCIO42 VCCDMI2 AU16 58 mA (1.05V)
20%
4V AF34 VCCIO2 PP5V_S0_PCH_V5REF 23
X5R 2 BB26 VCCIO43
115 mA AH34 VCCIO3 V5REF K49 < 1 mA
PCI/GPIO/LPC
402 BB28 VCCIO44

PLACE_NEAR=U1800.V12:2.54MM AF32 VCCIO4
PP3V3_S0 50 51 52 54 58 62 63 68 69 72
6 7 17 18 19 20 21 23 24 25 26 BC26 VCCIO45
27 28 30 34 37 40 42 46 47 48
PCH output, for decoupling only VCC3_3_8 J38 357 mA 73 80 83 84 85 87 88 99
BC28 VCCIO46
PPVOUT_S0_PCH_DCPSST V12 DCPSST VCC3_3_9 L38 (VCC3_3[1-14] total) BD26 VCCIO47
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=X.XV
VCC3_3_10 M36 BD28 VCCIO48
PCH output, for decoupling only PP1V8_S0 6 7 12 16 21 23 24 58 71 72 87
1 C2220 PPVOUT_S5_PCH_DCPSUS Y22 DCPSUS
VCC3_3_11 N36 BE26 VCCIO49
VCCPNAND1 AM16 156 mA (1.8V)
0.1UF MIN_LINE_WIDTH=0.2 mm VCC3_3_12 P36 BE28 VCCIO50
20% MIN_NECK_WIDTH=0.2 mm VCCPNAND2 AK16 NOTE: Connect to 3.3V if NAND not used.
10V U35 BG26
NAND / SPI
2 CERM VOLTAGE=X.XV VCC3_3_13 VCCIO51
VCCPNAND3 AK20
402 1 C2230 PP3V3_S0 48 50 51 52 54 58 62 63 68 69 BG28 VCCIO52
VCCPNAND4 AK19
0.1UF 6 7 17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 BH27 VCCIO53
20% VCC3_3_14 AD13 357 mA (VCC3_3[1-14] total) 72 73 80 83 84 85 87 88 99 VCCPNAND5 AK15
10V
2 CERM
402 AN30 VCCIO54 VCCPNAND6 AK13
PLACE_NEAR=U1800.Y22:2.54MM PP1V05_S0_PCH_VCCAPLL_SATA 23
AN31 VCCIO55 VCCPNAND7 AM12
B VCCSATAPLL1
VCCSATAPLL2
AK3
AK1
31 mA (if GPIO27 is low) 99
68 63 62 58 54 52 51 50 48 47
25 24 23 21 20 19 18 17 7 6 PP3V3_S0 VCCPNAND8 AM13 B
46 42 40 37 34 30 28 27 26 VCCPNAND9 AM15
31 27 23 21 20 19 18 17 7 6 PP3V3_S5 88 87 85 84 83 80 73 72 69
357 mA (VCC3_3[1-14] total) AN35 VCC3_3_1
99 85 83 73 72 71 66 57 35 PP1V05_S0 6 7 10 12 13 15 17 18 20 21 23
163 mA S0, 65 mA S3-S5 P18 VCCSUS3_3_29 24 25 26 40 70 73 86 PP3V3_S0 50 51 52 54 58 62 63 68 69 72
6 7 17 18 19 20 21 23 24 25 26
VCCIO9 AH22 3062 mA (VCCIO[1-56] total) 72 71 58 24 23 21 16 12 7 6 PP1V8_S0 27 28 30 34 37 40 42 46 47 48
(VCCSUS3_3[1-32] total) U19 VCCSUS3_3_30 87 VCCME3_3_1 AM8 85 mA S0, 22 mA M-on 73 80 83 84 85 87 88 99
PP1V8_S0 164 mA (VCCVRM[1-4] total) AT22 VCCVRM1

U20 VCCSUS3_3_31 6 7 12 16 21 23 24 58 71 72 87 VCCME3_3_2 AM9
FDI
U22 VCCSUS3_3_32 VCCVRM4 AT20 164 mA (VCCVRM[1-4] total) 23 PP1V05_S0_PCH_VCCAPLL_FDI VCCME3_3_3 AP11
99
5 mA (if GPIO27 is low) BJ18 VCCFDIPLL VCCME3_3_4 AP9
PCI/GPIO/LPC
68 63 62 58 54 52 51 50 48 47
25 24 23 21 20 19 18 17 7 6 PP3V3_S0
46 42 40 37 34 30 28 27 26
88 87 85 84 83 80 73 72 69
357 mA V15 VCC3_3_5 VCCIO10 AH19 GPIO27 HDA_SYNC VccVRM PLLs 21 20 18 17 15 13 12 10 7 6
86 73 70 40 26 25 24 23
PP1V05_S0
SATA
(VCC3_3[1-14] total) V16 VCC3_3_6 VCCIO11 AD20 3062 mA (VCCIO[1-56] total) AM23 VCCIO1
Y16 VCC3_3_7 VCCIO12 AF22 1 (IPU) 0 (IPD) 1.8V Float
VCCIO13 AD19
VCCIO14 AF20
1 (IPU) 1 1.5V Float
VCCIO15 AF19 0 X 1.05V 1.05V
VCCIO16 AH20
Note: 1.5V option consumes more current than 1.8V
VCCIO17 AB19
VCCIO18 AB20 PLLs = VccAClk, VccSATAPLL, VccAPLLEXP & VccFDIPLL
VCCIO19 AB22
VCCIO20 AD22
21 20 18 17 15 13 12 10 7 6 PP1V05_S0
CPU
86 73 70 40 26 25 24 23
< 1 mA AT18 V_CPU_IO1 PP1V05_S0 6 7 10 12 13 15 17 18 20 21 23
24 25 26 40 70 73 86
AU18 V_CPU_IO2 VCCME13 AA34 1849 mA S0, 700 mA M-on
VCCME14 Y34 (VCCME[1-16] total)
VCCME15 Y35
VCCME16 AA35
58 62 63 68 69 72 73 80 83 84
PP3V42_G3H PP3V3_S0 30 34
Verify S0 okay
A 49 48 47 46 45 43 23 17 7 6 6 7 17
A
RTC
HDA
73 66 65 64 53 18 19 20 21 23 24 25 26 27 28
2 mA S0-S5, ~6 uA G3 A12 VCCRTC VCCSUSHDA L30 6 mA S0, < 1 mA S3-S5 37 40 42 46 47 48 50 51 52 54
85 87 88 99 SYNC_MASTER=K17_REF SYNC_DATE=06/15/2009
PAGE TITLE
PCH Power
DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
22 OF 132
Current numbers from Ibex Peak EDS Spec Update rev 0.71, doc #386904 (Table 8-3). Pre-Silicon Mobile Estimates. IV ALL RIGHTS RESERVED 21 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AY7 OMIT H49 AB16 OMIT AK30
B11 U1800 H5 AA19 U1800 AK31
B15
IBEX_PEAK_M J24 AA20 IBEX_PEAK_M AK32
FCBGA FCBGA
B19 (9 OF 10) K11 AA22 AK34
(8 OF 10)
B23 K43 AM19 AK35
B31 K47 AA24 AK38
B35 K7 AA26 AK43
B39 L14 AA28 AK46
B43 L18 AA30 AK49
B47 L2 AA31 AK5
B7 L22 AA32 AK8
D BG12 L32 AB11 AL2 D

BB12 L36 AB15 AL52
BB16 L40 AB23 AM11
BB20 L52 AB30 BB44
BB24 M12 AB31 AD24
BB30 M16 AB32 AM20
BB34 M20 AB39 AM22
BB38 N38 AB43 AM24
BB42 M34 AB47 AM26
BB49 M38 AB5 AM28
BB5 M42 AB8 BA42
BC10 M46 AC2 AM30
BC14 M49 AC52 AM31
BC18 M5 AD11 AM32
BC2 M8 AD12 AM34
BC22 N24 AD16 AM35
BC32 P11 AD23 AM38
BC36 AD15 AD30 AM39
BC40 P22 AD31 AM42
BC44 P30 AD32 AU20
BC52 P32 AD34 AM46
BH9 P34 AU22 AV22
BD48 P42 AD42 AM49
BD49 P45 AD46 AM7
BD5 P47 AD49 AA50
BE12 R2 AD7 BB10
C BE16
BE20
R52
T12
AE2
AE4 VSS VSS
AN32
AN50
C
BE24 T41 AF12 AN52
BE30 T46 Y13 AP12
BE34 T49 AH49 AP42
BE38 T5 AU4 AP46
BE42 T8 AF35 AP49
BE46 U30 AP13 AP5
BE48 U31 AN34 AP8
BE50 U32 AF45 AR2
BE6 U34 AF46 AR52
BE8 P38 AF49 AT11
VSS VSS
BF3 V11 AF5 BA12
BF49 P16 AF8 AH48
BF51 V19 AG2 AT32
BG18 V20 AG52 AT36
BG24 V22 AH11 AT41
BG4 V30 AH15 AT47
BG50 V31 AH16 AT7
BH11 V32 AH24 AV12
BH15 V34 AH32 AV16
BH19 V35 AV18 AV20
BH23 V38 AH43 AV24
BH31 V43 AH47 AV30
BH35 V45 AH7 AV34
BH39 V46 AJ19 AV38
BH43 V47 AJ2 AV42
B BH47 V49 AJ20 AV46 B
BH7 V5 AJ22 AV49
C12 V7 AJ23 AV5
C50 V8 AJ26 AV8
D51 W2 AJ28 AW14
E12 W52 AJ32 AW18
E16 Y11 AJ34 AW2
E20 Y12 AT5 BF9
E24 Y15 AJ4 AW32
E30 Y19 AK12 AW36
E34 Y23 AM41 AW40
E38 Y28 AN19 AW52
E42 Y30 AK26 AY11
E46 Y31 AK22 AY43
E48 Y32 AK23 AY47
E6 Y38 AK28
E8 Y43
F49 Y46
F5 P49
G10 Y5
G14 Y6
G18 Y8
G2 P24
G22 T43
G32 AD51
G36 AT8
A G40 AD47 SYNC_MASTER=K17_REF SYNC_DATE=06/15/2009 A
G44 Y47 PAGE TITLE
G52 AT12 PCH Grounds

AF39 AM6 DRAWING NUMBER SIZE
H16 AT13
H20 AM5 REVISION
R
H30 AK45 <E4LABEL>
H34 AK39 NOTICE OF PROPRIETARY PROPERTY: BRANCH
H38 AV14 THE INFORMATION CONTAINED HEREIN IS THE
<BRANCH>
H42 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
23 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
85 83 73
PCH VCCRTC BYPASS PCH VCCPNAND BYPASS PCH VCCCORE BYPASS
57 35
20 19 18 17 7
72 71 6627 23
31
6
21
PP3V3_S5 (PCH RTC 3.3V PWR) (PCH NAND 1.8V/3.3V PWR) (PCH 1.05V CORE PWR)
99
72 66 7 6 PP5V_S5 PCH V5REF_SUS Filter & Follower
49 48 47 46 45 43 21 17 7 6 PP3V42_G3H 87 72 71 58 24 21 16 12 7 6 PP1V8_S0 21 20 18 17 15 13 12 10 7 6 PP1V05_S0
1 mA S0-S5 (PCH Reference for 5V Tolerance on USB) 73 66 65 64 53 86 73 70 40 26 25 24 23
2 4 2 mA S0-S5 /
R2400 2 D2400 6 uA G3 PLACE_NEAR=U1800.A12:2.54MM PLACE_NEAR=U1800.AK13:2.54MM 1 C2440 PLACE_NEAR=U1800.AB24:2.54MM
10 NC 0.1UF
5% BAT54DW-X-G C2420 1 1 C2421 1 C2422 C2470 1 1 C2471
NC
1/16W SOT-363 10%
MF-LF 3 1UF 0.1UF 0.1UF 2 16V 10UF 1UF
402 1 10% 10% 10% X5R 20% 10%
6.3V 2 16V
2 X5R 16V
2 X5R 402 6.3V 2 6.3V
2 CERM
CERM X5R
PP5V_S5_PCH_V5REFSUS 21 402 402 402 603 402
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.25MM 1 mA S0-S5
VOLTAGE=5V PLACE_NEAR=U1800.A12:2.54MM PLACE_NEAR=U1800.AB24:2.54MM
C2400 1 PLACE_NEAR=U1800.F24:2.54MM PLACE_NEAR=U1800.A12:2.54MM PCH VCCSUSHDA BYPASS
D 1UF
10%
10V 2
(PCH HD Audio 3.3V/1.5V PWR) D
X5R 69 68 63 62 58 54 52 51 50 48
PP3V3_S0 PCH VCCIO BYPASS
402 PCH VCCSUS3_3 BYPASS 25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26 (PCH CLK 1.05V PWR)
99
(PCH SUSPEND PCI 3.3V PWR) 99 88 87 85 84 83 80 73 72
88 87 85
72 71
27 23
66
21
PP3V3_S5 PLACE_NEAR=U1800.L30:2.54MM 1 C2445 21 20 18 17 15 13 12 10 7 6
86 73 70 40 26 25 24 23
PP1V05_S0
73 72 69
68 63 62
17 7
20 19
6
18 1UF
58 54 52 57 35 31 10%
2 6.3V
51 50 48 85 83 73
47 46 42
84 83
9940 37 34
8030 28 27
PP3V3_S0 PLACE_NEAR=U1800.P18:2.54MM 1 C2425 CERM
402 PLACE_NEAR=U1800.AF32:2.54MM 1 C2475 1 C2476 1 C2477
20 19
26 25
18 17 7 6
24 23 21 0.1UF
1UF 1UF 1UF
(VCCSUS3_3 Total)
54 52 47 42 7 6
88
PP5V_S0 PCH V5REF Filter & Follower 10%
86 72 70 69 68 2 16V
X5R
10% 10% 10%
1 mA (PCH Reference for 5V Tolerance on PCI) 402 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
1 402 402 402
R24012 5 D2400 PCH V_CPU_IO BYPASS
100 NC (PCH 1.1V/1.05V CPU I/O PWR)
5% BAT54DW-X-G PLACE_NEAR=U1800.AH23:2.54MM
NC
1/16W SOT-363 PLACE_NEAR=U1800.AH35:2.54MM

MF-LF 6 163 mA S0 / PCH USB/VCCSUS3_3 BYPASS 21 20 18 17 15 13 12 10 7 6 PP1V05_S0
402 1 86 73 70 40 26 25 24 23
65 mA S3-S5 (PCH SUSPEND USB 3.3V PWR)
PP5V_S0_PCH_V5REF 21 PLACE_NEAR=U1800.AT18:2.54MM PLACE_NEAR=U1800.AT18:2.54MM
MIN_LINE_WIDTH=0.3MM PP3V3_S5
MIN_NECK_WIDTH=0.25MM
VOLTAGE=5V
1 mA
31 27 23 21 20 19 18 17 7 6
99 85 83 73 72 71 66 57 35 C2450 1 1 C2451 1 C2452
C2401 1 PLACE_NEAR=U1800.K49:2.54MM 4.7UF 0.1UF 0.1UF PCH VCCIO BYPASS
PLACE_NEAR=U1800.U23:2.54MM 20% 10% 10%
1UF 6.3V 2 2 16V 2 16V (PCH USB 1.05V PWR)
10%
10V 2 PLACE_NEAR=U1800.A26:2.54MM 1 C2426 1 C2427 X5R
603
X5R
402
X5R
402
X5R 0.1UF 0.1UF 21 20 18 17 15 13 12 10 7 6 PP1V05_S0
402 10% 10% 86 73 70 40 26 25 24 23
2 16V
X5R 2 16V
X5R PLACE_NEAR=U1800.AT18:2.54MM
402 402 PLACE_NEAR=U1800.V24:2.54MM 1 C2480
1UF
10%
PCH VCCIO BYPASS 2 6.3V
CERM
(PCH DMI 1.05V PWR) 402
PCH VCCME3_3 BYPASS PP1V05_S0
21 20 18 17 15 13 12 10 7 6
(PCH ME 3.3V PWR) 86 73 70 40 26 25 24 23
C 69 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
PP3V3_S0 PLACE_NEAR=U1800.AT16:2.54MM 1 C2455 PCH VCCIO BYPASS
(PCH SATA 1.05V PWR)
C
99 88 87 85 84 83 80 73 72 1UF
10%
PLACE_NEAR=U1800.AM8:2.54MM 1 C2430 2 6.3V
CERM 21 20 18 17 15 13 12 10 7 6
86 73 70 40 26 25 24 23
PP1V05_S0
0.1UF 402
10%
2 16V
X5R PLACE_NEAR=U1800.AB19:2.54MM 1 C2485
402 1UF
10%
PCH VCCLAN BYPASS 2 6.3V
CERM
(PCH 1.05V LAN Core PWR) 402
PCH CORE/VCC3_3 BYPASS GND
(PCH MISC 3.3V PWR)
NO STUFF
PCH VCCIO BYPASS
69 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
PP3V3_S0 PLACE_NEAR=U1800.AF23:2.54MM 1 C2460 (PCH PCIE 1.05V PWR)
99 88 87 85 84 83 80 73 72 1UF
10%
PLACE_NEAR=U1800.V15:2.54MM 1 C2435 2 6.3V
CERM 21 20 18 17 15 13 12 10 7 6
86 73 70 40 26 25 24 23
PP1V05_S0
0.1UF 402
10%
2 16V
X5R PLACE_NEAR=U1800.AN20:2.54MM
402 C2490 1 1 C2491 1 C2492 1 C2493 1 C2494
PCH VCCME BYPASS 10UF 1UF 1UF 1UF 1UF
20% 10% 10% 10% 10%
(PCH 1.05V ME Core PWR) 6.3V 2 2 6.3V 2 6.3V 2 6.3V 2 6.3V
X5R CERM CERM CERM CERM
PCH VCCAPLLEXP Filter PCH VCC3_3 BYPASS 603 402 402 402 402
21 20 18 17 15 13 12 10 7 6 PP1V05_S0
(PCH PCIe PLL PWR) 99 (PCH PCI 3.3V PWR) 86 73 70 40 26 25 24 23
88 87 85 84 83 80 73 72 69
68 63 62 58 54 52 51 50 48
PLACE_NEAR=U1800.AN20:2.54MM PLACE_NEAR=U1800.AN20:2.54MM
PLACE_NEAR=U1800.AN20:2.54MM
21 PP1V05_S0_PCH_VCCAPLL_EXP 47 46 42 40 37 34 30 28 27 26
25 24 23 21 20 19 18 17 7 6 PP3V3_S0 PLACE_NEAR=U1800.AD38:2.54MM PLACE_NEAR=U1800.V39:2.54MM PLACE_NEAR=U1800.AN20:2.54MM
VOLTAGE=1.05V
OMIT WF: C2311 not in DG or CRB C2465 1 C2466 1 C2467 1 1 C2468 1 C2469
PLACE_NEAR=U1800.BJ24:2.54MM 1 C2413 PLACE_NEAR=U1800.J38:2.54MM 1 C2436 22UF 22UF 22UF 1UF 1UF
20% 20% 20% 10% 10%
1UF 0.1UF 6.3V
X5R-CERM 2
6.3V
X5R-CERM 2
6.3V
X5R-CERM 2 2 6.3V 2 6.3V
10% 10% CERM CERM
2 6.3V
CERM 2 16V
X5R
603 603 603 402 402
B 402 402
PLACE_NEAR=U1800.AD38:2.54MM
B
PLACE_NEAR=U1800.V39:2.54MM
PLACE_NEAR=U1800.AD38:2.54MM
PCH VCCFDIPLL Filter PCH VCC3_3 BYPASS
(PCH FDI PLL PWR) 99
88 87 85 84 83 80 73 72 69
(PCH SATA 3.3V PWR)
68 63 62 58 54 52 51 50 48
21 PP1V05_S0_PCH_VCCAPLL_FDI 47 46 42 40 37 34 30 28 27 26
25 24 23 21 20 19 18 17 7 6 PP3V3_S0
MIN_NECK_WIDTH=0.25MM OMIT WF: C2413 not in DG or CRB
VOLTAGE=1.05V
PLACE_NEAR=U1800.BJ18:2.54MM 1 C2415 PLACE_NEAR=U1800.AD13:2.54MM 1 C2437
1UF 0.1UF
10% 10%
2 6.3V
CERM 2 16V
X5R
402 402
PCH VCCSATAPLL Filter PCH VCC3_3 BYPASS

(PCH SATA PLL PWR) (PCH PCIe/DMI 3.3V PWR)
85 84 83 80 73 72 69 68 63
21 PP1V05_S0_PCH_VCCAPLL_SATA BB: C2417 removed from DG 42 40 37
18 17 7
34
6 PP3V3_S0
MIN_LINE_WIDTH=0.5MM 30 28 27 26 25 24 23 21 20
62 58 54 52 51 50 48 47
19
46
MIN_NECK_WIDTH=0.25MM NO STUFF 99 88 87
VOLTAGE=1.05V
PLACE_NEAR=U1800.AK1:2.54MM 1 C2417 PLACE_NEAR=U1800.AN35:2.54MM 1 C2438
1UF 0.1UF
10% 10%
2 6.3V
CERM 2 16V
X5R
402 402
PCH VCCACLK Filter PCH VCC3_3 BYPASS

(PCH Misc PLL PWR) (PCH CLK/HVCMOS 3.3V PWR)
A 21 PP1V05_S0_PCH_VCCA_CLK
85 84 83 80 73 72 69 68
BB: C2419 removed from DG 42 40 37
18 17 7
63
34
6 PP3V3_S0 SYNC_MASTER=K17_REF SYNC_DATE=06/15/2009 A
MIN_LINE_WIDTH=0.5MM 30 28 27 26 25 24 23 21 20 19 PAGE TITLE
VOLTAGE=1.05V
PLACE_NEAR=U1800.AP51:2.54MM 1
NO STUFF
C2419
62 58 54 52 51 50 48 47
99 88
46
87
PLACE_NEAR=U1800.AB34:2.54MM 1 C2439 PCH Non-GFX Decoupling

1UF 0.1UF DRAWING NUMBER SIZE
10%
2 6.3V
10%
2 16V Apple Inc. <SCH_NUM> D
CERM X5R REVISION
402 402 R
<E4LABEL>
<BRANCH>
24 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
GFX (CPU VCCAXG) DECOUPLING
3x 330uF 6 mOhm (2 stuffed), 3x 22uF 0603, 16x 1uF 0402
69 49 13 7 6 PPVCORE_S0_GFX
Place on bottom side of U1000.
1 C2500 1 C2501 1 C2502 1

C2505 1
C2506
22UF 22UF 22UF 330UF 330UF
20% 20% 20% 20% 20%
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 3 2 2.0V
POLY-TANT
3 2 2.0V
POLY-TANT
D
603 603 603 D2T-SM2 D2T-SM2
D
1 C2524 1 C2525 1 C2526 1 C2527 1 C2528 1 C2529 1 C2530 1 C2531 1 C2532 1 C2533 1 C2534 1 C2535 1 C2536 1 C2537 1 C2538 1 C2539
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R
402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402

5x 1uF 0402
13 7 PPVCORE_S0_CPU_VCAP2
1 C2510 1 C2511 1 C2512 1 C2513 1 C2514

1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10%
2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R
402 402 402 402 402
C C
Design recommendations from Calpella Small Form Factor Design Guide Rev 1.5 (doc #407364) table 2-34 and Calpella Small Form F actor Schematic Check List Rev 1.1 (doc #395914) table 3.26.
PLACE_NEAR=U1800.AE50:2.54MM PCH VCCADAC Filter

(PCH DAC PLL PWR)
L2550
69 68 63 62 58 54 52 51 50 48
26 25 23 21 20 19 18 17 7 6 PP3V3_S0 R2550 180-OHM-1.5A PP3V3_S0_PCH_VCCA_DAC 21
47 46 42 40 37 34 30 28 27 0 1 2 MIN_LINE_WIDTH=0.4 MM
99 88 87 85 84 83 80 73 72
69 mA 1 2 PP3V3_S0_PCH_VCCA_DAC_F MIN_NECK_WIDTH=0.2 MM 69 mA
MIN_LINE_WIDTH=0.5MM 0603 VOLTAGE=3.3V
5%
1/16W
69 mA
VOLTAGE=3.3V
MF-LF
402
C2550 1 1 C2551 1 C2552 PLACE_NEAR=U1800.AE50:2.54MM
10UF 0.1UF 0.01UF
20% 10% 20%
6.3V 2 2 16V 2 16V
X5R X5R CERM
603 402 402
PLACE_NEAR=U1800.AE50:2.54MM
PLACE_NEAR=U1800.AE50:2.54MM
PCH VCCADPLLA Filter

(PCH DPLLA PWR)
L2560
21 20 18 17 15 13 12 10 7 6 PP1V05_S0 R2560 10UH-0.12A-0.36OHM PP1V05_S0_PCH_VCCADPLLA 21
86 73 70 40 26 25 23 0 PP1V05_S0_PCH_VCCADPLLA_F 1 2 MIN_LINE_WIDTH=0.4 MM
137 mA 1 2 MIN_NECK_WIDTH=0.2 MM 68 mA
5%
1/16W
68 mA
MIN_NECK_WIDTH=0.25MM NO STUFF
VOLTAGE=1.05V
MF-LF
402 C2560 1 1 C2561 PLACE_NEAR=U1800.BB51:2.54MM
220UF 1UF
20% 10%
2.5V 2 2 6.3V
CERM
B POLY-TANT
CASE-B2-SM1 402 B
PLACE_NEAR=U1800.BB51:2.54MM
PCH VCCADPLLB Filter

(PCH DPLLB PWR)
L2565
R2565 10UH-0.12A-0.36OHM PP1V05_S0_PCH_VCCADPLLB 21
0 MIN_LINE_WIDTH=0.4 MM
1 2 PP1V05_S0_PCH_VCCADPLLB_F 1 2 MIN_NECK_WIDTH=0.2 MM 69 mA
5%
1/16W
69 mA
MIN_NECK_WIDTH=0.25MM NO STUFF
VOLTAGE=1.05V
MF-LF
402 C2565 1 1 C2566 PLACE_NEAR=U1800.BD51:2.54MM
220UF 1UF
20% 10%
2.5V 2 2 6.3V
CERM
POLY-TANT
CASE-B2-SM1 402
PLACE_NEAR=U1800.BD51:2.54MM
PLACE_NEAR=U1800.AP43:2.54MM PCH VCCTX_LVDS Filter

L2570 (PCH LVDS TX PWR)
87 72 71 58 23 21 16 12 7 6 PP1V8_S0 0.1UH PP1V8_S0_PCH_VCCTX_LVDS 21
1 2 MIN_LINE_WIDTH=0.4 MM
59 mA MIN_NECK_WIDTH=0.2 MM 59 mA
0805
VOLTAGE=1.8V
C2570 1 1 C2571 1 C2572 PLACE_NEAR=U1800.AP43:2.54MM

22UF 0.01UF 0.01UF
20% 20% 20%
6.3V 16V 16V
A X5R-CERM 2
603
2 CERM
402
2 CERM
402 SYNC_MASTER=K17_REF SYNC_DATE=06/15/2009 A
PLACE_NEAR=U1800.AP43:2.54MM PAGE TITLE
PLACE_NEAR=U1800.AP43:2.54MM
CPU/PCH GFX Decoupling
DRAWING NUMBER SIZE

REVISION
R
Design recommendations from Calpella Design Guide Rev 1.5 (doc #398905) Section 3.25.3 tables 161 and 162. <E4LABEL>
<BRANCH>
25 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Calpella Processor mini XDP

21 20 18 17 15 13 12 10 7 6 PP1V05_S0
86 73 70 40 26 24 23
XDP_CPU_BPM CRITICAL XDP

RP2600 OMIT 1
R2615
91 10 IN XDP_BPM_L<0> 1 8
J2600 51
5%
91 10 IN XDP_BPM_L<1> 2 0 7 LTH-030-01-G-D-NOPEGS 1/16W
5% F-ST-SM MF-LF
91 10 IN XDP_BPM_L<2> 3 1/16W 6
2 402
SM-LF
D 91 10 IN XDP_BPM_L<3> 4 5
91 10 BI XDP_PREQ_L OBSFN_A0
2
4
1
3 OBSFN_C0 CPU_CFG<8> IN 9 91
D
XDP_CPU_CFG 91 10 IN XDP_PRDY_L OBSFN_A1 6 5 OBSFN_C1 CPU_CFG<9> IN 9 91
RP2601 8 7
91 9 IN CPU_CFG<12> 4 5 XDP_OBSDATA_A<0> OBSDATA_A0 10 9 OBSDATA_C0 CPU_CFG<0> IN 9 91
91 9 IN CPU_CFG<13> 3 0 6 XDP_OBSDATA_A<1> OBSDATA_A1 12 11 OBSDATA_C1 CPU_CFG<1> IN 9 91

5%
91 9 IN CPU_CFG<14> 2 1/16W 7 14 13
SM-LF
91 9 IN CPU_CFG<15> 1 8 XDP_OBSDATA_A<2> OBSDATA_A2 16 15 OBSDATA_C2 CPU_CFG<2> IN 9 91
XDP_OBSDATA_A<3> OBSDATA_A3 18 17 OBSDATA_C3 CPU_CFG<3> IN 8 9 91

PLACEMENT_NOTE=Place R2501 close to R2500 to minimize stubs. 20 19
91 9 IN CPU_CFG<17> OBSFN_B0 22 21 OBSFN_D0 CPU_CFG<10> IN 9 91
91 9 IN CPU_CFG<16> OBSFN_B1 24 23 OBSFN_D1 CPU_CFG<11> IN 9 91

26 25
91 10 IN XDP_BPM_L<4> OBSDATA_B0 28 27 OBSDATA_D0 CPU_CFG<4> IN 9 91

32 31

XDP XDP_BPM_L<7> 36 35 CPU_CFG<7>
91 10 IN OBSDATA_B3 OBSDATA_D3 IN 9 91
R2610 38 37
1K
91 20 10 IN CPU_PWRGD 1 2 XDP_PWRGD PWRGD/HOOK0 40 39 ITPCLK/HOOK4 FSB_CLK133M_ITP_P IN 10 91
PM_PWRBTN_L 42 41 FSB_CLK133M_ITP_N XDP
5% 45 25 18 OUT HOOK1 ITPCLK#/HOOK5 IN 10 91
1/16W
MF-LF VCC_OBS_AB 44 43 VCC_OBS_CD R2611
402
XDP_CPUPWRGD 46 45 91 XDP_CPURST_L
1K FSB_CPURST_L
91 10 IN HOOK2 RESET#/HOOK6 1 2
IN 10 91
TP_XDP_HOOK3 HOOK3 48 47 DBR#/HOOK7 XDP_DBRESET_L OUT 10 25 27 91 5% PLACE_NEAR=U1000.N70:1.00MM
1/16W
50 49 NOTE: XDP_DBRESET_L must be pulled-up to 3.3V. MF-LF
402
63 48 47 42 32 30 28 26 25 17 BI SMBUS_PCH_DATA SDA 52 51 TDO XDP_TDO 25 91
94 88
63 48 47 42 32 30 28 26 25 17 BI SMBUS_PCH_CLK SCL 54 53 TRSTn XDP_TRST_L OUT 10 91
C 94 88
91 10 XDP_TCK
TCK1
TCK0
NC
56
58
55
57
TDI
TMS
XDP_TDI
XDP_TMS
25 91 C
OUT OUT 10 91
60 59 XDP_PRESENT#
XDP_NORMAL&XDP_CPU XDP XDP
R2690 C2600 1
516S0852
1 C2601
0.1uF 0.1uF
TABLE_5_HEAD
0 PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

10 OUT JTAG_CPU_TDI 1 2 XDP_TDI 25 91
10%
16V 2
10%
X5R 2 16V
X5R
TABLE_5_ITEM
XDP_CPU 5%
1/16W 402 402 516S0852 1 CONN,PLUG,B2B,60P,0.5MM,NOPEG J2600 CRITICAL XDP_CONN_CPU
R2695 MF-LF
402
JTAG_CPU_TDO 1
0 2 XDP_TDO
10 IN 25 91
XDP_NORMAL 5%
1/16W
1
R2691 MF-LF
402
0
5%
1/16W
MF-LF
402 2
XDP_GMCH
R2696
Calpella PCH mini XDP
JTAG_GMCH_TDI 1
0 2
10 OUT 72 69 68 63 62 58 54 52 51 50
26 24 23 21 20 19 18 17 7 6 PP3V3_S0
XDP_NORMAL&XDP_GMCH 5%
1/16W
48 47 46 42 40 37 34 30 28 27
99 88 87 85 84 83 80 73
R2692 MF-LF
402 CRITICAL
JTAG_GMCH_TDO 0
10 IN
1 2 XDP_CONN_PCH
5%
1/16W J2650
MF-LF
402
DF40C-60DS-0.4V
F-ST-SM-HF
1 2
TP_XDPPCH_OBSFN_A<0> OBSFN_A0 3 4 OBSFN_C0 ISOLATE_CPU_MEM_L IN 20 31 PCH GPIO28
TP_XDPPCH_OBSFN_A<1> OBSFN_A1 5 6 OBSFN_C1 SMC_IG_THROTTLE_L IN 20 45 46 PCH GPIO0
B PCH OC0# 19 IN PCH_GPIO59 OBSDATA_A0
7
9
8
10 OBSDATA_C0 FW_CLKREQ_L IN 17 40 PCH GPIO20
B
PCH OC1# 35 19 IN USB_HUB_SOFT_RESET_L OBSDATA_A1 11 12 OBSDATA_C1 AP_CLKREQ_L IN 17 33 PCH GPIO18
13 14
PCH OC2# 19 IN PCH_GPIO41 OBSDATA_A2 15 16 OBSDATA_C2 SATARDRVR_A_EN IN 17 42 PCH GPIO21

PCH OC3# 19 IN PCH_GPIO42 OBSDATA_A3 17 18 OBSDATA_C3 SATARDRVR_B_EN IN 17 PCH GPIO19
19 20
TP_XDPPCH_OBSFN_B<0> OBSFN_B0 21 22 OBSFN_D0 TP_XDPPCH_OBSFN_D<0>
TP_XDPPCH_OBSFN_B<1> OBSFN_B1 23 24 OBSFN_D1 TP_XDPPCH_OBSFN_D<1>
25 26
PCH OC4# 19 IN PCH_GPIO43 OBSDATA_B0 27 28 OBSDATA_D0 SDCARD_RESET IN 20 34 PCH GPIO36

PCH OC5# 19 IN PCH_GPIO9 OBSDATA_B1 29 30 OBSDATA_D1 JTAG_GMUX_TCK IN 20 87 PCH GPIO37
31 32
PCH OC6# 46 19 IN PCH_GPIO10 OBSDATA_B2 33 34 OBSDATA_D2 AUD_IPHS_SWITCH_EN IN 20 63 PCH GPIO16

PCH OC7# 19 IN PM_LATRIGGER_L OBSDATA_B3 35 36 OBSDATA_D3 ME_TEMP_ALERT_L IN 20 PCH GPIO49
37 38
87 73 45 27 IN ALL_SYS_PWRGD PWRGD/HOOK0 39 40 ITPCLK/HOOK4 TP_XDPPCH_HOOK4

45 25 18 PM_PWRBTN_L HOOK1 41 42 ITPCLK#/HOOK5 TP_XDPPCH_HOOK5
VCC_OBS_AB 43 44 VCC_OBS_CD
TP_XDPPCH_HOOK2 HOOK2 45 46 RESET#/HOOK6 XDPPCH_PLTRST_L IN 27 1K series R on PCH Support Page
TP_XDPPCH_HOOK3 HOOK3 47 48 DBR#/HOOK7 XDP_DBRESET_L 10 25 27 91
49 50 NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.
63 48 47 42 32 30 28 26 25 17 SMBUS_PCH_DATA SDA 51 52 TDO JTAG_PCH_TDO IN 17
94 88
63 48 47 42 32 30 28 26 25 17
94 88
SMBUS_PCH_CLK SCL 53 54 TRSTn TP_XDPPCH_TRST_L
TCK1 NC
55 56 TDI JTAG_PCH_TDI OUT 17
17 OUT JTAG_PCH_TCK TCK0 57 58 TMS JTAG_PCH_TMS OUT 17
A 59 60 XDP_PRESENT#
PAGE TITLE
518S0774 eXtended Debug Port (XDP)

DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
26 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
L2700 PLACE_NEAR=L2700.2:2 mm:NO_VIA

PLACE_NEAR=U2700.1:2 mm PLACE_NEAR=U2700.24:2 mm
72 69 68 63 62 58 54 52 51 50
25 24 23 21 20 19 18 17 7 6 PP3V3_S0 FERR-120-OHM-1.5A PLACE_NEAR=U2700.5:2 mm PLACE_NEAR=U2700.29:2 mm
48 47 46 42 40 37 34 30 28 27
1 2 PLACE_NEAR=U2700.17:2 mm
99 88 87 85 84 83 80 73 PP3V3_S0_CK505_F
0402 MIN_LINE_WIDTH=0.3 mm
VOLTAGE=3.3V
C2700 1 1 C2705 1 C2706 1 C2707 1 C2708 1 C2709
10UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 10% 10% 10% 10% 10%
6.3V 16V 16V 16V 16V 16V
X5R 2 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
603 402 402 402 402 402
L2710 PLACE_NEAR=L2710.2:2 mm:NO_VIA

PP1V05_S0 FERR-120-OHM-1.5A
C 21 20 18 17 15 13 12 10 7 6
86 73 70 40 25 24 23
1 2 PP1V05_S0_CK505_F
MIN_LINE_WIDTH=0.3 mm
PLACE_NEAR=U2700.15:2 mm
PLACE_NEAR=U2700.18:2 mm C
0402 MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
C2710 1 1 C2715 1 C2716
10UF 0.1UF 0.1UF
20% 10% 10%
6.3V 2 2 16V 2 16V
X5R X5R X5R
603 402 402
CRITICAL
Y2730
18
15
29
24
17
14.31818 NOTE: REF/FS pin is input until first CK_PWRGD rising edge.
1
PLACE_NEAR=Y2730.1:2 mm:NO_VIA 1 2 PLACE_NEAR=Y2730.2:2 mm:NO_VIA
FS=0 => 133MHz BCLKs, FS=1 => 100MHz BCLKs
VDD_CPU_IO
VDD_SRC_IO
VDD_27
VDD_DOT
VDD_REF
VDD_CPU
VDD_SRC
5X3.2-SM All other output frequencies are fixed.
C2730 1 1 C2731
18pF 18pF (IPD)
5%
50V
5%
50V REF_FS 30 PCH_CLK14P3M_REFCLK OUT 17 93 PCH REFCLK 14.31818MHz
CERM 2 2 CERM
402 402 CRITICAL USB 8 TP_CK505_USB Unused 48MHz
U2700 CPU0* 22 FSB_CLK133M_PCH_N OUT 17 93
R2790 1
CK505_CLK14P3M_XIN 28 XIN
SL28776
QFN CPU0 23 FSB_CLK133M_PCH_P 17 93 PCH BCLK 133MHz
OUT
10K CK505_CLK14P3M_XOUT
5% 27 XOUT
1/16W BYPASS=U2790::5 mm CPU1* 19 TP_CK505_CPU1N
MF-LF
402 2 C2790 1 88 63 48 47 42 32 30 28 25 17
94
IN SMBUS_PCH_CLK 32 SCLK CPU1 20 TP_CK505_CPU1P Unused BCLK 133MHz
0.1UF
20% 5 74HC1G00GWDG SMBUS_PCH_DATA 31 SDATA SRC1* 14 PCIE_CLK100M_PCH_N
10V 1 88 63 48 47 42 32 30 28 25 17 BI OUT 17 93
CERM 2 SC70-5 94
SRC1 13 PCIE_CLK100M_PCH_P 17 93 PCH DMI/PCIe 100MHz
402 4 CK505_CKPWRGD OUT
25
CPUIMVP_CLK_EN_L 2
U2790 CK_PWRGD/PWRDWN*
PCH_CLK100M_SATA_N
68 IN SRC0*/SATA* 11 OUT 17 93
73 IN CK505_27MHZ_EN_L 16 27MHZ_OE*
SRC0/SATA 10 PCH_CLK100M_SATA_P 17 93 PCH SATA 100MHz
B 3
No internal pull.
27M_NSS 6 CK505_CLK27M
OUT
27
B
Must be strapped appropriately
TP_CK505_CLK27M_SS GPU 27MHz Clocks (Single-Ended)
or connected to logic for 27M_SS 7
Muxed Graphics implementations. PCH_CLK96M_DOT_N
DOT96* 4 OUT 17 93
VSS_DOT
VSS_REF
VSS_CPU
VSS_SRC
DOT96 3 PCH_CLK96M_DOT_P PCH USB Clock 96MHz
VSS_27
OUT 17 93
THRM
PAD
21
12
26
33
A SYNC_MASTER=K17_MLB SYNC_DATE=06/23/2009 A
PAGE TITLE
Clock (CK505)
DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
27 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Platform Reset Connections

PCH RTC Crystal Unbuffered
R2881 LPCPLUS_RESET_L OUT 6 27 47 87 94
R2810 C2810 33
12pF 40 31 27 19 IN PLT_RESET_L 1 2 LPCPLUS_RESET_L OUT 6 27 47 87 94
PCH_CLK32K_RTCX2 1
0 2 PCH_CLK32K_RTCX2_R 1 2 MAKE_BASE=TRUE MAKE_BASE=TRUE
17 IN 5%
1/16W
5% MF-LF
1/16W 5% 402 R2883
R28111 MF-LF CRITICAL 50V 33
CERM SMC_LRESET_L
D
3
402 1 2
D 10M 402 OUT 45
2 4
5% Y2810 NC 5%
1/16W 32.768K NC 1/16W
MF-LF
MF-LF SM-2 C2811 R2882 402
1
402 2
12pF 0
1 2
1 2 ENET_RESET_L OUT 37 95
17 OUT PCH_CLK32K_RTCX1
5%
5% 1/16W
MF-LF
50V
CERM 402 R2888
402 0
1 2 AP_RESET_L OUT 33
PCH 25MHz Crystal R2871

0
5%
1/16W
MF-LF
402
1 2 PCA9557D_RESET_L OUT 32
C2815 5%
1/16W
XDP
R2815 12pF MF-LF
R2889
PCH_CLK25M_XTALOUT 0 PCH_CLK25M_XTALOUT_R 1 2 402
17 IN 1 2
1
1K 2 XDPPCH_PLTRST_L OUT 25
DCI 5%
1/16W 5% 5%
1 CRITICAL 50V
R2816 MF-LF
CERM 1/16W
3
402 402 R2887 MF-LF
10M
2 4
Y2815 NC 402
5% 1
0 2 GMUX_RESET_L
1/16W 25.0000M NC 27 87
MF-LF SM-3.2X2.5MM C2816 5%
MAKE_BASE=TRUE
1
402 2
12pF 1/16W GMUX_RESET_L OUT 27 87
1 2 MF-LF
17 OUT PCH_CLK25M_XTALIN 402
5%
R2893
50V 1
0 2 BKLT_PLT_RST_L OUT 89
CERM
402 5%
1/16W
Caesar II (ENET) 25MHz Crystal MF-LF

402
PLT_RESET_L OUT 19 27 31 40
C C2820 69 68 63 62 58 54 52 51 50 48
PP3V3_S0
Series R is R4283 C
R2820 27pF
25 24 23 21 20 19 18 17 7 6
95 37 IN BCM5764_CLK25M_XTALO 1
200 2 BCM5764_CLK25M_XTALO_R 1 2
47 46 42 40 37 34 30 28 27 26
99 88 87 85 84 83 80 73 72
Buffered
NO STUFF 5%
1/16W 5%
1 CRITICAL 50V 5 MC74VHC1G08
R2821 MF-LF CERM R2884
3
402 1 SC70-HF
10M 402 0
2 4
5% Y2820 NC
U2880 4 27 10 PLT_RST_BUF_L 1 2 SDCARD_PLT_RST_L OUT 34
1/16W 25.0000M NC 2 MAKE_BASE=TRUE
5%
MF-LF SM-3.2X2.5MM C2821 1/16W
1
402 2 1
27pF 3 R2880 MF-LF
402
95 37 OUT BCM5764_CLK25M_XTALI 1 2 C2880 1 5%
100K
PLT_RST_BUF_L
0.1UF 1/16W OUT 10 27
5% 20% MF-LF
50V 10V VTT voltage divider on CPU page
CERM CERM 2 2 402
402 402
Ethernet WAKE# Isolation

PP3V3_ENET 6 7 37 73
1
R2830 R2825
Q2830 PLACE_NEAR=U1800.N52 22
1 10K 94 19 IN LPC_CLK33M_SMC_R 1 2 LPC_CLK33M_SMC OUT 45 94
SSM3K15FV 5%
1/16W 5%
G
SOD-VESM-HF MF-LF 1/16W

B 2 402
MF-LF
402
PLACE_NEAR=U1800.P53
R2826
22
B
D
33 18 6 OUT PCIE_WAKE_L 37 27 ENET_WAKE_L ENET_WAKE_L IN 27 37 19 IN LPC_CLK33M_LPCPLUS_R 1 2 LPC_CLK33M_LPCPLUS OUT 6 47 94

3 2 MAKE_BASE=TRUE
5%
1/16W
R2827 MF-LF
PLACE_NEAR=U1800.P46 402
LPC_CLK33M_GMUX_R 27 19 LPC_CLK33M_GMUX_R 1
22 2 LPC_CLK33M_GMUX
27 19 IN OUT 87
MAKE_BASE=TRUE
5%
1/16W
MF-LF R2829
402
PLACE_NEAR=U1800.P48 22
19 IN PCH_CLK33M_PCIOUT 1 2 PCH_CLK33M_PCIIN OUT 17 93
5%
1/16W
R2824 MF-LF
PLACE_NEAR=U2700.6 402
0
27 26 IN CK505_CLK27M 27 26 CK505_CLK27M 1 2 GPU_CLK27M OUT 79 80 98
5%
1/16W
MF-LF
PCH S0 PWRGD 402
99 85 83 73 72 71 66
35 31 23 21 20 19 18 17 7
57
6 PP3V3_S5 PCH Reset Button
69 68 63 62 58 54 52 51 50
25 24 23 21 20 19 18 17 7
48
6 PP3V3_S0
47 46 42 40 37 34 30 28 27
99 88 87 85 84 83 80 73
26
72
69 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6 PP3V3_S0
47 46 42 40 37 34 30 28 27 26
99 88 87 85 84 83 80 73 72
R28501 1 C2850 1
10K 0.1UF
20%
R2895
5% 10K
1/16W 2 10V
CERM 5%
MF-LF 402 XDP 1/16W
402 2 MF-LF
R2896 2 402
0
A 5 MC74VHC1G08
91 25 10 IN XDP_DBRESET_L 1
5%
2 PM_SYSRST_L BI 6 18 45
87 73 45 25 IN ALL_SYS_PWRGD 1 SC70-HF 1/16W PAGE TITLE
R2851
0 U2850 4 PM_PCH_PWRGD OUT 18
MF-LF
402
OMIT
Chipset Support
68 IN CPUIMVP_PGOOD 1 2 CPUIMVP_PGOOD_R 2
1 DRAWING NUMBER SIZE
5% R2897 <SCH_NUM> D
1/16W
MF-LF
3 0
5%
Apple Inc. REVISION
402 1/16W R
MF-LF <E4LABEL>
2 402 NOTICE OF PROPRIETARY PROPERTY: BRANCH
SILK_PART=SYS RESET THE INFORMATION CONTAINED HEREIN IS THE
<BRANCH>
28 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
72 67 31 30 7 6 PP1V5_S3
DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)
Power aliases required by this page:
- =PP1V5_S0_MEM_A
- =PP1V5_S3_MEM_A
1 C2910 1 C2911 1 C2912 1 C2913 1 C2914 1 C2915 1 C2916 1 C2917 1 C2918 1 C2919 1 C2920 1 C2921 1 C2922 1 C2923
- =PP0V75_S0_MEM_VTT_A
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
- =PPSPD_S0_MEM_A (2.5 - 3.3V) 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
402 402 402 402 402 402 402 402 402 402 402 402 402 402
Signal aliases required by this page: 1 C2900 1 C2901
- =I2C_SODIMMA_SCL
10UF 10UF
- =I2C_SODIMMA_SDA 20% 20%
2 6.3V
X5R 2 6.3V
X5R
D BOM options provided by this page:
(NONE)
603 603
32 PP0V75_S3_MEM_VREFDQ_A D
1
C2930 1
C2931
2.2UF 0.1UF
20% 20%
6.3V 10V
2 CERM 2 CERM
402-LF 402
1 VREFDQ VSS 2
3 VSS DQ4 4 =MEM_A_DQ<4> 29
KEY
BI
92 11 MEM_A_CKE<0> 73 CKE0 CKE1 74 MEM_A_CKE<1> 11 92 29 =MEM_A_DQ<0> 5 DQ0 DQ5 6 =MEM_A_DQ<5> 29
IN IN BI BI
75 76 =MEM_A_DQ<1> 7 CRITICAL 8
VDD VDD 29 BI DQ1 VSS
77 78 9 10
MEM_A_BA<2>
NC
79
NC J2900 A15
80
MEM_A_A<15>
MEM_A_A<14>
IN 11 92
MEM_A_DM<0> 11
VSS
J2900
DQS0*
12
MEM_A_DQS_N<0>
MEM_A_DQS_P<0>
BI 11 29 92
92 11 IN BA2 F-RT-THB A14 IN 11 92 92 29 11 IN DM0 DQS0 BI 11 29 92

81 82 13 F-RT-THB 14
(SYMBOL 2 OF 2)
DDR3-SODIMM-DUAL-K6
VDD VDD VSS VSS
DDR3-SODIMM-DUAL-K6
(SYMBOL 1 OF 2)
92 11 MEM_A_A<12> 83 A12/BC* A11 84 MEM_A_A<11> 11 92 29 =MEM_A_DQ<2> 15 DQ2 DQ6 16 =MEM_A_DQ<6> 29
IN IN BI BI
92 11 MEM_A_A<9> 85 A9 A7 86 MEM_A_A<7> 11 92 29 =MEM_A_DQ<3> 17 DQ3 DQ7 18 =MEM_A_DQ<7> 29
IN IN BI BI
87 VDD VDD 88 19 VSS VSS 20
IN IN BI BI
IN IN BI BI
92 11 MEM_A_A<3> 95 A3 A2 96 MEM_A_A<2> 11 92 29 =MEM_A_DQS_N<1> 27 DQS1* DM1 28 =MEM_A_DM<1> 29
IN IN BI IN
92 11 MEM_A_A<1> 97 A1 A0 98 MEM_A_A<0> 11 92 29 =MEM_A_DQS_P<1> 29 DQS1 RESET* 30 MEM_RESET_L 30 31
IN IN BI IN
92 11 MEM_A_CLK_P<0> 101 CK0 CK1 102 MEM_A_CLK_P<1> 11 92 29 =MEM_A_DQ<10> 33 DQ10 DQ14 34 =MEM_A_DQ<14> 29
IN IN BI BI
92 11 MEM_A_CLK_N<0> 103 CK0* CK1* 104 MEM_A_CLK_N<1> 11 92 29 =MEM_A_DQ<11> 35 DQ11 DQ15 36 =MEM_A_DQ<15> 29
IN IN BI BI
C 92 11 MEM_A_A<10>
105
107
VDD
A10/AP
VDD
BA1
106
108 MEM_A_BA<1> 11 92 29 =MEM_A_DQ<16>
37
39
VSS
DQ16
VSS
DQ20
38
40 =MEM_A_DQ<20> 29
C
IN IN BI BI
92 11 MEM_A_BA<0> 109 BA0 RAS* 110 MEM_A_RAS_L 11 92 29 =MEM_A_DQ<17> 41 DQ17 DQ21 42 =MEM_A_DQ<21> 29
IN IN BI BI
92 11 MEM_A_WE_L 113 WE* S0* 114 MEM_A_CS_L<0> 11 92 29 =MEM_A_DQS_N<2> 45 DQS2* DM2 46 =MEM_A_DM<2> 29
IN IN BI IN
92 11 MEM_A_CAS_L 115 CAS* ODT0 116 MEM_A_ODT<0> 11 92 29 =MEM_A_DQS_P<2> 47 DQS2 VSS 48
IN IN BI
117 VDD VDD 118 49 VSS DQ22 50 =MEM_A_DQ<22> 29
BI
92 11 MEM_A_A<13> 119 A13 ODT1 120 MEM_A_ODT<1> 11 92 29 =MEM_A_DQ<18> 51 DQ18 DQ23 52 =MEM_A_DQ<23> 29
IN IN BI BI
MEM_A_CS_L<1> 121 S1* NC 122 =MEM_A_DQ<19> 53 DQ19 VSS 54
92 11 IN NC 29 BI
123 VDD VDD 124 55 VSS DQ28 56 =MEM_A_DQ<28> 29
BI
125 TEST VREFCA 126 =MEM_A_DQ<24> 57 DQ24 DQ29 58 =MEM_A_DQ<29>
NC 29 BI BI 29
127 VSS VSS 128 29 =MEM_A_DQ<25> 59 DQ25 VSS 60
BI
29 =MEM_A_DQ<32> 129 DQ32 DQ36 130 =MEM_A_DQ<36> 29
61 VSS DQS3* 62 =MEM_A_DQS_N<3> 29
BI BI BI
29 =MEM_A_DQ<33> 131 DQ33 DQ37 132 MEM_A_DQ<37> 11 29 92 29 =MEM_A_DM<3> 63 DM3 DQS3 64 =MEM_A_DQS_P<3> 29
BI BI IN BI
133 VSS VSS 134 65 VSS VSS 66
29 =MEM_A_DQS_N<4> 135 DQS4* DM4 136 =MEM_A_DM<4> 29 29 =MEM_A_DQ<26> 67 DQ26 DQ30 68 =MEM_A_DQ<30> 29
BI IN BI BI
29 =MEM_A_DQS_P<4> 137 DQS4 VSS 138 29 =MEM_A_DQ<27> 69 DQ27 DQ31 70 =MEM_A_DQ<31> 29
BI BI BI
139 VSS DQ38 140 =MEM_A_DQ<38> 29
71 VSS VSS 72
BI
29 =MEM_A_DQ<34> 141 DQ34 DQ39 142 =MEM_A_DQ<39> 29 KEY
BI BI
29 =MEM_A_DQ<35> 143 DQ35 VSS 144
BI
145 VSS DQ44 146 =MEM_A_DQ<44> 29 516-0229
BI
BI BI
29 =MEM_A_DQ<41> 149 DQ41 VSS 150
BI
151 VSS DQS5* 152 =MEM_A_DQS_N<5> 29
BI
29 =MEM_A_DM<5> 153 DM5 DQS5 154 =MEM_A_DQS_P<5> 29
IN BI
155 VSS VSS 156
B 29
29
BI
BI
=MEM_A_DQ<42>
=MEM_A_DQ<43>
157
159
DQ42
DQ43
DQ46
DQ47
158
160
=MEM_A_DQ<46>
=MEM_A_DQ<47>
BI
BI 29
29
B
161 VSS VSS 162
BI BI
BI BI
167 VSS VSS 168
29 =MEM_A_DQS_N<6> 169 DQS6* DM6 170 =MEM_A_DM<6> 29
BI IN
29 =MEM_A_DQS_P<6> 171 DQS6 VSS 172
BI
173 VSS DQ54 174 =MEM_A_DQ<54> 29
BI
29 =MEM_A_DQ<50> 175 DQ50 DQ55 176 =MEM_A_DQ<55> 29 PP0V75_S3_MEM_VREFCA_A 32
BI BI
29 =MEM_A_DQ<51> 177 DQ51 VSS 178
BI
179 VSS DQ60 180 =MEM_A_DQ<60> 29
BI
1
C2935 1
C2936
BI BI
29 =MEM_A_DQ<57> 183 DQ57 VSS 184 2.2UF 0.1UF
BI 20% 20%
185 VSS DQS7* 186 =MEM_A_DQS_N<7> 29 2
6.3V
2
10V
BI CERM CERM
29 =MEM_A_DM<7> 187 DM7 DQS7 188 =MEM_A_DQS_P<7> 29
402-LF 402
IN BI
189 VSS VSS 190
BI BI
BI BI
195 VSS VSS 196
MEM_A_SA<0> 197 SA0 EVENT* 198 MEM_EVENT_A_L 30 45 46
80 73 72 69 68 OUT
47 46 42 40 37
20 19 18 17 7 6PP3V3_S0 199 VDDSPD SDA 200 SMBUS_PCH_DATA 17 25 26 30 32 42 47 48 63 88 "Factory" (top) slot
34 30 27 26 25 24 23 21 BI 94
63 62 58 54 52 51 50 48 MEM_A_SA<1> 201 SA1 SCL 202 SMBUS_PCH_CLK 17 25 26 30 32 42 47 48 63 88
99 88 87 85 84 83 IN 94
203 VTT VTT 204 PP0V75_S0_DDRVTT 6 7 30 31 67
1 1
1
C2940 R2940 R2941
A 2
2.2UF
20%
6.3V
10K
5%
1/16W
MF-LF
10K
5%
1/16W
MF-LF
516-0229
SPD ADDR=0xA0(WR)/0xA1(RD)
SYNC_MASTER=MASTER SYNC_DATE=MASTER A
CERM
402 402
PAGE TITLE
402-LF 2 2
DDR3 SO-DIMM Connector A
DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
29 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU CHANNEL A DQS 0 -> DIMM A DQS 0 CPU CHANNEL B DQS 0 -> DIMM B DQS 0
92 29 28 11 MEM_A_DQS_N<0> MEM_A_DQS_N<0> 11 28 29 92 92 30 29 11 MEM_B_DQS_N<0> MEM_B_DQS_N<0> 11 29 30 92
92 29 28 11 MEM_A_DQS_P<0> MEM_A_DQS_P<0> 11 28 29 92 92 30 29 11 MEM_B_DQS_P<0> MEM_B_DQS_P<0> 11 29 30 92
92 29 28 11 MEM_A_DM<0> MEM_A_DM<0> 11 28 29 92 92 30 29 11 MEM_B_DM<0> MEM_B_DM<0> 11 29 30 92
92 11 MEM_A_DQ<7> =MEM_A_DQ<7> 28 92 11 MEM_B_DQ<7> =MEM_B_DQ<7> 30
D 92 11 MEM_A_DQ<0>
MAKE_BASE=TRUE
=MEM_A_DQ<4> 28 92 11 MEM_B_DQ<0>
MAKE_BASE=TRUE
=MEM_B_DQ<0> 30
D
92 11 MEM_A_DQS_N<1> =MEM_A_DQS_N<1> 28 92 11 MEM_B_DQS_N<1> =MEM_B_DQS_N<1> 30
92 11 MEM_A_DQS_P<1> =MEM_A_DQS_P<1> 28 92 11 MEM_B_DQS_P<1> =MEM_B_DQS_P<1> 30
92 11 MEM_A_DM<1> =MEM_A_DM<1> 28 92 11 MEM_B_DM<1> =MEM_B_DM<1> 30
C 92 11 MEM_A_DQS_N<3>
MAKE_BASE=TRUE
=MEM_A_DQS_N<3> 28 92 11 MEM_B_DQS_N<3>
MAKE_BASE=TRUE
=MEM_B_DQS_N<3> 30
C
92 29 28 11 MEM_A_DQ<37> MEM_A_DQ<37> 11 28 29 92 92 30 29 11 MEM_B_DQ<37> MEM_B_DQ<37> 11 29 30 92
B 92 11 MEM_A_DQS_P<5> MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQS_P<5> 28 92 11 MEM_B_DQS_P<5> MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DQS_P<5> 30 B
MEM_A_DQS_P<7> =MEM_A_DQS_P<7> MEM_B_DQS_P<7> =MEM_B_DQS_P<7>
A 92 11
92 11 MEM_A_DM<7> MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DM<7>
28
28
92 11
92 11 MEM_B_DM<7> MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DM<7>
30
30 SYNC_MASTER=MASTER SYNC_DATE=MASTER A
PAGE TITLE
92 11 MEM_A_DQ<62> MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQ<63> 28 92 11 MEM_B_DQ<62> MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DQ<62> 30 DDR3 Byte/Bit Swaps
92 11 MEM_A_DQ<61> =MEM_A_DQ<56> 28 92 11 MEM_B_DQ<61> =MEM_B_DQ<57> 30 DRAWING NUMBER SIZE
92 11 MEM_A_DQ<60>
MAKE_BASE=TRUE
=MEM_A_DQ<61> 28 92 11 MEM_B_DQ<60>
MAKE_BASE=TRUE
=MEM_B_DQ<56> 30
92 11 MEM_A_DQ<59> =MEM_A_DQ<59> 28 92 11 MEM_B_DQ<59> =MEM_B_DQ<59> 30 REVISION
MAKE_BASE=TRUE MAKE_BASE=TRUE R
92 11 MEM_A_DQ<58>
MAKE_BASE=TRUE
=MEM_A_DQ<58> 28 92 11 MEM_B_DQ<58>
MAKE_BASE=TRUE
=MEM_B_DQ<58> 30 <E4LABEL>
92 11 MEM_A_DQ<57> =MEM_A_DQ<57> 28 92 11 MEM_B_DQ<57> =MEM_B_DQ<60> 30 NOTICE OF PROPRIETARY PROPERTY: BRANCH
92 11 MEM_A_DQ<56>
MAKE_BASE=TRUE
=MEM_A_DQ<60> 28 92 11 MEM_B_DQ<56>
MAKE_BASE=TRUE
=MEM_B_DQ<61> 30 THE INFORMATION CONTAINED HEREIN IS THE
<BRANCH>
30 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
72 67 31 28 7 6 PP1V5_S3
DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)
- =PP1V5_S0_MEM_B
- =PP1V5_S3_MEM_B
1 C3110 1 C3111 1 C3112 1 C3113 1 C3114 1 C3115 1 C3116 1 C3117 1 C3118 1 C3119 1 C3120 1 C3121 1 C3122 1 C3123
- =PP0V75_S0_MEM_VTT_B
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
- =PPSPD_S0_MEM_B (2.5 - 3.3V) 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
402 402 402 402 402 402 402 402 402 402 402 402 402 402
Signal aliases required by this page: 1 C3100 1 C3101
- =I2C_SODIMMB_SCL
10UF 10UF
- =I2C_SODIMMB_SDA 20% 20%
2 6.3V
X5R 2 6.3V
X5R
D BOM options provided by this page:
(NONE)
603 603
32 PP0V75_S3_MEM_VREFDQ_B D
1
C3130 1
C3131
2.2UF 0.1UF
20% 20%
6.3V 10V
2 CERM 2 CERM
402-LF 402
1 VREFDQ VSS 2
3 VSS DQ4 4 =MEM_B_DQ<4> 29
KEY
BI
92 11 MEM_B_CKE<0> 73 CKE0 CKE1 74 MEM_B_CKE<1> 11 92 29 =MEM_B_DQ<0> 5 DQ0 DQ5 6 =MEM_B_DQ<5> 29
IN IN BI BI
75 76 =MEM_B_DQ<1> 7 CRITICAL 8
VDD VDD 29 BI DQ1 VSS
77 NC A15 78 MEM_B_A<15> 9 VSS DQS0* 10 MEM_B_DQS_N<0>
NC IN 11 92 BI 11 29 92
92 11 IN MEM_B_BA<2> 79 BA2 J3100 A14 80 MEM_B_A<14> IN 11 92 92 29 11 IN MEM_B_DM<0> 11 DM0 J3100 DQS0 12 MEM_B_DQS_P<0> BI 11 29 92
81 82 13 F-RT-BGA6 14
VDD F-RT-BGA6 VDD VSS VSS
DDR3-SODIMM
(1 OF 2)
(2 OF 2)
83 84 15 16
DDR3-SODIMM
92 11 IN MEM_B_A<12> A12/BC* A11 MEM_B_A<11> IN 11 92 29 BI =MEM_B_DQ<2> DQ2 DQ6 =MEM_B_DQ<6> BI 29
92 11 MEM_B_A<9> 85 A9 A7 86 MEM_B_A<7> 11 92 29 =MEM_B_DQ<3> 17 DQ3 DQ7 18 =MEM_B_DQ<7> 29

IN IN BI BI
IN IN BI BI
IN IN BI BI
92 11 MEM_B_A<3> 95 A3 A2 96 MEM_B_A<2> 11 92 29 =MEM_B_DQS_N<1> 27 DQS1* DM1 28 =MEM_B_DM<1> 29
IN IN BI IN
92 11 MEM_B_A<1> 97 A1 A0 98 MEM_B_A<0> 11 92 29 =MEM_B_DQS_P<1> 29 DQS1 RESET* 30 MEM_RESET_L 28 31
IN IN BI IN
92 11 MEM_B_CLK_P<0> 101 CK0 CK1 102 MEM_B_CLK_P<1> 11 92 29 =MEM_B_DQ<10> 33 DQ10 DQ14 34 =MEM_B_DQ<14> 29
IN IN BI BI
92 11 MEM_B_CLK_N<0> 103 CK0* CK1* 104 MEM_B_CLK_N<1> 11 92 29 =MEM_B_DQ<11> 35 DQ11 DQ15 36 =MEM_B_DQ<15> 29
IN IN BI BI
C 92 11 MEM_B_A<10>
105
107
VDD
A10/AP
VDD
BA1
106
108 MEM_B_BA<1> 11 92 29 =MEM_B_DQ<16>
37
39
VSS
DQ16
VSS
DQ20
38
40 =MEM_B_DQ<20> 29
C
IN IN BI BI
92 11 MEM_B_BA<0> 109 BA0 RAS* 110 MEM_B_RAS_L 11 92 29 =MEM_B_DQ<17> 41 DQ17 DQ21 42 =MEM_B_DQ<21> 29
IN IN BI BI
92 11 MEM_B_WE_L 113 WE* S0* 114 MEM_B_CS_L<0> 11 92 29 =MEM_B_DQS_N<2> 45 DQS2* DM2 46 =MEM_B_DM<2> 29
IN IN BI IN
92 11 MEM_B_CAS_L 115 CAS* ODT0 116 MEM_B_ODT<0> 11 92 29 =MEM_B_DQS_P<2> 47 DQS2 VSS 48
IN IN BI
117 VDD VDD 118 49 VSS DQ22 50 =MEM_B_DQ<22> 29
BI
92 11 MEM_B_A<13> 119 A13 ODT1 120 MEM_B_ODT<1> 11 92 29 =MEM_B_DQ<18> 51 DQ18 DQ23 52 =MEM_B_DQ<23> 29
IN IN BI BI
MEM_B_CS_L<1> 121 S1* NC 122 =MEM_B_DQ<19> 53 DQ19 VSS 54
92 11 IN NC 29 BI
123 VDD VDD 124 55 VSS DQ28 56 =MEM_B_DQ<28> 29
BI
125 TEST VREFCA 126 =MEM_B_DQ<24> 57 DQ24 DQ29 58 =MEM_B_DQ<29>
NC 29 BI BI 29
127 VSS VSS 128 29 =MEM_B_DQ<25> 59 DQ25 VSS 60
BI
29 =MEM_B_DQ<32> 129 DQ32 DQ36 130 =MEM_B_DQ<36> 29
61 VSS DQS3* 62 =MEM_B_DQS_N<3> 29
BI BI BI
29 =MEM_B_DQ<33> 131 DQ33 DQ37 132 =MEM_B_DQ<37> 29 29 =MEM_B_DM<3> 63 DM3 DQS3 64 =MEM_B_DQS_P<3> 29
BI BI IN BI
133 VSS VSS 134 65 VSS VSS 66
29 =MEM_B_DQS_N<4> 135 DQS4* DM4 136 =MEM_B_DM<4> 29 29 =MEM_B_DQ<26> 67 DQ26 DQ30 68 =MEM_B_DQ<30> 29
BI IN BI BI
29 =MEM_B_DQS_P<4> 137 DQS4 VSS 138 29 =MEM_B_DQ<27> 69 DQ27 DQ31 70 =MEM_B_DQ<31> 29
BI BI BI
139 VSS DQ38 140 =MEM_B_DQ<38> 29
71 VSS VSS 72
BI
92 29 11 MEM_B_DQ<37> 141 DQ34 DQ39 142 =MEM_B_DQ<39> 29 KEY
BI BI
29 =MEM_B_DQ<35> 143 DQ35 VSS 144
BI
145 VSS DQ44 146 =MEM_B_DQ<44> 29 516S0806
BI
BI BI
29 =MEM_B_DQ<41> 149 DQ41 VSS 150
BI
151 VSS DQS5* 152 =MEM_B_DQS_N<5> 29
BI
29 =MEM_B_DM<5> 153 DM5 DQS5 154 =MEM_B_DQS_P<5> 29
IN BI
155 VSS VSS 156
B 29
29
BI
BI
=MEM_B_DQ<42>
=MEM_B_DQ<43>
157
159
DQ42
DQ43
DQ46
DQ47
158
160
=MEM_B_DQ<46>
=MEM_B_DQ<47>
BI
BI 29
29
B
161 VSS VSS 162
BI BI
BI BI
167 VSS VSS 168
29 =MEM_B_DQS_N<6> 169 DQS6* DM6 170 =MEM_B_DM<6> 29
BI IN
29 =MEM_B_DQS_P<6> 171 DQS6 VSS 172
BI
173 VSS DQ54 174 =MEM_B_DQ<54> 29
BI
29 =MEM_B_DQ<50> 175 DQ50 DQ55 176 =MEM_B_DQ<55> 29 PP0V75_S3_MEM_VREFCA_B 32
BI BI
29 =MEM_B_DQ<51> 177 DQ51 VSS 178
BI
179 VSS DQ60 180 =MEM_B_DQ<60> 29
BI
1
C3135 1
C3136
BI BI
29 =MEM_B_DQ<57> 183 DQ57 VSS 184 2.2UF 0.1UF
BI 20% 20%
185 VSS DQS7* 186 =MEM_B_DQS_N<7> 29 2
6.3V
2
10V
BI CERM CERM
29 =MEM_B_DM<7> 187 DM7 DQS7 188 =MEM_B_DQS_P<7> 29
402-LF 402
IN BI
189 VSS VSS 190
BI BI
BI BI
195 VSS VSS 196
MEM_B_SA<0> 197 SA0 EVENT* 198 MEM_EVENT_A_L 28 45 46
88 87 85 84 83 80 OUT
51 50 48 47 46 42
21 20 19 18 17 7 6 PP3V3_S0 199 VDDSPD SDA 200 SMBUS_PCH_DATA 17 25 26 28 32 42 47 48 63 88
BI
40 37 34 28 27 26 25 24 23
73 72 69 68 63 62 58 54 52 MEM_B_SA<1> 201 202 SMBUS_PCH_CLK
94 "Expansion" (bottom) slot
99 SA1 SCL IN 17 25 26 28 32 42 47 48 63 88
94
203 VTT VTT 204 PP0V75_S0_DDRVTT 6 7 28 31 67
MTG PINS
1 1 205 206
1
C3140 R3140 R3141 MTG PIN MTG PIN
207 208
A 2
2.2UF
20%
6.3V
10K
5%
1/16W
MF-LF
10K
5%
1/16W
MF-LF
209
MTG PIN
MTG PIN
MTG PIN
MTG PIN 210 SYNC_MASTER=MASTER SYNC_DATE=MASTER A
CERM
402 402
211 MTG PIN MTG PIN 212 PAGE TITLE
402-LF 2 2
DDR3 SO-DIMM Connector B
DRAWING NUMBER SIZE
516S0806
SPD ADDR=0xA4(WR)/0xA5(RD) REVISION
R
<E4LABEL>
<BRANCH>
31 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well
as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.
ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.
WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated. D
D WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.
P1V5CPU_EN = (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L
MEMVTT_EN = (ISOLATE_CPU_MEM_L + PLT_RST_L) * PM_SLP_S3_L
1V5 S0 "PGOOD" for CPU
MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L 35 27 23 21 20 19 18 17 7 6PP3V3_S5
99 85 83 73 72 71 66 57
73 72 46 45 43 18 IN PM_SLP_S4_L PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page

CPUMEM_S0
1 PP1V5_S3RS0 PM_MEM_PWRGD
R3205 99 73 72 42 16 13 7 6 OUT 10 18 91
10K 1
R3222
5%
1/16W 10K
MF-LF 5%
2 402 1/16W CRITICAL 6
MF-LF
P1V5CPU_EN 2 402 D Q3220
OUT 72
R32201
27.4K DMB53D0UV
54 53 50 48 36 35 34 33 32 20 17 8 7 6 PP3V3_S3 CPUMEM_S0 1% SOT-563
101 87 73 72 55 1/16W
CPUMEM_S0 Q3205 D 6 MF-LF
402 2
PM_MEM_PWRGD_L 2 G
R32011 SSM6N15FEAPE
SOT563
100K
5% 3 CRITICAL
1/16W
MF-LF
402 2 2 G S 1 P1V5_S0_DIV 5 Q3220 S
DMB53D0UV 1
P1V5CPU_EN_L SOT-563
4
NO STUFF
CPUMEM_S0
D 3 D
CPUMEM_S0 R32211 C3220 1
Q3200 3
Q3205 33.2K
1% 0.001UF
SSM6N15FEAPE SSM6N15FEAPE 20%
C SOT563 SOT563
1/16W
MF-LF
402 2
50V
CERM 2
402
C
5 G S 4 4 S G 5
25 20 IN ISOLATE_CPU_MEM_L PM_SLP_S3_L IN 6 18 45 73 85
CPUMEM_S0
1
R3210
10K
5%
1/16W
MF-LF
2 402
MEMVTT_EN OUT 8 31 67
PP5V_S3
67 66 61 58 56 54 46 44 43 42 33 31 7 6
101 82 72
CPUMEM_S0 CPUMEM_S0
CPUMEM_S0
Q3210 D 6
MEMVTT Clamp
1 1 SSM6N15FEAPE Ensures CKE signals are held low in S3
R3215 R3202 SOT563
100K 100K
5% 5%
1/16W 1/16W
MF-LF MF-LF
402 2 402 2 2 G S 1 67 30 28 7 6 PP0V75_S0_DDRVTT
MEMVTT_EN_L CPUMEM_S0
R32501
CPUMEM_S0 CPUMEM_S0 10 75mA max load @ 0.75V
CPUMEM_S0 D 6 D 5%
Q3215 Q3200 3
Q3210 1/10W
MF-LF
60mW max power
SSM6N15FEAPE SSM6N15FEAPE 603 2
SSM6N15FEAPE SOT563 SOT563
VTTCLAMP_L
G 2
SOT563
2 G S 1 4 S G 5 67 66 61 58 56 54 46 44 43 42 33 31 7 6 PP5V_S3 CPUMEM_S0
101 82 72
Q3250 D 6
B CPUMEM_S0 B
D
PLT_RESET_L IN 19 27 40
SSM6N15FEAPE
R32511
6
SOT563
100K
5%
1/16W
MF-LF
402 2 2 G S 1
PP1V5_S3 6 7 28 30 67 72
CPUMEM_S0 VTTCLAMP_EN
CPUMEM_S0
Q3215 1
SSM6N15FEAPE R3216 CPUMEM_S0
NO STUFF
MEMRESET_ISOL_LS5V_L
20K Q3250 D 3
C3251 1
5
SOT563 5% SSM6N15FEAPE
1/16W
G
MF-LF SOT563 0.001UF

20%
2 402 50V
CERM 2
S
31 10 CPU_MEM_RESET_L CPU_MEM_RESET_L MEM_RESET_L 28 30

402
IN OUT
MAKE_BASE=TRUE 5 G S 4
3
4
67 31 8 IN MEMVTT_EN
CPUMEM_S3
R3217
1
0 2
5%
1/16W
MF-LF
402
Step ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L PM_SLP_S4_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN P1V5CPU_EN

S0 0 1 1 1 1 1 CPU_MEM_RESET_L 1 1
1 0 1 1 1 1 1 1 1
to 2 0 0 1 1 1 1 0 1
3 0 0 0 1 X 1 0 0
A S3 4 0 0 1 1 X 1 0 1
PAGE TITLE
to 5
6
0
0
1
1
1
1
1
1
0 (*)
1
1
1
1
1
1
1
CPU Memory S3 Support
DRAWING NUMBER SIZE
S0 7 1 1 1 1 1 CPU_MEM_RESET_L 1 1
REVISION
(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO. R
<E4LABEL>
NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0 THE INFORMATION CONTAINED HEREIN IS THE
<BRANCH>
transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 32 OF 132
must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L. III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NOTE: Must not enable more than two SO-DIMM margining
50 48 36 35 34 33 31 20 17 8 7 6 PP3V3_S3 buffers at once or VRef source may be overloaded.
101 87 73 72 55 54 53
VREFMRGN
OMIT
R3318 67 7 6 PPVTTDDR_S3 R3303
200 PLACE_NEAR=J2900.1:2.54mm
SHORT2 10mA max load 1 2
1 PP3V3_S3_VREFMRGN_DAC
MIN_LINE_WIDTH=0.3 mm 1%
NONE MIN_NECK_WIDTH=0.2 mm VREFMRGN VREFMRGN 1/16W
NONE VOLTAGE=3.3V MF-LF
NONE
402
C3300 1 1 C3301 VREFMRGN
VREFMRGN
402
PP0V75_S3_MEM_VREFDQ_A
2.2UF 0.1UF CRITICAL C3303 1 VREFMRGN MIN_LINE_WIDTH=0.3 mm
28
20% 20%
0.1UF
B1 U3302 MIN_NECK_WIDTH=0.2 mm
D
6.3V 2
CERM
402-LF
2 10V
CERM
402
VREFMRGN
U3300
20%
10V
CERM 2
A2
V+
MAX4253
UCSP
A1
R3304
133
VOLTAGE=0.75V
D
8
402 VREFMRGN_DQ_SODIMMA_BUF 1 2
VDD 1%
A3 A4 PLACE_NEAR=R3303.2:1mm
63 48 47 42 32 30 28 26 25 17 IN SMBUS_PCH_CLK 6 SCL
MSOP VOUTA
1 VREFMRGN_SODIMMA_DQ V- 1/16W
94 88 MF-LF
B4 402
DAC5574
63 48 47 42 32 30 28 26 25 17 BI SMBUS_PCH_DATA 7 SDA VOUTB 2 VREFMRGN_SODIMMB_DQ
94 88
9 A0 VOUTC 4 VREFMRGN_SODIMMS_CA
Addr=0x98(WR)/0x99(RD) 10 A1 VREFMRGN_MEMVREG_FBVREF
VOUTD 5 VREFMRGN
NOTE: MEMVREG and FRAMEBUF share R3305
GND
1
200 2 PLACE_NEAR=J3100.1:2.54mm
3 a DAC output, cannot enable VREFMRGN
both at the same time! 1
R3301 1%
1/16W
100K MF-LF
402
5%
1/16W VREFMRGN PP0V75_S3_MEM_VREFDQ_B 30
MF-LF B1 U3302 VREFMRGN MIN_LINE_WIDTH=0.3 mm
2 402 C2 MIN_NECK_WIDTH=0.2 mm
V+
MAX4253 R3306 VOLTAGE=0.75V
UCSP
OMIT C1 VREFMRGN_DQ_SODIMMB_BUF 1
133 2
R3319 C3 C4 1% PLACE_NEAR=R3305.2:1mm
SHORT2 V- 1/16W
1 PP3V3_S3_VREFMRGN_CTRL B4
MF-LF
MIN_LINE_WIDTH=0.3 mm 402
NONE MIN_NECK_WIDTH=0.2 mm
NONE
NONE
VOLTAGE=3.3V CRITICAL
VREFMRGN
16
402 VREFMRGN VREFMRGN
C3302 1 VREFMRGN
0.1UF
20%
VCC R3309
1
R3302 200 PLACE_NEAR=J2900.126:2.54mm
10V
CERM 2 U3301 100K
1 2
402 PCA9557 5% 1%
QFN 1/16W 1/16W
(OD) P0 6 NC MF-LF MF-LF
3 A0 VREFMRGN_DQ_SODIMMA_EN 2 402 VREFMRGN 402
PP0V75_S3_MEM_VREFCA_A
P1 7 VREFMRGN
C3304 1 VREFMRGN
28
C
C Addr=0x30(WR)/0x31(RD) 4 A1
5 A2
P2 9
P3 10
VREFMRGN_DQ_SODIMMB_EN
VREFMRGN_CA_SODIMMA_EN
0.1UF
20%
A2
B1
V+
U3303
MAX4253
UCSP R3310
VOLTAGE=0.75V
10V 133
P4 11 VREFMRGN_CA_SODIMMB_EN CERM 2 A1 VREFMRGN_CA_SODIMMA_BUF 1 2
402
P5 12 VREFMRGN_MEMVREG_EN A3 A4 1% PLACE_NEAR=R3309.2:1mm
V- 1/16W
63 48 47 42 32 30 28 26 25 17 IN SMBUS_PCH_CLK 1 SCL P6 13 VREFMRGN_FRAMEBUF_EN MF-LF
94 88 B4 402
63 48 47 42 32 30 28 26 25 17 BI SMBUS_PCH_DATA 2 SDA P7 14 NC
94 88
THRM RESET* 15 VREFMRGN

PAD GND
R3311
17
8
1
200 2
PLACE_NEAR=J3100.126:2.54mm
1%
VREFMRGN 1/16W
MF-LF
1
R3307 VREFMRGN
402
PP0V75_S3_MEM_VREFCA_B 30
100K VREFMRGN MIN_LINE_WIDTH=0.3 mm
PCA9557D_RESET_L 5% C2
B1 U3303 MIN_NECK_WIDTH=0.2 mm
27 IN 1/16W
MF-LF V+
MAX4253
UCSP R3312 VOLTAGE=0.75V
2 402 C1 VREFMRGN_CA_SODIMMB_BUF 1
133 2
RST* on ’platform reset’ so that system
watchdog will disable margining. C3 C4 1%
1/16W
PLACE_NEAR=R3311.2:1mm
V- MF-LF
NOTE: Margining will be disabled across all B4 402
soft-resets and sleep/wake cycles.
VREFMRGN
Required zero ohm resistors when no VREF margining circuit stuffed 1
R3308 VREFMRGN
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION 100K
5%
1/16W
C3305 1 VREFMRGN
116S0004 2 RES,MTL FILM,0,5%,0402,SM,LF R3303,R3305 CRITICAL VREFMRGN_NOT 0.1UF VREFMRGN
MF-LF
2 402
20%
10V C2
B1 U3304
CERM 2 MAX4253 R3314
116S0004 2 RES,MTL FILM,0,5%,0402,SM,LF R3309,R3311 CRITICAL VREFMRGN_NOT 402 V+ UCSP
B C1 VREFMRGN_MEMVREG_BUF
22.6K2
1 DDRREG_FB OUT 67 B
C3 C4 1% PLACE_NEAR=R7320.2:1mm
V- 1/16W
MF-LF
B4 402
Page Notes VREFMRGN

1
VREFMRGN
R3316
Power aliases required by this page: R3313 49.9 2
VREFMRGN 1 GPU_FB_A_VREF_DIV OUT 8 77
- =PP3V3_S3_VREFMRGN 100K B1 U3304
5% A2 1% PLACE_NEAR=R0900.2:1mm
- =PPVTT_S3_DDR_BUF 1/16W MAX4253 1/16W
MF-LF
MF-LF V+ UCSP
402
Signal aliases required by this page: 2 402 A1 VREFMRGN_FRAMEBUF_BUF
VREFMRGN
- =I2C_VREFDACS_SCL A3 A4
- =I2C_VREFDACS_SDA V- R3317
B4 49.9 2
- =I2C_PCA9557D_SCL 1 GPU_FB_B_VREF_DIV OUT 8 78
- =I2C_PCA9557D_SDA 1%
1/16W
PLACE_NEAR=R0901.2:1mm
MF-LF
BOM options provided by this page: VREFMRGN 402
VREFMRGN - Stuffs VREF Margining 1
R3315
Circuitry. 100K
5%
VREFMRGN_NOT - Bypasses VREF Margining 1/16W
MF-LF
Circuitry. 2 402
A MEM A VREF DQ MEM B VREF DQ MEM A VREF CA MEM B VREF CA MEM VREG GPU Frame Buffer (1.8V, 70% VRef) SYNC_MASTER=K17_REF SYNC_DATE=06/15/2009 A
PAGE TITLE
DAC Channel: A B C C D D FSB/DDR3/FRAMEBUF Vref Margining

DRAWING NUMBER SIZE
PCA9557D Pin: 1 2 3 4 5 6 Apple Inc. <SCH_NUM> D
REVISION
Nominal value 0.75V (DAC: 0x3A) 1.5V (DAC: 0x3A) 1.267V (DAC: 0x8B) R
<E4LABEL>
Margined target: 0.300V - 1.200V (+/- 450mV) 1.998V - 1.002V (+/- 498mV) 1.056V - 1.442V (+/- 180mV) NOTICE OF PROPRIETARY PROPERTY: BRANCH
DAC range: 0.000V - 1.501V (0x00 - 0x74) 0.000V - 1.501V (0x00 - 0x74) 0.000V - 3.300V (0x00 - 0xFF) THE INFORMATION CONTAINED HEREIN IS THE
<BRANCH>
VRef current: +3.4mA - -3.4mA (- = sourced) +33uA - -33uA (- = sourced) +6.0mA - -5.0mA (- = sourced) I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
33 OF 132
SHEET
DAC step size: 7.69mV / step @ output 8.59mV / step @ output 1.51mV / step @ output III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AP_PWR_EN IN 20 73
D 3V S3 WLAN FET D
25 17 OUT AP_CLKREQ_L MOSFET TPCP8102
CHANNEL P-TYPE
6 D Q3401
SSM6N15FEAPE RDS(ON) 20-30 MOHM @2.5V
SOT563
LOADING 0.727 A (EDP)
1
S G 2
6 AP_CLKREQ_Q_L CRITICAL
Q3450
155S0367
TPCP8102
MIN_NECK_WIDTH=0.4 mm 23V1K-SM
727 MA PEAK
L3404 MIN_LINE_WIDTH=1 mm
5 6 7 8
FERR-120-OHM-3A XW3452 MIN_LINE_WIDTH=1 mm
1 2 3
PLACEMENT_NOTE=Place close to J3401. 606 MA NOMINAL MAX MIN_NECK_WIDTH=0.5 mm
C3431 SM
PCIE_AP_R2D_P PP3V3_WLAN 1 PP3V3_WLAN_F
S
D
94 6 6 56 33
1 2 0.1uF PCIE_AP_R2D_C_P 17 94
2 1 2 PP3V3_S3 53 54 55 72 73 87
6 7 8 17 20 31 32
IN 33 34 35 36 48 50
MIN_LINE_WIDTH=1 mm
94 6 PCIE_AP_R2D_N 1 2 0.1uF 10% 16V X5R 402 PCIE_AP_R2D_C_N IN 17 94 MIN_NECK_WIDTH=0.2 mm 0603 101
PP3V3_WLAN_R
4G
10% 16V X5R 402 1
C3422 1
C3421 1 1
C3420 C3451 1 R3451
C3430 10K
516S0582 PLACEMENT_NOTE=Place close to J3401. 0.1uF
20%
0.1uF
20%
10UF
20%
0.033UF
10% 5%
1/16W
10V 10V 10V 16V
2 2 2 2 MF-LF
CRITICAL CERM CERM X5R C3450 X5R
402 402 805
0.1UF 402 R3450 2
402
J3401
500913-0302
PCIE_AP_D2R_P OUT 6 17 94 PLACEMENT_NOTE=Place close to J3401. PLACEMENT_NOTE=Place close to Q3450. 1 2 P3V3WLAN_SS 1
33K 2 PM_WLAN_EN_L IN 33 73
32
F-ST-SM
31 PCIE_AP_D2R_N OUT 94
6
CRITICAL
L3401 AIRPORT 10%
16V
5%
1/16W
MF-LF
C 17 90-OHM-100MA
DLP11S
SYM_VER-1
PLACEMENT_NOTE=Place close to Q3450. X5R
402
402
C
2 1 4 3 PCIE_CLK100M_AP_P 17 94
IN
4 3 99 6 PCIE_CLK100M_AP_CONN_P
6 5 99 6 PCIE_CLK100M_AP_CONN_N
8 7
1 2 PCIE_CLK100M_AP_N IN 17 94
10 PLACEMENT_NOTE=Place close to J3401.

9
12 11
NC
14 13
NC
16 15 L3403
18
20
17
19
BLUETOOTH 90-OHM
DLP0NS
SYM_VER-1
CRITICAL
PLACE_NEAR=J3401.21:2.54MM
22 21 99 6 CONN_USB2_BT_P
4 3 USB_BT_P BI 36 93
24 23 99 6 CONN_USB2_BT_N
26 25 1 2 USB_BT_N BI 36 93
28 27 PP3V3_S3_BT_F PLACEMENT_NOTE=Place close to J3401.
30 29 MIN_NECK_WIDTH=0.2 mm L3406
1 C3432
2 1 PP3V3_S3 6 7 8 17 20 31 32 33 34 35 36 48 50 53 54
34 33 0.01UF 55 72 73 87 101
10%
2 16V FERR-120-OHM-1.5A
CERM 0402-LF
402
PLACEMENT_NOTE=PLACE L3406 NEAR J3401.
PLACEMENT_NOTE=PLACE C3432 NEAR J3401
B RC (R3453 AND C3453)VALUE IS CHOSEN TO MEET THE 100 MS DELAY REQUIREMENT BETWEEN B
3.3 WLAN POWER GETTING STABLE AND AIRPORT CARD COMING OUT OF RESET
PP3V3_WLAN_F 33 56
PP3V3_S3 6 7 8 17 20 31 32 33 34 35 36 48 50 53 54
1
55 72 73 87 101
PCIE_WAKE_L 6 18 27
R3453
OUT 110K
5%
U3402
74LVC1G17 5
1/16W
MF-LF
402
2
TC7SZ08AFEAPE 5 SOT353-1
SOT665
A
2 WLAN_SMIT_BUF 4 2 R3455
1
6 AP_RESET_CONN_L 4
U3401
Y NC WLAN_SMIT_RC 1 2 WLAN_SMIT_DISCHRG
1 5%
B
3 1 1/16W
MF-LF
518S0767 3 NC 1 402 3 D Q3401
C3453 1 R3454
62K SSM6N15FEAPE
CRITICAL AP_RESET_L 27
1UF 5% NOSTUFF SOT563
IN 10%
1/16W
J3402 6.3V
CERM 2 MF-LF
402
819Q-3506-K281
F-RT-SM
402 2
4 S G 5
8
PM_WLAN_EN_L 33 73
6 PP5V_S3_ALSCAMERA_F
6
5 SMBUS_SMC_A_S3_SCL IN 6 45 48 54 97 MIN_NECK_WIDTH=0.2 mm
4 SMBUS_SMC_A_S3_SDA 275 mA peak
BI 6 45 48 54 97
93 6 USB_CAMERA_CONN_P
206 mA nominal max
A
3
2
1
93 6 USB_CAMERA_CONN_N ALS L3408
FERR-120-OHM-1.5A
PLACEMENT_NOTE=Place close to J3402
SYNC_MASTER=K18_COMMS SYNC_DATE=06/15/2009 A
2 1 PP5V_S3 6 7 31 42 43 44 46 54 56 58 61 66 67 72
PAGE TITLE
7 CRITICAL
L3407
CAMERA 1 C3452
0402-LF
82 101
X16/ALS/CAMERA CONNECTOR
DRAWING NUMBER SIZE
90-OHM
DLP0NS PLACE_NEAR=J3402.6:2.54MM 0.1uF <SCH_NUM> D
SYM_VER-1 20%
2 10V
Apple Inc. REVISION
4 3 USB_CAMERA_P 35
CERM R
BI 402
<E4LABEL>
1 2 USB_CAMERA_N BI 35 THE INFORMATION CONTAINED HEREIN IS THE
<BRANCH>
PLACEMENT_NOTE=Place close to J3402 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
34 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Caesar IV Support
BCM57765
37 BI SDCONN_DATA<0> R3550 0 1 2 SD_D<0> 6 34
5% 1/16W MF-LF 402
BCM57765
37 SDCONN_DATA<1> R3551 0 1 2 SD_D<1> 6 34
D GL137
R3511 BYPASS=U3500.15:16:5 mm
BI
BCM57765
5% 1/16W MF-LF 402
D
50 48 36 35 33 32 31 20 17 8 7 6 PP3V3_S3
0
BYPASS=U3500.26:27:5 mm 37 BI SDCONN_DATA<2> R3552 0 1 2 SD_D<2> 6 34
101 87 73 72 55 54 53 BYPASS=U3500.35:34:5 mm 5% 1/16W MF-LF 402
1 2 PP3V3_S3_CARDREADER_DVDD BCM57765
MIN_LINE_WIDTH=0.40MM R3553 0
5% MIN_NECK_WIDTH=0.20MM GL137 GL137 GL137 GL137 37 BI SDCONN_DATA<3> 1 2 SD_D<3> 6 34
1/16W VOLTAGE=3.3V 5% 1/16W MF-LF 402
MF-LF
402
C3500 1 1 C3501 1 C3502 1 C3503
10UF 0.1UF 0.1UF 0.1UF 37 BI SDCONN_DATA<4..7> SD_D<4..7> 6 34
2 20% 20% 20% 20% MAKE_BASE=TRUE
6.3V 2 2 10V 2 10V 2 10V BCM57765
X5R CERM CERM CERM
GL137 603 402 402 402 SDCONN_CLK R3554 0 1 2 SD_CLK
L3500 37 IN
BCM57765
5% 1/16W MF-LF 402
6 34
0.22UH
0805-1 37 OUT SDCONN_CMD R3556 0 1 2 SD_CMD 6 34
5% 1/16W MF-LF 402 MAKE_BASE=TRUE
1 37 34 6 OUT SD_WP SD_WP 6 34 37

BYPASS=U3500.6:5:5 mm MAKE_BASE=TRUE
BYPASS=U3500.11:12:5 mm
PP3V3_S3_CARDREADER_AVDD
MIN_LINE_WIDTH=0.40MM 37 34 6 OUT SD_CD_L SD_CD_L 6 34 37
MIN_NECK_WIDTH=0.20MMGL137 GL137 GL137 MAKE_BASE=TRUE
VOLTAGE=3.3V
C3514 1 1 C3504 1 C3508 BCM57765
10UF 0.1UF 0.1UF
20%
6.3V 2
20% 20% 72 69 68 63 62 58 54 52 51 50
25 24 23 21 20 19 18 17 7 6 PP3V3_S0 R3555
X5R 2 10V
CERM 2 10V
CERM
48 47 46 42 40 37 30 28 27 26
99 88 87 85 84 83 80 73
0
1 2
603 402 402
5%
1/10W
MF-LF
603
Keep this net short! PP3V3_SW_SD_PWR
PP1V8_S3_CARDREADER MIN_NECK_WIDTH=0.20 MM
BYPASS=U3500.4:5:5 mm MIN_LINE_WIDTH=0.30MM 1 VOLTAGE=3.3V CRITICAL
GL137 MIN_NECK_WIDTH=0.20MM R3505 MAKE_BASE=TRUE
C3506 1 VOLTAGE=1.8V
NC
C3507 1 1 C3505 39K J3500
GL137 2.2UF 0.1UF 5% Max Current = 250 mA SD-CARD-K19-K24
0.1UF 20% 20%
AVDD 11
15
26
35
25
36
20% 6.3V 10V 1/16W F-RT-TH
R35121
6
4
10V CERM1 2 2 CERM MF-LF
CERM 2 10K 603 402 2 402 3
C C
VDD18O
DVDD
VDD5V
PMOSO
402 VSS
5% 6
GL137 NO STUFF 1/16W VSS
MF-LF
R35071 1
R3508 402 2 34 6 SD_CLK 5
CLK
10K 10K SD_CMD 2
5%
1/16W
5%
1/16W 93 36 8 USB_SDCARD_N 7 DM U3500 D0 40
34 6
34 6 SD_D<0> 7
CMD
DAT0
BI
MF-LF
402 2
MF-LF
USB_SDCARD_P 8 DP GL137A D1 43 SD_D<1> 8
2 402 DAT1
93 36 8 34 6
BI LQFP
D2 37 34 6 SD_D<2> 9 DAT2
GL137_GPIO1 48 GPIO1
CRITICAL D3 29 34 6 SD_D<3> 1
GL137_GPIO2 47 GPIO2 CD/DAT3
GL137 D4 28 34 6 SD_D<4> 10
46 GPIO3 DAT4
NO STUFF GL137 NC 30 SD_D<5> 11
D5 34 6 DAT5
R35091 1
R3510 NC
19
SK D6 32 34 6 SD_D<6> 12
DAT6
10K 10K 20 CS 38 SD_D<7> 13
5% 5% NC D7 34 6
DAT7
1/16W 1/16W 14
MF-LF MF-LF 21 DO
402 2 NC CLK 39 SD_CLK_R CARD_DETECT_SW
2 402 22 DI (IPD) 15
NC (IPD) SD_WP 3 37 34 6 SD_WP CARD_DETECT_GND
16
GL137_CLK12M_X1 13 X1 41 WRITE_PROTECT_SW
(IPD) SD_CMD 4
GL137_CLK12M_X2 14 X2 2 GL137_PDMOD VDD
NO STUFF (IPU) PDMOD
23 SD_CD_L 17
R3503 GL137_RREF 10 RREF (IPU) SD_CDZ 37 34 6
18
SHLD_PIN
1
1M 2 1 NO STUFF GL137 SHLD_PIN
GL137_TESTMOD 17 TESTMOD (IPD)
(IPU) XD_CDZ
31
NC
R3513 1 R3504 19
SHLD_PIN
5% XD_CE NC 0 20
1/16W GL137 GL137 18 EXTRSTZ* (IPU) 42 10K 1 2 SHLD_PIN
MF-LF GL137_RESET_L (IPD) XD_WEZ NC 5%
GL137 402
R35061 1
R3502 NO STUFF (IPD) XD_RBZ 44
NC
1/16W
MF-LF
5%
1/16W
NO STUFF
CRITICAL 715
1% 5%
0
C3513 1 (IPD) XD_WPZ 45 402 2 MF-LF
402
1 C3515
Y3500 1/16W 1/16W NC 10PF 516-0225
MF-LF MF-LF 0.1UF 5%
12.000M-100PPM 402 2 20% (IPU) MS_INS 24 2 50V
1 2 2 402 10V NC CERM
CERM 2
402 (IPD) MS_BS 33 NC
402-1
8X4.5X1.4-SM PDMOD: POWER DOWN MODES
GL137 GL137 GND
B C3511
33PF
C3512
33PF
NC = DISABLE (DEFAULT)
10K LOW = POWER SAVING MODE ENABLE
B
5
9
12
16
27
34
1 2 1 2 10K HIGH = REMOTE WAKE UP ENABLE
GL137
5% 5%
50V 50V Q3500 D 3
CERM CERM
402 402 SSM6N15FEAPE
SOT563
5 G S 4
25 20 IN SDCARD_RESET SDCARD_PLT_RST
GL137
Q3500 D 6
SSM6N15FEAPE
SOT563
2 G S 1
27 IN SDCARD_PLT_RST_L
A SYNC_MASTER=T27_REF SYNC_DATE=08/26/2009 A
PAGE TITLE
SecureDigital Card Reader

DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
35 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PP3V3_S3
USB HUB-1
53 50 48 36 35 34 33 32 31 20 17 8 7 6
101 87 73 72 55 54
R3640
20K
31 27 23 21 20 19 18 17 7 6PP3V3_S5 1 2
99 85 83 73 72 71 66 57
5%
1/16W
MF-LF
1
402 R3641
10K
1 5%
R3642 NOSTUFF 1/16W
100K
5%
1 C3641
100PF
MF-LF
2402
1/16W 5%
MF-LF
402 2 2 50V
CERM USB_HUB_RESET
D L3658
FERR-120-OHM-1.5A
402
6
USB_HUB_RESET_L D
3
101 87 73 72
33 32 31 20 17 8 7 6PP3V3_S3 1 2 PPUSB_HUB1_VDDPLL3V3 D
55 54 53 50 48 36 35 34
0402 MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM Q3640 D
Q3640
VOLTAGE=3.3V 2 2N7002DW-X-G
P3V3S3_EN_RC 2N7002DW-X-G
1 C3636
0.01UF
1 C3637
100PF
1 C3638
10UF
1 C3639
0.1UF
PP3V3_S3 6 7 8 17 20 31 32 33 34 35 36 48 50 53
54 55 72 73 87 101
G S SOT-363 5 G S SOT-363
10% 5% 20% 10% 1
2 16V
CERM
402
2 50V
CERM
402
2 6.3V
X5R
603
2 16V
X7R-CERM
402
1 C3623
0.1UF
1 C3625
0.1UF
C3626
0.01UF
C3629
1
0.01UF
1 1 C3640
0.47UF
4
10% 10% 10% 10% 10%

2 16V
X7R-CERM 2 16V
X7R-CERM 2 16V
CERM 2 16V
CERM
6.3V
2 CERM-X5R
402 402 402 402 402
1 C3618
10UF
20%
6.3V
L3629
FERR-120-OHM-1.5A MIN_LINE_WIDTH=0.4MM
2 X5R
603 1 2 VOLTAGE=3.3V
PPUSB_HUB1_VDDA3V3
0402 PPUSB_HUB1_VDD1V8
1 C3642
0.01UF
1 C3643
100PF
1 C3644
10UF
1 C3645
0.1UF
1 C3646
0.1UF
1 C3647
0.1UF
VOLTAGE=1.8V
10% 5% 20% 10% 10% 10% PPUSB_HUB1_VDD1V8PLL
2 16V
CERM
402
2 50V
CERM
402
2 6.3V
X5R
603
2 16V
X7R-CERM
402
2 16V
X7R-CERM
402
2 16V
X7R-CERM
402
1 C3628
0.1UF
1 C3630
1UF
VOLTAGE=1.8V 1 C3624
0.1UF
1 C3627
1UF
10%
2 16V
X7R-CERM
10%
2 16V
X5R
10% 10% 402 402
2 16V
X7R-CERM 2 16V
X5R
402 402 D3600
SOD-523
53 50 48 36 35 34 33 32 31 20 17 8 7 6 PP3V3_S3
101 87 73 72 55 54 25 19 IN USB_HUB_SOFT_RESET_L 2 1
29
10
VDD33PLL 36
VDD33CR 15
VDD33 23
VDD18 14
VDD18PLL 34
5
NOSTUFF HUB1_NONREM0_1 BAT54XV2T1
C CRITICAL
R3697 1 1
R3699 VDDA33
C
Y3600 10K 5%
10K
5%
24.000M-60PPM-16PF 1/16W 1/16W
1 2 MF-LF MF-LF
CRITICAL CRITICAL 4022 2 402
5X3.2X1.4-SM
C3619 1 1 C3620 U3600
18PF 5%
R3691
1M 5%
18PF QFN
50V 1 2 2 50V USX2061
CERM 2 CERM USB_HUB1_TEST 11 TEST USBDN1_DM/PRT_DIS_M1 1 USB_CAMERA_N
402 5% 402 BI 33
Camera
1/16W OMIT USBDN1_DP/PRT_DIS_P1 2 USB_CAMERA_P BI 33
MF-LF 36 35 USB_HUB_RESET_L 26 RESET*
402 3
33 USBDN2_DM/PRT_DIS_M2 USB_IR_N BI 44 93
CRITICAL USB_HUB1_XTAL1 XTAL1/CLKIN 4 IR Receiver
32 USBDN2_DP/PRT_DIS_P2 USB_IR_P BI 44 93
USB_HUB1_XTAL2 XTAL2
USBDN3_DM/PRT_DOS_M3 6 USB_EXTB_N 43 93
USB_HUB1_LOCAL_PWR 28 BI
SUSP_IND/LOCAL_PWR/NON_REM0 7 USB_EXTB_P External B
USBDN3_DP/PRT_DIS_P3 BI 43 93
USB_HUB1_SMBDATA 22 SDA/SMBDATA/NON_REM1
USBDN4_DM/PRT_DIS_M4 8 USB_EXTC_N 8 93
PP3V3_S3 6 7 8 17 20 31 32 33 34 35 36 48 50 53 54
BI 55 72 73 87 101
USB_HUB1_SMBCLK 24 9 USB_EXTC_P External C
SCL/SMBCLK/CFG_SEL0 USBDN4_DP/PRT_DIS_P4 BI 8 93
101 USB_HUB1_CFG_SEL1 25 HS_IND/CFG_SEL1 PRTPWR1 12 TP_USB_HUB1_PRTPWR1

54 53 50 48
32 31 20 17 8 7 6 PP3V3_S3 16
36 35 34 33
87 73 72 55 PRTPWR2 NC_USB_HUB1_PRTPWR2
HUB1_NONREM1_1 NOSTUFF 18
PRTPWR3 NC_USB_HUB1_PRTPWR3
C3634 R36921
1
R3694 1
R3698
10K PRTPWR4 20 NC_USB_HUB1_PRTPWR4 R36821
R36041 1
0.1UF 4 NOSTUFF 10K 10K
5% 5% 13
10K
5%
10K 10% VCC
5%
1/16W 1/16W 1/16W IPU OCS1* TP_USB_HUB1_OCS1 1/16W
5% MF-LF MF-LF MF-LF
1/16W 2 16V
X5R U3614 MF-LF
4022 2402 2402 IPU OCS2* 17 NC_USB_HUB1_OCS2 4022
MF-LF 402
4022 AT24C02B OCS3* 19 USB_EXTB_OC_L
SOT23-5 IPU IN 43
SDA 3 OCS4* 21 NC_USB_HUB1_OCS4

WP_HUB1 5 WP IPU IN 8
SCL 1
B GND
RBIAS 35 USB_HUB1_RBIAS B
VBUS_DET 27 USB_HUB1_VBUS_DET
2
HUB1_NONREM1_0 HUB1_NONREM0_0 30
USBUP_DM USB_HUB1_UP_N
1
R3665 1
R3666
10K
1
R3667
10K
1
R3668 USBUP_DP 31 USB_HUB1_UP_P
BI
BI
19 93
19 93
1
CRITICAL
10K
5% 5% 5% 100 THRML_PAD
R3600
1/16W 1/16W 1/16W 5% 12K
MF-LF MF-LF
37
MF-LF 1/16W 1%
2402 2402 2402 MF-LF 1/16W
2 402 MF
2 402
SEL1 SEL0 DESCRIPTION

K17/K18 configuration: 0 0 Internal Default with Self powered Operation
0 1 SMBUS Slave Config
1 0 Internal Default with Bus powered Operation
BOM TABLE
1 1 EEPROM Supported
TABLE_5_HEAD
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

TABLE_5_ITEM
338S0720 2 SMSC USB2514 U3600,U3700 CRITICAL USBHUB_2514

TABLE_5_ITEM
338S0824 2 SMSC USB2514B U3600,U3700 CRITICAL USBHUB_2514B

TABLE_5_ITEM
338S0721 2 SMSC USX2061 U3600,U3700 CRITICAL USBHUB_2061

PAGE TITLE
NON_REM1
0 0
NON_REM0 DESCRIPTION
All ports are removable TABLE_BOMGROUP_HEAD
USB HUB 1 DRAWING NUMBER SIZE
0 1 Port 1 is non removable BOM GROUP BOM OPTIONS <SCH_NUM> D
1 0 Port 1 and 2 are non removable TABLE_BOMGROUP_ITEM Apple Inc. REVISION
HUB1_ALLREM HUB1_NONREM1_0,HUB1_NONREM0_0
1 1 Port 1, 2, and 3 are non removable TABLE_BOMGROUP_ITEM
R
<E4LABEL>
HUB1_1NONREM HUB1_NONREM1_0,HUB1_NONREM0_1 NOTICE OF PROPRIETARY PROPERTY: BRANCH
HUB1_2NONREM HUB1_NONREM1_1,HUB1_NONREM0_0
TABLE_BOMGROUP_ITEM

<BRANCH>
TABLE_BOMGROUP_ITEM THE POSESSOR AGREES TO THE FOLLOWING: PAGE
HUB1_3NONREM HUB1_NONREM1_1,HUB1_NONREM0_1 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
36 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
USB HUB-2
D D
FERR-120-OHM-1.5A
L3758
53 50 48 36 35 34 33 32 31 20 17 8 7 6PP3V3_S3 1 2 PPUSB_HUB2_VDDPLL3V3
101 87 73 72 55 54
VOLTAGE=3.3V
1 C3736
0.01UF
1 C3737
100PF
1 C3738
10UF
1 C3739
0.1UF
PP3V3_S3 6 7 8 17 20 31 32 33 34 35 36 48 50 53 54
55 72 73 87 101
10% 5% 20% 10%

2 16V
CERM
402
2 50V
CERM
402
2 6.3V
X5R
603
2 16V
X7R-CERM
402
1 C3723
0.1UF
1 C3725
0.1UF
C3726
0.01UF
C3729
1
0.01UF
1
10% 10% 10% 10%
2 16V
X7R-CERM 2 16V
X7R-CERM 2 16V
CERM 2 16V
CERM
402 402 402 402
1 C3718
10UF
20% L3729
FERR-120-OHM-1.5A VOLTAGE=3.3V
2 6.3V
X5R MIN_LINE_WIDTH=0.4MM
603 1 2 MIN_NECK_WIDTH=0.2MM PPUSB_HUB2_VDDA3V3
0402 PPUSB_HUB2_VDD1V8
1 C3742
0.01UF
1 C3743
100PF
1 C3744
10UF
1 C3745
0.1UF
1 C3746
0.1UF
1 C3747
0.1UF
VOLTAGE=1.8V
10%
2 16V
CERM
5%
2 50V
CERM
20%
2 6.3V
X5R
10%
2 16V
X7R-CERM
10%
2 16V
X7R-CERM
10%
2 16V
X7R-CERM
PPUSB_HUB2_VDD1V8PLL
1 C3728
0.1UF
1 C3730
1UF
402 402 603 402 402 402 MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.8V
1 C3724
0.1UF
1 C3727
1UF
10%
2 16V
X7R-CERM
10%
2 16V
X5R
10% 10% 402 402
2 16V
X7R-CERM 2 16V
X5R
402 402
53 50 48 36 35 34 33 32 31 20 17 8 7 6 PP3V3_S3
101 87 73 72 55 54
C C
29
10
VDD33PLL 36
VDD33CR 15
VDD33 23
VDD18 14
VDD18PLL 34
5
NOSTUFF HUB2_NONREM0_1
CRITICAL
Y3700
R3797
10K
1 1
R3799
10K
VDDA33
24.000M-60PPM-16PF 5% 5%
1 2 1/16W 1/16W
MF-LF MF-LF
CRITICAL CRITICAL 4022 2 402
5X3.2X1.4-SM
C3719 1 1 C3720 U3700
18PF 5%
R3791
1M 5%
18PF QFN
50V 1 2 2 50V USX2061
CERM 2 CERM USB_HUB2_TEST 11 TEST USBDN1_DM/PRT_DIS_M1 1 USB_BT_N
402 5% 402 BI 33 93
Bluetooth
1/16W OMIT USBDN1_DP/PRT_DIS_P1 2 USB_BT_P BI 33 93
MF-LF 35 IN USB_HUB_RESET_L 26 RESET*
402 3
33 USBDN2_DM/PRT_DIS_M2 USB_TPAD_N BI 53 93
CRITICAL USB_HUB2_XTAL1 XTAL1/CLKIN 4 Trackpad/Keyboard
32 USBDN2_DP/PRT_DIS_P2 USB_TPAD_P BI 53 93
USB_HUB2_XTAL2 XTAL2
USBDN3_DM/PRT_DOS_M3 6 USB_SDCARD_N 8 34 93
USB_HUB2_LOCAL_PWR 28 BI
SUSP_IND/LOCAL_PWR/NON_REM0 7 USB_SDCARD_P SD Card/Express Card
USBDN3_DP/PRT_DIS_P3 BI 8 34 93
USB_HUB2_SMBDATA 22 SDA/SMBDATA/NON_REM1
USBDN4_DM/PRT_DIS_M4 8 USB_EXTA_N 43 93 PP3V3_S3 6 7 8 17 20 31 32 33 34 35 36 48 50 53 54
BI
USB_HUB2_SMBCLK 24 9 USB_EXTA_P External A 55 72 73 87 101
SCL/SMBCLK/CFG_SEL0 USBDN4_DP/PRT_DIS_P4 BI 43 93
1
USB_HUB2_CFG_SEL1 25 HS_IND/CFG_SEL1 PRTPWR1 12 TP_USB_HUB2_PRTPWR1 R3782
53 50 48 36 35 34 33 32 31 20 17 8 7 6 PP3V3_S3 16 NC_USB_HUB2_PRTPWR2
10K
101 87 73 72 55 54 PRTPWR2 5%
NOSTUFF 18 1/16W
HUB2_NONREM1_1 PRTPWR3 NC_USB_HUB2_PRTPWR3 MF-LF
R37921
1
R3794 1
R3798
10K PRTPWR4 20 NC_USB_HUB2_PRTPWR4 4022
R37041 4 NOSTUFF 10K 10K
5% 5% 13
10K VCC
5%
1/16W 1/16W 1/16W IPU OCS1* TP_USB_HUB2_OCS1
5% MF-LF MF-LF 17
1/16W U3714 MF-LF
4022 2402 2402 IPU OCS2* NC_USB_HUB2_OCS2
MF-LF
4022 AT24C02B OCS3* 19 NC_USB_HUB2_OCS3
SOT23-5 IPU IN 8
B 1 C3734
0.1UF
WP_HUB2 5 WP
SDA 3
SCL 1
IPU OCS4* 21
35
USB_EXTA_OC_L IN 43
B
10% RBIAS USB_HUB2_RBIAS
2 16V
X5R GND
27 USB_HUB2_VBUS_DET
402 2 VBUS_DET
HUB2_NONREM1_0 HUB2_NONREM0_0 30 USB_HUB2_UP_N
USBUP_DM
1
R3765 R3766
1
10K
R3767
10K
1
1
R3768 USBUP_DP 31 USB_HUB2_UP_P
BI
BI
19 93
19 93
CRITICAL
1
10K
5% 5% 5% 100 THRML_PAD
R3700
1/16W 1/16W 1/16W 5% 12K
MF-LF MF-LF
37
MF-LF 1/16W 1%
2402 2402 2402 MF-LF 1/16W
2 402 MF
2 402
SEL1 SEL0 DESCRIPTION

K17/K18 configuration: 0 0 Internal Default with Self powered Operation
0 1 SMBUS Slave Config
1 0 Internal Default with Bus powered Operation
1 1 EEPROM Supported
NON_REM1 NON_REM0 DESCRIPTION

A 0 0 All ports are removable TABLE_BOMGROUP_HEAD
SYNC_MASTER=K23F SYNC_DATE=10/06/2009 A
0 1 Port 1 is non removable BOM GROUP BOM OPTIONS PAGE TITLE
1
1
0
1
Port 1 and 2 are non removable
Port 1, 2, and 3 are non removable
HUB2_ALLREM HUB2_NONREM1_0,HUB2_NONREM0_0
TABLE_BOMGROUP_ITEM
USB HUB 2 DRAWING NUMBER SIZE

TABLE_BOMGROUP_ITEM
HUB2_1NONREM HUB2_NONREM1_0,HUB2_NONREM0_1
TABLE_BOMGROUP_ITEM
REVISION
HUB2_2NONREM HUB2_NONREM1_1,HUB2_NONREM0_0 R
TABLE_BOMGROUP_ITEM
<E4LABEL>
HUB2_3NONREM HUB2_NONREM1_1,HUB2_NONREM0_1 NOTICE OF PROPRIETARY PROPERTY: BRANCH
<BRANCH>
37 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BCM57765 SR pins are internal 1.2V switching regulator.
If unused: Okay to float all 4 pins. (Broadcom not so sure now)
If used: VDD/VDDP connect to =PP3V3_ENET_PHY (add bypassing), LX connects to inductor, VFB to =PP1V2_ENET_PHY
TP_BCM57765_SR_VDDP BCM57765_SR_LX 37
BCM57765 BCM57765_SR_VDD BCM57765_SR_VFB CRITICAL
PP3V3_ENET R3915
37 37
L3920
73 37 27 7 6
0 FERR-600-OHM-0.5A PP1V2_ENET 6 7 37 71 72
86mA (1000base-T, Caesar II) 1 2 37 BCM57765_VDDO_PIN20 1 2
MIN_LINE_WIDTH=0.4 mm PP1V2_ENET_PHY_AVDDL 396mA (1000base-T, Caesar II)
CRITICAL 5% MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.4 mm SM
L3900 1/16W
MF-LF
BCM57765 VOLTAGE=3.3V MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.2V
FERR-600-OHM-0.5A 402
R3900 C3921 1 1 C3920
1 2 37 PP3V3_ENET_PHY_XTALVDDH 1
0 2 BCM57765_XTALVDDH 0.1UF 4.7UF
37
MIN_LINE_WIDTH=0.4 mm MIN_LINE_WIDTH=0.4 mm 10% 10%
SM MIN_NECK_WIDTH=0.2 mm 5% MIN_NECK_WIDTH=0.2 mm 16V 2 6.3V
X7R-CERM 2
D VOLTAGE=3.3V
C3900 1
0.1UF
1/16W
MF-LF
402
VOLTAGE=3.3V 402
X5R-CERM
603
CRITICAL
D
10%
16V L3925
CRITICAL X7R-CERM 2 FERR-600-OHM-0.5A
402
L3905 PP1V2_ENET_PHY_PCIEPLL
1 2
FERR-600-OHM-0.5A MIN_NECK_WIDTH=0.2 mm SM
1 2 VOLTAGE=1.2V
PP3V3_ENET_PHY_BIASVDDH
C3926 1 1 C3925
VOLTAGE=3.3V 0.1UF 4.7UF
1 C3905 10%
16V
10%
2 6.3V
0.1UF X7R-CERM 2 X5R-CERM
10% 402 603
2 16V
X7R-CERM CRITICAL
CRITICAL
L3910
402 L3930
FERR-600-OHM-0.5A
FERR-600-OHM-0.5A
PP1V2_ENET_PHY_GPHYPLL 1 2
1 2 PP3V3_ENET_PHY_AVDDH MIN_LINE_WIDTH=0.4 mm
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm SM
SM MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.2V
VOLTAGE=3.3V
R3910 1 1 C3910 1 C3911 C3931 1 1 C3930
4.7K 0.1UF 0.1UF 0.1UF 4.7UF
5% 10% 10% 10% 10%
1/16W 2 16V
X7R-CERM 2 16V
X7R-CERM
16V
X7R-CERM 2 2 6.3V
X5R-CERM
MF-LF 402 402 402 603
402 2
BCM57765 BCM57765
R39401 1
R3941 C3915 1 1 C3916 C3936 1 1 C3935
4.7K 4.7K 4.7UF 0.1UF 0.1UF 10UF
42
48
BIASVDDH 37
VDDC 17
20
56
62
VDDC 14
REGCTL12 15
VDDIO 16
WAKE* 13
39
45
51
29
32
GPHY_PLLVDDL 36
VDDC 35
VDDC 61
10% 10% 10% 10%
7
5% 5% 6.3V
1/16W 1/16W X5R-CERM 2 2 16V
X7R-CERM
16V
X7R-CERM 2 2 6.3V
X5R
C C
VDDIO
XTALVDDH
VDDIO
VDDIO
MF-LF MF-LF 603 402 402 805
69 68 63 62 58 54 52 51 50 48
PP3V3_S0
PCIE_PLLVDDL
25 24 23 21 20 19 18 17 7 6 402 2 2 402 AVDDH AVDDL
47 46 42 40 37 34 30 28 27 26
99 88 87 85 84 83 80 73 72
BCM57765
1
C3950 R3942
1K
0.1uF 5%
PCIE_ENET_D2R_N 1 2 1/16W CRITICAL
94 17 OUT MF-LF
2 402 OMIT
10%
16V C3951 37 BCM57765_VMAIN_PRSNT 58 SMB_DATA (IPD)
U3900 TRD0_P 40 ENET_MDI_P<0> 38 95 CR_BUS_PWR is not for SD Card power,
X5R BI
402 0.1uF BCM5764M 41 ENET_MDI_N<0>
PCIE_ENET_D2R_P 1 2 QFN-8X8 TRD0_N BI 38 95 just decoupling for BCM57765 CR I/Os.
94 17 OUT 94 PCIE_ENET_D2R_C_N 27 PCIE_TXD_N
VERSION 2 TRD1_P 44 ENET_MDI_P<1> BI 38 95
10%
16V
94 PCIE_ENET_D2R_C_P 28 PCIE_TXD_P TRD1_N 43 ENET_MDI_N<1> BI 38 95 BCM57765 BCM57765 BCM57765
C3955 X5R
402 94 PCIE_ENET_R2D_P 33 PCIE_RXD_P TRD2_P 46 ENET_MDI_P<2> BI 38 95 C3970 1 1 C3971 1 C3972
0.1uF TRD2_N 47 ENET_MDI_N<2> BI 38 95
4.7UF 0.1UF 0.1UF
94 PCIE_ENET_R2D_N 34 PCIE_RXD_N 10% 10% 10%
PCIE_ENET_R2D_C_P 1 2 TRD3_P 50 ENET_MDI_P<3> 6.3V 16V 16V
94 17 IN BI 38 95
X5R-CERM 2 2 X7R-CERM 2 X7R-CERM
94 17 PCIE_CLK100M_ENET_P 31 PCIE_REFCLK_P TRD3_N 49 ENET_MDI_N<3> 38 95
603 402 402
10% IN BI
16V C3956 94 17 IN PCIE_CLK100M_ENET_N 30 PCIE_REFCLK_N
X5R
402 0.1uF PP3V3R1V8_SW_SD_VIO
GPIO_0/SERIAL_DO 5
(IPD)
NC MIN_LINE_WIDTH=0.3 mm
94 17 IN PCIE_ENET_R2D_C_N 1 2 95 27 IN ENET_RESET_L 11 PERST* (IPD) MIN_NECK_WIDTH=0.2 mm
GPIO_1/SERIAL_DI 8 VOLTAGE=3.3V BCM57765
BCM57765 ENET_CLKREQ_L 12 CLKREQ* BCM57765_MEDIA_SENSE R3972 0 ENET_ENERGY_DET
R3943 10%
16V 17 OUT (OD) GPIO_2 9 1 2
OUT 17 37
X5R 5% 1/16W MF-LF 402
ENET_WAKE_L 1
0 2 402 BCM57765_WAKE_L 3 LINKLED* (OD) BCM57765
37 27 OUT
NC 1 BCM57765_SD_DETECT R3973 0 1 2 SD_CD_L IN 6 34
(See note) 5%
1/16W
5% 1/16W MF-LF 402
MF-LF 20 IN ENET_LOW_PWR 4 LOW_PWR (IPD) PCIE_VDDL 26 37 BCM57765_CR_CMD R3974 0 1 2 SDCONN_CMD IN 34
WAKE# 402 PLACE_NEAR=L3999.1:1 mm 5% 1/16W MF-LF 402
DC0 21 SDCONN_CLK OUT 34
Must isolate from PCIe WAKE# if PHY 37 BCM57765_SMB_CLK 6 VDDC
is powered-down in S3/S5. Standard BCM57765_SMB_DATA 10 UART_MODE (IPD-BCM5764M) DC4 25 SDCONN_DATA<0> BI 34
N-channel FET isolation suggested. DC3 24 SDCONN_DATA<1> BI 34

37 BCM5764_SCLK 66 SCLK
B 23 SDCONN_DATA<2>
B
(IPU)
If PHY is always powered then alias BCM5764_MISO 64 DC2 BI 34
37 SI
=ENET_WAKE_L to PCIE_WAKE_L. DC1 22 SDCONN_DATA<3> BI 34
BCM5764_MOSI 65 SO
37
BCM5764_CS_L 63 NC 52 BCM57765_CR_DATA<4> R3975 0 1 2 SDCONN_DATA<4> BI 34

CS* 5% 1/16W MF-LF 402
37
VMAIN_PRSNT 53 37 BCM57765_CR_DATA<5> R3976 0 1 2 SDCONN_DATA<5> BI 34
R3977 0 5% 1/16W MF-LF 402

TP_BCM5764_SPD100LED_L 2 SPD100LED* VAUX_PRSNT 54 37 BCM57765_CR_DATA<6> 1 2 SDCONN_DATA<6> BI 34
5% 1/16W MF-LF 402
TP_BCM5764_TRAFFICLED_L 67 TRAFFICLED* VDDC 55 37 BCM57765_CR_DATA<7> R3978 0 1 2 SDCONN_DATA<7> BI 34
5% 1/16W MF-LF 402
SMB_CLK 59 BCM57765_CE_L_MS_INS_L 37 BCM57765
95 27 IN BCM5764_CLK25M_XTALI 18 XTALI All resistors above BOMOPTIONed BCM57765
ENERGY_DET 60 BCM57765_CR_LED 37
95 27 OUT BCM5764_CLK25M_XTALO 19 XTALO
DC5 57 SD_WP IN 6 34
BCM5764_RDAC 38 RDAC SPD1000LED* 68 TP_BCM57765_XD_DET BCM57765 supports both active-levels for WP.
THRM_PAD
PHY Non-Volatile Memory BCM5764M Support
69
1
R3965 All parts below BOMOPTIONed BCM5764M
1.24K
ROM contains MAC address, PCIe config 1% BCM5764M pin-function BCM5764M
1/16W R3980 0 1
info as well as code for Bonjour proxy. MF-LF 60-ENERGY_DET 37 BCM57765_CR_LED 2 ENET_ENERGY_DET 17 37
Required for proper PHY operation. 2 402 5% 1/16W MF-LF 402

13-WAKE* 37 BCM57765_SR_VFB R3981 0 1 2 ENET_WAKE_L (See note) 27 37
(Required ROM size TBD) 5% 1/16W MF-LF 402
73 37 27 7 6 PP3V3_ENET 53-VMAIN_PRSNT 37 BCM57765_CR_DATA<5> R3982 1K 1 2 PP3V3_S0 50 51 52 54 58 62 63 68 69 72
6 7 17 18 19 20 21 23 24 25 26
5% 1/16W MF-LF 402 27 28 30 34 37 40 42 46 47 48
73 80 83 84 85 87 88 99
59-SMB_CLK 37 BCM57765_CE_L_MS_INS_L R3983 4.7K 1 2 PP3V3_ENET 6 7 27 37 73
R3984 4.7K 5% 1/16W MF-LF 402

58-SMB_DATA 37 BCM57765_VMAIN_PRSNT 1 2
R3985 5% 1/16W MF-LF 402
6
1 C3990 54-VAUX_PRSNT 37 BCM57765_CR_DATA<6> 1K 1 2

0.1UF R3986 0 5% 1/16W MF-LF 402
VCC
10% 16-VDDIO 37 BCM57765_SR_LX 1 2
5% 1/16W MF-LF 402
U3990 2 16V
X7R-CERM R3987 0
402 20-XTALVDDH 37 BCM57765_VDDO_PIN20 1 2 PP3V3_ENET_PHY_XTALVDDH 37
AT45DB011D 5% 1/16W MF-LF 402
BCM5764_SCLK 2
SOIC-8S1
BCM5764_MOSI 55-VDDC 37 BCM57765_CR_DATA<7> R3988 0 1 2 PP1V2_ENET 6 7 37 71 72
SI 1 5% 1/16W MF-LF 402
37 SCK
OMIT
37
17-VDDC BCM57765_XTALVDDH R3989 0 1 2
A BCM5764_CS_L 4 14-VDDC
37
37 BCM57765_SR_VDD R3998 0 1 2 5%
5%
1/16W
1/16W
MF-LF
MF-LF
402
402
SYNC_MASTER=T27_REF SYNC_DATE=08/20/2009 A
37 CS*
BCM5764_MISO 06-VDDC 37 BCM57765_SMB_CLK R3999 0 1 2 PAGE TITLE
SO 8
5 WP*
BCM57765 BCM5764M
37
L3999
5% 1/16W MF-LF 402
Ethernet PHY (Caesar II/IV)
3 1 1 FERR-600-OHM-0.5A DRAWING NUMBER SIZE
RESET* R3990 R3997 <SCH_NUM> D
GND 4.7K 4.7K 26-PCIE_VDDL 37 BCM57765_CR_CMD PLACE_NEAR=U3900.26:2 mm 1 2 Apple Inc.
5% 5% REVISION
7
1/16W 1/16W BCM5764M BCM5764M SM CRITICAL R

MF-LF MF-LF
C3999 1 1 C3998 <E4LABEL>
2 402 2 402 Keep net short, NOTICE OF PROPRIETARY PROPERTY: BRANCH
NOTE: Pull-down on SO plus internal pull-ups on with no stubs. 0.1UF 4.7UF
other 3 SPI pins configures BCM57765 for the
10%
16V
10%
2 6.3V
THE INFORMATION CONTAINED HEREIN IS THE <BRANCH>
X7R-CERM 2 X5R-CERM PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Atmel AT45DB011D (1Mbit) ROM. If a different 402 603
ROM is used then the straps must change.
PLACE_NEAR=U3900.26:1 mm PLACE_NEAR=L3999.1:1 mm I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
39 OF 132
NOTE: BCM5764M requires SI pull-down instead of SO.
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
(NONE)
Signal aliases required by this page:
(NONE)
BOM options provided by this page:
(NONE)
D D
Place one of 0.1uf cap close to each centertap pin of transformer
ENETCONN_CTAP
1 C4000 1 C40021 C40041 C4006
0.1UF 0.1UF 0.1UF 0.1UF
10% 10% 10% 10%
2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R
402 402 402 402
CRITICAL
T4000
SM
95 37 BI ENET_MDI_P<0> 1 12 99 ENETCONN_P<0>
95 37 BI ENET_MDI_N<0> 2 11 99 ENETCONN_N<0> CRITICAL
3 10 ENET_CTAP0 J4000
RJ45-M97-3
TX F-RT-TH
TLA-6T213HF 9
C 4 9 ENET_CTAP1 10
C
95 37 BI ENET_MDI_N<1> 5 8 99 ENETCONN_N<1> 1
2
95 37 BI ENET_MDI_P<1> 6 7 99 ENETCONN_P<1> 3
RX 4
5
CRITICAL 6
T4001
SM
7
95 37 BI ENET_MDI_N<2> 1 12 99 ENETCONN_N<2> 8
95 37 BI ENET_MDI_P<2> 2 11 99 ENETCONN_P<2> 11
12
3 10 ENET_CTAP2
TX
514-0636
TLA-6T213HF
4 9 ENET_CTAP3
95 37 BI ENET_MDI_N<3> 5 8 99 ENETCONN_N<3>
95 37 BI ENET_MDI_P<3> 6 7 99 ENETCONN_P<3>
RX
Transformers should be
mirrored on opposite
sides of the board
R4000
75
1R40011
75
1
R4002
75
1R4003
75
5% 5%
1/16W 1/16W
5%
1/16W
5%
1/16W
CRITICAL
B MF-LF
4022
MF-LF
4022
MF-LF
2402
MF-LF
2402
C4008
1000PF B
ENET_BOB_SMITH_CAP
1 2
MIN_NECK_WIDTH=0.25 mm 10%
2KV
CERM
1206
PLACE_NEAR=T4001.1:5mm PLACE_NEAR=T4000.5:5mm
6 5 7 4 9 2 10 1 6 5 7 4 9 2 10 1
NC
IO
NC
IO
NC
IO
NC
IO
NC
IO
NC
IO
NC
IO
NC
IO
D4001 D4000
GND
GND
RCLAMP0524P RCLAMP0524P
SLP2510P8 SLP2510P8
3 3
CRITICAL CRITICAL
PAGE TITLE
Ethernet Connector
DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
40 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PP3V3_FW_FWPHY 6 7 39 40 41
7 mA I/O
138 mA
C4120 1 C4121 1 C4122 1 C4123 1 C4124 1

1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10%
6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2
CERM CERM CERM CERM CERM
402 402 402 402 402
L4130
TABLE_5_HEAD
120-OHM-0.3A-EMI
D PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
TABLE_5_ITEM
114 mA FireWire PHY
PP3V3_FW_FWPHY_VDDA 1 2 D
114S0557 1 RES,0.475 ohm,1%,1/16W,0402 R4100 CRITICAL MIN_LINE_WIDTH=0.4 MM 0402-LF
VOLTAGE=3.3V
C4130 1 C4131 1 C4132 1
1UF 1UF 1UF
10% 10% 10%
6.3V 2 6.3V 2 6.3V 2
CERM CERM CERM
402 402 402
OMIT L4110 L4135

R4100 120-OHM-0.3A-EMI 120-OHM-0.3A-EMI
PP1V0_FW_FWPHY 1
0.2 2 PP1V0_FW_R 1 2 PP1V0_FW_FWPHY_AVDD 25 mA PCIe SerDes 17 mA PCIe SerDes
PP3V3_FW_FWPHY_VP25 1 2
40 7 6
MIN_LINE_WIDTH=0.4 MM 0402-LF MIN_LINE_WIDTH=0.4 MM MIN_LINE_WIDTH=0.4 MM 0402-LF
135 mA 1% MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM
1/16W VOLTAGE=1.0V VOLTAGE=1.0V VOLTAGE=3.3V
MF-LF
402
1 C4110 1 C4111 C4135 1 C4136 1
1UF 1UF 1UF 1UF
10% 10% 10% 10%
2 6.3V
CERM 2 6.3V
CERM
6.3V 2
CERM
6.3V 2
CERM
402 402 402 402
110 mA Digital Core 0 mA VReg PWR
1 C4100 1 C4101 1 C4102 1 C4103 1 C4104 1 C4105 1 C4106 C4141 1 1 C4140

1UF 1UF 1UF 1UF 1UF 1UF 1UF 0.1UF 1UF
10% 10% 10% 10% 10% 10% 10% 20% 10%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
10V
CERM 2 2 6.3V
CERM
402 402 402 402 402 402 402 402 402
C PLACEMENT_NOTE=Place C4170 close to U1800

PLACEMENT_NOTE=Place C4171 close to U1800
C
B12
C13
E10
H12
M12
N11
C12
G12
L11
A12
L10
K12
C4170
1 10%
2 16V PCIE_FW_R2D_C_N
A1
B1
E2
H2
K2
L1
N3
C1
F1
J1
L3
M2
D5
D6
D8
L5
L6
L9
IN 17 94
0.1UF X5R 402
VDD10 VDD33 VDDH VP VP25 VREG_PWR C4171
1 10%
2 16V PCIE_FW_R2D_C_P IN 17 94
B13 ATBUSB OMIT N8 PCIE_FW_R2D_N 0.1UF X5R 402
NC PCIE_RXD0N 94
A13 ATBUSH CRITICAL N7 PCIE_FW_R2D_P

PCIE_RXD0P 94
NC
A11 ATBUSN
U4100 PCIE_TXD0N N5 94 PCIE_FW_D2R_C_N C4175
1 2 16V
10% PCIE_FW_D2R_N
NC 0.1UF OUT 17 94
FW643 PCIE_TXD0P N6 94 PCIE_FW_D2R_C_P X5R 402

41 IN FWPHY_DS0 F12 DS0 (IPD) NT-19
C4176
1 10%
2 16V
BGA PCIE_FW_D2R_P OUT 17 94
41 IN FWPHY_DS1 E12 DS1 (IPD) NT-20 0.1UF X5R 402
REFCLKN N9 PCIE_CLK100M_FW_N IN 17 94
41 IN FWPHY_DS2 E13 DS2 (IPD) NT-21 PCI EXPRESS PHY PLACEMENT_NOTE=Place C4175 close to U4100
REFCLKP N10 PCIE_CLK100M_FW_P IN 17 94 PLACEMENT_NOTE=Place C4176 close to U4100
96 41 BI NC_FW0_TPAN B8 TPA0N
96 41 6 BI NC_FW0_TPAP A8 TPA0P
NT-4 (IPU) TCK M4 TP_FW643_TCK
96 41 40 BI FW_PORT1_TPA_N B5 TPA1N
NT-3 (IPU) TDI N2 NC_FW643_TDI 6
96 41 40 BI FW_PORT1_TPA_P A5 TPA1P TEST CONTROLLER PP3V3_FW_FWPHY 6 7 39 40 41
(IPU) TDO M1 TP_FW643_TDO
41 6 BI NC_FW2_TPAN B3 TPA2N
NT-1 (IPU) TMS M3 TP_FW643_TMS
41 6 BI NC_FW2_TPAP A3 TPA2P 1394 PHY FW643_LDO
96 41 6 BI NC_FW0_TPBN B9 TPB0N NT-2 (IPU) TRST* N1 FW643_TRST_L R41651 1
R4166
96 41 6 BI NC_FW0_TPBP A9 TPB0P 10K 10K
5% 5%
96 41 40 BI FW_PORT1_TPB_N B6 TPB1N 1/16W 1/16W
MF-LF MF-LF
96 41 40 BI FW_PORT1_TPB_P A6 TPB1P 402 2 2 402
NT-10 (IPD) WAKE* C2 FW643_WAKE_L OUT 8 40
41 6 BI NC_FW2_TPBN B4 TPB2N
41 PPVP_FW_CPS FIXME!!! - TYPO IN SYMBOL REGCTL REGCLT D13 FW643_REGCTL
41 6 BI NC_FW2_TPBP A4 TPB2P
POWER MANAGEMENT VAUX_DETECT E1 FW643_VAUX_DETECT
R41601 41 BI NC_FW0_TPBIAS B7 TPBIAS0 NT-12 (IPD) VAUX_DISABLE D2 TP_FW643_VAUX_ENABLE
B 200K
1%
1/16W
41 40
41 6
BI
BI
FW_P1_TPBIAS
NC_FW2_TPBIAS
C3 TPBIAS1
A2 TPBIAS2
NT-13 (OD) CLKREQN L2 FW_CLKREQ_PHY_L OUT 40
1
R4164
10K
B
MF-LF 5%
402 2 1/16W
FW643_R0 B11 R0 MF-LF
PLACE_NEAR=U4100.B10:2mm 2 402
FW643_TPCPS B10 TPCPS
NT-16 (IPD) SCIFCLK G2 TP_FW643_SCIFCLK
SCIF NT-14 (IPD) SCIFDAIN G1 TP_FW643_SCIFDAIN
C4150 TP_FW643_NAND_TREE K1 NAND_TREE NT-OUT
R4150 NT-17 SCIFDOUT H1 TP_FW643_SCIFDOUT
22PF FW643_REXT L8 REXT
1 2 412 NOTE: NT-xx notes show NT-15 (IPD) SCIFMC F2 TP_FW643_SCIFMC
FW_CLK24P576M_XO 1 2 FW_CLK24P576M_XO_R F13 XO
NAND tree order.
5% CRITICAL 1% FW_CLK24P576M_XI G13 XI NT-9
1/16W
50V Y4150 MF-LF
1
CERM 402 TP_FW643_SE M13 SE (IPD)

402 NC 24.576MHZ R41611 1
R4170 SERIAL EEPROM NT-7 SCL N12 FW643_SCL
2 4
SM-3.2X2.5MM TP_FW643_SM N13 SM (IPD)

C4151 NC 2.94K
1%
191
1% TP_FW643_MODE_A J2 MODE_A (IPD) NT-18
CONTROLLER NT-6 SDA M11 TP_FW643_SDA
3
22PF 1/16W 1/16W

TP_FW643_CE L13
1 2 MF-LF MF-LF CE (IPD)
402 2 2 402 TP_FW643_FW620_L D12 FW620* (IPU) MISCELLANEOUS
5% TP_FW643_JASI_EN D1 JASI_EN (IPD) NT-11
50V
CERM 6 NC_FW643_AVREG A10 AVREG CHIP RESET NT-5 PERST* N4 FW_RESET_L 40
402 IN
TP_FW643_VBUF H13 VBUF
FW643_PU_RST_L K13 1
FW_RESET* (IPU) NT-8 R4163
TP_FW643_OCR10_CTL J12 OCR_CTL_V10 10K
5%
R41621 1 C4162 NC
J13 OCR_CTL_V12 (Reserved) 1/16W
MF-LF
470K 0.33UF 2 402
5% 10% VSS VREG_VSS
1/16W
MF-LF 2 6.3V
B2
D4
D7
D9
D10
E4
E5
E9
F4
F6
F7
F8
F10
G4
G6
G7
G8
G10
H4
H6
H7
H8
H10
J4
J5
J9
J10
K4
K5
K7
K8
K9
L7
K6
K10
L12
402 2 CERM-X5R
402
PAGE TITLE
FireWire LLC/PHY (FW643)

DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
41 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
- =PPBUS_S5_FWPWRSW (system supply for bus power)

3.3V FW FET
- =PP3V3_FW_LATEVG_ACTIVE
I(max) = 1.7A (85C)
- =PPVP_FW_SUMNODE (power passthru summation node)
99
68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6 PP3V3_S0
47 46 42 40 37 34 30 28 27 26
(NONE)
88 87 85 84 83 80 73 72 69
U4201
C4201 1 TPS22924 99
68 63 62 58 54 52 51 50 48 PP3V3_S0
CSP
1UF
10%
A2 A1 PP3V3_FW_FWPHY 6 7 39 40 41
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
88 87 85 84 83 80 73 72 69
6.3V 2 B2 VIN VOUT B1 1
CERM
402
R4281
CRITICAL 100K
R4280 5%
D 40 20 IN FW_PWR_EN C2 ON
GND 40 39 7 6 PP1V0_FW_FWPHY 1
10K 2
1/16W
MF-LF
2 402
D
PP3V3_FW_FWPHY
C1
41 40 39 7 6 1%
1/16W
MF-LF
402
3 CRITICAL
FW_PLUG_DET_L OUT 8 20 40 Q4299
P1V0_FW_RC 5
R4277
10K
1 1
R4276
100K 1.05V FW FET DMB53D0UV
SOT-563
5%
1/16W
5%
1/16W
40 26
10 7 6PP1V05_S0
25 24 23 21 20 18 17 15 13 12
C4281 1 4
MF-LF
402 2
MF-LF 86 73 70
U4202 1UF
10%
2 402 C4202 1 TPS22924 6.3V
3 CRITICAL CSP CERM 2
1UF A2 A1 PP1V0_FW_FWPHY 6 7 39 40
402
FW_WAKE 5 Q4276 10%
6.3V 2 B2 VIN VOUT B1
DMB53D0UV CERM
402 CRITICAL
SOT-563
NOSTUFF C2 ON
4
1 C4276 GND P1V0_RESET_GATE
0.1UF
C1
10%
16V
2 X5R R4283
402 1
10K 2 PLT_RESET_L IN 19 27 31
FW_CLKREQ_L OUT 17 25 5%
CRITICAL 6 1/16W
MF-LF
CRITICAL 6 402
D Q4276
DMB53D0UV D Q4299
39 8 FW643_WAKE_L 2 G
SOT-563
Q4261 D 3 DMB53D0UV
IN SSM6N15FEAPE 2 G
SOT-563
SOT563
FW_RESET_L OUT 39
S 5 G S 4
C 1 S
1
C
PP1V05_FW PGOOD/FW_RESET_L
40
40 39 IN FW_CLKREQ_PHY_L 39 FW_CLKREQ_PHY_L
MAKE_BASE=TRUE
FireWire Port Power Switch
CRITICAL
Q4260 CRITICAL
CRITICAL
NDS9407 F4260 D4260
SOI-HF 1.1A-24V SM
8 PPBUS_FW_FWPWRSW_F 1 2 PPBUS_FW_FWPWRSW_D 1 2 PPVP_FW 6 7 41
86 82 70 69 67 66 65 49 7 6 PPBUS_G3H 3
7 MIN_LINE_WIDTH=0.5 mm MIN_LINE_WIDTH=0.5 mm
89
2 MIN_NECK_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm
6 VOLTAGE=12.6V MINISMDC110H24 VOLTAGE=12.6V CRS08-1.5A-30V
1 1
R4260 C4260 1 5
470K 0.1UF
1 5% 10%
R4262 1/16W
MF-LF 25V 2
X5R 4
10K 2 402 402
5%
1/16W
MF-LF FWPWR_EN_L_DIV
402 2
4
B S (SYM-VER2)
SOT-363 PP1V05_S0
B
FWPWR_EN_TRI 1 21 20 18 17 15 13 12 10 7 6
5
G BSS8402DW R4261 86 73 70 40 26 25 24 23
Q4262 330K
5%
R42631 D 1/16W
MF-LF 1 1
10 3 2 402
1
R4275 R4270 R4271
5% FW_PLUG_DET_L
1/16W 1K 330K 56K OUT 8 20 40
MF-LF 5% 5% 5%
402 2 1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF
FWPWR_EN_TRI_R 2 402 2 402 2 402 3 CRITICAL
FWPWR_EN_L
FW_PWR_EN_L FW_DET_MIRROR FW_PLUG_DET 5 Q4275
6 D 6 DMB53D0UV
Late-VG Protection Q4261 NOSTUFF SOT-563
D SSM6N15FEAPE C4261 1 CRITICAL 3 6 CRITICAL 4
Q4262 SOT563
0.1UF Q4270 Q4270
1 C4270
BSS8402DW 10% BC847CDXV6TXG 5 2 BC847CDXV6TXG 0.1UF
69 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6 PP3V3_S0 2 G 25V 2
X5R SOT563 SOT563
10%
16V
47 46 42 40 37 34 30 28 27 26 SOT-363 402 2 X5R
99 88 87 85 84 83 80 73 72 S (SYM-VER1) 2 G S 1
PLACE_NEAR=U4200.1:2mm 4 1 402
1 C4200 1
0.1UF FW_P1_TPBIAS_R FW_DET_EMIT
10%
2 16V
X5R 1 1
402 R4272 R4273
1K 12K
1
VCC CRITICAL 6 5% 5%
1/16W 1/16W
PLACE_NEAR=J4310.1:2mm
U4200 D Q4275 MF-LF MF-LF
TPD4S1394 2 402 2 402
FW_PORT1_TPB_P 8 D1+ LLP
TP_FW_LATEVG_VCLMP DMB53D0UV
96 41 39 BI VCLMP 3 SOT-563 PLACE_NEAR=C4360.1:2mm
96 41 39 BI FW_PORT1_TPB_N 7 D1- 40 20 IN FW_PWR_EN 2 G
FWPWR_EN 4 FWPWR_EN
A 96 41 39
96 41 39
BI FW_PORT1_TPA_P
FW_PORT1_TPA_N
6 D2+
5 D2-
CRITICAL
BI 1 PAGE TITLE
GND R4201 S
FireWire Port Power
2
100K
5% 1
1/16W DRAWING NUMBER SIZE
MF-LF
2 402 Apple Inc. <SCH_NUM> D
REVISION
R
<E4LABEL>
FW_P1_TPBIAS NOTICE OF PROPRIETARY PROPERTY: BRANCH
41 39 IN
<BRANCH>
42 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
41 40 39 7 6 PP3V3_FW_FWPHY
- =PPVP_FW_PORT1
- =PP3V3_FW_LATEVG R43821 R43801
10K 10K
1% 1%
1/16W 1/16W
MF-LF MF-LF
- =GND_CHASSIS_FW_PORT1 402 2 402 2
- =GND_CHASSIS_FW_EMI_R
41 39 FWPHY_DS0 FWPHY_DS0 39 41
(NONE)
FireWire PHY Config Straps 41 39
MAKE_BASE=TRUE
FWPHY_DS2 FWPHY_DS2
D
D NOTE: This page is expected to contain
Configures PHY for:
MAKE_BASE=TRUE
39 41
the necessary aliases to map the 41 39 FWPHY_DS1 FWPHY_DS1 39 41

MAKE_BASE=TRUE
FireWire TPA/TPB pairs to their - 1-port Portable Power Class (0)
appropriate connectors and/or to
properly terminate unused signals. - Port "1" Bilingual (1394B) R43811
10K
1%
BOM options provided by this page: 1/16W
MF-LF
(NONE) 402 2
NOTE: FireWire TPA/TPB pairs are NOT

constrained on this page. It is
assumed that FireWire PHY page will
provide the appropriate constraints 41 39 NC_FW0_TPBIAS NC_FW0_TPBIAS MAKE_BASE=TRUE 39 41
to apply to entire TPA/TPB XNets. 41 39 6 NC_FW2_TPBIAS NC_FW2_TPBIAS MAKE_BASE=TRUE 6 39 41
96 41 39 NC_FW0_TPAN NC_FW0_TPAN MAKE_BASE=TRUE 39 41 96

1394b implementation based on Apple
96 41 39 6 NC_FW0_TPAP NC_FW0_TPAP MAKE_BASE=TRUE 6 39 41 96
FireWire Design Guide (FWDG 0.6, 5/14/03)
41 39 6 NC_FW2_TPAN NC_FW2_TPAN MAKE_BASE=TRUE 6 39 41
41 39 6 NC_FW2_TPAP NC_FW2_TPAP MAKE_BASE=TRUE 6 39 41
96 41 39 6 NC_FW0_TPBN NC_FW0_TPBN MAKE_BASE=TRUE 6 39 41 96
96 41 39 6 NC_FW0_TPBP NC_FW0_TPBP MAKE_BASE=TRUE 6 39 41 96
Termination 41 39 6 NC_FW2_TPBN
NC_FW2_TPBP
NC_FW2_TPBN
NC_FW2_TPBP
MAKE_BASE=TRUE 6 39 41
41 39 6 MAKE_BASE=TRUE 6 39 41
Place close to FireWire PHY
BSS8402DW
TI PHYs require 1uF even though
FW_P1_TPBIAS
Q4300
40 39
FW spec calls out 0.33uF
SOT-363
(SYM-VER2)
C 1 C4360 C
0.33UF
10%
2 6.3V
CERM-X5R Cable Power
PPVP_FW
D
402
3
41 40 7 6
41 39 PPVP_FW_CPS MAKE_BASE=TRUE PPVP_FW_CPS 39 41 CRITICAL
L4310 Note: Trace PPVP_FW_PORT1 must handle up to 5A
VOLTAGE=12.6V FERR-250-OHM
R43111 41 40 7 6 PPVP_FW
G
470K 1 2 PPVP_FW_PORT1_F
5
5% SM MIN_LINE_WIDTH=0.5 mm
1/16W MIN_NECK_WIDTH=0.25 mm
MF-LF VOLTAGE=33V
402 2 1 C4314
0.01UF
10%
CPS_EN_L_DIV 2 50V
X7R
402
R43121
1
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
R4360 R43611
330K
5%
PORT 1
1/16W
56.2 56.2 MF-LF BILINGUAL
1% 1% 402 2
1/16W 1/16W CPS_EN_L
MF-LF MF-LF
PLACE_NEAR=U4100.A5:2mm 2 402 402 2 PLACE_NEAR=U4100.B5:2mm
96 41 40 39 FW_PORT1_TPA_P FW_PORT1_TPA_P 39 40 41 96 6 CRITICAL

MAKE_BASE=TRUE
FW_PORT1_TPA_N FW_PORT1_TPA_N D J4310
96 41 40 39 39 40 41 96 1394B-M97
MAKE_BASE=TRUE Q4300 F-RT-TH
96 41 40 39 FW_PORT1_TPB_P FW_PORT1_TPB_P 39 40 41 96
2 G BSS8402DW TPB- TPB(R)
MAKE_BASE=TRUE 41 40 39 7 6 PP3V3_FW_FWPHY 96 41 40 39 FW_PORT1_TPB_N 1 TPB-
SOT-363
96 41 40 39 FW_PORT1_TPB_N FW_PORT1_TPB_N 39 40 41 96
S (SYM-VER1) (FW_PORT1_BREF) 9 TPB<R> OUTPUT
MAKE_BASE=TRUE
SIGNAL_MODEL=EMPTY 1 96 41 40 39 FW_PORT1_TPB_P 2 TPB+ TPB+
VP
PLACE_NEAR=U4100.B6:4mm 1 SIGNAL_MODEL=EMPTY PLACE_NEAR=U4100.A6:4mm 8 VP

R4362 R43631
B 56.2
1%
56.2
1% (GND_FW_PORT1_VG)
NC 7
6
NCSC/NC
VG
B
1/16W 1/16W
MF-LF MF-LF 96 41 40 39 FW_PORT1_TPA_N 3 TPA- TPA-
VG
2 402 402 2
FW_PORT1_AREF 5 TPA<R> INPUT
96 41 40 39 FW_PORT1_TPA_P 4 TPA+ TPA(R)
TPA+
FW_PORT1_TPB_C
10
11
1 C4364 R4364
1 C4319 1 12 CHASSIS
4.99K 0.1uF GND
220pF 1% 10% 13
5% 1/16W 50V 2
2 25V
CERM MF-LF X7R
603-1
402 402 2
1
R4319 AREF needs to be isolated from all
1M
5% local grounds per 1394b spec 514S0605
1/16W
MF-LF
2 402 When a bilingual device is connected to a
beta-only device, there is no DC path
between them (to avoid ground offset issue)
PLACEMENT_NOTE=Place C4319 close to connector pin 5.
BREF should be hard-connected to logic

ground for speed signaling and connection
PAGE TITLE
FireWire Ports
DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
43 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ODD Power Control SATA ODD Connector
CRITICAL
CRITICAL
Q4590
TPCP8102 PP5V_SW_ODD_R
FL4520
90-OHM-100MA
42
67 66 61 58 56 54 46 44 43 42 33 31 7 6 PP5V_S3 DLP11S
SYM_VER-1
101 82 72 23V1K-SM
J4500 connection separated to CRITICAL C4521 1
7 8
3 4 SATA_ODD_R2D_UF_P 2 SATA_ODD_R2D_C_P
3
99 17 93
IN
support debug sense resistor. J4500 10% 16V CERM 402
0.01UF
1 2
D
R45961 C4595 1 Alias together if no sense R. 54722-0164
6
F-ST-SM
100K 0.068UF 2 1 SATA_ODD_R2D_UF_N C4520 1 2 SATA_ODD_R2D_C_N
5
99 17 93
10% 1 2 IN
G
5% 10V 10% 16V CERM 402
1/16W CERM 2 SATA_ODD_R2D_P 0.01UF
4
MF-LF 3 4 93 6
D 402 2
R4595
402
C4596 5 6 93 6 SATA_ODD_R2D_N
CRITICAL
D
0.01UF 56 42 6 PP5V_SW_ODD 7 8
NOTE: 3.3V must be S0 if 5V is S3 or S5 to 100K 2 1 2 FL4525
ODD_PWR_EN_LS5V_L 1 ODD_PWR_SS 9 10 99 SATA_ODD_D2R_UF_N
ensure the drive is unpowered in S3/S5. 5% 11 12 99 SATA_ODD_D2R_UF_P
90-OHM-100MA
DLP11S
99 1/16W 10% SYM_VER-1
68 63 62 58 54 52 51 50 48
PP3V3_S0 MF-LF 16V 13 14
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
88 87 85 84 83 80 73 72 69
Q4596 D 6 402 CERM
402 15 16
4 3 93 6 SATA_ODD_D2R_C_N C4526 1 2 SATA_ODD_D2R_N OUT 17 93
SSM6N15FEAPE 69 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6 PP3V3_S0 0.01UF 10% 16V CERM 402
1 SOT563
R4597 47 46 42 40 37 34 30 28 27 26
99 88 87 85 84 83 80 73 72
C4525 1
100K 1 2 93 6 SATA_ODD_D2R_C_P 2 SATA_ODD_D2R_P OUT 17 93
5%
1/16W R45901 516S0616 0.01UF 10% 16V CERM 402
MF-LF 2 G S 1 33K
402 2 5%
1/16W
MF-LF
ODD_PWR_EN 402 2
45 6 OUT SMC_ODD_DETECT
Q4596 D 3
SSM6N15FEAPE Indicates disc presence
SOT563
5 G S 4
PS8511A / PS8515A Straps
20 IN ODD_PWR_EN_L 99 73 72 42 31 16 13 7 6 PP1V5_S3RS0
NO STUFF RDRV:8515A1&RDRV:8515A2
XW4598 R45112 2
R4515 2
R4517
SM 10K 10K 10K NO STUFF
5% 5% 5%
PP5V_SW_ODD_R 1 2 PP5V_SW_ODD 1/16W 1/16W 1/16W
42
MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.4mm
MIN_NECK_WIDTH=0.4mm
6 42 56
PS8511A: MF-LF
402 1
MF-LF MF-LF
VOLTAGE=5V VOLTAGE=5V PIN NAME 1 402 1 402
9 A_PRE (IPD) SATARDRVR_A_B_SD

C 8 B_PRE (IPD) SATARDRVR_A_I2C_ADDR
42
42
C
20 A_BST# (IPU) SATARDRVR_A_A_SD 42
10 B_BST# (IPU) SATARDRVR_A_I2C_EN 42
SATA HDD/IR/SIL Connector NO STUFF

RDRV:8515A1&RDRV:8515A2
NO STUFF R45122
10K
NO STUFF
2
R4516
10K
2
NO STUFF
R4518
10K
PLACE_NEAR=J4501.9:3mm R45191 1
R4520 5%
1/16W
5%
1/16W
5%
1/16W
10K 10K MF-LF MF-LF MF-LF
CRITICAL 5% 5% 402 1 1 402 1 402
L4500 XW4599
SM
1/16W
MF-LF
1/16W
MF-LF
PLACE_NEAR=L4500.1:2mm FERR-70-OHM-4A PP5V_S0_HDD_R 1 2 PP5V_S0 6 7 23 47 52 54 68 69 70 72 86
402 2 2 402
PP5V_S0_HDD_FLT 1 2 MIN_LINE_WIDTH=0.6mm 88 RDRV:8515A1&RDRV:8515A2
6 MIN_NECK_WIDTH=0.4mm
MIN_NECK_WIDTH=0.4mm 0603 VOLTAGE=5V R4513
VOLTAGE=5V 0 19 A_EQ (IPD)
2 C4501 2 C4502 88 63 48 47 32 30 28 26 25 17
94 IN SMBUS_PCH_CLK 2 1 SATARDRVR_A_I2C_SCL 42
0.1UF 0.1UF 5%
20% 20% PLACE_NEAR=L4500.2:2mm 1/16W RDRV:8515A1&RDRV:8515A2
10V 10V
1 CERM
402
1 CERM
402
MF-LF
402 R4514
0 18 B_EQ (IPD)
66 61 58 56
42 33 31 7 6 PP5V_S3 88 63 48 47 32 30 28 26 25 17 IN SMBUS_PCH_DATA 2 1 SATARDRVR_A_I2C_SDA 42
54 46 44 43 94
101 82 72 67 5%
1/16W
2
R4532 CRITICAL
MF-LF
402
10
5%
1/16W
J4501 IR_RX_OUT OUT 6 44 PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
MF-LF 54722-0224
402 1
6 PP5V_S3_IR_R
1
3
F-ST-SM
2
4
6 SYS_LED_ANODE_R
R4531
2
4.7 1 SYS_LED_ANODE IN 6 46
SATA Redriver 338S0769
338S0778
1
1
SATA 3GB/S REDRIVER, LOW POWER
SATA 3GB/S REDRIVER, LOW POWER
U4510
U4510
CRITICAL
CRITICAL
RDRV:8511
RDRV:8515A1
MIN_NECK_WIDTH=0.2mm 5%
VOLTAGE=5V NC 1/16W
5 6 C4531 1 MF-LF
402 PLACE_NEAR=U4510.16:3mm PP1V5_S3RS0 BOMOPTIONs:
0.001UF 6 7 13 16 31
B 1 C4532
0.1UF
NC
7
9
8
10
NC 10%
50V
CERM 2
PLACE_NEAR=U4510.16:3mm 42 72 73 99 - RDRV:8511 stuffs PS8511A & associated parts (STRAPS TBD!!!)
- RDRV:8515A1&RDRV:8515A2 stuffs PS8515A & associated parts
B
10% 11 12 402 RDRV:8511&RDRV:8515A1&RDRV:8515A2
(All 4 C’s) - RDRV:NO stuffs bypass path (neither IC or associated parts stuffed)
16V
2 X7R-CERM 13 14 RDRV:8511&RDRV:8515A1&RDRV:8515A2
C4514 1 1 C4519
CRITICAL CRITICAL
402 1UF 0.01UF
16
15 16 10% 10% RDRV:8515A2
C4516 1
6
17 18
93 6 SATA_HDD_D2R_C_P 2 2
R4510 6.3V
CERM-X5R 2
16V
2 CERM (All 4 C’s) FL4502
90-OHM-100MA
10% 16V 10K 402 402
19 20 0.01UF CERM 402 (C4514, VDD RDRV:8511&RDRV:8515A1&RDRV:8515A2 DLP11S
SYM_VER-1
5%
21 22 SATA_HDD_D2R_C_N C4515 1 2 1/16W C4519 & R4510) U4510 SATA_HDD_D2R_RDRV_OUT_P C4518 1 2 SATA_HDD_D2R_UF_P 3 4 SATA_HDD_D2R_P
93 6 MF-LF 93 99
OUT 17 93
0.01UF 10% 16V 1 402 PS8515A-A2 0.01UF 10% 16V

CERM 402 CERM 402
TQFN
93 SATA_HDD_D2R_RDRV_IN_P 1 A_INP A_OUTP 15 93 SATA_HDD_D2R_RDRV_OUT_N C4517 1 2 99 SATA_HDD_D2R_UF_N 2 1 SATA_HDD_D2R_N OUT 17 93
516S0687 93 SATA_HDD_D2R_RDRV_IN_N 2 A_INN A_OUTN 14 0.01UF 10% 16V

CERM 402
CRITICAL 4
93 SATA_HDD_R2D_RDRV_OUT_N B_OUTN B_INN 12
FL4501 93 SATA_HDD_R2D_RDRV_OUT_P 5 B_OUTP B_INP 11 93 SATA_HDD_R2D_RDRV_IN_N C4513 1 2 SATA_HDD_R2D_C_N IN 17 93
90-OHM-100MA
DLP11S 25 17 IN SATARDRVR_A_EN 7 0.01UF 10% 16V
CERM 402
SYM_VER-1
EN (IPU)
3 4 99 SATA_HDD_R2D_UF_N C4511 1 2 SATARDRVR_A_AUTOPWR_EN 17 AUTOPW_EN 93 SATA_HDD_R2D_RDRV_IN_P C4512 1 2 SATA_HDD_R2D_C_P IN 17 93
93 6 SATA_HDD_R2D_N 10% 16V (IPD) 10% 16V
0.01UF 10 0.01UF
93 6 SATA_HDD_R2D_P CERM 402 42 SATARDRVR_A_I2C_EN I2C_EN (IPD) A_SD 20 SATARDRVR_A_A_SD 42 CERM 402
2 1 99 SATA_HDD_R2D_UF_P C4510 1 2 42 SATARDRVR_A_I2C_ADDR 8 I2C_ADDR B_SD 9 SATARDRVR_A_B_SD 42
10% 16V (IPD)
0.01UF CERM 402 SATARDRVR_A_I2C_SCL 19 PS8515A:
42 SCL_CTL
SATARDRVR_A_I2C_SDA 18 x_SD pins are outputs (All 4 R’s, 2 C’s)
42 SDA_CTL
SIGNAL_MODEL=EMPTY
NOTE: Internal pulls are ~150K GND THRM RDRV:NO
PAD
10PF
C4582 1
3
13
21
338S0848 (PS8515A2) 2 5% 50V
Addr: 0x94(Wr)/0x95(Rd) CERM 402

(All 4 C’s)
A SIGNAL_MODEL=EMPTY
Redriver Bypass Path R4580 1 2
1% 1/16W
SYNC_MASTER=T27_REF SYNC_DATE=10/01/2009 A
RDRV:NO 51.1 MF-LF 402 PAGE TITLE
C4580 1 2 SATA_HDD_R2D_NORDRV_P C4583 1

10PF
2 5% 50V
SATA Connectors
10% 16V DRAWING NUMBER SIZE
0.01UF CERM 402 CERM 402
C4581 1 2 SATA_HDD_R2D_NORDRV_N R4581 1 2 REVISION
1% 1/16W R
0.01UF 10% 16V
CERM 402 51.1 MF-LF 402 <E4LABEL>
C4585 1 2 SATA_HDD_D2R_NORDRV_N R4585 1 2 THE INFORMATION CONTAINED HEREIN IS THE <BRANCH>
5% 1/16W PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
0.01UF 10% 16V 0 MF-LF 402 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
CERM 402
C4586 1 2 SATA_HDD_D2R_NORDRV_P R4586 1 2
45 OF 132
5% 1/16W SHEET
0.01UF 10% 16V 0 MF-LF 402 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
CERM 402 IV ALL RIGHTS RESERVED 42 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
Port Power Switch Left USB Port A

CRITICAL CRITICAL
Q4690 L4605
FERR-220-OHM-2.5A
TPS2064DGN
C 72 67 66 61 58 56 54 46 44 42 33 31 7 6
101 82
PP5V_S3 2 IN
MSOP
OUT1
7 PP5V_S3_RTUSB_A_ILIM
1 2 6 PP5V_S3_RTUSB_A_F
C
72 46 45 31 18 PM_SLP_S4_L 36 USB_EXTA_OC_L 8
OC1* VOLTAGE=5V VOLTAGE=5V CRITICAL
73
OUT
3 EN1 OUT2 6 PP5V_S3_RTUSB_B_ILIM C4605 1
J4600
MIN_LINE_WIDTH=0.5 mm 0.01uF USB
1 USB_EXTB_OC_L 5 OC2* 20%
R4690 35 OUT MIN_NECK_WIDTH=0.375 mm
VOLTAGE=5V 16V CRITICAL F-RT-TH-M97-4
5.1K 4
EN2
CERM 2
402 L4600
90-OHM-100MA
5
5% 6
1/16W DLP11S
MF-LF USB_PWR_EN GND TPAD SYM_VER-1
2 402 1 9 CRITICAL CRITICAL 99 USB2_EXTA_MUXED_N 4 3 99 6 USB2_LT1_N 1

C4690 1 1 C4691 C4695 1
10UF 0.1UF
10UF
1
C4696 C4617
10UF
1 1
C4616 2
C4692 1 20%
6.3V 2
20%
2 10V 20%
100UF
20% 20%
100UF
20%
99 USB2_EXTA_MUXED_P 1 2 99 6 USB2_LT1_P 3
0.47UF X5R CERM 6.3V 2 2 6.3V 6.3V 2 2 6.3V 4
10% 603 402 X5R POLY-TANT X5R POLY-TANT
10V 2 603 CASE-B2-SM 603 CASE-B2-SM
X5R 2 5 3 4
402 7
NC
IO
NC
IO
6 VBUS 8
1 GND
D4600
RCLAMP0502N
SLP1210N6
CRITICAL
CRITICAL
We can add protection to 5V if we want, but leaving NC for now
L4615
FERR-220-OHM-2.5A
1 2 6 PP5V_S3_RTUSB_B_F Place L4600 and L4605 at connector pin
VOLTAGE=5V
B 1 C4615 B
0.01uF
20%
2 16V
CERM
402
CRITICAL
J4610
USB/SMC Debug Mux USB
F-RT-TH-M97-4
5
SMC_DEBUG_YES CRITICAL 6
73 66 65
PP3V42_G3H
L4610
90-OHM-100MA
45 23 21 17 7 6
64 53 49 48 47 46 DLP11S
SYM_VER-1 1
1 USB_EXTB_N 4 3 USB_LT2_N 2
SMC_DEBUG_YES R4650 93 35 BI 99 6
C4650 1 10K 99 6 USB_LT2_P 3

9
0.1UF 5% 4
20% 1/16W
10V VCC MF-LF 93 35 BI USB_EXTB_P 1 2
CERM 2 2 402
47 46 45 6 SMC_RX_L 402 5 M+ Y+ 1 7
IN
47 46 45 6 OUT SMC_TX_L 4 M-
U4650 Y- 2 2 5 3 4 8
NC
IO
NC
IO
PI3USB102ZLE 6 VBUS
93 36 USB_EXTA_P 7 D+ TQFN
BI
USB_EXTA_N 6 D- CRITICAL 1 GND
93 36 BI
8 OE* SEL 10 USB_DEBUGPRT_EN_L IN 45
GND SEL=0 Choose SMC D4610

RCLAMP0502N
SEL=1 Choose USB SLP1210N6
3
CRITICAL
A SMC_DEBUG_NO
R4651 PAGE TITLE
1
0
5%
2
SMC_DEBUG_NO
Left USB Port B External USB Connectors
DRAWING NUMBER SIZE
1/16W
MF-LF
402 R4652 Apple Inc. <SCH_NUM> D
1
0 2
REVISION
R
5%
<E4LABEL>
1/16W
MF-LF
402 THE INFORMATION CONTAINED HEREIN IS THE
<BRANCH>
46 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
IR SUPPORT
D 72 67 66 61 58 56 54 46 43 42 33 31 7 6PP5V_S3
D
101 82
1 C4801
0.1UF
10%
2 16V
X7R-CERM
402
14
VCC
U4800
CY7C63803-LQXC
QFN
93 35 BI USB_IR_P 12 P1.0/D+ P0.0 7
DIFFERENTIAL_PAIR=USB2_IR
93 35 BI USB_IR_N 13 P1.1/D- P0.1 6
DIFFERENTIAL_PAIR=USB2_IR
IR_VREF_FILTER
15 P1.2/VREG INT0/P0.2 5
16 P1.3/SSEL INT1/P0.3 4
17 P1.4/SCLK INT2/P0.4 3 R4800
1 C4803 18 P1.5/SMOSI TIO0/P0.5 2 IR_RX_OUT_RC 1
100 2 IR_RX_OUT
1UF IN 6 42
10% 19 P1.6/SMISO TIO1/P0.6 1 5%
2 10V
X5R 1/16W
402-1 MF-LF
8 CRITICAL 402
9 OMIT
10 P/N 338S0633
1 C4804
0.001UF
20 10%
21 NC 2 50V
CERM
402
22
C 23
24
C
THRML
PAD VSS
25
11
B B
PAGE TITLE
Front Flex Support

DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
48 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NOTE: Unused pins have "SMC_Pxx" names. Unused
pins designed as outputs can be left floating,
those designated as inputs require pull-ups. PP3V3_S5_AVREF_SMC
46 6
49 48 47 46 43 23 21 17 7 6 PP3V42_G3H
73 66 65 64 53
C4902 1 1 C4903 1 C4904 1 C4905 1 C4906

22UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 20%
6.3V 2 2 10V 2 10V 2 10V 2 10V
CERM CERM CERM CERM CERM
805 402 402 402 402
D R4999 PLACE_NEAR=U4900.M12:3mm
PLACE_NEAR=U4900.M12:3mm
SMC_VCL PLACE_NEAR=U4900.E1:3mm
D
1
4.7 2 PP3V3_S5_SMC_AVCC
MIN_LINE_WIDTH=0.25 MM C4907 1
M12
H10
L11
5% MIN_NECK_WIDTH=0.1 MM 0.47UF
B1
M1
E1
1/16W VOLTAGE=3.3V
MF-LF
402
C4920 1 10%
6.3V
0.1UF CERM-X5R 2
20% 402
U4900 10V
CERM 2
AVCC VCC VCL AVREF
8 OUT TP_SMC_EXCARD_PWR_EN B12 P10 H8S2117 P60 L13 SMC_PM_G2_EN OUT 66 73
402
U4900 R49091 1
R4901
46 OUT TP_SMC_RSTGATE_L A13 P11 LGA-HF P61 K12 NC NC E5 NC 10K 10K
ALL_SYS_PWRGD H8S2117 5% 5%
87 73 27 25 IN A12 P12 (1 OF 3) P62 K11 NC LGA-HF 1/16W 1/16W
MF-LF MF-LF
73 IN RSMRST_PWRGD B13 P13 OMIT P63 J12 NC 402 2 2 402
(3 OF 3)
NC D11 P14 P64 K13 SMC_ADAPTER_EN OUT 18 46 73
OMIT MD1 D1 SMC_MD1 IN 6 47
18 OUT PM_RSMRST_L C13 P15 P65 J10 NC MD2 H1 SMC_KBC_MDE
68 OUT CPUIMVP_VR_ON C12 P16 P66 J11 SMC_PROCHOT_3_3_L IN 46 65 47 46 6 IN SMC_RESET_L D3 RES*
25 18 OUT PM_PWRBTN_L D10 P17 P67 H12 SMC_BIL_BUTTON_L IN 6 46 64
46 SMC_XTAL A3 XTAL
46 6 OUT NC_ESTARLDO_EN D13 P20 P70 N10 SMC_CPU_ISENSE IN 50 46 SMC_EXTAL A2 EXTAL NMI E3 SMC_NMI IN 6 47
NC E11 P21 P71 M11 SMC_CPU_VSENSE IN 49
NC D12 P22 P72 L10 SMC_GPU_ISENSE IN 50
NC F11 P23 P73 N11 SMC_GPU_VSENSE IN 49

ETRST H3 SMC_TRST_L IN 6 47
46 TP_SMC_P24 E13 P24 P74 N12 SMC_DCIN_ISENSE IN 49
E12 M13 SMC_PBUS_VSENSE NO STUFF

NC P25 P75 IN 49 AVSS L9 1 1 1
49 46 SMC_BMON_MUX_SEL F13 P26 P76 N13 SMC_BATT_ISENSE IN 49 VSS R4902 R4998 R4903
SMC_GFX_ISENSE 10K 10K 0
NC E10 P27 P77 L12 IN 46 50 5% 5% 5%
1/16W 1/16W 1/16W
XW4900
D2
L3
F10
B11
C5
MF-LF MF-LF MF-LF
94 87 47 17 6 BI LPC_AD<0> A9 P30 P80 A7 SMC_WAKE_SCI_L OUT 17 SM 2 402 2 402 2 402
94 87 47 17 6 BI LPC_AD<1> D9 P31 P81 B6 NC 2 1
94 87 47 17 6 BI LPC_AD<2> C8 P32 P82 C7 PM_CLKRUN_L OUT 6 18 47
LPC_AD<3> LPC_PWRDWN_L PLACE_NEAR=U4900.L3:4mm

C 94 87 47 17 6
94 87 47 17 6
BI
IN LPC_FRAME_L
B7
A8
P33
P34
P83
P84
D5
A6 SMC_TX_L
IN
OUT
6 18 47
6 43 45 46 47
C
27 IN SMC_LRESET_L D8 P35 P85 B5 SMC_RX_L IN 6 43 45 46 47
GND_SMC_AVSS 46 49 50
94 27 IN LPC_CLK33M_SMC D7 P36 P86 C6 (OC) SMBUS_SMC_MGMT_SCL BI 48 56 97
47 17 6 BI LPC_SERIRQ D6 P37
P90 J4 SMC_ONOFF_L IN 6 46 53
NC D4 P40 P91 G3 SMC_BC_ACOK IN 46 64 65
46 6 TP_SMC_P41 A5 P41 P92 H2 SMC_P92 46
97 56 48 BI SMBUS_SMC_MGMT_SDA (OC) B4 P42 P93 G1 PM_SLP_S3_L IN 6 18 31 73 85
55 OUT SMS_PWRDN A1 P43 P94 H4 PM_SLP_S4_L IN 18 31 43 46 72 73
NC C2 P44 P95 G4 PM_SLP_S5_L IN 18 46 NOTE: P94 and P95 are shorted, P95 could be spare.
NC B2 P45 P96 F4 SMC_CLK32K IN 46
80 OUT SMC_GFX_THROTTLE_L C1 P46 P97 F1 (OC) SMBUS_SMC_0_S0_SDA BI 48 51 81 97
54 OUT SMC_SYS_KBDLED C3 P47
47 46 45 43 6 OUT SMC_TX_L G2 P50

47 46 45 43 6 IN SMC_RX_L F3 P51
97 81 51 48 BI SMBUS_SMC_0_S0_SCL (OC) E4 P52
U4900
(DEBUG_SW_1) 46 SMC_PA0 N3 PA0 H8S2117 PE0 K1 SMC_CASE_OPEN IN 46
17 OUT SPI_DESCRIPTOR_OVERRIDE_L (OC) N1 PA1 LGA-HF PE1 J3 SMC_TCK IN 6 46 47
27 18 6 OUT PM_SYSRST_L (OC) M3 PA2 (2 OF 3) PE2 K2 SMC_TDI IN 6 46 47
43 OUT USB_DEBUGPRT_EN_L (OC) M2 PA3 OMIT PE3 J1 SMC_TDO OUT 6 46 47
46 30 28 BI MEM_EVENT_A_L (OC) N2 PA4 PE4 K4 SMC_TMS IN 6 46 47
B 46
64 46
BI
BI
MEM_EVENT_B_L
SYS_ONEWIRE
(OC)
(OC)
L1
K3
PA5
PA6
PF0 K5 G3_POWERON_L IN 46
B
PF1 N5 SMC_SYS_LED OUT 46
18 OUT PM_BATLOW_L (OC) L2 PA7
PF2 M6 SMC_LID IN 46 53 64
NC B8 PB0 PF3 L5 NC
20 OUT SMC_RUNTIME_SCI_L C9 PB1 PF4 M5 NC
42 6 IN SMC_ODD_DETECT B9 PB2 PF5 N4 TP_SMC_PF5 46
46 25 20 SMC_IG_THROTTLE_L (See below) A10 PB3 PF6 L4 NC

46 IN SMC_EXCARD_CP C10 PB4 PF7 M4 NC
NC B10 PB5
PG0 M8 NC
46 IN SMC_EXCARD_OC_L C11 PB6
PG1 N7 SMS_INT_L IN 46 NOTE: SMS Interrupt can be active high or low, rename net accordingly.
80 IN SMC_GFX_OVERTEMP_L A11 PB7
PG2 K8 (OC) SMBUS_SMC_BSA_SDA BI 6 48 64 65 97 If SMS interrupt is not used, pull up to SMC rail.
52 OUT SMC_FAN_0_CTL G11 PC0 PG3 K7 (OC) SMBUS_SMC_BSA_SCL BI 6 48 64 65 97
52 OUT SMC_FAN_1_CTL G13 PC1 PG4 K6 (OC) SMBUS_SMC_A_S3_SDA BI 6 33 48 54 97
46 6 OUT NC_SMC_FAN_2_CTL F12 PC2 PG5 N6 (OC) SMBUS_SMC_A_S3_SCL BI 6 33 48 54 97
46 6 OUT NC_SMC_FAN_3_CTL H13 PC3 PG6 M7 (OC) SMBUS_SMC_B_S0_SDA BI 48 51 97
52 IN SMC_FAN_0_TACH G10 PC4 PG7 L6 (OC) SMBUS_SMC_B_S0_SCL BI 48 51 97
52 IN SMC_FAN_1_TACH G12 PC5

PH0 E2 SMC_PROCHOT OUT 46
46 6 IN NC_SMC_FAN_2_TACH H11 PC6
PH1 F2 SMC_THRMTRIP OUT 46
46 6 IN NC_SMC_FAN_3_TACH J13 PC7
PH2 J2 NC
55 IN SMS_X_AXIS M10 PD0 PH3 A4 NC_ALS_GAIN OUT 6 46
55 IN SMS_Y_AXIS N9 PD1 PH4 B3 NC

55 IN SMS_Z_AXIS K10 PD2 PH5 C4 NC
50 46 IN SMC_GPU_1V8_ISENSE L8 PD3
50 46 IN SMC_CPUVTT_ISENSE M9 PD4
SMC_P1V5S3_ISENSE N8
A 50 46
49 46
IN
IN SMC_GFX_VSENSE K9
PD5
PD6 SYNC_MASTER=K17_REF SYNC_DATE=06/15/2009 A
49 46 IN SMC_CPU_HI_ISENSE L7 PD7 PAGE TITLE
SMC
DRAWING NUMBER SIZE
SMC_PB3: Apple Inc. <SCH_NUM> D

REVISION
R
SMC_IG_THROTTLE_L for MG systems. <E4LABEL>
Otherwise, TP/NC okay (was ISENSE_CAL_EN) NOTICE OF PROPRIETARY PROPERTY: BRANCH
<BRANCH>
49 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NC_SMC_FAN_2_CTL NC_SMC_FAN_2_CTL
SMC Reset "Button" / Brownout Detect MAKE_BASE=TRUE
6 45 46
SMC FSB to 3.3V Level Shifting
46 45 6 NC_SMC_FAN_2_TACH NC_SMC_FAN_2_TACH 6 45 46
MAKE_BASE=TRUE 69 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6 PP3V3_S0
46 45 6 NC_SMC_FAN_3_CTL NC_SMC_FAN_3_CTL 6 45 46 47 46 42 40 37 34 30 28 27 26
48 47 46 45 43 23 21 17 7 6 PP3V42_G3H MAKE_BASE=TRUE 99 88 87 85 84 83 80 73 72
73 66 65 64 53 49
46 45 6 NC_SMC_FAN_3_TACH NC_SMC_FAN_3_TACH 6 45 46
MAKE_BASE=TRUE 1 1
1
R5061 R5060
CRITICAL R5000 100K 10K
C5000 1 1K NC_ESTARLDO_EN NC_ESTARLDO_EN 5%
1/16W
5%
1/16W
0.1uF 46 45 6 6 45 46
20%
10V
U5000 5%
1/16W
NC_ALS_GAIN
MAKE_BASE=TRUE
NC_ALS_GAIN
MF-LF
2 402
MF-LF
2 402 TO SMC
CERM 2 NCP303LSN MF-LF 46 45 6 6 45 46
402 SOT23-5-HF 2 402 MAKE_BASE=TRUE
SMC_PROCHOT_3_3_L 45
TP_SMC_RSTGATE_L TP_SMC_RSTGATE_L OUT
46 45 45 46
D
SMC_MANUAL_RST_L
OMIT NC
5
4
CD
NC
OUT
IN
1
2
SMC_RESET_L OUT 6 45 47 65 MAKE_BASE=TRUE
6
D
1
R5001 GND SMC_BC_ACOK SMC_BC_ACOK
0
C5001 1 3
65 64 46 45
MAKE_BASE=TRUE
45 46 64 65
D Q5060
SILK_PART=SMC_RST 5% 0.01UF 49 46 45 SMC_BMON_MUX_SEL SMC_BMON_MUX_SEL 45 46 49 DMB53D0UV
1/10W 10% MAKE_BASE=TRUE
MF-LF 16V SOT-563
CERM 2 CPU_PROCHOT_BUF 2 G
2 603 402
46 45 25 20 SMC_IG_THROTTLE_L SMC_IG_THROTTLE_L 20 25 45 46
MAKE_BASE=TRUE TO CPU R5062 3
NC 46 45 SMS_INT_L
MAKE_BASE=TRUE
SMS_INT_L 45 46
91 68 10 BI CPU_PROCHOT_L 1
3.3K 2 CPU_PROCHOT_L_R 5 Q5060 S
DMB53D0UV
D 3 D 6 5% SOT-563 1
Q5032 Q5032 49 46 45 SMC_GFX_VSENSE SMC_GFX_VSENSE 45 46 49
1/16W
MF-LF 4
48 47 46 45 43 23 21 17 7 6 PP3V42_G3H SSM6N15FEAPE SSM6N15FEAPE MAKE_BASE=TRUE 402
73 66 65 64 53 49 SOT563 SOT563 6 D
49 46 45 SMC_CPU_HI_ISENSE SMC_CPU_HI_ISENSE
MAKE_BASE=TRUE
45 46 49 Q5059
U5001 SSM6N15FEAPE
5 50 46 45 SMC_CPUVTT_ISENSE SMC_CPUVTT_ISENSE 45 46 50 SOT563
1 SN74LVC1G02 5 G S 4 2 G S 1 MAKE_BASE=TRUE
53 IN SMC_TPAD_RST_L SOT553-5
4 50 46 45 SMC_P1V5S3_ISENSE SMC_P1V5S3_ISENSE 45 46 50
SMC_TPAD_RST NC NC MAKE_BASE=TRUE
SMC_ONOFF_L 2 SMC_GFX_ISENSE SMC_GFX_ISENSE 1 S G 2
53 46 45 6 IN 02 50 46 45 45 46 50
MAKE_BASE=TRUE
3
SMC_PROCHOT IN 45
50 46 45 SMC_GPU_1V8_ISENSE SMC_GPU_1V8_ISENSE 45 46 50
MAKE_BASE=TRUE
91 20 10 OUT PM_THRMTRIP_L
46 45 TP_SMC_P24 TP_SMC_P24 45 46
MAKE_BASE=TRUE
46 45 6 TP_SMC_P41 TP_SMC_P41 6 45 46 3 D
MAKE_BASE=TRUE Q5059
SMC AVREF Supply 46 45 TP_SMC_PF5 TP_SMC_PF5
MAKE_BASE=TRUE
45 46 SSM6N15FEAPE
SOT563
CRITICAL
SMC_EXCARD
VR5020
C 47 46 45 43 23 21 17 7 6
73 66 65 64 53 49 48
PP3V42_G3H REF3333
SOT23-3 PP3V3_S5_AVREF_SMC
6 45
46 45 SMC_EXCARD_OC_L
R5095
1
0 2 PCH_GPIO10 19 25
4 S G 5
SMC_THRMTRIP 45
C
OUT IN IN
1 IN OUT 2 MIN_NECK_WIDTH=0.1 mm
VOLTAGE=3.3V 5%
1/16W
GND MF-LF
3
1 C5026 402
0.01UF
10%
2 16V
CERM
402
1 C5020 C5025 1
0.47UF 10uF
10%
6.3V
2 CERM-X5R
20%
6.3V 2
X5R
SMC G3Hot 32kHz Oscillator 48 47 46 45 43 23 21 17 7 6
73 66 65 64 53 49
PP3V42_G3H
402 603 To support timed wake-up events in G3Hot
53 46 45 6 SMC_ONOFF_L R5070 10K 1 2
GND_SMC_AVSS SMC_OSC_YES G3_POWERON_L R5072 10K 1 2 5% 1/16W MF-LF 402
TABLE_ALT_HEAD
45 49 50
L5010 45
SMC_LID R5071 100K 1 2

5% 1/16W MF-LF 402
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
VOLTAGE=0V PP3V42_G3H FERR-120-OHM-0.2A 64 53 45
5% 1/16W MF-LF 402
PART NUMBER 48 47 46 45 43 23 21 17 7 6
73 66 65 64 53 49
1 2 PP3V42_G3H_SMC_CLK_F 47 45 43 6 SMC_TX_L R5073 10K 1 2
5% 1/16W MF-LF 402
353S1381 353S1912 ALL Intersil ISL60002-33
TABLE_ALT_ITEM
0603 MIN_LINE_WIDTH=0.2 MM 47 45 43 6 SMC_RX_L R5074 100K 1 2

MIN_NECK_WIDTH=0.2 MM SMC_OSC_YES SMC_OSC_YES SYS_ONEWIRE NO STUFF R5075 2.0K 1 2 5% 1/16W MF-LF 402
VOLTAGE=3.425V 64 45
C5002 1 1 C5003 SMC_TMS R5077 10K 1 2 5% 1/16W MF-LF 402
4.7UF 0.1UF 47 45 6
5% 1/16W MF-LF 402
20%
6.3V 2
20% SMC_TDO R5078 10K 1 2
2 10V
47 45 6
CERM CERM R5079 10K 5% 1/16W MF-LF 402
SMC_TDI 1 2
SMC Crystal Circuit CRITICAL
603 402 47 45 6
47 45 6 SMC_TCK R5080 10K 1 2

5% 1/16W MF-LF 402
R5081 10K 5% 1/16W MF-LF 402
C5010 12 64 45 6 SMC_BIL_BUTTON_L 1 2
R5010 15pF VDD 65 64 46 45 SMC_BC_ACOK R5087 470K 1 2 5% 1/16W MF-LF 402
SMC_XTAL 1
0 2 SMC_XTAL_R 1 2 U5010 NO STUFF SMS_INT_L R5093 10K 1 2 5% 1/16W MF-LF 402
45 46 45
5%
5%
32.768KHZ-9-3.6V
SG-3040LC-SM R5011 5% 1/16W MF-LF 402
1/16W CRITICAL 50V SMC_CLK32K_R 22 SMC_CLK32K R5076 100K
MF-LF 1 7 1 2 SMC_P92 1 2
402 Y5010 1 CERM
402
VIO
OMIT
OUT
5%
OUT 45 45
SMC_PA0 R5091 100K 1 2 5% 1/16W MF-LF 402

20.00MHZ 45
B 5X3.2-SM
2 C5011 NC
NC
2
3
NC0
NC1
NC4
NC5
8
9
NC
NC
1/16W
MF-LF
402 SMC_EXCARD_NOT
5% 1/16W MF-LF 402
B
15pF 4 SMC_EXCARD_OC_L R5092 100K 1 2
1 2 NC NC2 NC6 10 NC 46 45
45 SMC_EXTAL 5% 1/16W MF-LF 402
NC 5 NC3 NC7 11 NC
5% GND
50V
CERM
TABLE_5_HEAD
6 73 45 18 SMC_ADAPTER_EN R5085 10K 1 2

402 PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
R5086 10K 5% 1/16W MF-LF 402
45 SMC_CASE_OPEN 1 2
CRITICAL
TABLE_5_ITEM
5% 1/16W MF-LF 402

197S0350 1 OSC,XTAL,32.768KHZ,LF,HF U5010 SMC_OSC_YES
R5012 45 SMC_EXCARD_CP R5088 10K 1 2
R5090 100K 5% 1/16W MF-LF 402
0 PM_SLP_S5_L 1 2
System (Sleep) LED Circuit 94 18 IN PM_CLK32K_SUSCLK 1 2
45 18
73 72 45 43 31 18 PM_SLP_S4_L R5094 100K 1 2

5% 1/16W MF-LF 402
5% 5% 1/16W MF-LF 402
1/16W
82 MF-LF
58 56 54 44
7 6 PP5V_S3 402
43 42 33 31
72 67 66 61
101
R50311 1
R5030
CPU PM_EXTTS_L / MEM_EVENT_L Level Shifting 69 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
99 88 87 85 84 83 80 73 72
PP3V3_S0
523 20 MEM_EVENT_B_L R5089 10K 1 2
1% 1% 45
1/16W 1/16W 5% 1/16W MF-LF 402
MF-LF
402 2
MF-LF
2 402
R5044
0
1 2 PM_EXT_TS_L<1> OUT 10 91
SYS_LED_ILIM
5%
1/16W
69 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6 PP3V3_S0 MF-LF
47 46 42 40 37 34 30 28 27 26 402
SYS_LED_L_VDIV 99 88 87 85 84 83 80 73 72
1 PM_EXT_TS_L<0> OUT 10 91
R5042
1 10K 6
R5032 5% TO CPU
1/16W
1.47K 6 5 4 CRITICAL 69 68 63 62 58 54 52 51 50 48
PP3V3_S0 MF-LF D
Q5040
A 1%
1/16W
MF-LF D B E Q5030
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
99 88 87 85 84 83 80 73 72
2 402
MEM_EVENT 2
2N7002DW-X-G
SOT-363 SYNC_MASTER=K18_SENSORS SYNC_DATE=06/29/2009 A
402 2 DMB54D0UV
R5040 1
G S
Debug Power "Buttons" PAGE TITLE
SYS_LED_L
SOT-563
10K
5% 3 1 SMC Support
1/16W SMC_ONOFF_L OUT 6 45 46 53 DRAWING NUMBER SIZE
Q1
Q2 MF-LF
402 2
D
Q5040 OMIT OMIT <SCH_NUM> D
FROM DIMMS 2N7002DW-X-G 1 1 Apple Inc.
46 45 30 28 MEM_EVENT_A_L 5 G S
SOT-363 R5016 R5015 R
REVISION
S G C IN 0
5%
0
5%
<E4LABEL>
1 2 3 46 45 30 28 BI MEM_EVENT_A_L 4 1/10W 1/10W NOTICE OF PROPRIETARY PROPERTY: BRANCH
MAKE_BASE=TRUE MF-LF MF-LF
TO/FROM SMC
603 2 2 603 THE INFORMATION CONTAINED HEREIN IS THE
<BRANCH>
SILK_PART=PWR_BTN SILK_PART=PWR_BTN THE POSESSOR AGREES TO THE FOLLOWING: PAGE
45 SMC_SYS_LED SYS_LED_ANODE 6 42
PLACEMENT_NOTE=Place R5015 on top side I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
50 OF 132
IN OUT
PLACEMENT_NOTE=Place R5016 on bottom side III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
LPC+SPI Connector
CRITICAL
LPCPLUS
J5100
55909-0374
M-ST-SM
49 48 46 45 43 23 21 17 7 6
73 66 65 64 53
PP3V42_G3H 31 32
72 70 69 68 54 52 42 23 7 6
88 86
PP5V_S0
1 2 LPC_CLK33M_LPCPLUS IN 6 27 94
94 87 45 17 6 BI LPC_AD<0> 3 4 LPC_AD<2> BI 6 17 45 87 94
94 87 45 17 6 BI LPC_AD<1> 5 6 LPC_AD<3> BI 6 17 45 87 94
7 8
47 6 IN SPI_ALT_MOSI 9 10 SPIROM_USE_MLB OUT 6 20 57
47 6 OUT SPI_ALT_MISO 11 12 SPI_ALT_CLK IN 6 47
94 87 45 17 6 IN LPC_FRAME_L 13 14 SPI_ALT_CS_L IN 6 47
45 18 6 OUT PM_CLKRUN_L 15 16 LPC_SERIRQ BI 6 17 45
46 45 6 OUT SMC_TMS 17 18 LPC_PWRDWN_L IN 6 18 45
94 87 27 6 IN LPCPLUS_RESET_L 19 20 SMC_TDI OUT 6 45 46
46 45 6 OUT SMC_TDO 21 22 SMC_TCK OUT 6 45 46
45 6 IN SMC_TRST_L 23 24 SMC_RESET_L OUT 6 45 46 65
45 6 OUT SMC_MD1 25 26 SMC_NMI OUT 6 45
46 45 43 6 IN SMC_TX_L 27 28 SMC_RX_L OUT 6 43 45 46

29 30 LPCPLUS_GPIO OUT 6 20
C 33 34 C
516S0573
SPI Bus Series Termination

SPI_ALT_MISO 6 47
SPI_ALT_MOSI 6 47
SPI_ALT_CLK 6 47
SPI_ALT_CS_L 6 47
LPCPLUS LPCPLUS LPCPLUS LPCPLUS

1 1 1 1
R5128 R5127 R5126 R5125 PLACE_NEAR=J5100.14:5mm
0 47 47 47 PLACE_NEAR=J5100.12:5mm
5% 5% 5% 5% PLACE_NEAR=J5100.9:5mm
1/16W 1/16W 1/16W 1/16W PLACE_NEAR=J5100.11:5mm
MF-LF MF-LF MF-LF MF-LF
2 402 2 402 2 402 2 402
PLACE_NEAR=U1800.AV3:5mm R5110 R5120

15 47
94 17 IN SPI_CS0_R_L 1 2 94 SPI_CS0_L 1 2 SPI_MLB_CS_L OUT 57
5% 5% PLACE_NEAR=R5125.2:5mm
1/16W 1/16W
B PLACE_NEAR=U1800.BA2:5mm R5111
15
MF-LF
402 R5121
47
MF-LF
402 B
94 17 IN SPI_CLK_R 1 2 94 SPI_CLK 1 2 SPI_MLB_CLK OUT 57
1/16W 1/16W
PLACE_NEAR=U1800.AY1:5mm R5112 MF-LF R5122 MF-LF
402 402
SPI_MOSI_R 1
15 2 94 SPI_MOSI 1
47 2 SPI_MLB_MOSI
94 17 IN OUT 57
1/16W 1/16W
MF-LF R5123 MF-LF
402 402
15
94 17 OUT SPI_MISO 1 2 SPI_MLB_MISO IN 57
5% PLACE_NEAR=U6100.2:5mm
1/16W
MF-LF
402
69 68 63 62 58 54 52 51 50
25 24 23 21 20 19 18 17 7 6PP3V3_S0
48 46 42 40 37 34 30 28 27 26
99 88 87 85 84 83 80 73 72
EFI_DEBUG
EFI_DEBUG EFI_DEBUG 1 C5101
1 1 0.1UF
R5101 R5103 20%
10V
0 0
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
8
VCC
EFI_DEBUG
2 CERM
402 EFI Debug ROM
U5101
DEBUGROM_E2 3 E2 M24M01-R SMBUS_PCH_DATA
SO8N SDA 5 BI 17 25 26 28 30 32 42 48 63 88
94
DEBUGROM_E1 2 E1
CRITICAL SCL 6 SMBUS_PCH_CLK
A 7 WC*
E0/NC0 1
IN 17 25 26 28 30 32 42 48 63 88
94
NC PAGE TITLE
NO STUFF NO STUFF
1
R5102 1R5104
VSS
4 LPC+SPI Debug Connector
DRAWING NUMBER SIZE
0 0
5%
1/16W
5%
1/16W Apple Inc. <SCH_NUM> D
MF-LF MF-LF Write: 0xAC 0xAE REVISION
2 402 2 402 Read: 0xAD 0xAF
R
<E4LABEL>
<BRANCH>
51 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PCH SMBus "0" Connections SMC "0" SMBus Connections SMC "Battery A" SMBus Connections
99 99
68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6 PP3V3_S0 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6 PP3V3_S0 49 47 46 45 43 23 21 17 7 6 PP3V42_G3H
47 46 42 40 37 34 30 28 27 26 47 46 42 40 37 34 30 28 27 26 73 66 65 64 53
88 87 85 84 83 80 73 72 69 88 87 85 84 83 80 73 72 69
Ibex Peak-M R52001 1

R5201 SO-DIMM "A" SMC R52501 1
R5251 GPU Temp (Ext) SMC R52801 1
R5281 Battery Charger
1K 1K 4.7K 4.7K 1K 1K
5% 5% J2900 5% 5% 5% 5%
U1800 1/16W 1/16W U4900 1/16W 1/16W EMC1414-A: U5550 U4900 1/16W 1/16W ISL6258 - U7000
MF-LF MF-LF (Write: 0xA0 Read: 0xA1) MF-LF MF-LF MF-LF MF-LF
(MASTER) 402 2 2 402 (MASTER) 97
402 2 2 402 (Write: 0x98 Read: 0x99) (MASTER) 402 2 2 402 (Write: 0x12 Read: 0x13)
81
51 48
94 88 63 48
28 26 25 17 SMBUS_PCH_CLK SMBUS_PCH_CLK 42
17
47
25
48
26 81 51 48 45 SMBUS_SMC_0_S0_SCL 45 SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SCL 45 48 51 64 48 45 6 SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SCL 6 45 48
D
47 42 32 30
94 88 63 48
28 26 25 17
MAKE_BASE=TRUE
SMBUS_PCH_DATA SMBUS_PCH_DATA
28
63
42
17
30
88
47
25
32
94
48
26
97
81 51 48 45 SMBUS_SMC_0_S0_SDA
97 81 MAKE_BASE=TRUE
51 48
45 SMBUS_SMC_0_S0_SDA SMBUS_SMC_0_S0_SDA
81 97
45 48 51
97 65
64 48 45 6 SMBUS_SMC_BSA_SDA
MAKE_BASE=TRUE
SMBUS_SMC_BSA_SDA SMBUS_SMC_BSA_SDA
64 65 97
6 45 48
D
47 42 32 30 MAKE_BASE=TRUE 28
63
30
88
32
94
97 MAKE_BASE=TRUE 81 97 97 65 MAKE_BASE=TRUE 64 65 97
VRef DACs SO-DIMM "B" GPU Temp (Int) Battery

J3100
U2900 GT216: U8000 J6955
(Write: 0x98 Read: 0x99)
(Write: 0xA4 Read: 0xA5)
(Write: 0x9E Read: 0x9F)
Battery (See Table)
97
48
26
47
25
42
17 SMBUS_PCH_CLK SMBUS_PCH_CLK 42 47 48
SMBUS_SMC_0_S0_SCL 51
45
Battery Manager - (Write: 0x16 Read: 0x17) SMBUS_SMC_BSA_SCL
17 25 26 6 45 48
32
94
30
88
28
63
28
63
30
88
32
94
48
81 Battery LED Driver - (Write: 0x36 Read: 0x37) 64 65 97
48 47 42 51
26
32
25
30
17
28
SMBUS_PCH_DATA SMBUS_PCH_DATA 42
17
28
47
25
30
48
26
32
SMBUS_SMC_0_S0_SDA 45
48
Battery Temp - (Write: 0x90 Read: 0x91) SMBUS_SMC_BSA_SDA 6 45 48
64 65 97
94 88 63 63 88 94 81
97
Margin Control CK505 (Clock)

U2901 U2700 SMC "A" SMBus Connections SMC "Management" SMBus Connections
(Write: 0x30 Read: 0x31) (Write: 0xD2 Read: 0xD3) NOTE: SMC RMT bus remains powered and may be active in S3 state
The bus formerly known as "Battery B"
48 47 42
26
32
25
30
17
28
SMBUS_PCH_CLK SMBUS_PCH_CLK 42
17
47
25
48
26 53 50 48 36 35 34 33 32 31 20 17 8 7 6 PP3V3_S3 53 50 48 36 35 34 33 32 31 20 17 8 7 6 PP3V3_S3
28 30 32 101 87 73 72 55 54 101 87 73 72 55 54
94 88 63 63 88 94
48 47 42
26
32
25
30
17
28
17
47
25
48
26
28 30 32
94 88 63 63 88 94
SMC R52701 1
R5271 Trackpad SMC R52901 1
R5291 Sensor ADC A
1K 1K 4.7K 4.7K
5% 5% 5% 5%
U4900 1/16W 1/16W J5800 U4900 1/16W 1/16W U5930
EFI Debug Serial LED BACKLIGHT (MASTER)
MF-LF
402 2
MF-LF
(Write: 0x90 Read: 0x91) (MASTER)
MF-LF MF-LF
(Write: 0x10 Read: 0x11)
U9701 2 402 402 2 2 402
97
U5101 SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SCL 97
SMBUS_SMC_MGMT_SCL 56 48
SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SCL
(WRITE: 0x58 READ: 0x59) 6 6 33 97 56 48 45 45 45 48 56
C (Write: 0xAC/AE Read: 0xAD/AF)

48
26
47
25
42
17 SMBUS_PCH_CLK SMBUS_PCH_CLK 42
17
47
25
48
26
54 48 45 33
97
48 45 33 6
97 54
SMBUS_SMC_A_S3_SDA
MAKE_BASE=TRUE
SMBUS_SMC_A_S3_SDA
MAKE_BASE=TRUE
SMBUS_SMC_A_S3_SDA
45 48 54
97
6 33
45 48 54
97 56 48 45 SMBUS_SMC_MGMT_SDA
97
56 48
45
MAKE_BASE=TRUE
SMBUS_SMC_MGMT_SDA
MAKE_BASE=TRUE
SMBUS_SMC_MGMT_SDA
97
45 48 56
97
C
32 30 28 28 30 32
94 88 63 63 88 94
48 47 42
26
32
25
30
17
28
17
28
47
25
30
48
26
32
94 88 63 63 88 94
ALS
J3401
XDP Connectors Mikey (Write: 0x72 Read: 0x73)
J2600 & J2650 U6800 SMBUS_SMC_A_S3_SCL 97
6 33
(MASTER) (Write: 0x72 Read: 0x73) 45 48 54
SMBUS_SMC_A_S3_SDA 97
6 33
94 88 63 48
28 26 25 17 SMBUS_PCH_CLK SMBUS_PCH_CLK 42
17
47
25
48
26 45 48 54
47 42 32 30 28 30 32
63 88 94
94 88 63 48
28 26 25 17 SMBUS_PCH_DATA SMBUS_PCH_DATA 42
17
47
25
48
26
47 42 32 30 28 30 32
63 88 94
HDD Redriver Control A

SMC "B" SMBus Connections
U4510 99
68 63 62 58 54 52 51 50 48
PP3V3_S0
25 24 23 21 20 19 18 17 7 6
(Write: 0x94 Read: 0x95) 47 46 42 40 37 34 30 28 27 26
88 87 85 84 83 80 73 72 69
SMBUS_PCH_CLK 42
17
47
25
48
26
28 30 32
SMBUS_PCH_DATA
63
42
17
88
47
25
94
48
26 SMC R52601 1
R5261 CPU Temp
28
63
30
88
32
94
4.7K 4.7K
5% 5%
U4900 1/16W 1/16W EMC1414-A: U5570
MF-LF MF-LF
(MASTER) 402 2 2 402 (Write: 0x98 Read: 0x99)
97
51 48
51 48 45 SMBUS_SMC_B_S0_SCL 45 SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SCL 45 48 51
B PCH "SMLink 0" Connections 97
97 51 48 45 SMBUS_SMC_B_S0_SDA
97 MAKE_BASE=TRUE
51 48
45 SMBUS_SMC_B_S0_SDA SMBUS_SMC_B_S0_SDA
97
45 48 51
B
MAKE_BASE=TRUE 97
99
68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6 PP3V3_S0
47 46 42 40 37 34 30 28 27 26
88 87 85 84 83 80 73 72 69

R5211
8.2K 8.2K
5% 5%
U1800 1/16W 1/16W
MF-LF MF-LF
(MASTER) 402 2 2 402
94 17 SML_PCH_0_CLK
MAKE_BASE=TRUE
94 17 SML_PCH_0_DATA
MAKE_BASE=TRUE
PCH "SMLink 1" Connections

99
68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6 PP3V3_S0
47 46 42 40 37 34 30 28 27 26
88 87 85 84 83 80 73 72 69
NO STUFF NO STUFF
R5221
8.2K 8.2K R5223
5% 5%
U1800 0
A (Write: 0x90 Read: 0x91)
1/16W
MF-LF
402 2
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
SYNC_MASTER=K18_SENSORS SYNC_DATE=06/18/2009 A
402 PAGE TITLE
SML_PCH_1_CLK
94 17
MAKE_BASE=TRUE
1 2
K18 SMBus Connections
94 17 SML_PCH_1_DATA 1 2 DRAWING NUMBER SIZE
MAKE_BASE=TRUE
R5222 Apple Inc. <SCH_NUM> D
0 REVISION
5% R
1/16W
MF-LF
<E4LABEL>
SMLink 1 is slave port to 402 NOTICE OF PROPRIETARY PROPERTY: BRANCH
access PCH & CPU via PECI. THE INFORMATION CONTAINED HEREIN IS THE
<BRANCH>
52 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU Voltage Sense / Filter
PLACE_NEAR=U4900.M11:5mm
XW5309
PBUS Voltage Sense & Filter
68 15 12 7 6 PPVCORE_S0_CPU SM
R5309
4.53K
1 2 CPUVSENSE_IN 1 2 SMC_CPU_VSENSE OUT 45
Q5315
1% FDG6332CG
1/16W SC70-6
MF-LF 1
C5309 PLACE_NEAR=U4900.M11:5mm
PLACEMENT_NOTE=Place near U1000 402
0.22UF PPBUS_G3H
P-CHN
82 70 69 67 66 65 49 40 7 6
20% 89 86
6.3V 4 S D 3 PPBUS_G3H_VSENSE
2 X5R
VOLTAGE=6V
1
GND_SMC_AVSS 45 46 49 50
R5315 G R5385 1 PLACE_NEAR=U4900.M13:5mm
100K 5 27.4K
D GPU Voltage Sense / Filter

5%
1/16W
MF-LF
1%
1/16W
MF-LF
D
402
2
402
2
Rthevenin = 4504 ohms
PLACE_NEAR=U4900.N11:5mm
XW5359 R5359 PBUSVSENS_EN_DIV SMC_PBUS_VSENSE OUT 45
82 75 7 6 PPVCORE_GPU SM
4.53K
1 2 GPUVSENSE_IN 1 2 SMC_GPU_VSENSE OUT 45
1 1
1% R5316 R5386 1
C5385
1/16W 100K 5.49K 0.22UF
MF-LF
402
1
C5359 5% 1%
20%
0.22UF PLACE_NEAR=U4900.N11:5mm 1/16W 1/16W
PLACEMENT_NOTE=Place near U8000 20%
MF-LF MF-LF 2
6.3V
X5R PLACE_NEAR=U4900.M13:5mm
6.3V 402 402 402
2 2
2 X5R
402 PBUSVSENS_EN_L GND_SMC_AVSS 45 46 49 50
GND_SMC_AVSS 45 46 49 50 PLACE_NEAR=U4900.M13:5mm
D
GFX Voltage Sense / Filter
N-CHN
Q5315
PLACE_NEAR=U4900.K9:5mm G FDG6332CG
PM_SLP_S3_L_R 2
69 24 13 7 6 PPVCORE_S0_GFX
XW5399
SM R5399
73 72
Enables PBUS VSense divider when high. S

SC70-6
GFXVSENSE_IN1 2 1
4.53K2 SMC_GFX_VSENSE 1
OUT 45 46
PLACEMENT_NOTE=Place near U1000 1%

1/16W
MF-LF
402
1 C5399 PLACE_NEAR=U4900.K9:5mm
0.22UF
20%
6.3V
2 X5R
402
CPU VCore High Side Current Sensor

C C
48 47 46 45 43 23 21 17 7 6
73 66 65 64 53 49
PP3V42_G3H
1 C5388
0.1UF
20%
10V
2 CERM
3
402
68 7 OUT PPBUS_CPU_IMVP_ISNS V+
PLACE_NEAR=U4900.L7:5mm
OMIT U5388 R5335
TABLE_5_HEAD
R5388 1 3 99 ISNS_CPU_N INA213 4.53K

0.001
5 IN- SC70 OUT 6 CPUVCORE_HISIDE_IOUT 1 2 SMC_CPU_HI_ISENSE OUT 45 46
TABLE_5_ITEM
1% 1%
102S0858 1 RES,0.010 OHM,1%,1/2W,1206 R5388 CRITICAL 1W 1/16W
MF
1206
99 ISNS_CPU_P 4 IN+ REF 1 MF-LF 1
C5335
2 4 GAIN: 500X 402
0.22UF
20%
GND 6.3V PLACE_NEAR=U4900.L7:5mm
2 X5R
PPBUS_G3H
2
402
82 70 69 67 66 65 49 40 7 6 IN
89 86
EDP for PPVIN_S5_CPU_IMVP_ISNS_R = 5.867 amps for K18.
BMON Current Sense - Entire circuit must be near SMC (U4900)

B B
DCIN Current Sense Filter
48 47 46 45 43 23 21 17 7 6
73 66 65 64 53 49
PP3V42_G3H
BMON_ENG
BMON_ENG 1 C5369 PLACE_NEAR=U4900.N12:5mm
BMON_ENG U5313 20%

0.1uF R5380
4.53K
1 C5318
NC7SB3157P6XG 2 10V
CERM 65 IN CHGR_AMON 1 2 SMC_DCIN_ISENSE OUT 45
1 SC70 SEL 6 402
0.1uF BMON_INA_OUT B1 SMC_BMON_MUX_SEL IN 45 46 1%
1/16W
20% BMON_ENG MF-LF 1
C5380
3
2 10V
CERM
1 402
0.22UF
REGULATOR SIDE: 402 V+ 2 5 20% PLACE_NEAR=U4900.N12:5mm
GND VCC 6.3V
PLACE_NEAR=U4900.N13:5mm
U5323 0 R5391
2 X5R
402
INA213 BMON_AMUX_OUT 45.3K2 SMC_BATT_ISENSE
99 65 OUT CHGR_CSO_R_P 5 IN- SC70 OUT 6 65 IN CHGR_BMON 3 4 1 OUT 45 GND_SMC_AVSS 45 46 49 50
B0 A
VER 1 BMON_ENG 1/16W
1%
99 65 IN CHGR_CSO_R_N 4 IN+ REF 1 1
R5371 MF-LF
402
1 C5390
BMON_PROD 100K 0.022UF
10%
LOAD SIDE: GND R5330 5%
1/16W 16V
2 CERM-X5R
2
0 1 MF-LF 402
2
2402
5% PLACE_NEAR=U4900.N13:5mm
1/16W
MF-LF
Monitors battery discharge 402
GAIN: 50X
current from battery to PBUS
A U5303 only senses current up to 6.6A SYNC_MASTER=K18_SENSORS SYNC_DATE=06/29/2009 A

PAGE TITLE
Current & Voltage Sensing

DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
53 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
GPU VCore Current Sense
CPU VCore Load Side Current Sense / Filter
CRITICAL
R5409 U5410
2.87K 8 OPA2333 PLACE_NEAR=U4900.L10:5mm
82 IN GFXIMVP6_IMON 1 2 99 GPUISENS_P DFN R5411
5
CRITICAL 1%
1/16W
V+ 7 GPUVCORE_IOUT 1
4.53K
2 SMC_GPU_ISENSE OUT 45
R5459
U5450 PLACE_NEAR=U4900.N10:5mm
MF-LF
402 6 V- 1%
8 OPA2333 1/16W
CPUIMVP_IMON 1
2.87K
2 CPUISENS_P 5 DFN R5453 R5410 THRM
4 MF-LF
402
1
C5408
91 68 12 IN
V+ 4.53K 10K 9 0.22UF PLACE_NEAR=U4900.L10:5mm
1% 7 CPUVCORE_IOUT 1 2 SMC_CPU_ISENSE 45 1 2 99 GPUISENS_N Gain: 1.4x 20%
D
1/16W
MF-LF
402
6 V- 1%
1/16W
OUT
1%
1/16W
2
6.3V
X5R
402
D
THRM MF-LF MF-LF
4 402 402 GND_SMC_AVSS 45 46 49 50
9 1 C5453
R5450 R5412
10K 0.22UF 4.02K
1 2 CPUISENS_N PLACE_NEAR=U4900.N10:5mm 20%
6.3V
1 2
2 X5R
1% 1%
1/16W 402 1/16W
MF-LF MF-LF
402 402
R5452
20.0K
Gain: 3X C5407
1 2 470PF
1% 1 2
1/16W
MF-LF
402 10% NOSTUFF
50V
CERM
402
C5457
470PF
1 2
1.8V FB Current Sense
10% NOSTUFF
50V
CERM
402 69 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6 PP3V3_S0
47 46 42 40 37 34 30 28 27 26
99 88 87 85 84 83 80 73 72
1 C5410
0.1UF
20%
10V
2 CERM
402
86 7 6 IN PP1V8R1V55_S0GPU_ISNS_R CRITICAL
R5415
U5410
CRITICAL 2.32K 8 OPA2333 PLACE_NEAR=U4900.L8:5mm
R5413 1 3 ISNS_P1V8GPU_P 1 2 ISNS_P1V8GPU_R_P3 DFN R5418
GFX VCore Current Sense 0.001 V+ 1
4.53K
SMC_GPU_1V8_ISENSE
C 99
68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6PP3V3_S0
47 46 42 40 37 34 30 28 27 26
1%
1W
MF-1
1%
1/16W
MF-LF
402
2 V-
P1V8_S0GPU_IOUT 1
1%
1/16W
2
OUT 45 46
C
88 87 85 84 83 80 73 72 69 0612
2 4
R5414 THRM
4 MF-LF 1
C5411
1 C5444 2.32K 402
0.1UF
99 ISNS_P1V8GPU_N 1 2 99 ISNS_P1V8GPU_R_N 9 0.22UF
20% PLACE_NEAR=U4900.L8:5mm
CRITICAL 20%
10V 78 77 76 75 56 8 7 6 OUT PP1V8R1V55_S0GPU_ISNS 1% Gain: 431x 2
6.3V
X5R
2 1/16W
R5484 U5430 CERM

402
PLACE_NEAR=U4900.L12:5mm
MF-LF
402
402
8 OPA2333 GND_SMC_AVSS 45 46 49 50
7.15K2 R5479 NOSTUFF
99 69 IN GFXIMVP_CS_R_P 1 99 GFX_ISNS_R_P 3 DFN 1
R5416
1%
V+ 1 GFXIMVP_ISNS_IOUT 1
4.53K
2 SMC_GFX_ISENSE C5409 1 R5417
OUT 45 46
470PF 1M
1/16W
2 10% 1%
1
1M
2
SIGNAL_MODEL=EMPTY
MF-LF
402
V- 1%
50V 1/16W
1/16W
CERM 2 MF-LF
R5481 THRM
4 GAIN: 140X MF-LF
402 1 C5479 402 2 402
1%
1/16W
C5412
GFXIMVP_CS_R_N 1
7.15K2 GFX_ISNS_R_N
9
0.22UF
MF-LF
402
99 69 IN 99 470PF
1%
PLACE_NEAR=U4900.L12:5mm 20%
6.3V 1 2 SIGNAL_MODEL=EMPTY
2 X5R
1/16W 402
MF-LF
10% NOSTUFF
402
R5483 50V
1M CERM
402
NOSTUFF 1 2
C5482 1 1
R5482 1%
1/16W
SIGNAL_MODEL=EMPTY
470PF 1M MF-LF
10% 1% 402
50V
CERM 2 1/16W NOSTUFF
402 MF-LF C5443 CPU & MEM 1.5V S3 (DDR) Current Sense
2 402 470PF
1 2
10% SIGNAL_MODEL=EMPTY
54 53 48 36 35 34 33 32 31 20 17 8 7 6 PP3V3_S3
50V 101 87 73 72 55
CERM
402
1 C5454
0.1UF
20%
B 2
10V
CERM
402
B
CRITICAL
R5444 U5450
8 OPA2333 PLACE_NEAR=U4900.N8:5mm
ISNS_1V5_S3_P 1
4.12K2 DDRISNS_R_P DFN R5440
99 67 IN 99 3
1%
V+ 1 CPUDDR_IOUT 1
4.53K
2 SMC_P1V5S3_ISENSE 45 46
1/16W OUT
R5443 MF-LF
402
2 V- 1%
1/16W
ISNS_1V5_S3_N 1
4.12K2 DDRISNS_R_N
THRM
4 MF-LF 1
C5490
99 Gain: 243x 402
CPUVTT 1.05V Current Sense 99 67 IN
1%
9 0.22UF
20%
1/16W 6.3V
2 X5R
MF-LF
402 402
NOSTUFF 1
C5442 1 R5442 R5441 PLACE_NEAR=U4900.N8:5mm
470PF 1M 1
1M
2
SIGNAL_MODEL=EMPTY
10% 1%
50V 1/16W
CRITICAL CERM 2
402
MF-LF
2 402
1%
1/16W
U5430 MF-LF
402 C5441
8 OPA2333 470PF
R5474 99 CPUVTTISNS_R_P 5 DFN PLACE_NEAR=U4900.M9:5mm 1 2 SIGNAL_MODEL=EMPTY
CPUVTTS0_CS_P 7.15K2
1
V+ 7 R5487
99 70 IN
4.53K 10% NOSTUFF
1% 6 V- CPUVTT_IOUT 1 2 SMC_CPUVTT_ISENSE OUT 45 46
50V
CERM
1/16W
402
R5473 MF-LF
402
THRM
4 1%
1/16W
CPUVTTS0_CS_N 7.15K2 9 MF-LF 1

C5480
99 70 IN 1 99 CPUVTTISNS_R_N Gain: 140x 402
0.22UF
1% 20%
1/16W 6.3V
2 X5R
MF-LF
A 402 402
NOSTUFF PAGE TITLE
1
C5472 1
470PF
R5472
1M
R5471
1M SIGNAL_MODEL=EMPTY
Current Sensing
1% 1 2 PLACE_NEAR=U4900.M9:5mm DRAWING NUMBER SIZE
10% 1/16W
50V
CERM 2 MF-LF 1%
NOSTUFF Apple Inc. <SCH_NUM> D
2 402
1/16W
402 MF-LF
402 C5471 R
REVISION
470PF
SIGNAL_MODEL=EMPTY
<E4LABEL>
1 2 NOTICE OF PROPRIETARY PROPERTY: BRANCH
10% THE INFORMATION CONTAINED HEREIN IS THE

<BRANCH>
50V THE POSESSOR AGREES TO THE FOLLOWING: PAGE
CERM
402 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
54 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
GPU Proximity/GPU Die/Left Heat Pipe/Right Fin Stack

R5550
47
69 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6 PP3V3_S0 1 2 PP3V3_S0_GPUTHMSNS_R
47 46 42 40 37 34 30 28 27 26
99 88 87 85 84 83 80 73 72
5% MIN_NECK_WIDTH=0.25 mm
1/16W
MF-LF
402 0.1uF
20%
PLACE_NEAR=U5550.2:5mm
2 10V
CERM
R55511 1
R5552
99 80 79 GPU_TDIODE_P PLACE_NEAR=U5550.3:5mm 10K 10K
D Detect GPU Die Temperature
BI
SIGNAL_MODEL=EMPTY
1
VDD
402 5%
1/16W
MF-LF
5%
1/16W
MF-LF
D
402 2 2 402
C5551 1
U5550
0.0022uF EMC1414-A
10%
50V MSOP
CERM 2 2 DP1 THERM*/ADDR 7 GPUTHMSNS_THM_L
402
Detect Right Fin Stack Temperature GPU_TDIODE_N 3 DN1 8 GPUTHMSNS_ALERT_L
99 80 79 BI ALERT*
GPUTHMSNS_D_P CRITICAL
4 DP2/DN3 9 SMBUS_SMC_0_S0_SDA
Q5501 99 SMDATA BI 45 48 81 97
BC846BMXXH 2
5 DN2/DP3 10
SOT732-3 3 SIGNAL_MODEL=EMPTY SMCLK SMBUS_SMC_0_S0_SCL BI 45 48 81 97
Placement note:
1
Q5503 1 C5552 1 GND
0.0022uF 6
Place Q5501 on bottom side BC846BMXXH 10%
50V
SOT732-3
close to the right fin stack 3 2 CERM 2
402
99 GPUTHMSNS_D_N Placement note:
Place U5550 on bottom side under GPU
Detect Left Heat Pipe Temperature PLACE_NEAR=U5550.4:5mm
Placement note:
Place Q5503 on top side under left heat pipe near GPU Write Address: 0x98
Read Address: 0x99
C C
CPU Proximity/CPU Die/PCH Proximity/Battery Charger Proximity

R5570
47
69 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6 PP3V3_S0 1 2 PP3V3_S0_CPUTHMSNS_R
47 46 42 40 37 34 30 28 27 26
99 88 87 85 84 83 80 73 72
1/16W
MF-LF
402 0.1uF R55711 1
R5572
1 20%
VDD 2 10V
CERM 10K 10K
402 5% 5%
U5570 1/16W
MF-LF
1/16W
MF-LF
PLACE_NEAR=U5570.2:5mm EMC1414-A 402 2 2 402
PLACE_NEAR=U5570.3:5mm MSOP
99 9 CPU_THERMD_P 2 DP1 THERM*/ADDR 7 CPUTHMSNS_THM_L
BI
SIGNAL_MODEL=EMPTY
Detect CPU Die Temperature

C5571 1 3 DN1 ALERT* 8 CPUTHMSNS_ALERT_L
0.0022uF CRITICAL
10% 4 DP2/DN3 SMDATA 9 SMBUS_SMC_B_S0_SDA 45 48 97
50V BI
CERM 2
402 5 DN2/DP3 SMCLK 10 SMBUS_SMC_B_S0_SCL 45 48 97
CPU_THERMD_N BI
99 9 BI GND
6
B Detect Battery Charger Proximity Temperature
Note: EMC1414 can perform Beta B
99 CPUTHMSNS_D2_P Placement note:
Q5502 SIGNAL_MODEL=EMPTY
Place U5570 under CPU Compensation for External Diode 1 only
BC846BMXXH 2 3
SOT732-3 C5590 1
1 Q5504 1 0.0022uF
10%
Placement note: BC846BMXXH 50V
CERM 2
SOT732-3 402
Place Q5502 on bottom side 3 2
close to battery charger circuit 99 CPUTHMSNS_D2_N Write Address: 0x98
Read Address: 0x99
Detect PCH Proximity Temperature PLACE_NEAR=U5570.4:5mm
Placement note:
Place Q5504 under PCH
A SYNC_MASTER=K18_SENSORS SYNC_DATE=06/18/2009 A
PAGE TITLE
Thermal Sensors
DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
55 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
C Left Fan Right Fan C

99
PP5V_S0 99
PP5V_S0
68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
PP3V3_S0 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
PP3V3_S0
88 87 85 84 83 80 73 72 69
CRITICAL 88 87 85 84 83 80 73 72 69
CRITICAL
1
J5650 1
J5660
R5650 78171-0004
M-RT-SM
R5660 78171-0004
M-RT-SM
47K 5 47K 5
5% 5%
1/16W 1/16W
MF-LF MF-LF
R5655 402 2 1 R5665 402 2 1
SMC_FAN_0_TACH 1
47K 2 6 FAN_LT_TACH 2 SMC_FAN_1_TACH 1
47K 2 6 FAN_RT_TACH 2
45 OUT 45 OUT
5% 3 5% 3
1/16W 1/16W
MF-LF 4 MF-LF 4
402 402
R56511 6 R56611 6
100K 100K
5% 5 5% 2
1/16W
MF-LF
Q5660 1/16W
MF-LF
Q5660
402 2 G 2N7002DW-X-G 518S0369 402 2 G 2N7002DW-X-G 518S0369
SOT-363 SOT-363
45 SMC_FAN_0_CTL 4 S D 3 6 FAN_LT_PWM 45 SMC_FAN_1_CTL 1 S D 6 6 FAN_RT_PWM
IN IN
B B
PAGE TITLE
Fan Connectors
DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
56 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
KEYBOARD CONNECTOR
PSOC USB CONTROLLER IC PIN NAME CURRENT R_SNS V_SNS POWER
J5713
TMP102 V+ 10UA 2.55 KOHM 0.0255 V 0.255E-6 W
80UA 0.204 V 16.32E-6 W APN 518S0637
3V3 LDO VDD 60MA MAX 10 OHM 0.6 V 36E-3 W NC 32
USB INTERFACES TO MLB TRACKPAD PICK BUTTONS VOUT 60MA MAX 0.2 OHM 0.012 V 0.72E-3 W
SPI HOST TO Z2 KEYBOARD SCANNER PSOC VDD 8MA (TYP) 1.5 OHM 0.012 V 96E-6 W IN
PP3V3_S3
30
D 14MA (MAX) 0.021 V 294E-6 W
WS_KBD1
29 D
PP3V3_S3_PSOC 53 53 6
28
18V BOOSTER VIN 4MA (MAX) 4.7 OHM 0.0188 V 75.2E-6 W
53 6 WS_KBD2
WS_KBD23 6 53
WS_KBD22 6 53
WS_KBD21 6 53
WS_KBD20 6 53
WS_KBD19 6 53
WS_KBD18 6 53
27
53 6 WS_KBD3
PICKB_L 26
53 6 WS_KBD4
54 6
BUTTON_DISABLE 25
53 6 WS_KBD5
53
54 Z2_HOST_INTN 24
53 6 WS_KBD6
WS_LEFT_SHIFT_KEY 23
53 6 WS_KBD7
53
53 WS_LEFT_OPTION_KEY 22
53 6 WS_KBD8
21
53 6 WS_KBD9
20
56
55
54
53
52
51
50
49
48
47
46
45
44
43
53 6 WS_KBD10
19
P2_5
P2_7
P0_1
P0_3
P0_5
P0_7
VSS
VDD
P0_6
P0_4
P0_2
P0_0
P2_6
P2_4
R5714 53 6 WS_KBD11
18
1 42 WS_KBD15_C 1
470 2 53 6 WS_KBD12
17
WS_CONTROL_KEY P2_3 P2_2 WS_KBD17 6 53 53
53 6 WS_KBD13
53
Z2_KEY_ACT_L 2 41 WS_KBD16N 53 1% 16
54 6 P2_1 P2_0 1/16W 53 6 WS_KBD14
TP_BOOT_CFG1 3 P4_7 CRITICAL P4_6 40 WS_KBD15_C 53 MF-LF 15
402 6 WS_KBD15_CAP
TP_P4_5 4 39 WS_KBD14 6 53 14
5
P4_5 U5701 P4_4
38
6 WS_KBD16_NUM
13
54 6 Z2_DEBUG3 P4_3 CY8C24794 P4_2 WS_KBD13 6 53
53 6 WS_KBD17
Z2_RESET 6 MLF 37 WS_KBD12 6 53 12
54 6 P4_1 P4_0 53 6 WS_KBD18
54 6 PSOC_MISO 7 P3_7 (SYM-VER2) P3_6 36 WS_KBD11 6 53 R5715 11
10K 53 6 WS_KBD19
54 6 PSOC_F_CS_L 8 P3_5 APN 337S2983 P3_4 35 WS_KBD10 6 53 53 WS_KBD16N 1 2 10
53 6 WS_KBD20
PSOC_MOSI 9 34 WS_KBD9 6 53 1% 9
54 6 P3_3 OMIT
P3_2 1/16W 53 6 WS_KBD21
PSOC_SCLK 10 33 WS_KBD8 6 53 MF-LF 8
54 6 P3_1 P3_0 402 53 6 WS_KBD22
54 6 Z2_MISO 11 P5_7 P5_6 32 WS_KBD7 6 53 R5710 7
53 6 WS_KBD23
Z2_CS_L 12 31 WS_KBD1 6 53 1K 6
54 6 P5_5 P5_4 46 45 6 SMC_ONOFF_L 1 2 6 WS_KBD_ONOFF_L
OUT 5
54 Z2_MOSI 13 P5_3 P5_2 30 WS_KBD2 6 53 5% 6 PP3V42_G3H
Z2_SCLK 14 P5_1 P5_0 29 WS_KBD3 6 53 1/16W47 4673456643652364215317497 48 4
53 6 WS_LEFT_SHIFT_KBD
54 6
23 P7_7
24 P7_0
25 P1_0
26 P1_2
27 P1_4
28 P1_6
MF-LF
15 P1_7
16 P1_5
17 P1_3
18 P1_1
C 402 3
C
19 VSS
22 VDD
THRML 1 C5710 53 6 WS_LEFT_OPTION_KBD

20 D+
21 D-
57 2
PAD 0.1UF 53 6 WS_CONTROL_KBD
20% 1
2 10V
CERM
402
PLACEMENT_NOTE=NEAR J5713 NC 31
TP_PSOC_SCL WS_KBD4 6
ISOLATION CIRCUIT F-RT-SM
53
FF14-30A-R11B-B-3H
WS_KBD5 6 53 49 48 47 46 45 43 23 21 17 7 6
73 66 65 64 53
PP3V42_G3H C5725
WS_KBD6 6 53 0.1UF
2 1
TP_PSOC_SDA
TP_ISSP_SDATA_P1_0 CRITICAL 20%
SMC_MANUAL_RESET LOGIC
10V
5 TC7SZ08AFEAPE
ISSP SDATA/I2C SDA 101 87 73 PP3V3_S3 2 SOT665 CERM
34 33 32 31 20 17 8 7 6
72 55 54 53 50 48 36 35 A 402 48 47 46 45 43 23 21 17 7 6 PP3V42_G3H
NC_PSOC_P1_3 4 WS_LEFT_SHIFT_KEY 53 73 66 65 64 53 49
6
Z2_CLKIN 6 54
WS_LEFT_SHIFT_KBD 1
U5725Y 1 C5758
53 6 B 0.1UF
10%
3 16V
2 X7R-CERM
402
TP_P7_7
8 6 TP_ISSP_SCLK_P1_1
ISSP SCLK/I2C SCL
48 47 46 45 43 23 21 17 7 6
PP3V42_G3H APN 311S0406
73 66 65 64 53 49
CRITICAL CRITICAL
R5701 5 TC7SZ08AFEAPE 5
DIFFERENTIAL_PAIR=USB2_TPAD PP3V3_S3 2 SOT665 SN74LVC1G10
24 36 35 34 33 32 31 20 17 8 7 6
101 87 73 72 55 54 53 50 48 A
WS_LEFT_OPTION_KEY 53 53 6 WS_LEFT_SHIFT_KBD 1 A SC70
USB_TPAD_P 1 2 USB_TPAD_R_P 4
93 36
5% PP3V3_S3_PSOC 53 WS_LEFT_OPTION_KBD 1
U5726Y 53 6 WS_LEFT_OPTION_KBD 3
U5703
B Y
4 46
1/16W DIFFERENTIAL_PAIR=USB2_TPAD
53 6 B 53 6 WS_CONTROL_KBD 6 C SMC_TPAD_RST_L
MF-LF NET_SPACING_TYPE=USB
402 NET_PHYSICAL_TYPE=USB_85D 3
B TO MLB CONNECTOR
2
B
R5702
24
93 36 USB_TPAD_N 1 2 USB_TPAD_R_N
1
DIFFERENTIAL_PAIR=USB2_TPAD 5%
1/16W
DIFFERENTIAL_PAIR=USB2_TPAD
NET_SPACING_TYPE=USB PP3V42_G3H
R5769 1
R5770 1
R5771
MF-LF NET_PHYSICAL_TYPE=USB_85D 33K 33K 33K
402 49 48 47 46 45 43 23 21 17 7 6 5% 5%
73 66 65 64 53
1/16W 5%
MF-LF 1/16W 1/16W
CRITICAL MF-LF MF-LF
5 TC7SZ08AFEAPE 2 402 2 402
PP3V3_S3 2 SOT665 2 402
48 36 35 34 33 32 31 20 17 8 7 6 A
101 87 73 72 55 54 53 50
4 WS_CONTROL_KEY 53
WS_CONTROL_KBD 1
U5727Y
53 6 B
3
U5701 CHIP DECOUPLING
PLACE C5701, C5702 & C5703 PLACE C5704, C5705 & C5706
CLOSE TO U5701 VDD PIN 22 CLOSE TO U5701 VDD PIN 49
TPAD BUTTONS DISABLE

R5704 BUTTON_DISABLE
1.5 PP3V3_S3 53 PLACE THESE COMPONENTS CLOSE TO J5800
53 PP3V3_S3_PSOC 1 2 6 7 8 17 20 31 32 33 34 35 36 48 50 53
MIN_LINE_WIDTH=0.50MM 54 55 72 73 87 101
THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB
MIN_NECK_WIDTH=0.20MM 5%
VOLTAGE=3.3V 1/16W
MF-LF
1 C5701 1 C5702 1 C5703 1 C5704 1 C5705 1 C5706 402
4.7UF 100PF 0.1UF 100PF 0.1UF 4.7UF
20% 5% 10% 5% 10% 20% Q5701
2 6.3V
X5R 2 50V
CERM 2 16V
X7R-CERM 2 50V
CERM 2 16V
X7R-CERM 2 6.3V
X5R SSM3K15FV D 3
603 402 402 402 402 603 SOD-VESM-HF
PAGE TITLE
THE TPAD BUTTONS WILL BE DISABLE
SMC_LID
1 G S 2 WHEN THE LID IS CLOSED
LID OPEN => SMC_LID_LC ~ 3.42V
WELLSPRING 1
64 46 45 DRAWING NUMBER SIZE
IN
LID CLOSE => SMC_LID_LC < 0.50V
REVISION
R
<E4LABEL>
<BRANCH>
57 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BOOSTER +18.5VDC FOR SENSORS
BOOSTER DESIGN CONSIDERATION:

- POWER CONSUMPTION
- DROOP LINE REGULATION
D
- RIPPLE TO MEET ERS
- 100-300 KHZ CLEAN SPECTRUM
D
- STARTUP TIME LESS THAN 2MS
APN 152S0504 - R5812,R5813,C5818 MODIFIED
72 67 66 61 58 56 46 44 43 42 33 31 7 6
101 82
PP5V_S3 CRITICAL IPD FLEX CONNECTOR
L5801 D5802
3.3UH-870MA SOD-323 R5806
R5805
0
2
INPUT_SW 1 2 BOOST_SW 1 2 PP18V5_S3_SW 1 2 PP18V5_S3
1/16W
MF-LF
MIN_LINE_WIDTH=0.50MM MIN_LINE_WIDTH=0.50MM
402
VLF3010AT-SM-HF MIN_LINE_WIDTH=0.50MM APN 516S0689
5%
5%
0
0.50MM MIN_NECK_WIDTH=0.20MM MIN_NECK_WIDTH=0.20MM
0.20MM MIN_NECK_WIDTH=0.20MMB0520WSXG VOLTAGE=18.5V 1/16W VOLTAGE=18.5V
SWITCH_NODE=TRUE
MF-LF
APN 371S0313 402 CRITICAL
1
1
1 C5818 R5812 J5800
PP5V_S3_BOOSTER 39PF 1M 55560-0228
5% 1%
MIN_LINE_WIDTH=0.50MM 1/16W M-ST-SM
MIN_NECK_WIDTH=0.20MM 2 50V
CERM MF-LF
VOLTAGE=5V APN 353S1401 402 2 402 2 1
2
53 6 Z2_CS_L 4 3 Z2_KEY_ACT_L 6 53
VIN 6 5 Z2_RESET 6 53
53 6 Z2_DEBUG3
U5805
1 C5819 8 7 PSOC_F_CS_L 6 53
1 L 4 BOOST_FB 1UF 53 Z2_MOSI
FB 10%
53 6 Z2_MISO PICKB_L 6 53
TPS61045 10 9
QFN 2 25V
X5R
3 5 Z2_BOOST_EN 603-1 53 6 Z2_SCLK
12 11 PSOC_MISO 6 53
DO CTRL 6 54
54 6 Z2_BOOST_EN
14 13 PSOC_MOSI 6 53
CRITICAL 1
R5813 16 15 PSOC_SCLK 6 53
8 53 Z2_HOST_INTN
SW
71.5K 18 17 SMBUS_SMC_A_S3_SDA 6 33 45 48
7 PGND
1%
6 GND
THRML
PAD 1 1/16W Z2_CLKIN 20 19 SMBUS_SMC_A_S3_SCL 69733 45 48
1 C5816 1 C5817 R5811 MF-LF
2 402
53 6
PP3V3_S3 22 21 PP18V5_S3 6 54
97
100K 53 50 48 36 35 34 33 32 31 20 17 8 7 6
9
0.1UF 2.2UF 1%
101 87 73 72 55
10% 10% 1/16W
2 16V
X7R-CERM 2 16V
X5R MF-LF
402 603 2 402
C C
B B
Keyboard LED Driver

69 68 63 62 58 52 51 50 48
25 24 23 21 20 19 18 17 7 6
PP3V3_S0 72 70 69 68 52 47 42 23 7 6 PP5V_S0 CRITICAL
88 86
47 46 42 40 37 34 30 28 27 26
99 88 87 85 84 83 80 73 72 L5850 J5815 pin 1 is grounded
10UH-0.58A-0.35OHM CRITICAL
1 1 2 KBDLED_SW on keyboard backlight flex
To detect Keyboard backlight, SMC will R5853 MIN_LINE_WIDTH=0.3 MM J5815
470K 1098AS-SM MIN_NECK_WIDTH=0.25 MM FF18-4A-R11AD-B-3H
5% SWITCH_NODE=TRUE
tristate SMC_SYS_KBDLED: 1/16W C5850 1 F-RT-SM
1
MF-LF 1UF SMC_KDBLED_PRESENT_L 1

LOW = keyboard backlight present 402 2 10% VIN 54 6
10V 2 2
X5R SW 3
HIGH= keyboard backlight not present 402-1 3
45 SMC_SYS_KBDLED 6 CTRL LED 5 6 KBDLED_ANODE 4
BOM OPTION: KBDLED_YES MIN_LINE_WIDTH=0.2 MM
CRITICAL 1
NO STUFF U5850 R5855 APN 518S0612
A R5853 ALWAYS PRESENT R58541 R58521 LT3491
DFN
10
1%
1/16W
4.7K 10K MF-LF PAGE TITLE
5%
1/16W
MF-LF
5%
1/16W
MF-LF
2 402 KBD BACKLIGHT CONNECTOR WELLSPRING 2
402 2 402 2 CAP 4 KBDLED_CAP DRAWING NUMBER SIZE
THRML MIN_NECK_WIDTH=0.25 MM
GND PAD 1 C5855 REVISION
1UF
7
2
R
10% <E4LABEL>
2 35V
X5R NOTICE OF PROPRIETARY PROPERTY: BRANCH
603 THE INFORMATION CONTAINED HEREIN IS THE <BRANCH>
54 6
SMC_KDBLED_PRESENT_L PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
58 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
Analog SMS
R5921 PULLS UP SMS_PWRDN TO TURN OFF SMS WHEN PIN IS NOT BEING DRIVEN BY SMC
Desired orientation when
53 50 48 36 35 34 33 32 31 20 17 8 7 6 PP3V3_S3
101 87 73 72 55 54 placed on board top-side:
1 C5922 1 C5926
14
NO STUFF 0.1UF 10UF
R59211 VDD
10%
2 16V
X5R
20%
2 4V
X5R
10K 402 603 +Y
5%
1/16W U5920
MF-LF
402 2
AP344ALH +X
Front of system
LGA
1 FS VOUTX 12 SMS_X_AXIS OUT 45 +Z (up)
55 45 IN SMS_PWRDN 55 45 SMS_PWRDN 5 PD CRITICAL
MAKE_BASE=TRUE VOUTY 10 SMS_Y_AXIS OUT 45
SMS_SELFTEST 2 ST
VOUTZ 8 SMS_Z_AXIS OUT 45
15 RES
C NO STUFF
1
NC 4 RES Circle indicates pin 1 location when placed C
R5922 NC 3 NC NC 11 NC
in correct orientation
10K 6 NC
5% NC NC 13 NC
1/16W
MF-LF NC 9 NC NC 16 NC 1 C5923 1 C5924 1 C5925
2 402 GND 0.1UF 0.1UF 0.1UF
10% 10% 10%
16V 16V 16V
7
2 X5R 2 X5R 2 X5R
402 402 402
PLACE CAPS ON SMS OUTPUT SIGNALS CLOSE TO SMC
1 1 1
R5940 R5941 R5942
0 0 0
5% 5% 5%
1/16W 1/16W 1/16W
Alternate location Analog SMS MF-LF
2 402
MF-LF
2 402
MF-LF
2 402
55 54
101
53
Desired orientation when
35 34
17 8 7
33
6 PP3V3_S3
32 31 20 placed on board top-side:
50 48
87 73
36
72 NO STUFF NO STUFF
1 C5932 1 C5936
14
0.1UF 10UF
B VDD
10%
2 16V
X5R
20%
2 4V
X5R
B
402 603 +Y
U5930
AP344ALH +X
Front of system
LGA
1 FS VOUTX 12 SMS_ALT_X_AXIS +Z (up)
5 PD CRITICAL
VOUTY 10 SMS_ALT_Y_AXIS
SMS_ALT_SELFTEST 2 ST
VOUTZ 8 SMS_ALT_Z_AXIS
15 RES
NC 4 RES Circle indicates pin 1 location when placed
1
R5932 NC 3 NC NC 11 NC
in correct orientation
10K 6 NC
5% NC NC 13 NC
1/16W
MF-LF NC 9 NC NC 16 NC
2 402 GND
7
PAGE TITLE
Sudden Motion Sensor (SMS)

DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
59 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MIN_LINE_WIDTH=0.3mm MIN_LINE_WIDTH=0.3mm
R6003 MIN_NECK_WIDTH=0.25mm MIN_NECK_WIDTH=0.25mm R6004 82 101
PP5V_S3 1
10 2
PP5V_S3_DEBUG_ADC_AVDD_R PP5V_S3_DEBUG_ADC_DVDD_R 1
10 2
PP5V_S3 61 66
46 54
67 66 61 58 56 54 46 44 43 42 33 31 7 6 6 7 31 33 42
PLACE_NEAR=R3404.1:3mm PLACE_NEAR=R4598.2:3mm 101 82 72 VOLTAGE=5V VOLTAGE=5V 43 44
56 58
5% 5% 67 72
1/16W 1/16W DEBUG_ADC
XW6010
SM
XW6020
SM
DEBUG_ADC MF-LF
402
DEBUG_ADC DEBUG_ADC DEBUG_ADC DEBUG_ADC MF-LF
402
PP3V3_WLAN_F 1 2 P3V3_WLAN_F_XW PP5V_SW_ODD 1 2 P5V_SW_ODD_XW
1 C6000 1 C6001 C6002 1 C6003 1
33 42 6
0.1UF 10UF 0.1UF 10UF
20% 20% 20% 20%
DEBUG_ADC DEBUG_ADC 2 10V
CERM 2 10V
X5R
10V
CERM 2
10V 2
X5R
1 1 PLACE_NEAR=U6000.23:5mm 402 603 402 603
R6010 PLACE_NEAR=U6000.22:5mm
R6020
12
13
21
649K 1M
1% 1%
1/16W DEBUG_ADC 1/16W DEBUG_ADC
MF-LF MF-LF AVDD DVDD
2 402 R6012 2 402 R6022 DEBUG_ADC
226K 2 226K 2 U6000 R6001 D
D P3V3_WLAN_F_DIV
DEBUG_ADC
1
1%
ADC_CH0 56 P5V_SW_ODD_DIV
DEBUG_ADC
1
1%
ADC_CH1 56
56 ADC_CH0 22 CH0
LTC2309
QFN AD0 14 1
0 2
PLACE_NEAR=U4900.F1:3mm
SMBUS_SMC_MGMT_SDA BI 45 48 97
1 1/16W DEBUG_ADC 1
1/16W DEBUG_ADC
R6011 MF-LF R6021 MF-LF ADC_CH1 23 CH1 AD1 15 5%
1M
402 1 C6012 681K
402 1 C6022 56
ADC_CH2 24 CH2
DEBUG_ADC 1/16W
MF-LF
DEBUG_ADC
2.2UF 2.2UF 56
402
1%
1/16W 10% 1%
1/16W 10% 56 ADC_CH3 1 CH3 SDA 17 ADC_SDA R6002 PLACE_NEAR=U4900.E4:3mm
MF-LF 2 6.3V
X5R MF-LF 2 6.3V
X5R 0 SMBUS_SMC_MGMT_SCL
2 402 402 2 402 402 56 ADC_CH4 2 CH4 SCL 16 ADC_SCL 1 2 IN 45 48 97
56 ADC_CH5 3 CH5 5%
PLACE_NEAR=U6000.22:5mm PLACE_NEAR=U6000.23:5mm 1/16W
56 ADC_CH6 4 CH6 VREF 7 ADC_VREF MF-LF
402
56 ADC_CH7 5 CH7
6 COM REFCOMP 8 ADC_REFCOMP
DIVIDER: ~ 2/5 DEBUG_ADC DEBUG_ADC DEBUG_ADC
DIVIDER: ~ 2/3
I2C ADDRESS: 0X10 / 0X11 GND
THRM
PAD
1 C6004 1 C6005 1 C6006
ADC RANGE: 0V TO 4.096V 0.1UF 10UF 2.2UF
20% 20% 20%
9
10
11
18
19
20
25
LSB: 0.001V 2 10V
CERM 2 6.3V
X5R 2 6.3V
CERM
402 603 402-LF
67 66 61 58 56 54 46 44 43 42 33 31 7 6 PP5V_S3
101 82 72
DEBUG_ADC DEBUG_ADC
1 C6030 1 C6040
0.1UF 0.1UF
DEBUG_ADC 20% DEBUG_ADC 20%
2 10V
CERM 2 10V
CERM
R6030 402 R6050 402
243 DEBUG_ADC PLACE_NEAR=U6000.24:5mm 499 DEBUG_ADC
IN TP_ISNS_AIRPORT_P 1 2 99 ISNS_AIRPORT_R_P IN TP_ISNS_ODD_P 1 2 99 ISNS_ODD_R_P
1% U6030 DEBUG_ADC 1% U6040 DEBUG_ADC
1/16W 8 OPA2333 1/16W 8 OPA2333
C MF-LF
402 3
V+
DFN
1 ISNS_AIRPORT_IOUT 1 226K 2
R6034
ADC_CH2 56
MF-LF
402 3
V+
DFN
1 ISNS_ODD_IOUT
R6054
1
226K 2
ADC_CH4 56
C
DEBUG_ADC 2 1%
DEBUG_ADC 2 1%
V- 1/16W DEBUG_ADC V- 1/16W DEBUG_ADC
R6031 THRM MF-LF R6051 THRM MF-LF
TP_ISNS_AIRPORT_N 1
243 2 99 ISNS_AIRPORT_R_N 9
4
GAIN: 1239X 402 1 C6034 TP_ISNS_ODD_N 1
499 2 99 ISNS_ODD_R_N 9
4
GAIN: 561X 402 1 C6054
IN 2.2UF IN 2.2UF
1% 10% 1% 10%
1/16W 2 6.3V
X5R 1/16W 2 6.3V
X5R
MF-LF MF-LF
402 402 402 PLACE_NEAR=U6000.2:5mm 402
DEBUG_ADC DEBUG_ADC
DEBUG_ADC
1 PLACE_NEAR=U6000.24:5mm DEBUG_ADC
1
C6032 1 R6032 R6033 C6052 1 R6052 R6053
470PF 301K 1
301K 2 470PF 280K 1
280K 2
1% 1%
NOSTUFF 10%
50V 1/16W 10%
50V 1/16W
CERM 2 MF-LF 1%
1/16W
NOSTUFF CERM 2 MF-LF 1%
1/16W
402 2 402 MF-LF 402 2 402 MF-LF
402 C6033 402 C6053
470PF 470PF
1 2 1 2
10% NOSTUFF 10% NOSTUFF

50V 50V
CERM CERM
402 DEBUG_ADC 402
PLACE_NEAR=U6000.1:5mm R6060
412 PLACE_NEAR=U6000.3:5mm
FB Voltage Sense / Filter IN TP_ISNS_HDD_P 1 2 99 ISNS_HDD_R_P
DEBUG_ADC 1% U6040 DEBUG_ADC
1/16W OPA2333
78 77 76 75 50 8 7 6
XW6040
PP1V8R1V55_S0GPU_ISNS SM R6044 MF-LF
402 5
8
DFN R6064
FBVSENSE_IN 226K 2 V+ 7 ISNS_HDD_IOUT 226K 2
1 2 1 ADC_CH3 56 1 ADC_CH5 56
DEBUG_ADC
PLACEMENT_NOTE=Place near R5413 1% 6 V- 1%
1/16W
MF-LF
DEBUG_ADC R6061 THRM
1/16W
MF-LF
DEBUG_ADC
402 1 C6044 TP_ISNS_HDD_N 1
412 2 99 ISNS_HDD_R_N 9
4
GAIN: 845X 402 1 C6064
2.2UF 2.2UF
B 10%
2 6.3V
X5R
IN
1%
1/16W
10%
2 6.3V
X5R
B
MF-LF
402 402 402
DEBUG_ADC PLACE_NEAR=U6000.3:5mm
DEBUG_ADC
1
C6062 1 R6062 R6063
470PF 348K 1
348K 2
10% 1%
50V 1/16W
NOSTUFF CERM 2 MF-LF 1%
1/16W
402 2 402 MF-LF
402 C6063
470PF
1 2
10% NOSTUFF
50V
CERM
402
PLACE_NEAR=D9701.2:3mm
67 66 61 58 56 54 46 44 43 42 33 31 7 6 PP5V_S3
101 82 72 DEBUG_ADC
1 C6050 XW6080
SM
0.1UF PPVOUT_S0_LCDBKLT
20% 88 83 6 1 2 PVOUT_S0_LCDBKLT_XW
2 10V
CERM
402 DEBUG_ADC
1
PLACE_NEAR=U6000.4:5mm R6080 PLACE_NEAR=U6000.5:5mm
3
1M
V+ 1%
DEBUG_ADC 1/16W DEBUG_ADC
MF-LF
U6050 R6074 2 402 R6082
INA210
ISNS_LCDBKLT_IOUT 1 226K 2
226K 2
IN TP_ISNS_LCDBKLT_N 5 IN- SC70 OUT 6 ADC_CH6 56 PVOUT_S0_LCDBKLT_DIV 1 ADC_CH7 56
1% DEBUG_ADC 1%
TP_ISNS_LCDBKLT_P DEBUG_ADC GAIN: 200X 1/16W DEBUG_ADC 1
1/16W DEBUG_ADC
IN
4 IN+ REF 1 MF-LF
402 1 C6074 R6081 MF-LF
402 1 C6082
52.3K
A GND
2.2UF
10%
2 6.3V
1%
1/16W
MF-LF
2.2UF
10%
2 6.3V
X5R X5R
2
PAGE TITLE
402 2 402 402
PLACE_NEAR=U6000.5:5mm DEBUG SENSORS AND ADC
PLACE_NEAR=U6000.4:5mm DRAWING NUMBER SIZE

REVISION
DIVIDER: ~ 1/20 R
<E4LABEL>
<BRANCH>
60 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
C C
31 27 23 21 20 19 18 17 7 6
99 85 83 73 72 71 66 35
PP3V3_S5
1
R6101 C6100 1 CRITICAL
8
3.3K 0.1UF VCC
5% 20%
1/16W
MF-LF 10V
CERM 2 U6100
2 402 402 32MBIT
SOP
47 IN SPI_MLB_CLK 6 SCLK SI/SIO0 5 SPI_MLB_MOSI IN 47
MX25L3205DM2I-12G
SPI_MLB_CS_L 1 CE*
OMIT
47 IN
SO/SIO1 2 SPI_MLB_MISO OUT 47
SPI_WP_L 3 WP*/ACC
47 20 6 IN SPIROM_USE_MLB 7 HOLD*
NOTE: If HOLD* is asserted GND
4
ROM will ignore SPI cycles.
B B
PAGE TITLE
SPI ROM
DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
61 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AUDIO CODEC
CRITICAL APPLE P/N 353S2592
L6201
FERR-220-OHM PP5V_S3 6 7 31 33 42 43 44 46 54 56 58 61 66 67
72 82 101
87 72 71 24 23 21 16 12 7 6 PP1V8_S0 1 2 PP1V8_S0_AUDIO_DIG
IN
0402 VOLTAGE=1.8V
CRITICAL MIN_LINE_WIDTH=0.10MM
PP3V3_S0 50 51 52 54 58 62 63 68 69 72
MIN_NECK_WIDTH=0.10MM 6 7 17 18 19 20 21 23 24 25 26
C6210 1 1 C6211 27 28 30 34 37 40 42 46 47 48
73 80 83 84 85 87 88 99
4.7UF 0.1UF
20% 10% PP4V5_AUDIO_ANALOG IN
4V 2 2 16V CRITICAL VOLTAGE=4.5V
58
X5R X5R CRITICAL CRITICAL MIN_LINE_WIDTH=0.15MM
402 402
1 C6216 1 C6215 1 C6214 1 1 C6213 MIN_NECK_WIDTH=0.10MM
C6219 1UF 0.1UF
D 10UF
20% C6218 1 C6217
10%
1CRITICAL10V
X5R 2
10%
16V 2
X5R
0.1UF
10%
16V 2
10UF
20%
D
62 60 58 GND_AUDIO_HP_AMP 16V
TANT-POLY 2 0.1UF 10UF 402-1 402 X5R 2 6.3V
X5R
58 PP4V5_AUDIO_ANALOG 2012-LLP 10% 20% 402 603
IN 16V 2
24
46
25
CRITICAL CRITICAL X5R 2 16V
9
TANT-POLY GND_AUDIO_HP_AMP
C6221 1 1 C6220 VD VA_REF VA_HP VA
402 2012-LLP
GND_AUDIO_CODEC
58 60 62
1
R6210 10UF 10UF 58 59 63
20% 20% VBIAS_DAC 29 VBIAS_DAC
2.67K 6.3V 2 2 6.3V
1% X5R X5R HPOUT_L 38 MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM AUD_HP_PORT_L 60
1/16W 603 603 CS4206_FP 44 VHP_FILT+ OUT
MF-LF HPOUT_R 40 MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM AUD_HP_PORT_R OUT 60
2 402 CS4206_FN 41 VHP_FILT-
HPREF 39 MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM AUD_HP_PORT_REF IN 62
NC TP_AUD_GPIO_0 2 GPIO0/DMIC_SDA1 LINEOUT_L1+ 35 TP_AUD_LO1_P_L NC

NC TP_AUD_GPIO_1 12 GPIO1/DMIC_SDA2
/SPDIF_OUT2
LINEOUT_L1- 34 TP_AUD_LO1_N_L NC
NC TP_AUD_GPIO_2 14 GPIO2 LINEOUT_R1+ 36 AUD_LO1_P_R OUT 61
61 OUT AUD_GPIO_3 15 GPIO3 LINEOUT_R1- 37 AUD_LO1_N_R OUT 61
63 IN AUD_SENSE_A 13 SENSE_A LINEOUT_L2+ 31 AUD_LO2_P_L OUT 61
CS4206_FLYP LINEOUT_L2- 30 AUD_LO2_N_L OUT 61
CS4206_FLYC LINEOUT_R2+ 32 AUD_LO2_P_R OUT 61

CRITICAL CRITICAL 45 FLYP
AUD_LO2_N_R
LINEOUT_R2- 33
C6222 1 1 C6223 43 FLYC OUT 61
2.2UF 2.2UF 42 FLYN

20% 20%
6.3V 2 2 6.3V MICBIAS 16 AUD_CODEC_MICBIAS 63
CERM
402-LF
CERM
402-LF U6201 OUT
CS4206_FLYN
3 VL_HD CS4206ACNZC
QFN
VCOM 28 CS4206_VCOM
CRITICAL
1 VL_IF
AUD_LI_P_L
C 94 17 IN HDA_BIT_CLK 6 BITCLK
LINEIN_L+
LINEIN_C-
21
22 AUD_LI_REF
IN
IN
59
59
C
94 17 IN HDA_SYNC LINEIN_R+ 23 AUD_LI_P_R IN 59
R6211 10 SYNC
39
94 17 OUT HDA_SDIN0 1 2 94 AUD_SDI_R 8 SDI MICIN_L+ 18 AUD_MIC_INP_L IN 63
5% 5 SDO MICIN_L- 17 AUD_MIC_INN_L IN 63

1/16W
MF-LF MICIN_R+ 19 AUD_MIC_INP_R IN 63
402 11 RESET*
94 17 IN HDA_SDOUT MICIN_R- 20 AUD_MIC_INN_R IN 63
94 17 IN HDA_RST_L
62 IN AUD_SPDIF_IN 47 SPDIF_IN
AUD_SPDIF_OUT_CHIP 48 SPDIF_OUT
VREF+_ADC 27 CS4206_VREF_ADC NC
R6212
39
62 OUT AUD_SPDIF_OUT 1 2 DMIC_SCL 4 TP_AUD_DMIC_CLK NC
5%
1/16W
MF-LF
402 DGND THRM_PAD AGND
49
26
CRITICAL CRITICAL
C6224 1 1
C6225
1UF 10UF 1
10%
20V
20%
2 16V
R6213
TANT 2 POLY-TANT 100K
CASE-P3-HF CASE-B2-SM 5%
1/16W
MF-LF
2 402
63 59 58 GND_AUDIO_CODEC MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V
B B
4.5V POWER SUPPLY FOR CODEC

APPLE P/N 353S2234
CRITICAL CRITICAL MIN_LINE_WIDTH=0.15MM
L6200 MIN_LINE_WIDTH=0.15MM
FERR-220-OHM MIN_NECK_WIDTH=0.10MM
U6200
VOLTAGE=4.5V NOTES ON CODEC I/O
VOLTAGE=5V MAX8840-4.5V
67 66 61 58 56 54 46 44 43 42 33 31 7 6 PP5V_S3 1 2 4V5_REG_IN 1 IN UDFN
OUT 6 PP4V5_AUDIO_ANALOG 58
DIFF FSINPUT= 2.45VRMS
IN OUT
101 82 72
0402 SE FSINPUT= 1.22VRMS
R6200 BP 4 4V5_NR
DAC1 FSOUTPUT= 1.34VRMS
99 88
63 62 58 54 52 51 50 48 47
PP3V3_S0 1
2.21K2 4V5_REG_EN 3 SHDN*
CRITICAL
DAC2/3 FSOUTPUTDIFF= 2.67VRMS
25 24 23 21 20 19 18 17 7 6
46 42 40 37 34 30 28 27 26 IN
GND NC 5 C6202 DAC2/3 FSOUTPUTSE= 1.34VRMS
87 85 84 83 80 73 72 69 68 1%
1/16W
0.1UF 1 C6203
1UF
2
MF-LF
402
1 C6200 CRITICAL 1 2
10%
1UF 1 C6201 2 10V
X5R
10% 10%
10V
2 X5R 1UF 16V 402-1
10% X7R-CERM
402-1 XW6200
SM
2 10V
X5R
402
402-1
1 2 GND_AUDIO_CODEC 58 59 63
VOLTAGE=0V
NOSTUFF
R6201
0
A 1
5%
2
SYNC_MASTER=K18_AUDIO SYNC_DATE=09/21/2009 A
1/16W PAGE TITLE
MF-LF
402 AUDIO: CODEC/REGULATOR
DRAWING NUMBER SIZE
XW6201
SM MIN_LINE_WIDTH=0.15MM <SCH_NUM> D
1 2 MIN_NECK_WIDTH=0.10MM
GND_AUDIO_HP_AMP 58 60 62
Apple Inc. REVISION
VOLTAGE=0V R
<E4LABEL>
<BRANCH>
62 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
LINE INPUT VOLTAGE DIVIDER

CODEC RIN = 20K OHMS
NET RIN = 18K OHMS
FC = 8 HZ
VIN = 2VRMS, CODEC VIN = 1.14 VRMS
CRITICAL
R6301 C6301
3.3UF
AUD_LI_L 7.87K2
1 AUD_LI_L_DIV 1 2 AUD_LI_P_L
62 IN OUT 58
MIN_LINE_WIDTH=.1MM MIN_LINE_WIDTH=.1MM MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM 1% MIN_NECK_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
1/16W 10%
MF-LF 10V
402 CERM-X5R
805-1
C C
1
R6302
21.5K
1%
1/16W
MF-LF
2 402 CRITICAL
C6302
3.3UF
1 2
10%
10V
CERM-X5R
805-1
AUD_LI_REF OUT 58
62 IN AUD_LI_GND MIN_LINE_WIDTH=.1MM
MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
1
R6300
10
1% CRITICAL
1/16W
MF-LF
2 402
C6312
3.3UF
1 2
63 58 GND_AUDIO_CODEC 10%
IN 10V
CERM-X5R
805-1
1
R6312
B 21.5K
1%
B
1/16W
MF-LF
2 402
CRITICAL
R6311 C6311
3.3UF
7.87K2 1 2
62 IN AUD_LI_R 1 AUD_LI_R_DIV AUD_LI_P_R OUT 58
MIN_LINE_WIDTH=.1MM MIN_LINE_WIDTH=.1MM MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM 1% MIN_NECK_WIDTH=.1MM 10% MIN_NECK_WIDTH=.1MM
1/16W 10V
MF-LF CERM-X5R
402
805-1
A SYNC_MASTER=K18_AUDIO SYNC_DATE=07/29/2009 A
PAGE TITLE
AUDIO: LINE INPUT FILTER

DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
63 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
ZOBEL NETWORK & 1ST ORDER DAC FILTER PLACEHOLDER

R6501
0
AUD_HP_PORT_L 1 2 AUD_HP_L OUT
C 58 IN
CRITICAL
5%
1/10W
62
C
MF-LF
C6500 1 603
0.1UF
10% 1
16V
X7R-CERM 2
R6502
402 3.32K
1%
NC AUD_HP_ZOBEL_L 1/16W
MF-LF
1 2 402
R6500
39
5%
1/16W
MF-LF
402 2
62 58 IN GND_AUDIO_HP_AMP
R65101
39
5%
1/16W
MF-LF
402 2 1
R6512
NC AUD_HP_ZOBEL_R 3.32K
1%
CRITICAL 1/16W
MF-LF
C6510 1
2 402
0.1UF
10%
16V
X7R-CERM 2
402 R6511
AUD_HP_PORT_R 1
0 2 AUD_HP_R
58 IN OUT 62
5%
B 1/10W
MF-LF
603
B
A SYNC_MASTER=K18_AUDIO SYNC_DATE=07/29/2009 A
PAGE TITLE
AUDIO: HEADPHONE FILTER

DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
65 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
3X MONO SPEAKER AMPLIFIERS (SSM2315)

APN: 353S2500
GAIN = 6DB
1ST ORDER FC (L&R) = 120 HZ +/- 30%
1ST ORDER FC (SUB) = 58HZ +/- 30%
D PLACE C6610 CLOSE TO VDD PIN

D
67 66 61 58 56 54 46 44 43 42 33 31 7 6 PP5V_S3
101 82 72
CRITICAL
CRITICAL 1 C6613
CRITICAL CRITICAL C6612 1 0.1UF
47UF 10%
L6611 C6611 20%
6.3V
2 16V
X5R
FERR-1000-OHM 0.033UF TANT-POLY 2 402
CASE-A4
B1
B2
1 2 AUD_SPKRAMP_LIN_N 1 2 MIN_LINE_WIDTH=0.30 mm
58 IN AUD_LO2_N_L
0402 MIN_NECK_WIDTH=0.20 MM
NO_TEST=TRUE 10% VDD PVDD SPKRCONN_L_OUT_P OUT 6 62 99
16V
X5R
402
U6610
SSM2315
CRITICAL CRITICAL SSM2315L_N C1 IN- WLCSP OUT+ C3
L6610 C6610 SSM2315L_P A1 IN+ OUT_ A3
FERR-1000-OHM 0.033UF CRITICAL
C2 SD* MIN_NECK_WIDTH=0.20 MM
58 AUD_LO2_P_L 1 2 AUD_SPKRAMP_LIN_P 1 2
IN SPKRCONN_L_OUT_N OUT 6 62 99
0402 NO_TEST=TRUE GND
10%
16V
B3
A2
X5R
61 AUD_SPKRAMP_SHUTDOWN_L 402
CRITICAL R66011
100K
L6601 5%
1/16W
FERR-1000-OHM MF-LF
1 2 402 2
58 IN AUD_GPIO_3
0402
C C
PLACE C6620 CLOSE TO VDD PIN

67 66 61 58 56 54 46 44 43 42 33 31 7 6 PP5V_S3
101 82 72
CRITICAL
C6622 1 CRITICAL
CRITICAL CRITICAL 47UF
20%
1 C6623
L6621 6.3V 0.1UF
C6621
B1
B2
TANT-POLY 2 10% MIN_LINE_WIDTH=0.30 mm
FERR-1000-OHM 0.033UF CASE-A4 2 16V MIN_NECK_WIDTH=0.20 MM
X5R
1 2 1 2 VDD PVDD 402 SPKRCONN_R_OUT_P
58 IN AUD_LO2_N_R AUD_SPKRAMP_RIN_N OUT 6 62 99
0402 NO_TEST=TRUE 10%
U6620
16V SSM2315
X5R SSM2315R_N C1 IN- WLCSP OUT+ C3
402
CRITICAL CRITICAL SSM2315R_P A1 IN+ OUT_ A3 MIN_LINE_WIDTH=0.30 mm
L6620 C6620 C2 SD* CRITICAL MIN_NECK_WIDTH=0.20 MM
FERR-1000-OHM 0.033UF SPKRCONN_R_OUT_N 6 62 99
OUT
58 AUD_LO2_P_R 1 2 AUD_SPKRAMP_RIN_P 1 2 GND
IN
0402 NO_TEST=TRUE
B3
A2
10%
16V
X5R
402
61 AUD_SPKRAMP_SHUTDOWN_L
B B
PLACE C6630 CLOSE TO VDD PIN
67 66 61 58 56 54 46 44 43 42 33 31 7 6 PP5V_S3
101 82 72
CRITICAL
CRITICAL
CRITICAL CRITICAL C6632 1 1 C6633
L6631 C6631 100UF
20% 0.1UF
B1
B2
FERR-1000-OHM 10% MIN_LINE_WIDTH=0.30 mm

0.068UF 6.3V 2
1 2 AUD_SPKRAMP_SUBIN_N 1 2
TANT
CASE-AL1 2 16V
X5R MIN_NECK_WIDTH=0.20 MM
58 IN AUD_LO1_N_R VDD PVDD 402 SPKRCONN_S_OUT_P OUT 6 62 99
10V
U6630
CERM SSM2315
402 SSM2315S_N C1 IN- WLCSP OUT+ C3
CRITICAL CRITICAL A1 IN+
L6630 SSM2315S_P OUT_ A3 MIN_LINE_WIDTH=0.30 mm
FERR-1000-OHM C6630 CRITICAL MIN_NECK_WIDTH=0.20 MM
0.068UF C2 SD*
1 2 AUD_SPKRAMP_SUBIN_P 1 2
SPKRCONN_S_OUT_N OUT 6 62 99
58 IN AUD_LO1_P_R GND
A2
B3
10V
CERM
402
AUD_SPKRAMP_SHUTDOWN_L
A 61
PAGE TITLE
AUDIO: SPEAKER AMP

DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
66 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AUDIO JACK 1 LO/HP JACK, SPDIF TX
D
AUD_SPDIF_OUT IN 58
MIC CONNECTOR D
L6703
FERR-1000-OHM CRITICAL CRITICAL
1 2 HS_MIC_P OUT 63
J6780
78171-0003
0402 APN: 518S0520 M-RT-SM
99 88 87 L6702 4
73 72 69 68
51 50 48 47 FERR-1000-OHM CRITICAL
30 28 27 26
19 18 17 7 6 PP3V3_S0 1 2
25 24 23 21 20
46 42 40 37 34
HS_MIC_N OUT 63 63 6 OUT BI_MIC_N 1
63 62 58 54 52
85 84 83 80 0402 BI_MIC_SHIELD 2
APN: 514-0671 L6707
CRITICAL
63 6 OUT
BI_MIC_P 3
FERR-220-OHM 63 6 OUT
1 2 AUD_HP_PORT_REF 58
J6700 CRITICAL 0402
BI 5
SPDIF-TXRX-K24 L6701
F-RT-TH FERR-220-OHM-2.5A
MIC 6 AUD_CONNJ1_SLEEVE2 1 2 GND_AUDIO_HP_AMP 58 60
OUT
DETECT 5 AUD_CONNJ1_SLEEVEDET 0603 CRITICAL
SWITCH 2 AUD_CONNJ1_TIPDET L6704
LEFT 1 AUD_CONNJ1_TIP FERR-220-OHM
RIGHT 3 AUD_CONNJ1_RING 1 2 AUD_HP_R 60
BI
GND 4 AUD_CONNJ1_SLEEVE 0402
AUDIO CRITICAL
7 L6706
A - VIN FERR-220-OHM
8
B - VCC 1 2 AUD_HP_L BI 60
9
C - GND 0402
OPERATING VOLTAGE 3.3 R6700
10K
C POF
10
1
5%
2 AUD_J1_SLEEVEDET_R OUT 63 C
1/16W
SHELL 11 MF-LF
12 CRITICAL 2
402
CRITICAL L6705
SHIELD
13
1 C6700 1 C6701 CRITICAL 2 DZ6704 DZ6700
2
PINS 0.1UF 2.2UF DZ6703 6.8V-100PF FERR-1000-OHM CRITICAL SPEAKER CONNECTOR
10% 20% 402 6.8V-100PF
2 16V
X5R 2 6.3V
CERM
6.8V-100PF 402 1 2 AUD_J1_TIPDET_R OUT 63
402 402-LF 402
1 CRITICAL 0402 CRITICAL
2
CRITICAL 2
1
1
DZ6706 DZ6701 J6781
78171-0002
6.8V-100PF
402
6.8V-100PF
402
1 C6705 APN: 518S0519 M-RT-SM
100PF 3
5%
1 1 2 50V
CERM
402 99 61 6 SPKRCONN_L_OUT_P 1
IN
MIN_NECK_WIDTH=0.10 MM GND_CHASSIS_AUDIO_JACK 8 62 99 61 6 IN SPKRCONN_L_OUT_N 2
VOLTAGE=0V
4
XW6701
SM CRITICAL
1 2
J6782
XW6702 78171-0004
M-RT-SM
GND PATCH SM APN: 518S0521 5
1 2
73 72 69 68 63 R6701 99 61 6 IN SPKRCONN_S_OUT_P 1
46 42 40 37 34
20 19 18 17 7 6 PP3V3_S0 0 99 61 6 IN SPKRCONN_S_OUT_N 2
30 28 27 26 25 24 23 21 62 8 GND_CHASSIS_AUDIO_JACK 1 2
62 58 54 52 51 50 48 47
99 88 87 85 84 83 80 99 61 6 IN SPKRCONN_R_OUT_P 3
5%
1/16W 99 61 6 IN SPKRCONN_R_OUT_N 4
MF-LF NOSTUFF
B APN: 514-0635 402 NOSTUFF
CRITICAL CRITICAL B
6
C6783 1 1 C6784
R6749 33PF
5% 5%
33PF
J6750 AUD_J2_OPT_OUT 4.7 50V
1 2 AUD_SPDIF_IN OUT 58 NOSTUFF NOSTUFF CERM 2 2 50V
CERM
AUDIO-RCVR-M97 5% CRITICAL CRITICAL 402 402
F-RT-TH5 1/16W
DETECT FOR PLUG TYPE 5 MF-LF
402 CRITICAL
C6781 1 1 C6782
33PF 33PF
SWITCH 2 AUD_CONNJ2_TIPDET L6754 5%
50V
5%
50V
LEFT 1 FERR-1000-OHM CERM 2 2 CERM
402 402
RIGHT 3 AUD_CONNJ2_RING 1 2 AUD_LI_R 59
BI
GROUND 4 0402
CRITICAL
AUDIO
L6756
6 FERR-1000-OHM
A - VDD
B - GND 7 AUD_CONNJ2_TIP 1 2 AUD_LI_L 59
BI
8 0402
C - VOUT
CRITICAL
OPERATING VOLTAGE 3.3 L6758
POF 600-OHM-300MA
9 AUD_CONNJ2_SLEEVE 1 2 AUD_LI_GND 59
SHELL 10 0402
11 CRITICAL
SHIELD CRITICAL
PINS
12
1 C6750 CRITICAL DZ6754
2 L6752
2 FERR-1000-OHM
1UF DZ6758 6.8V-100PF
10% 402 1 2 AUD_J2_TIPDET_R
2 10V
63
X5R
ESDALC5-1BM2 OUT
SOD882 CRITICAL 0402
402-1 2 1
2
CRITICAL DZ6756
A DZ6757
ESDALC5-1BM2
1 6.8V-100PF
402 1 C6756 SYNC_MASTER=K18_AUDIO SYNC_DATE=07/29/2009 A
SOD882 PAGE TITLE
100PF
1
1 5%
50V
2 CERM
AUDIO: JACKS
402 DRAWING NUMBER SIZE
GND_CHASSIS_AUDIO_JACK 8 62 Apple Inc. <SCH_NUM> D

REVISION
R
<E4LABEL>
AUDIO JACK 2 LINE IN JACK, SPDIF RX THE INFORMATION CONTAINED HEREIN IS THE
<BRANCH>
67 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CODEC OUTPUT SIGNAL PATHS
FUNCTION VOLUME CONVERTER PIN COMPLEX MUTE CONTROL DET ASSIGNMENT PORT B LEFT(HEADSET MIC)
HP/LINE OUT 0X02 (2) 0X02 (2) 0X09 (9,A) N/A 0X09 (A) CRITICAL HP=80HZ, LP=8.82KHZ
SATELLITES 0X04 (4) 0X04 (4) 0X0B (11) GPIO_3 N/A MIKEY MIN_LINE_WIDTH=0.1MM
SUB 0X03 (3) 0X03 (03) 0X0A (10) GPIO_3 N/A L6880 MIN_NECK_WIDTH=0.1MM
SPDIF OUT N/A 0X08 (8) 0X10 (16) N/A 0X0C (B) FERR-1000-OHMVOLTAGE=3.3V
69 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6 PP3V3_S0 1 2 PP3V3_S0_HS_RX
47 46 42 40 37 34 30 28 27 26
99 88 87 85 84 83 80 73 72 0402 DRC MIKEY
CODEC INPUT SIGNAL PATHS
CRITICAL APN:353S2256
D FUNCTION
LINE IN
CONVERTER
0X05 (5)
PIN COMPLEX
0X0C (12,C)
VREF
N/A
DET ASSIGNMENT
0X0C (12,C)
MIKEY 1
C6880 D
3
10UF MIKEY
SPDIF IN 0X07 (7) 0X0F (15) N/A N/A 6.3V 20% 2 AVDD
603 X5R
BUILT-IN MIC 0X06 (6) 0X0D (13,B,RIGHT) MIC_BIAS (80%) N/A U6880
CD3275
HEADSET MIC 0X06 (6) 0X0D (13,V22,B,LEFT) MIKEY MIKEY PULLUPS ON MCP PAGE
DRC
88 48 47 42 32 30 28 26 25 17 SMBUS_PCH_CLK 6 SCL MICBIAS 1 HS_MIC_BIAS
IN
94 MIKEY
SYSTEM INT AND GPIO LINES SMBUS_PCH_DATA 5 2 HS_SW_DET
88 48 47 42 32 30 28 26 25 17
94 BI SDA DETECT CRITICAL
1
FUNCTION INT GPIO
19 OUT AUD_I2C_INT_L 7 INT* BYPASS 10 HS_RX_BP C6882
MIKEY ENABLE SATA4GP/GPIO 16 2.2UF
20%
MIKEY INTERRUPT PIRQ H GPIO 5 25 20 IN AUD_IPHS_SWITCH_EN 8 ENABLE 2 6.3V
TANT
PERIPHERAL DETECT PIRQ F GPIO 3 GND THM 402
4
9
11
MIKEY 1 GND_AUDIO_CODEC
C6881 58 59 63
0.01UF MIKEY MIKEY

16V 10%
402 CERM 2 1 1
R6881 R6882
63 59 58 GND_AUDIO_CODEC 1K 2.2K
1% 5%
1/16W 1/16W
MIKEY MF-LF MF-LF
CRITICAL 402 2 2 402
C6883 MIKEY
0.1UF R6884
AUD_MIC_INP_L 1 2 HS_MIC_HI_RC 1
2.2K 2 HS_MIC_P
58 OUT IN 62
PORT A DETECT (HEADPHONES) PORT B DETECT(SPDIF DELEGATE)
MIKEY 10%
5%
CRITICAL 25V
1/16W
C6886 X5R MIKEY MF-LF
1 MIKEY
402 402
AUD_SENSE_A 1
63 58 OUT 0.1UF R6883 1 MIKEY
C6885
PP3V3_S0_AUDIO_F 58 OUT AUD_MIC_INN_L 1 2 100K
5%
C6884 27PF
63
1 1 0.0082UF 2 5% 50V
R6806 R6805 10% 1/16W
2 10% 25V CERM 402
C 1 APN:376S0613 1%
39.2K 20.0K
1%
25V
X5R
402 XW6880
MF-LF
2 402
X7R 402
CRITICAL
CRITICAL C
R6801 1/16W
MF-LF
1/16W
MF-LF
SM
220K AUD_OUTJACK_INSERT_L 2 402 2 402 63 59 58 GND_AUDIO_CODEC 1 2 HS_MIC_N IN 62
5%
1/16W AUD_PORTA_DET_L NC AUD_PORTB_DET_L NC
MF-LF D 3
2 402 Q6800
SSM6N15FEAPE Q6801 D 3 Q6801 D 6
SOT563
SSM6N15FEAPE SSM6N15FEAPE
R6802 SOT563 SOT563
AUD_J1_TIPDET_R 1
47K 2 AUD_J1_DET_RC
63 62 IN
5 G S 4
5%
1/16W 1 PORT B RIGHT(BUILT-IN MIC)
5 G S 4 2 G S 1
MF-LF
402
C6801
0.1UF
10V
R6850 R6851
2 20% 100
CERM 402 58 IN AUD_CODEC_MICBIAS 1 2 MIC_BIAS_FILT 1 2.4K 2
63 59 58 GND_AUDIO_CODEC 1% CRITICAL 1%
1/16W 1/16W
1
R6803 MF-LF
402 C6852 MF
402-1
220K 2 2.2UF
63 PP3V3_S0_AUDIO_F 1 AUD_J1_SLEEVEDET_INV 20%
2 6.3V
TANT
1 5%
402
R6804 1/16W
MF-LF 63 59 58 GND_AUDIO_CODEC
220K 402 D 6
5% Q6800 63 62 AUD_J1_SLEEVEDET_R CRITICAL
L6850
1/16W
MF-LF SSM6N15FEAPE C6850 FERR-1000-OHM
SOT563 0.1UF
2 402
63 62 AUD_J1_SLEEVEDET_R 58 AUD_MIC_INP_R 1 2 BI_MIC_HI_F 1 2 BI_MIC_P 6 62
IN OUT IN
CRITICAL 10% 0402
1 C6802 2 G S 1 C6851 25V 1 CRITICAL
CRITICAL
0.01UF 0.1UF X5R R6852 1 1
10%
2 16V AUD_MIC_INN_R 1 2
402 100K
5%
C6853 C6854
CERM 58 OUT
1/16W 0.001UF 27PF
63 59 58 GND_AUDIO_CODEC 402
10% MF-LF 50V 10%
402 CERM 2 2 5% 50V
CERM 402 L6851
2 402 FERR-1000-OHM
B 25V
X5R
402
R6853
2.4K 2 BI_MIC_LO_F 1 2 BI_MIC_N IN 6 62
B
63 59 58 GND_AUDIO_CODEC 1
0402
1%
1/16W
EXTRACTION NOTIFICATION
XW6851
SM
MF
402-1
1 2 BI_MIC_SHIELD IN 6 62
CRITICAL
HP=80HZ
L6862
99 88
FERR-1000-OHM
72 69 68 63 62 58
46
21
42
20
40
19
37
18
34
17
30
7 6 PP3V3_S0 1 2 PP3V3_S0_AUDIO_F 63
28 27 26 25 24 23
IN
54
87
52
85
51
84
50
83
48
80
47
73
1 MIN_NECK_WIDTH=0.1MM
C6861 VOLTAGE=3.3V
0.1UF PORT C DETECT (LINE-IN)
10V 20% 2
402 CERM
63 59 58 GND_AUDIO_CODEC R6865 R6861 63 58 OUT AUD_SENSE_A
1
100K 2 AUD_PERPH_DET_R 1
100 2 AUD_IP_PERIPHERAL_DET OUT 19
5%
1/16W
5%
1/16W R68131
R6864 MF-LF MF-LF 63 PP3V3_S0_AUDIO_F 10K
402 402 1%
1
220K 2 AUD_J1_TIPDET_INV 1/16W
MF-LF
1 402 2
5%
1/16W R6811
MF-LF 270K AUD_INJACK_INSERT_L NC
402 Q6803 Q6803 D 3 5%
SSM6N15FEAPE
SOT563
D 6
SSM6N15FEAPE
1/16W
MF-LF Q6802
SOT563 2 402 SSM3K15FV D 3
SOD-VESM-HF
R6860
15K R6812
A 63 62 AUD_J1_TIPDET_R1
5%
2 TIPDET_FILT
2 G S 1
5 G S 4
62 AUD_J2_TIPDET_R 1
47K 2 AUD_J2_DET_RC
APN:376S0612
1/16W IN PAGE TITLE
1
MF-LF
402 C6860
0.1UF
5%
1/16W
MF-LF
1
C6811
1 G S 2
AUDIO: JACK TRANSLATORS
10V 402 0.1UF DRAWING NUMBER SIZE
2 20%
CERM 402 2 20% 10V
CERM 402 Apple Inc. <SCH_NUM> D
63 59 58 GND_AUDIO_CODEC REVISION
63 59 58 GND_AUDIO_CODEC R
<E4LABEL>
<BRANCH>
68 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MagSafe DC Power Jack

CRITICAL
CRITICAL
J6900 F6905
D 78048-0573
M-RT-SM 6 PP18V5_DCIN_FUSE
6AMP-24V
1 2
PPDCIN_G3H 6 7 65
D
MIN_LINE_WIDTH=1mm
1 MIN_NECK_WIDTH=0.20mm
PWR VOLTAGE=18.5V 1206-2
2
1 C6905 PP3V42_G3H 6 7 17 21 23 43 45 46 47 48 49
53 64 65 66 73
PWR
0.01UF
GND 3 20%
2 50V
SMC_BC_ACOK_VCC 1 C6908
GND 4 CERM 0.1UF
603 20% PLACEMENT_NOTE=PLACE NEAR U6900 and U6901
SIG 5 1
R6929 2 10V
CERM
1
2.0K VCC TC7SZ08AFEAPE 402
5% SOT665
1/16W 5
MF-LF U6900 A
2 SMC_BC_ACOK IN 45 46 65
2 402 MAX9940 4
SC70-5 Y U6901
46 45 BI SYS_ONEWIRE 4 INT EXT 5 B
1
CRITICAL 3
GND NC
3
NC
PP3V42_G3H
BIL CONNECTOR
48 47 46 45 43 23 21 17 7 6
73 66 65 64 53 49
516S0523
C6951 1
1-Wire OverVoltage Protection 0.1UF

10%
25V
CRITICAL
J6955
X5R 2 CPB6312-0101F
6 ADAPTER_SENSE 402
F-ST-SM
14 13
The chassis ground will otherwise float and can 2 1

send transients onto ADAPTER_SENSE when AC is 4 3
C connected. R6961
100 NC
6 5
NC C
53 46 45 SMC_LID 2 1 6 SMC_LID_R 8 7
OUT 402 1/16W
97
SMBUS_SMC_BSA_SDA 10 9
5%
MF-LF
48 45 6
65 64 BI TO SMC
48 45 6 SMBUS_SMC_BSA_SCL 12 11 SMC_BIL_BUTTON_L 6 45 46
65 64 BI OUT
97
C6955 1 C6953 1
C6952 1
C6954 1
16 15
0.001UF 47PF 47PF 0.001UF
10% 5% 5% 10%
50V 50V 50V 50V
CERM 2 CERM 2 CERM 2 CERM 2
402 402 402 402
3.425V "G3Hot" Supply

Supply needs to guarantee 3.31V delivered to SMC VRef generator
R6990
PPDCIN_G3H_OR_PBUS 1
1 2 PPDCIN_G3H_OR_PBUS_R
65
MIN_LINE_WIDTH=0.6 mm MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.4 mm 5% MIN_NECK_WIDTH=0.3 mm
VOLTAGE=18.5V 1/16W VOLTAGE=18.5V P3V42G3H_BOOST
MF-LF
402 C6990 1
7
1UF C6994 1
10%
25V VIN BOOST 0.1UF
X5R 2 10% CRITICAL
603-1 U6990 16V 2
X5R L6995
LT3970 402 33UH PP3V42_G3H
518-0358 0 DFN 6 7 17 21 23 43 45 46 47 48 49
53 64 65 66 73
1 2 2 EN/UVL0 SW 6 P3V42G3H_SW 1 2
B CRITICAL R6993 P3V42_EN_R CRITICAL
MIN_NECK_WIDTH=0.25 mm CDPH4D19FHF-SM Vout = 3.425
B
J6950 BATTERY CONNECTOR 1/16W
MF-LF
NC
9 PG
10 RT
353s2730
BD 8
1
SWITCH_NODE=TRUE
P3V42_BD_R
DIDT=TRUE
1
0 2 250mA max output
BAT-K19 402
5%
FB R6992 1
<Ra>
(Switcher limit)
M-RT-TH
PPVBAT_G3H_CONN GND THRM
1/16W
MF-LF C6995 1 R6995
P1 1 6 65 P3V42_RT PAD 402
47PF 1.00M
5% 1%
11
2 5% 1/8W
4
5
P2 50V
1 CERM 2 MF-LF
P3 3
R6991 402 2 805 1 C6999
P4 4 SMBUS_SMC_BSA_SCL 6 45 48 64 65 97 150K 22UF
1% P3V42G3H_FB 20%
P5 5 SYS_DETECT_L 1/16W
MF-LF <Rb> 2 6.3V
X5R-CERM
6 SMBUS_SMC_BSA_SDA
P6 6
2 402 1 603
7
CRITICAL 45 48 64 65 97
R6996
P7
8
D6950 C6950
549K
R6950 1
1
1%
1
P8 RCLAMP2402B 1/16W
9 SC-75 10K 0.1UF MF-LF
P9 10%
5%
1/16W
25V
2 2 402
10 X5R
SHLD_PIN MF-LF 402
402 2
SHLD_PIN 11
3
SHLD_PIN 12 GND
13
Vout = 1.25V * (1 + Ra / Rb)
SHLD_PIN
A SYNC_MASTER=K18_POWER SYNC_DATE=06/30/2009 A
PAGE TITLE
DC-In & Battery Connectors

DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
69 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
This node is powered

through body diodes:
Reverse-Current Protection * DCIN through Q7080.
Inrush Limiter
* PBUS through Q7085,
CRITICAL Charger TOP FETs and CRITICAL
Q7080 Q7055. Q7085
FROM ADAPTER HAT1128R01 HAT1128R01
SOI PPDCIN_G3H_OR_PBUS 64 SOI
64 7 6 PPDCIN_G3H MIN_LINE_WIDTH=0.6 mm
8
D4 3 VOLTAGE=18.5V 3 D4
8 PPDCIN_G3H_INRUSH
D
7
6
D3
S3
S2 2 2
S3
S2 D3
7
6
VOLTAGE=18.5V D
5
D2
D1 S1 1 1
R7080 1 C70851 R7085 1 S1
D2
D1 5
100K 0.1UF 470K
GATE 5% 10% 1% GATE
1/16W 25V
2 X5R 1/16W
4 MF-LF 402 MF-LF 4
2 402 2 402
CHGR_SGATE_DIV CHGR_AGATE_DIV
MIN_NECK_WIDTH=0.3 mm MIN_NECK_WIDTH=0.3 mm
1 1
R7081 R7086
62K 332K
5% 1%
CRITICAL 1/16W 1/16W
MF-LF MF-LF
D7005 2 402 402 2
BAT30CWFILM
SOT-323 (CHGR_SGATE) (CHGR_AGATE)
1
R7005
20 R7021
3 CHGR_DCIN_D_R 1 2 (CHGR_DCIN)
1
10 2
5%
2 1/16W CRITICAL
ACIN pin threshold is 3.2V, +/- 50mV MF-LF 5%
CHGR_CSI_R_P 4 2
402
1 C7020 1/16W
MF-LF
99
R7020
Divider sets ACIN threshold at 13.55V 0.047UF 402 0.020
0.5%
10% 1W
10V CHGR_CSI_R_N
Input impedance of ~40K meets 2 CERM R7022 99 MF-LF
30mA max load 402 3 1 0612
sparkitecture requirements 1
10 2
PP5V1_CHGR_VDD R7001 PPDCIN_G3H_CHGR
MIN_LINE_WIDTH=0.2 mm 4.7 5% MIN_LINE_WIDTH=0.6 mm
48 47 46 45 43 23 21 17 7 6 PP3V42_G3H MIN_NECK_WIDTH=0.1 mm 1 2 PP5V1_CHGR_VDDP 1/16W MIN_NECK_WIDTH=0.4 mm CRITICAL CRITICAL
73 66 64 53 49 VOLTAGE=5.1V MIN_LINE_WIDTH=0.2 mm MF-LF VOLTAGE=18.5V
5%
1/16W
VOLTAGE=5.1V
402 1
C7030 1
C7031 1 C7035 1 C7036 1 C7037
MF-LF 22UF 22UF 1UF 1UF 0.001UF
402 C7001 1 C7022 1 1 C7021 20%
2 25V
20%
2 25V
10%
25V
2 X5R
10%
25V
2 X5R
10%
2 50V
NO STUFF 1UF 0.1UF 0.1UF POLY-TANT POLY-TANT X7R
BATT_3S C7002 1 10% 10% 10% CASE-D2-SM CASE-D2-SM 603-1 603-1 402
C
C R70121 1UF
10%
1
R7002
100K
10V 2
X5R
402
25V 2
X5R
402
2 25V
X5R
402
1K 10V 2 5%
19
20
1% X5R 1/16W
1/16W 402 65 MF-LF
MF-LF 2 402 5
402 2 GND_CHGR_AGND VDD VDDP
R7000 12 VHST CRITICAL DCIN 2 CHGR_DCIN CRITICAL
1 SMC_RESET_L
0
CHGR_RST_L 13
D Max Current = 8A
R7010 IN 1 2 SMB_RST_N
SGATE 26 CHGR_SGATE Q7030
30.1K
1%
5% 48
1/16W97
45 6
64 IN SMBUS_SMC_BSA_SCL 11 SCL U7000 AGATE 1 CHGR_AGATE 1 C7025
4 G RJK0332DPB-01 (L7030 limit)
1/16W MF-LF48 SMBUS_SMC_BSA_SDA 10 SDA TQFN 0.22UF LFPAK-SM
MF-LF 402 97
45 6 BI
CSIP 28 CHGR_CSI_P f = 400 kHz
ISL6259HRTZ
64 97
2 402 73 IN CHGR_VFRQ 4 VFRQ 10%
CSIN 27 97 CHGR_CSI_N 10V
2 CERM S CRITICAL
CHGR_CELL 6 CELL CRITICAL
Float CELL for 1S 25 CHGR_BOOT
402
L7030 TO SYSTEM
CHGR_ACIN 3 ACIN BOOT
DIDT=TRUE
1 2 3
3
4.7UH-10.2A
F7040
UGATE 24 CHGR_UGATE 8AMP-24V
GATE_NODE=TRUE DIDT=TRUE
1 CHGR_ICOMP 5 ICOMP PHASE 23 CHGR_PHASE 2 1 2 PPBUS_G3H 6 7 40 49 66 67 69 70 82
R7011 CHGR_VCOMP 7 VCOMP MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm FDA1254F-SM
86 89
9.31K LGATE 21 CHGR_LGATE SWITCH_NODE=TRUE 1206

1% CHGR_VNEG 8 VNEG GATE_NODE=TRUE DIDT=TRUE DIDT=TRUE 1
1/16W 1 CHGR_CSO_P 18 CSOP 16 CHGR_BGATE NO STUFF
MF-LF
2 402
R7015 97 BGATE
R70391
220K 97 CHGR_CSO_N 17 CSON 20V/V AMON 9 CHGR_AMON OUT 49
5% 180
THRM_PAD
1/16W 36V/V BMON 15 CHGR_BMON 5%

(AGND)
OUT 49
MF-LF 1/10W PPVBAT_G3H_CHGR_REG
BATT_2S 2 402
1 C7050 (OD) ACOK 14 SMC_BC_ACOK OUT 45 46 64 MF-LF MIN_LINE_WIDTH=0.6 mm
CRITICAL
PGND
1UF 603 2 MIN_NECK_WIDTH=0.4 mm

R70131 CHGR_VCOMP_R 10%
16V 5
VOLTAGE=12.6V 1
C7040 1 C7045
1K 2 X5R
22UF 0.001UF
1% 10%
402 CHGR_PHASE_RC
29
22
1/16W 353S2392 CRITICAL 20%

MF-LF C7015 1 DIDT=TRUE 2 25V
POLY-TANT 2 50V
X7R
402 2 470PF
10% 4
Q7035 CASE-D2-SM 402
50V RJK0305DPB BATT_2S CRITICAL
CERM 2 NO STUFF
402
LFPAK-HF
1 C7039 R7050 Q7055
0.005 SI7137DP
470PF
B 10%
2 50V
CERM
1%
1W
MF
SO-8
TO/FROM BATTERY B
R70161 XW7000 402
0612
S
1 2 3 1 2 PPVBAT_G3H_CHGR_R
3.01K
2 3
D
1% 3 4 MIN_NECK_WIDTH=0.4 mm PPVBAT_G3H_CONN 6 64
1/16W 1 2 (GND) VOLTAGE=12.6V MIN_LINE_WIDTH=0.6 mm
5
MF-LF
C7055 1 C7056 1 C7057 1 MIN_NECK_WIDTH=0.4 mm
1
402 2 1UF 0.1UF 0.01uF VOLTAGE=12.6V
G
10% 10% 10%
CHGR_VNEG_R 25V 16V 2 16V
X5R 2 X5R CERM 2
4
603-1 402 402
1 C7016 (CHGR_CSO_P) R7051 2.2 1 2 99 49 CHGR_CSO_R_P
5% 1/16W MF-LF 402
470PF
10% (CHGR_CSO_N) R7052 0 1 2 99 49 CHGR_CSO_R_N
2 50V
CERM 5% 1/16W MF-LF 402
402
(PPVBAT_G3H_CHGR_R) (PPVBAT_G3H_CHGR_R)
(CHGR_BGATE)
1 C7042 C7011 1 1 C7000 C7005 1 C7026 1
0.033UF 0.01UF 1UF 0.22UF 0.001UF
10% 10% 10% 20% 10%
2 16V
X5R
16V
CERM 2 2 10V
X5R
25V 2
X5R
50V
CERM 2
TABLE_5_HEAD
402 402 402-1 603 402 PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
65 GND_CHGR_AGND TABLE_5_ITEM
MIN_LINE_WIDTH=0.2 mm 107S0139 1 RES,0.010,0.5%,1W,0612-1 R7050 CRITICAL BATT_3S

VOLTAGE=0V
PAGE TITLE
PBus Supply & Battery Charger

DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
70 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
73 45
SMC_PM_G2_EN
1
R7273
100K
D 5%
1/16W
MF-LF
D
2 402
86 82 70 69 67 65 49 40 7 6
PPBUS_G3H
89
CRITICAL
R7264 C7280 1 C7282 1
0 68UF 0.001UF
CRITICAL 2 1 P3V3S5_VBST_R 20% 10%
C7243 1
1 C7241 72 23 7 6 PP5V_S5 16V
POLY-TANT 2
1 C7281CERM
50V 2
0.001UF C7240 1 1UF
5%
1/16W CASE-D2E-SM 1UF 402
10%
50V 68UF MF-LF 10%
CERM 2 20% 10% P5VP3V3_VREG3 402 2 25V
402 16V
POLY-TANT 2 2 25V
X5R
X5R
603-1
603-1 R7224 P5VP3V3_VREF
CASE-D2E-SM
0
P5VS3_VBST_R 2 1
C7200 1 C7203 1 1 C7205
5 5% 1UF 10UF
1/16W 1UF 10% 20% C7264 1
CRITICAL
1 C7224 MF-LF
402
10%
25V 2
25V
X5R 2
10V
2 X5R 0.1UF
D 0.1UF X5R 603-1 603 10%
16
10% 603-1 1 50V 2
3
f=365KHz Q7220 G 4 2 50V
X7R VIN VREF C7201 X7R
603-1 f=460KHz
SIS424DN 603-1 14 SKIPSEL VREG3 8
2
0.22UF 99
72 67 61 58 56 54 46 44 43 42 33 31 7 6
101 82
PP5V_S3 PWRPK-1212-8-SM 2 10% CRITICAL PP3V3_S5 31 35 57 71
6 7 17 18 19
20 21 23 27
10V
4 TONSEL VREG5 17 CERM D1 Q7260 72 73 83 85
Vout = 5.0V S
22 VBST1
U7201 402 RJK0384DPA 152S1115 Vout = 3.3V
P5VS3_VBST QFN VBST2 9 P3V3S5_VBST WPAK CRITICAL
9.1A MAX OUTPUT CRITICAL MIN_LINE_WIDTH=0.6 mm MIN_LINE_WIDTH=0.6 mm 1 G1 7.2A MAX OUTPUT
L7220 3 2 1 MIN_NECK_WIDTH=0.2 mm
P5VS3_DRVH TPS51125
21 DRVH1 DRVH2 10 P3V3S5_DRVH MIN_NECK_WIDTH=0.2 mm L7260
(Q7220 limit) MIN_LINE_WIDTH=0.6 mm GATE_NODE=TRUE DIDT=TRUE GATE_NODE=TRUE DIDT=TRUE MIN_LINE_WIDTH=0.6 mm S1/D2 7 2.2UH-10A-14MOHM (L7260 limit)
MIN_NECK_WIDTH=0.2 mm 20 LL1 MIN_NECK_WIDTH=0.2 mm
1 2 P5VS3_LL LL2 11 P3V3S5_LL 1 2
4.7UH-13A-15MOHM MIN_LINE_WIDTH=0.6 mm SWITCH_NODE=TRUE DIDT=TRUE CRITICAL SWITCH_NODE=TRUE DIDT=TRUE MIN_LINE_WIDTH=0.6 mm FDVE0830-SM
CRITICAL PCMB104E4R7-SM MIN_NECK_WIDTH=0.2 mm 19 DRVL1 MIN_NECK_WIDTH=0.2 mm NO STUFF CRITICAL
P5VS3_DRVL DRVL2 12 P3V3S5_DRVL 6 G2
R7262 1
C7252 1 C7250 1 NO STUFF1 Q7225 5 MIN_LINE_WIDTH=0.6 mm
CRITICAL MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE DIDT=TRUE GATE_NODE=TRUE DIDT=TRUE MIN_LINE_WIDTH=0.6 mm
10
1
C7292
330UF 10UF R7222 24 VO1 VO2 7
150UF-.025-OHM
C 20%
6.3V
POLY-TANT 2
20%
10V 2
X5R
10
5%
1/16W
SIS426DN
PWRPK-12128
D (P5VS5_VO1)
P5VS3_VFB 2 VFB1 VFB2 5

(P3V3S5_V02)
P3V3S5_VFB
S2
5%
1/16W
MF-LF
402 2
20%
2 6.3V
TANT
C
C7290 1
5
CASE-D3L-SM1 805 MF-LF CASE-B2-SM
402 2 P3V3S5_RC 10UF
1 C7251 P5VS3_RC 4
P5VS3_ENTRIP 1 ENTRIP1 ENTRIP2 6 P3V3S5_ENTRIP
NO STUFF 20% 1 C7291
0.001UF NO STUFF G 2 6.3V 2
10% VCLK 18 C7262 1 X5R 0.001UF
2 50V
CERM C7222 1 S NC
100PF XW7261
SM
603 10%
50V
2 CERM
402 100PF PGOOD 23 5%
XW7220
2 5%
50V
3 2 1 1
R7200 50V
CERM 2 1 2 402
CERM 2
88.7K EN0 13 NO STUFF 402 PLACE_NEAR=C7292.1:1mm
XW7260
SM XW7221
2
402 1%
5V3V3_REG_EN 1 C7208 1 SM
1/16W
MF-LF
GND THRM_PAD
220PF
R7206
15
25
1 2 402 5% 88.7K 1
SM 1%
2 25V
PLACE_NEAR=L7260.1:1mm
PLACE_NEAR=L7220.1:1mm CERM 1/16W
PLACE_NEAR=C7252.1:1mm
1 402 MF-LF P3V3_S5_V02_XW
P5V_S3_REG_XW P5V_S3_V01_XW 2 402 P3V3_S5_REG_XW
1
1
R7220 XW7200 R7260
SM 6.49K
15.0K 1%
1% GND_P5VP3V3_SGND 1 2 1/16W
1/16W MIN_LINE_WIDTH=0.6 mm MF-LF
MF-LF MIN_NECK_WIDTH=0.2 mm 2 402
2 402 VOLTAGE=0V PLACE_NEAR=U7201.25:1mm
1
1
R7221 R7261
One master PGOOD for both 5V and 3V3 10K
10K P5V3V3_PGOOD 1%
1% 73 OUT 1/16W
1/16W MF-LF
MF-LF 2 402
2 402
Q7210 D 6
SSM6N15FEAPE
SOT563
B 48 47 46 45 43 23 21 17 7 6
PP3V42_G3H B
73 66 65 64 53 49 2 G S 1
1 Q7211 D 3
R7210 SSM6N15FEAPE
10K SOT563
5%
1/16W
MF-LF
2 402
5 G S 4
P5VS3_EN_L
Q7210 D 3
46 45 43 23 21 17 7 6
PP3V42_G3H
SSM6N15FEAPE 73 66 65 64 53 49 48 47
SOT563
1
R7211
10K
5%
5 G S 4 1/16W
MF-LF
73 P5VS3_EN 2 402
P3V3S5_EN_L
Q7211 D 6
SSM6N15FEAPE
SOT563
2 G S 1
73
P3V3S5_EN
PAGE TITLE
5V / 3.3V Power Supply

DRAWING NUMBER SIZE

REVISION
R
.
<E4LABEL>
<BRANCH>
72 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
72 67 31 30 28 7 6 PP1V5_S3
89 86 82
PPBUS_G3H
1 C7355 49 40 7 6
70 69 66 65
10UF
20% CRITICAL CRITICAL
2 6.3V
X5R
603 C7330 1 C7331 1 1 C7332 1 C7333
68UF 68UF 1UF 0.001UF
20% 20% 10% 10%
72 66 61 58 56 54 46 44 43 42 33 31 7 6 PP5V_S3 R7305 16V
POLY-TANT 2
16V
POLY-TANT 2 2 25V
X5R 2 50V
X7R
101 82
1
4.7 2 PP5V_S3_DDRREG_V5FILT CASE-D2E-SM CASE-D2E-SM 603-1 402
1/16W VOLTAGE=5V
MF-LF 5
402
ISNS_1V5_S3_P OUT 50 99
D CRITICAL
C7300 1 C7305 1
4 G
Q7330 ISNS_1V5_S3_N
(DDRREG_DRVH) CSD58856Q5A
15
14
23
10UF 1UF MIN_LINE_WIDTH=0.6 mm
OUT 50 99
20% 10% MIN_NECK_WIDTH=0.17 mm MLP5X6-LFPAK-Q5A
10V 2 10V 2
X5R X5R V5IN V5FILT VLDOIN
603 402-1 R73101 S
5.23K
C 6 COMP
CRITICAL
VDDQSNS 8 1%
1/16W
MF-LF 1 2 3
CRITICAL
L7330 VOLTAGE=1.5V
C
31 8 IN MEMVTT_EN 10 S3 VTT Enable
MODE 4 402 2
R7325 C7325 1.0UH-21A
DDRREG_EN 0.1UF PPDDR_S3_REG_R 4 3 PP1V5_S3
73 IN 11 S5 VDDQ/VTTREF Enable 0 1 2
VBST 22 DDRREG_VBST 1 2 DDRREG_VBST_R 1 2 6 7 28 30 31 67 72
73 OUT DDRREG_PGOOD 13 PGOOD VDDQ PGOOD U7300 MIN_LINE_WIDTH=0.6 mm MIN_LINE_WIDTH=0.6 mm FDU1040D-SM 2 0612 1
1/16W
MIN_NECK_WIDTH=0.17 mm 10% CRITICAL MF-1 Vout = 1.5V
32 7 6 PPVTTDDR_S3 TPS51116 DRVH 21 DDRREG_DRVH MF-LF 50V 1
C7340 1W
1% 13A max output
10mA max load QFN GATE_NODE=TRUE 402 X7R 5
5 VTTREF DIDT=TRUE 603-1 270UF 0.001 (Q7335 limit)
31 30 28 7 6 PP0V75_S0_DDRVTT SYM (2 OF 2) 20%
Vout = VDDQSNS/2 LL 20 DDRREG_LL (DDRREG_LL) CRITICAL 2 2V f = 400 kHz
24 VTT SWITCH_NODE=TRUE MIN_LINE_WIDTH=0.6 mm D TANT
CASE-B4-SM
R7350
Vout = VTTREF
DIDT=TRUE MIN_NECK_WIDTH=0.17 mm Q7335 CRITICAL
XW7360
SM
DRVL 19 DDRREG_DRVL (DDRREG_DRVL) 4 G CSD58857Q5 CRITICAL
1 2 DDRREG_VTTSNS 2 VTTSNS
MLP5X6-LFPAK-Q5
C7341 1 1 C7345 1 C7346 2
DDRREG_CS 270UF 10UF
PLACE_NEAR=C3101.1:1mm
CS 16
S 20% 20% 0.001UF XW7301
CRITICAL CRITICAL NC 7 NC0 2V 2
TANT
2 6.3V
X5R
10%
50V
SM
2 X7R
C7360 1 1 C7361 NC 12 NC1 VDDQSET 9 32 DDRREG_FB
1 2 3
CASE-B4-SM 603
402 1
22UF 22UF
20% 20% VTTGND THRM_PAD GND PGND CS_GND DDRREG_FB_XW
6.3V 2 6.3V
X5R-CERM 2 X5R-CERM 1 XW7335
25
18
17
603 603 PLACEMENT_NOTE=Place next to Q7335
SM
PLACE_NEAR=C3101.1:1mm PLACE_NEAR=C3101.1:3mm PLACE_NEAR=L7330.2:1mm
DDRREG_CSGND (DDRREG_CSGND) 1 2
1
MIN_NECK_WIDTH=0.17 mm R7320
15.0K
C7360, C7361 close to memory 1%
1/16W
(DDRREG_VDDQSNS) MF-LF
MIN_LINE_WIDTH=0.2 mm 2 402
C7350 1 2
(DDRREG_FB)
<Ra>
0.033UF XW7300
10%
16V 2
SM Vout = 0.75V * (1 + Ra / Rb) 1
X5R
402 1 R7321
15.0K
1%
B 1/16W
MF-LF
2 402
B
GND_DDRREG_SGND <Rb>
VOLTAGE=0V
PAGE TITLE
1.5V DDR3 Supply

DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
73 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PLACE_NEAR=Q7410.1:8mm
PLACE_NEAR=Q7410.1:8mm PLACE_NEAR=Q7410.1:8mm PLACE_NEAR=Q7420.1:8mm
49 7 PPBUS_CPU_IMVP_ISNS PLACE_NEAR=Q7410.1:8mm PLACE_NEAR=Q7410.1:8mm PLACE_NEAR=Q7420.1:8mm
CRITICAL CRITICAL CRITICAL CRITICAL
C7405 1 C7410 1 C7413 1 C7415 1 1 C7411 1 C7412 1 C7421 1 C7422
68UF 68UF 68UF 68UF 10UF 0.001UF 10UF 0.001UF
20% 20% 20% 20% 10% 10% 10% 10%
16V 2
POLY-TANT
16V 2
POLY-TANT
16V 2
POLY-TANT
16V 2
POLY-TANT
25V
2 X5R 2 50V
X7R
25V
2 X5R 2 50V
X7R
CASE-D2E-SM CASE-D2E-SM CASE-D2E-SM CASE-D2E-SM 805 402 805 402
CRITICAL
L7415
0.36UH-20%-40A-0.00075OHM
D 99 88 87 85 84 83
51 50 48 47 46 42 40
21 20 19 18 17 7 6 PP3V3_S0 5
1
PIMA104E-SM
2
D
37 34 30 28 27 26 25 24 23
80 73 72 69 63 62 58 54 52
2 2
D CRITICAL
54 52 47 42 23 7 6
88 86 72 70 69
PP5V_S0 Q7410 XW7416 XW7417
4 G SM SM
RJK0365DPA-02
WPAK 1 PLACE_NEAR=L7415.1:4mm 1PLACE_NEAR=L7415.2:4mm
S CPUIMVP_PHASE1X CPUIMVP_ISEN1N_R
PP5V_S0_CPUIMVP_V5FILT MIN_LINE_WIDTH=0.25 MM MIN_LINE_WIDTH=0.25 MM
MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.15 MM MIN_NECK_WIDTH=0.15 MM
VOLTAGE=5V 1 2 3
C7401 1
1 C7400 1
R7416
4.7UF (CPUIMVP_PHASE1) 22.1K
2.2UF 10%
10V 1%
20% 2 X5R 1/16W
10V
X5R-CERM 2 805 5 MF-LF
402 2 402 R7417
D
294K 2
CRITICAL 1
Q7415 R7418 1%
1/16W
4 G RJK0208DPA 0402 MF-LF
WPAK 402
R7419
2 1 CPUIMVP_ISEN1_NTC 141.2K2
38
26
S
1%
C7403 V5FILT V5IN
1 2 3
1/16W
MF-LF
33PF U7400 150KOHM-5% 402
1 2
TPS51621 C7420
27.0NF
5% 36 TONSEL QFN 22 CPUIMVP_BOOT1 R7414 2 0
CPUIMVP_BOOT1_RC C7414 1 2 1UF
CPUIMVP_ISEN1P_R 1 2 48A max current
R7403 50V
CERM
VBST1
21 5% 1/16W
1
MF-LF 402
10% 25V X5R 603-2 MIN_LINE_WIDTH=0.25 MM PPVCORE_S0_CPU
3.92K2 39 DRVH1 CPUIMVP_UGATE1 MIN_NECK_WIDTH=0.15 MM 6 7 12 15 49
1 402 CPUIMVP_DROOP DROOP 23 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM GATE_NODE=TRUE DIDT=TRUE 10%
1% 8
353S2942 LL1
24
CPUIMVP_PHASE1
MIN_LINE_WIDTH=1.5 MM MIN_NECK_WIDTH=0.2 MM SWITCH_NODE=TRUE DIDT=TRUE
5 R74211 10V
X5R R74221
1/16W 91 12 IN CPU_VCCSENSE_P VSNS DRVL1 CPUIMVP_LGATE1 0 402 0
C MF-LF
402 91 68 12 IN CPU_VCCSENSE_N 7 GNDSNS
VBST2 29 CPUIMVP_BOOT2
R7424 2
5% 1/16W
0
1
CPUIMVP_BOOT2_RC
MF-LF 402
GATE_NODE=TRUE
C7424 1 2
DIDT=TRUE
1UF D CRITICAL
Q7420
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
C
CPUIMVP_VREF 40 30 CPUIMVP_UGATE2 10% 25V X5R 603-2 4 G
VREF DRVH2 RJK0365DPA-02
28 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM GATE_NODE=TRUE DIDT=TRUE
20 CRITICAL LL2 CPUIMVP_PHASE2 WPAK CPUIMVP_ISEN1P 68 68 CPUIMVP_ISEN1N
8 IN CPUIMVP_VID<0> VID0 27 MIN_LINE_WIDTH=1.5 MM MIN_NECK_WIDTH=0.2 MM SWITCH_NODE=TRUE DIDT=TRUE MIN_LINE_WIDTH=0.25 MM MIN_LINE_WIDTH=0.25 MM
19 DRVL2 CPUIMVP_LGATE2 MIN_NECK_WIDTH=0.15 MM MIN_NECK_WIDTH=0.15 MM
8 IN CPUIMVP_VID<1> VID1 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM GATE_NODE=TRUE DIDT=TRUE S
CPUIMVP_VID<2> 18 VID2 33 CPUIMVP_PGOOD
8 IN PGOOD OUT 27
CPUIMVP_VID<3> 17 34 CPUIMVP_CLK_EN_L CRITICAL

VID3 CLK_EN* 1 2 3
1 C7402
8 IN
CPUIMVP_VID<4> 16 VID4 VR_ON 35 CPUIMVP_VR_ON
OUT 26
L7425
8 IN IN 45 0.36UH-20%-40A-0.00075OHM
0.22UF 8 IN CPUIMVP_VID<5> 15 VID5 DPRSLPVR 12 PM_DPRSLPVR IN 12 15 91
10% (CPUIMVP_PHASE2) 1 2
CPUIMVP_VID<6> 14 13 CPU_PSI_L
2 10V
CERM 8 IN VID6 PSI* IN 12 15 91
PIMA104E-SM
402
MODE 1 2
CPUIMVP_SLEW 37 SLEW 2
6 THERM 9 CPUIMVP_NTC 5 XW7426
SM XW7427
68 CPUIMVP_ISEN1P CSP1 R7440 0
5 VR_TT* 10 CPUIMVP_VR_TT_L 2 1 CPU_PROCHOT_L OUT 10 46 91
SM
68 CPUIMVP_ISEN1N CSN1 5% 1/16W MF-LF 402 1
R74001 IMON 11 CPUIMVP_IMON OUT 12 50 91 D CRITICAL PLACE_NEAR=L7425.1:4mm 1 PLACE_NEAR=L7425.2:4mm
249K 68 CPUIMVP_ISEN2P 3 CSP2 TRIPSEL 31 1
Q7425 CPUIMVP_PHASE2X CPUIMVP_ISEN2N_R
1%
1/16W 68 CPUIMVP_ISEN2N 4 CSN2 OSRSEL 32 R7450 1 C7450 4 G RJK0208DPA MIN_LINE_WIDTH=0.25 MM MIN_LINE_WIDTH=0.25 MM
MF-LF 16.9K 0.0033UF
WPAK MIN_NECK_WIDTH=0.15 MM MIN_NECK_WIDTH=0.15 MM
402 2 1% 10%
1/16W 50V 1
OMIT OMIT OMIT OMIT
THRM
GND PGND PAD
MF-LF
2 402
2 CERM
402
S R7426
22.1K
C7440 1 C7441 1 1 C7442 1 C7443 91 68 12 CPU_VCCSENSE_N 1%
2
25
41
NOSTUFF NOSTUFF NOSTUFF NOSTUFF 1 2 3 1/16W

NONE NONE NONE NONE MF-LF
NONE 2 NONE 2 NONE NONE IMON output range: 1.1V 2 402 R7427
NONE NONE 2 NONE 2 NONE
402 402 402 402 1
294K 2
R74451 1%
1/16W
R7428
100K MF-LF 0402
XW7400 5%
1/16W R7429 402
SM MF-LF 41.2K2
B 2 1
402 2 1
1%
CPUIMVP_ISEN2_NTC 2 1
B
1/16W
MF-LF
402
C7430 150KOHM-5%
27.0NF
CPUIMVP_AGND CPUIMVP_ISEN2P_R 1 2
MIN_LINE_WIDTH=0.6 mm MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.15 mm MIN_NECK_WIDTH=0.15 MM 10%
VOLTAGE=0V 1 10V
R7430 X5R
402
R74311
0 0
5% 5%
1/16W 1/16W
MF-LF MF-LF
402 2 402 2
Loadline = DCR * K * 5.95 / (R7403 * 2uA/mV) CPUIMVP_ISEN2P 68 68 CPUIMVP_ISEN2N
Loadline = 1.83 mohm MIN_LINE_WIDTH=0.25 MM
VIMON = Io * DCR * 2uA/mV * R7450

50 A = 1.00 V
K = (R7417 || (R7418 + R7419)) / (R7417 || (R7418 + R7419) + R7416) = 0.66
PAGE TITLE
CPU IMVP VCore Regulator

DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
74 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
GFX IMVP VCORE
86 82 70 67 66 65 49 40 7 6 PPBUS_G3H
89
70 69 68 54 52 47 42 23 7 6PP5V_S0
88 86 72
NO STUFF
R7514 1 D7514
CRITICAL CRITICAL
5%
0
BAT30CWFILM C7520 1 C7521 1 1 C7523 1 C7524
99
C7510 1 C7513 1 1/16W SOT-323 68UF 68UF 1UF 1000PF
68 63 62 58 54 52 51 50 48
PP3V3_S0 GFXIMVP_DROOP MF-LF 20% 20% 10% 5%
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26 2.2UF 2.2UF 402 1 16V 2 16V 2 2 25V
X5R 2 25V
88 87 85 84 83 80 73 72 69 10% 10% 2 POLY-TANT POLY-TANT NP0-C0G
16V 2 16V 2 CASE-D2E-SM CASE-D2E-SM 603-1 402
X5R X5R GFXIMVP_VBST_R 3 5
603 603
21
1
R7512 CRITICAL
C 1K
1%
1/16W
C7511 1
1
R7511
1.69K
V5IN
C7514
1UF
1
2
GFXIMVP_UGATE
D
Q7530
C
33PF 10% 4 G
MF-LF
402 2 5%
50V
1%
1/16W U7500 16V 2
X5R MIN_LINE_WIDTH=0.6 mm CSD58856Q5A
MLP5X6-LFPAK-Q5A
CERM 2 MF-LF MIN_NECK_WIDTH=0.2 mm
402 2 402
TPS51981 402 GATE_NODE=TRUE
QFN DIDT=TRUE CRITICAL
S
31 DROOP V5FILT 30 GFXIMVP_V5FILT 88 99
CRITICAL R7540 Vout = VID controlled
GFXIMVP_TONSEL 27 TONSEL CRITICAL PP3V3_S0 50 51 52 54 58 62 63 68 69 72 0.001 22A max output
VBST 18 GFXIMVP_VBST 6 7 17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
73 80 83 84 85 87
1 2 3 L7530 1%
1W f = 350KHz
91 13 GFX_VSENSE_P 5 VSNS 353S2664 DRVH 17 0.68UH-27A-1.7MOHM MF-1
IN 0612
91 13 GFX_VSENSE_N 4 GNDSNS LL 19 GFXIMVP_PHASE 1 2 PPVCORE_S0_GFX_REG_R 2 1 PPVCORE_S0_GFX 6 7 13 24 49
IN
20 MIN_LINE_WIDTH=0.6 mm FDU1040D-SM
MIN_LINE_WIDTH=0.6 mm 4 3
32 DRVL MIN_NECK_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm
69 GFXIMVP_VREF VREF SWITCH_NODE=TRUE VOLTAGE=1.05V
23 DIDT=TRUE
16 PGOOD GFXIMVP_PGOOD OUT 73
8 IN GFXIMVP_VID<0> VID0 24 1
8 IN GFXIMVP_VID<1> 15 VID1
CLK_EN*
25
NC R7517
14 VR_ON GFX_VR_EN IN 13 91 200K 5
GFXIMVP_VID<2> VID2 1%
C7512 1 1
R7513
8 IN
GFXIMVP_VID<3> 13 VID3
DPRSLPVR 9 GFX_DPRSLPVR IN 13 91 1/16W
MF-LF CRITICAL 1 C7556 1 C7557
0.22UF 46.4K
8 IN
MODE 22
PP5V_S0 23 42 47 52 54 68 69 70 72 86 D
10% GFXIMVP_VID<4> 12 6
2 402 10UF 1000PF
10V
CERM 2
1%
1/10W
8 IN
GFXIMVP_VID<5> 11
VID4
28 GFXIMVP_IMONC
7
88
GFXIMVP_LGATE 4 G
Q7535 20%
6.3V
5%
25V
402 MF-LF 8 IN VID5 IMONC CSD58857Q5 2 X5R 2 NP0-C0G
2 603 10 26 MIN_LINE_WIDTH=0.6MM 603
8 IN GFXIMVP_VID<6> VID6 TRIPSEL GFXIMVP_VREF_R MIN_NECK_WIDTH=0.2MM MLP5X6-LFPAK-Q5 402
8 GATE_NODE=TRUE
29 IMON GFXIMVP_IMON OUT 13 91 DIDT=TRUE
GFXIMVP_ISLEW ISLEW 7 S
VR_TT* NC
2 CSP THERM 6 GFXIMVP_THERM
3 1 2 3
99 GFXIMVP_CS_N CSN
PGND
SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY NO STUFF

GND
R7516 1 1
R7515 1
R7518 1
R7509 1
R7510
150K
1%
C7515 1
22.6K 100K
1 C7517 0 0
GFXIMVP_CS_P 0.0033UF 0.022UF
1
33
99 1/16W 10% 1% 1% 10% 5% 5%

MF-LF 1/16W 1/16W 1/16W 1/16W
XW7500
SM
402 2
50V
CERM 2 MF-LF MF-LF 2 16V
CERM-X5R MF-LF MF-LF
402 2 402 2 402 402 402
B PLACE_NEAR=U7500.33:1mm 2 1
402 2 2
B
GND_GFXIMVP_AGND GFXIMVP_VREF
VOLTAGE=0V (GND_GFXIMVP_AGND) 69
MIN_LINE_WIDTH=0.6 mm (GFX_VSENSE_N)
MIN_NECK_WIDTH=0.2 mm R7542
1
0 2 GFXIMVP_CS_R_N
99 50
5%
1/16W
MF-LF
402
R7541
0
1 2 99 50 GFXIMVP_CS_R_P
PLACE_NEAR=U7500.2:2mm OMIT 5%
1/16W
C7549 1 OMIT C7542 1 MF-LF
402
C7541 1 NOSTUFF
10PF NONE
5% NOSTUFF NONE 2
50V NONE NONE
CERM 2 NONE 2 402
402 NONE
(GND_GFXIMVP_AGND)
Imon= Io xR7540 x2uA/mV x R7515
Imon= Io x45.2mV/A
A 22A => 1V SYNC_MASTER=K18_POWER SYNC_DATE=07/08/2009 A
PAGE TITLE
GFX IMVP VCore Regulator

DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
75 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU VTT (1.05V S0) Regulator

D 86 82 69 67 66 65 49 40 7 6PPBUS_G3H
D
72 69 68 54 52 47 42 23 7 6PP5V_S0 89
88 86
CRITICAL CRITICAL CRITICAL

R76011 1 C7601 C7620 1 C7621 1 C7623 1 1 C7622
2.2 10UF 68UF 68UF 68UF 0.001UF
5% 20% 20% 20% 20% 10%
1/10W 2 10V
X5R 16V 2
POLY-TANT
16V 2
POLY-TANT
16V 2
POLY-TANT
2 50V
X7R
MF-LF 603 402
603 2 CPUVTTS0_BOOT_RC CASE-D2E-SM CASE-D2E-SM CASE-D2E-SM
PP5V_S0_CPUVTTS0_VCC MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
R7630
13
14
1
VCC PVCC
0 1 C7630
5%
1/16W
1UF
10%
U7600 MF-LF
402 2 16V
X5R
2
402 5
ISL95870
3 UTQFN CPUVTTS0_VBST
73 IN CPUVTTS0_EN EN BOOT 12 MIN_LINE_WIDTH=0.3 mm D CRITICAL
CPUVTTS0_FB 6
MIN_NECK_WIDTH=0.2 mm Q7630
FB UGATE 11 CPUVTTS0_DRVH 4 G CSD58856Q5A
MIN_LINE_WIDTH=0.6 mm MLP5X6-LFPAK-Q5A
CPUVTTS0_SREF 4 MIN_NECK_WIDTH=0.2 mm
SREF PHASE 10 GATE_NODE=TRUE
DIDT=TRUE CRITICAL
CPUVTTS0_VO S 152S1085
91 10 OUT CPUVTTS0_PGOOD 8 VO LGATE 15
CRITICAL
R7640
CPUVTTS0_OCSET 0.001
7 OCSET CRITICAL 1 2 3 L7630 1%
91 12 IN CPU_VTTSENSE_P 0.68UH-27A-1.7MOHM 1W
MF-1
9 0612
R7604 PGOOD
CPUVTTS0_LL 1 2 PPCPUVTT_S0_REG_R 2 1 PP1V05_S0 6 7 10 12 13 15 17 18 20 21 23
3.01K2
C 91 12 IN CPU_VTTSENSE_N 1
1%
CPUVTTS0_RTN 2 RTN
SWITCH_NODE=TRUE 5
FDU1040D-SM
VOLTAGE=1.05V
4 3
Vout = 1.05V
24 25 26 40 73 86
C
1/16W CPUVTTS0_FSEL 5 FSEL
DIDT=TRUE
MF-LF
402 GND PGND D
27A max output
CRITICAL CPUVTTS0_CS_P CPUVTTS0_CS_N
Q7635 99 50 99 50
f = 300 kHz
16
CPUVTTS0_DRVL 4 G CSD58857Q5
MIN_NECK_WIDTH=0.2 mm MLP5X6-LFPAK-Q5
1 C7647
GATE_NODE=TRUE 10UF
DIDT=TRUE 20%
1 1 S 6.3V
2 X5R
R7605 R7603 603
C7602 1 2.74K
1% 5%
0
R7641 1
2.2UF 1/16W 1/16W 1 2 3
10% MF-LF MF-LF
3.48K
16V 1%
X5R 2 402 2 2 402 1/16W
603 MF-LF
402 2
1 C7603 C7640
C7604 1 1 C7605 0.047UF
1000PF
0.001UF 0.001UF 10% 2 1
10% 10%
50V 2 2 50V 2 10V
CERM
X7R X7R 402 5%
402 402 25V
NP0-C0G
402
XW7600
SM
CPUVTTS0_AGND 1 2
1
R7642
MIN_LINE_WIDTH=0.6 mm 3.48K
VOLTAGE=0V 1/16W
MF-LF
2 402
SIGNAL_MODEL=EMPTY (CPUVTTS0_OCSET)
NO STUFF
C7641 1
B 0.0022UF
10%
50V
(CPUVTTS0_VO)
B
CERM 2
402
2
CPUVTTS0_FB_RC R7644
3.01K
1%
SIGNAL_MODEL=EMPTY 1/16W
MF-LF
NO STUFF 1 402
R76432 <Ra>
100
1%
1/16W
MF-LF
402 1
Vout = 0.5V * (1 + Ra / Rb)
(CPUVTTS0_FB)
<Rb>
1
R7645
2.74K
1%
1/16W
MF-LF
2 402
(CPUVTTS0_AGND)
PAGE TITLE
CPUVTT (1.05V) Power Supply

DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
76 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
1.2V S3 Regulator
D D
31 27 23 21 20 19 18 17 7 6
99 85 83 73 72 71 66 57 35
PP3V3_S5
1
C7760
22UF
20%
1.05V S5 LDO
6.3V
2 CERM
805
152S0771 Ibex Peak-M requires JTAG pull-ups to be powered at 1.05V in S5.

CRITICAL CRITICAL Pull-ups (3) must be 51 ohms to support XDP (not required in production).
L7760
U7760 2.2UH-1.2A 70mA is required to support pull-ups. Alternative is strong voltage
SC194A PCAA031B-SM dividers (200/100) to 3.3V S5, which burns 100mW in all S-states.
MLP10
1 VIN LX 10 P1V2ENET_SW 1 2 PP1V2_ENET 6 7 37 72 CRITICAL
MIN_LINE_WIDTH=0.4 mm SWITCH_NODE=TRUE
4 EN 353S2719 MIN_NECK_WIDTH=0.2 mm DIDT=TRUE XDP_PCH
73 8 IN PM_ENET_EN VOUT 5 Vout = 1.2V
3 SYNC/PWM MAX CURRENT = 0.7A U7740
XW7761 C7761
FREQ = 1MHZ PP3V3_S5
TPS720105
6 VID0 1
31 27 23 21 20 19 18 17 7 6
99 85 83 73 72 71 66 57 35
SON PP1V05_S5
SM 6 7 17
4 BIAS
P1V2ENET_FB 1 2 22UF
7 VID1 PLACE_NEAR=L7760.2:1MM
2
20%
6.3V 6 IN OUT 1
Vout = 1.05V
CERM
2 MODE 805
3 EN NC 2
Max Current = 0.35A
THRM NC
GND PGND PAD XDP_PCH THRM
XDP_PCH
C7740 1 C7741
8
11
GND PAD 1
1UF 5 7 2.2UF
10% 10%
6.3V 2 2 6.3V
C CERM
402
X5R
402 C
1.8V S0 Regulator
31 27 23 21 20 19 18 17 7 6
99 85 83 73 72 71 66 57 35
PP3V3_S5
CRITICAL
C7724 1 C7720 1
1
VIN 2
1000PF 22UF 152S1088

VDD
5% 20%
25V 6.3V
NP0-C0G 2 CERM 2 L7720
402 805
1.0UH-6.5A
U7720 IHLP2020CZ
ISL8014 PP1V8_S0 6 7 12 16 21 23 24 58 72 87
P1V8S0_EN 5 EN QFN P1V8S0_SW 1 2

LX 14
73 IN
CRITICAL LX 15
SWITCH_NODE=TRUE
DIDT=TRUE CRITICAL Vout = 1.794V
B 73 P1V8S0_PGOOD 7 PG
XW7700
SM
CRITICAL
Max Current = 2.7A B
OUT
VFB 8 P1V8S0_FB P1V8S0_FB_XW 1 2
1 C7723 1 C7721
47PF 22UF Freq = ???
P1V8S0_SYNCH 4 SYNCH 5% 20%
THRM_PAD
PLACE_NEAR=L7720.2:1MM 50V 6.3V

16 2 CERM 2 CERM
NC
NC
6
NC
R77201 402 805
113K
12 PGND
10 SGND
13 1%
NC 1/16W
MF-LF
402 2
9
11
17
<Ra>
1 CRITICAL
R7722 R77211
10K
5% 90.9K C7722 1
1/16W 1% 22UF
MF-LF 1/16W 20%
6.3V
2 402 MF-LF CERM 2
402 2 805
<Rb>
Vout = 0.8V * (1 + Ra / Rb)
PAGE TITLE
Misc Power Supplies

DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
77 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
3.3V S3 FET CRITICAL

Q7810 Q7830
SIA417DJ
SIA417DJ SC70-6L 50 51 52 54 58 62 63 68 69 73
SC70-6L PP3V3_S0 6 7 17 18 19 20 21 23 24 25 26
7
31 27 23 21 20 19 18 17 7 6 PP3V3_S5 27 28 30 34 37 40 42 46 47 48
7
PP3V3_S5 99 85 83 73 72 71 66 57 35 80 83 84 85 87 88 99
S
31 27 23 21 20 19 18 17 7 6
D
4
1
99 85 83 73 72 71 66 57 35
D
4
1
PP3V3_S3 6 7 8 17 20 31 32 33 34 35 36 48 50 53 54
55 73 87 101 3.3V S0 FET
R7832
1
C7831 1
1
C7811 1
D
G
R7812
D 0.033UF MOSFET SiA417
G
100K
Q7812 D 6 10K 0.033UF
10%
3.3V S3 FET Q7812 D 3 5%
10%
16V
3
5% 16V 1/16W X5R 2
SSM6N15FEAPE SSM6N15FEAPE CHANNEL P-TYPE 8V/5V
3
1/16W X5R 2 MF-LF 402
SOT563 SOT563
MF-LF 402
MOSFET SiA417
402
2 C7830
402
2 C7810 R7830 0.01UF RDS(ON) 23 mOhm @4.5V
R7810 0.01UF 47K
47K CHANNEL P-TYPE 8V/5V P3V3S0_EN_L 1 2 P3V3S0_SS 1 2
2 G S 1 P3V3S3_EN_L 1 2 P3V3S3_SS 1 2
PM_SLP_S3_L_R
5 G S 4 5%
LOADING 2.3 A (EDP)
73 46 73 72 49 IN
31 18
45 43
IN PM_SLP_S4_L 5%
1/16W 10%
RDS(ON) 23 mOhm @4.5V 1/16W
MF-LF
10%
16V
MF-LF 16V 402 CERM
402 CERM
402
LOADING 1.568 A (EDP) 402
1.5V S3/S0 FET

67 31 30 28 7 6 PP1V5_S3
72 66 23 7 6 PP5V_S5
C7801 1
0.1UF
20%
10V
CERM
402
2 1
VCC
5 APN 376S0651
3.3V S0 GPU FET CRITICAL
U7801 Q7870
SLG5AP020 CRITICAL
SIA417DJ
D SC70-6L
P1V5CPU_EN 2 TDFN
31 IN ON D 5 R7801 Q7801 PP3V3_S0GPU 6 7 74 79 80 81 82 84
4 7
CRITICAL 31 27 23 21 20 19 18 17 7 6 PP3V3_S5
0 SI7108DN 99 85 83 73 72 71 66 57 35
D
4
1
3 SHDN* G 7 1 2 G
NO STUFF 6
P1V5S0FET_GATE 5% P1V5S0FET_GATE_R
PWRPK-1212-8-HF
3.3V S0 GPU FET
S 1/16W S
C7802 1 MF-LF
R7872 1 C7871 1
MOSFET SiA417
C
G
402
C 4.7UF
10%
6.3V THRM
PG 8
NC
1 2 3 PP1V5_S3RS0 6 7 13 16 31 42 73 99 51K
5%
1UF
10%
10V CHANNEL P-TYPE 8V/5V
3
X5R-CERM 2 GND PAD
1/16W
MF-LF
X5R 2
603 402
RDS(ON) 23 mOhm @4.5V
4
402
2 C7870
R7870 0.01UF
P3V3GPU_EN_L
1K
P3V3GPU_SS 1 2
LOADING 0.8 A (EDP)
1.5V S3/S0 FET 1 2
Q7872 5%
1/16W 10%
16V
SSM3K15FV D 3 MF-LF
MOSFET SI7108DN SOD-VESM-HF
402 CERM
402
CHANNEL N-TYPE
RDS(ON) 6 mOhm @4.5V EG_RAIL2_EN
87 73 IN
1 G S 2
LOADING 3.2 A (EDP)
1.2V S0 FET 1.2V S0 FET

MOSFET SI2306BDS-GE3
71 37 7 6 PP1V2_ENET CHANNEL N-TYPE
72 66 23 7 6 PP5V_S5
RDS(ON) 65 mOhm @4.5V
Q7860
1 TPCP8102
C7850 LOADING 0.124 A (EDP) PP5V_S0 6 7 23 42 47 52 54 68 69 70 72
0.1UF 23V1K-SM 86 88
1
20%
7 8
10V
2 3
2 VCC
CERM
67 66 61 58 56 54 46 44 43 42 33 31 7 6 PP5V_S3
402
5.0V S0 FET
D
3 101 82
U7850 376S0748
5 6
1
SLG5AP020 CRITICAL R7862 1
B D C7861 B
G
1
TDFN MOSFET TPCP8102
73 P1V2S0_EN 2 ON D 5 R7850 47K
IN
Q7850 0.033UF
4
CRITICAL 5%
0 G 1/16W
10%
CHANNEL P-TYPE
3 SHDN* G 7 1 2 1 SI2306BDS-GE3 MF-LF
16V
X5R
2
6
P1V2S0_GATE 5% P1V2S0_GATE_R S SOT23 402
2
R7860
402 C7860 RDS(ON) 18 MOHM @4.5V
S 1/16W 0.01UF
MF-LF 47K
8
402
2
P5V0S0_EN_L 1 2 P5V0S0_SS 1 2
LOADING 3.5 A (EDP)
PG NC PP1V2_S0 6 7 87
5%
THRM 1/16W 10%
GND PAD MF-LF 16V
CERM
4
Q7865 402
402
SSM3K15FV D 3
SOD-VESM-HF
1 G S 2
73 72 49 IN PM_SLP_S3_L_R
1.8V S0 GPU_IFPX FET

87 71 58 24 23 21 16 12 7 6 PP1V8_S0
88
52 47 42 23 7 6 PP5V_S0
86 72 70 69 68 54
1.8V S0 GPU_IFPX FET
C7880 1
0.1UF MOSFET SI2312BDS
1
20%
10V
CERM 2 VCC CHANNEL N-TYPE
402 376S0683
U7880 3 RDS(ON) 31 mOhm @4.5V
SLG5AP020
A 87 86 73 IN EG_RAIL4_EN 2 ON TDFN
CRITICAL
D 5
D CRITICAL
Q7880
LOADING 0.3 A (EDP)
SYNC_MASTER=K18_POWER SYNC_DATE=06/10/2009 A
PAGE TITLE
3 7 P1V8GPUIFPXFET_GATE 1 G SI2312BDS
SHDN* G
6
S
SOT23 Power FETs
S DRAWING NUMBER SIZE
PG 8
2
PP1V8_GPUIFPX Apple Inc. <SCH_NUM> D
NC 6 7 81
REVISION
THRM R
GND PAD <E4LABEL>
4

<BRANCH>
78 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
State SMC_PM_G2_ENABLE PM_SLP_S4_L PM_SLP_S3_L
3.3V,5V S3 ENABLE
Run (S0) 1 1 1
(PM_S4_STATE_L)
Sleep (S3) 1 1 0 73 72 46 45 43 31 18 IN PM_SLP_S4_L PM_SLP_S4_L OUT 18 31 43 45 46 72 73
MAKE_BASE=TRUE
Soft-Off (S5) 1 0 0 2 2
R7911 R7912
0
Battery Off (G3Hot) 0 0 0 5.1K
5%
3.3V S5 ENABLE 1/16W
5%
1/16W
1 MF-LF 1 MF-LF
R7902 402 402
100 S5 rail PWRGD PLACE_NEAR=Q7210.2:3mm
66 45 IN SMC_PM_G2_EN 2 1 73 66 P3V3S5_EN P3V3S5_EN OUT 66 73
MAKE_BASE=TRUE PLACE_NEAR=U7300.11:3mm
D
5%
1/16W
MF-LF
NO STUFF
48 47 46 45 43 23 21 17 7 6
73 66 65 64 53 49
PP3V42_G3H 73 66 P5VS3_EN
MAKE_BASE=TRUE
P5VS3_EN OUT 66 73 D
R79581 402 1 C7902
100K 0.068UF C7940 1 73 67 DDRREG_EN
MAKE_BASE=TRUE
DDRREG_EN OUT 67 73
5%
10%
10V
0.1uF 1
R7940 NO STUFF
1/16W 2 20%
MF-LF
402
CERM
402
31 27 23 21 20 19 18 17 7 6
PP3V3_S5 10V
CERM 2 100K
5%
PLACE_NEAR=U7300.11:3mm 1 C7910 1 C7912
PLACE_NEAR=U4900.L13:3mm 2 PLACE_NEAR=Q7211.2:2mm 99 85 83 73 72 71 66 57 35 402 1/16W 0.47UF 0.47UF
CRITICAL MF-LF 10% 10% PLACE_NEAR=Q7210.2:3mm
6
6.3V 6.3V
2 402 2 CERM-X5R 2 CERM-X5R
VDD 402 402
5 SENSE
U7940 RESET* 1 RSMRST_PWRGD 45
TPS3808G33DBVRG4
S5_PGOOD_CT 4 CT SOT23-6 MR* 3
(IPU)
C7941 1 GND
0.001UF
2
20%
50V
CERM 2
402
99
Other S0 RAILS
68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6 PP3V3_S0
47 46 42 40 37 34 30 28 27 26
88 87 85 84 83 80 73 72 69
S0 ENABLE
(PM_SLP_S3_L)
R7978 R7992 1
PM_SLP_S3_L 100 73 72 49 PM_SLP_S3_L_R
85 73 45 31 18 6 IN
1 2 10K
MAKE_BASE=TRUE 5%
5% PM_SLP_S3_L_R OUT 49 72 73 1/16W
1/16W MF-LF
MF-LF 402 2
2
PM_SLP_S4_L
IN 18 31 43 45 46 72 73
402
R7979 1 2 R7981 R7985 2 R7986
PM_SLP_S3_L_R OUT 49 72 73
33K 20K PM_SLP_S3_L_R R7995

100K 5% 5.1K OUT 49 72 73
5% 5% 1/16W 0
1/16W 1/16W MF-LF 5% 73 S0PGOOD_PWROK 1 2
1
C MF-LF
402 2
MF-LF
402
1 402
1
1/16W
MF-LF
R7996
5%
1/16W
MF-LF
IG
EG
PM_ALL_GFX_PGOOD
HIGH
PM_ALL_GPU_PGOOD
C
VFRQ_SLPS4 VFRQ_SLPS3 PLACE_NEAR=U1800.P12:5mm 73 71 P1V8S0_EN P1V8S0_EN OUT 71 73 0 402
P1V8S0_PGOOD 1 2
2
R7933 R7932 MAKE_BASE=TRUE 71 IN

5%
0 0 73 66 1/16W R7997
5% 5%4921481747746
6 PP3V42_G3H MF-LF 0
1/16W 1/16W 45 43 23 73 72 P1V2S0_EN P1V2S0_EN OUT 72 73 66 IN P5V3V3_PGOOD 402 1 2
MF-LF MF-LF 65 64 53 MAKE_BASE=TRUE
1
402 402 NO STUFF 5%

73 70 CPUVTTS0_EN CPUVTTS0_EN 1/16W
OUT 70 73
R7998 MF-LF PP3V3_S5 85 99
2
R7931 MAKE_BASE=TRUE 6 7 17 18 19 20 21 23 27 31
0 402 35 57 66 71 72 73 83
DDRREG_PGOOD 1 2
10K CHGR VFRQ Generation PLACE_NEAR=U7720.5:6mm
67 IN
5% PLACE_NEAR=U7600.25:6mm PLACE_NEAR=U7850.2:6mm 5%
1/16W 1/16W R7988 PLACE_NEAR=U7980.1:2mm
MF-LF MF-LF 0
1
402 1 C7981 1 C7985 1 C7986 69 IN GFXIMVP_PGOOD 402 1 2

R7994 1
1 C7989
CHGR_VFRQ OUT 65
0.47UF 1UF 0.47UF 5% 0 0.1UF
10% 10% 10% 1/16W 5%
20%
Q7931 2 6.3V
CERM-X5R 2 6.3V
CERM 2 6.3V
CERM-X5R
MF-LF 1/16W 2
10V
CERM
402 MF-LF
SSM3K15FV D 3
NO STUFF 402 402 402
402
2 402
69 68 63 62 58 54 52 51 50 48
PP3V3_S0 NO STUFF
2
SOD-VESM-HF R7935 25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
99 88 87 85 84 83 80 73 72 S0_PWR_PGOOD
0
5%
1/16W
MF-LF
1
402 NO STUFF 5 TC7SZ08AFEAPE
2
1 G S 2 27MHZ OE EN Generation R7999 2
A
SOT665
10K R7991 4 ALL_SYS_PWRGD OUT
5% 0 1
U7980Y 25 27 45 87
1/16W 87 86 82 73 8 PM_ALL_GPU_PGOOD 1 2 ALL_GFX_PGOOD_R B

MF-LF
1
(Need to confirm if SMC can provide 1 pin for control)
402 5%
VFRQ_EN_GATE 1/16W 3
CK505_27MHZ_EN_L OUT 26 MF-LF
402
ENET Enable Generation 3.3V ENET FET EXT GPU PWRGD Pullup SSM3K15FV
Q7995
SOD-VESM-HF
D 3
"ENET" = "S0" || ("S3" && "AC" && "WOL_EN") CRITICAL

Q7922
B NOTE: S3 term is guaranteed by source of R7920 & Q7920, MUST BE S3 RAIL. NTR4101P
SOT-23-HF
69 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
99 88 87 85 84 83 80 73 72
PP3V3_S0
B
36 35 34 33 32 31 20 17 8 7 6 PP3V3_S3 PP3V3_ENET 6 7 27 37
R7990 1 1 G S 2
101 87 72 55 54 53 50 48
2 S D 3 100K
5% 3.3V 1.05V AND 1.5V S0 RAILS MONITOR CIRCUIT
1/16W
MF-LF
402 2
R7920 1
R7921 1 1 C7921 G
10K 10K 0.033UF 69 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
PP3V3_S0
5% 5% 10% 1 PM_ALL_GPU_PGOOD 47 46 42 40 37 34 30 28 27 26
1/16W 1/16W 16V
2 X5R
87 86 82 73 8 IN 99 88 87 85 84 83 80 73 72
PM_ALL_GPU_PGOOD RAIL_MON C7971 1 PLACE_NEAR=U7971.7:2mm
MF-LF MF-LF C7922
7
402 87 86 82 73 8 IN
402 2 402 2 R7922 0.01UF 87 86 82 73 8 IN PM_ALL_GPU_PGOOD VDD VDDA 0.1uF
100K 2 20%
71 8 PM_ENET_EN 1 P3V3ENET_SS 2 1 PM_ALL_GPU_PGOOD 8 73 82 86 87
10V
2
OUT
5% 10%
MAKE_BASE=TRUE
OUT
U7971 CERM
402
1/16W ISL88042IRTJJZ
3 MF-LF 16V TDFN
CERM
C7920 1 D Q7921 402
402 69 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6 PP3V3_S0 3 V2MON MR* 1
NC
0.22UF 2N7002DW-X-G 47 46 42 40 37 34 30 28 27 26
WLAN Enable Generation 5 V3MON CRITICAL

99 88 87 85 84 83 80 73 72
10% SOT-363 PP1V5_S3RS0
10V S G 5 PM_ENET_EN_L 86 70 40 26 25 24 23
PP1V05_S0 6 V4MON 8 S0PGOOD_PWROK
CERM 2 21 20 18 17 15 13 12 10 7 6 RST* 73
402
4 6 "WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0")) GPU Rail Sequencing GND THRM_PAD
9
NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal. V2MON THRESHOLD IS 3.0V
GT216 GPU requires rails to come V3MON THRESHOLD IS 0.6V
D Q7921 up in the following order:
V4MON THRESHOLD IS 0.6V
2N7002DW-X-G
SOT-363 1) 1.05V 2) GPU 3V3 3) GPU Vcore 4) GDDR3 1V8
85 73 45 31 18 6 IN PM_SLP_S3_L 2 G S PM_WLAN_EN_L OUT 33
3 1 6
Q7920 D D Q7925
2N7002DW-X-G 2N7002DW-X-G
SOT-363 SOT-363
20 WOL_EN 5 G S S G 2 AP_PWR_EN 20 33 87 86 73
EG_RAIL1_EN EG_RAIL1_EN 73 86 87
IN IN
A 4 1
87 73 72
MAKE_BASE=TRUE
EG_RAIL2_EN EG_RAIL2_EN 72 73 87
MAKE_BASE=TRUE PAGE TITLE
AC_EN_L (AC_EN_L)
87 82 73
EG_RAIL3_EN EG_RAIL3_EN
73 82 87
Power Control
6 3 MAKE_BASE=TRUE DRAWING NUMBER SIZE
Q7925 EG_RAIL4_EN EG_RAIL4_EN Apple Inc. <SCH_NUM> D
D
Q7920 2N7002DW-X-G
D 87 86 73 72
MAKE_BASE=TRUE
72 73 86 87
REVISION
2N7002DW-X-G SOT-363 R
46 45 18 SMC_ADAPTER_EN 2 G S
SOT-363
(PM_SLP_S3_L) 5 G S
<E4LABEL>
IN
1 4 THE INFORMATION CONTAINED HEREIN IS THE
<BRANCH>
79 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT
Page Notes U8000
NV-GT216
BGA 0.1uF
- =PP1V2_GPU_PEX_PLLXVDD (1 OF 9) C8055 1 2 PEG_D2R_P<0> OUT 8 9 91
PEG_R2D_C_P<0> C8020 0.1uF 1 2 PEG_R2D_P<0> AP17 AL17 PEG_D2R_C_P<0> 10% 16V X5R 402
- =PP1V2_GPU_PEX_IOVDDQ 91 9 8 IN 91 PEX_RX0 PEX_TX0 91
10% 16V X5R 40291 PEG_R2D_N<0> PEG_D2R_C_N<0> C8056 0.1uF 1 2 PEG_D2R_N<0>

- =PP1V2_GPU_PEX_IOVDD AN17 PEX_RX0* PEX_TX0* AM17 91
OUT 8 91
PEG_R2D_C_N<0> C8021 0.1uF 1 2 10% 16V X5R 402

91 8 IN
10% 16V X5R 402 0.1uF
(NONE)
C8057 1 2 PEG_D2R_P<1> OUT 8 9 91
PEG_R2D_C_P<1> C8022 0.1uF 1 2 PEG_R2D_P<1> PEG_D2R_C_P<1> 10% 16V X5R 402

91 9 8 IN 91 AN19 PEX_RX1 PEX_TX1 AM18 91
10% 16V X5R 40291 PEG_R2D_N<1> AP19 PEG_D2R_C_N<1> C8058 0.1uF 1 2 PEG_D2R_N<1>
PEX_RX1* PEX_TX1* AM19 91
OUT 8 91
(NONE)
PEG_R2D_C_N<1> C8023 0.1uF 1 2 10% 16V X5R 402
91 8
D
IN
10% 16V X5R 402
C8059 0.1uF 1 2 PEG_D2R_P<2> OUT 8 9 91
D
PP1V05_S0GPU PEG_R2D_C_P<2> C8024 0.1uF 1 2 PEG_R2D_P<2> AR19 PEG_D2R_C_P<2> 10% 16V X5R 402
86 81 79 76 74 7 6 91 9 8 IN 91 PEX_RX2 PEX_TX2 AL19 91
PP1V05_S0GPU 10% 16V X5R 40291 PEG_R2D_N<2> AR20 PEG_D2R_C_N<2> C8060 0.1uF 1 2 PEG_D2R_N<2>
86 81 79 76 74 7 6 PEX_RX2* PEX_TX2* AK19 91
OUT 8 91
PP1V05_S0GPU PEG_R2D_C_N<2> C8025 0.1uF 1 2 10% 16V X5R 402

86 81 79 76 74 7 6 91 8 IN
10% 16V X5R 402 0.1uF
C8061 1 2 PEG_D2R_P<3> OUT 8 9 91
PEG_R2D_C_P<3> C8026 0.1uF 1 2 PEG_R2D_P<3> AP20 PEG_D2R_C_P<3> 10% 16V X5R 402
91 9 8 IN 91 PEX_RX3 PEX_TX3 AL20 91
10% 16V X5R 40291 PEG_R2D_N<3> AN20 PEG_D2R_C_N<3> C8062 0.1uF 1 2 PEG_D2R_N<3>
OUT 8 91
PEG_R2D_C_N<3> C8027 0.1uF 1 2 10% 16V X5R 402

91 8 IN
10% 16V X5R 402 0.1uF
C8063 1 2 PEG_D2R_P<4> OUT 8 9 91
PEG_R2D_C_P<4> C8028 0.1uF 1 2 PEG_R2D_P<4> AN22 PEG_D2R_C_P<4> 10% 16V X5R 402
91 9 8 IN 91 PEX_RX4 PEX_TX4 AM21 91
10% 16V X5R 40291 PEG_R2D_N<4> AP22 PEG_D2R_C_N<4> C8064 0.1uF 1 2 PEG_D2R_N<4>
OUT 8 91
PEG_R2D_C_N<4> C8029 0.1uF 1 2 10% 16V X5R 402

91 8 IN
10% 16V X5R 402 0.1uF
C8065 1 2 PEG_D2R_P<5> OUT 8 9 91
PEG_R2D_C_P<5> C8030 0.1uF 1 2 PEG_R2D_P<5> AR22 PEG_D2R_C_P<5> 10% 16V X5R 402
PEX 1.1V Current = 2A 91 9 8 IN 91 PEX_RX5 PEX_TX5 AL22 91
10% 16V X5R 40291 PEG_R2D_N<5> AR23 AK22 PEG_D2R_C_N<5> C8066 0.1uF 1 2 PEG_D2R_N<5>
PEX_RX5* PEX_TX5* 91
OUT 8 91
PEG_R2D_C_N<5> C8031 0.1uF 1 2 10% 16V X5R 402

250mA 91 8 IN
10% 16V X5R 402 0.1uF
C8067 1 2 PEG_D2R_P<6> OUT 8 9 91
91 PEX_RX6 PEX_TX6 91
1 C8002 1 C8001 1 C8000 91 9 8 IN
10% 16V X5R 40291 PEG_R2D_N<6> AN23 PEX_RX6* PEX_TX6* AM23 91 PEG_D2R_C_N<6> C8068 0.1uF 1 2 PEG_D2R_N<6>
1UF 4.7UF 22UF 0.1uF OUT 8 91
10% 20% 20% 91 8 PEG_R2D_C_N<6> C8033 1 2 10% 16V X5R 402
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM-X5R
IN
10% 16V X5R 402
NC_GPU_DFM 402 603 805 C8069 0.1uF 1 2 PEG_D2R_P<7> OUT 8 9 91
NO_TEST=TRUE
PEG_R2D_C_P<7> C8034 0.1uF 1 2 PEG_R2D_P<7> PEG_D2R_C_P<7> 10% 16V X5R 402
OMIT 91 9 8 IN 91 AN25 PEX_RX7 PEX_TX7 AM24 91
10% 16V X5R 40291 PEG_R2D_N<7> AP25 AM25 PEG_D2R_C_N<7> C8070 0.1uF 1 2 PEG_D2R_N<7>
PEX_RX7* PEX_TX7* 91
OUT 8 91
PEG_R2D_C_N<7> C8035 0.1uF 1 2 10% 16V X5R 402

C U8000
NV-GT216
1 C8003
1UF
1 C8004
0.1UF
1 C8005
0.1UF
91 8 IN
10% 16V X5R 402
C8071 0.1uF 1 2 PEG_D2R_P<8> 8 9 91
C
BGA 10% 20% 20% OUT
C8036 0.1uF
(2 OF 9) 2 6.3V
CERM 2 10V
CERM 2 10V
CERM 91 9 8 IN PEG_R2D_C_P<8> 1 2 91 PEG_R2D_P<8> AR25 PEX_RX8 PEX_TX8 AL25 91 PEG_D2R_C_P<8> 10% 16V X5R 402
402 402 402 10% 16V X5R 40291 PEG_R2D_N<8> PEG_D2R_C_N<8> C8072 0.1uF 1 2 PEG_D2R_N<8>
H32 PEX_IOVDD1 AK16 AR26 PEX_RX8* PEX_TX8* AK25 91
OUT 8 91
PEG_R2D_C_N<8> C8037 0.1uF 1 2 10% 16V X5R 402

M7 PEX_IOVDD2 AK17 91 8 IN
10% 16V X5R 402 0.1uF
P6 PEX_IOVDD3 AK21 C8073 1 2 PEG_D2R_P<9> OUT 8 9 91
A5 PEX_IOVDD4 AK24
91 9 8 IN 91 PEX_RX9 PEX_TX9 91
U7 PEX_IOVDD5 AK27 10% 16V X5R 40291 PEG_R2D_N<9> AN26 AM26 PEG_D2R_C_N<9> C8074 0.1uF 1 2 PEG_D2R_N<9>
1500mA PEX_RX9* PEX_TX9* 91
OUT 8 91
V6
PEG_R2D_C_N<9> C8039 0.1uF 1 2 10% 16V X5R 402
91 8 IN
AB7 10% 16V X5R 402
C8075 0.1uF
AD6 1 C8008 1 C8007 1 C8006 1 C8018 0.1uF
1 2 PEG_D2R_P<10> OUT 8 9 91
AF6 PEX_IOVDDQ1 AG11 1UF

10%
4.7UF
20%
22UF
20%
10UF
20% 91 9 8 IN PEG_R2D_C_P<10> C8040 1 2 91 PEG_R2D_P<10> AN28 PEX_RX10 PEX_TX10 AM27 91 PEG_D2R_C_P<10> 10% 16V X5R 402
C8076 0.1uF
AG6 PEX_IOVDDQ2 AG12 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM-X5R 2 6.3V
X5R
10% 16V X5R 40291 PEG_R2D_N<10> AP28 PEX_RX10* PEX_TX10* AM28 91 PEG_D2R_C_N<10> 1 2 PEG_D2R_N<10> OUT 8 91
402 603 805 603 PEG_R2D_C_N<10> C8041 0.1uF 1 2 10% 16V X5R 402
AJ5 PEX_IOVDDQ3 AG13 91 8 IN
10% 16V X5R 402 0.1uF
AK15 PEX_IOVDDQ4 AG15 C8077 1 2 PEG_D2R_P<11> OUT 8 9 91
AL7 PEX_IOVDDQ5 AG16
PEG_R2D_C_P<11> C8042 0.1uF 1 2 PEG_R2D_P<11> AR28 PEG_D2R_C_P<11> 10% 16V X5R 402
91 9 8 IN 91 PEX_RX11 PEX_TX11 AL28 91
E7 PEX_IOVDDQ6 AG17 C8078 0.1uF
1 C8009 1 C8010 1 C8011 0.1uF
10% 16V X5R 40291 PEG_R2D_N<11> AR29 PEX_RX11* PEX_TX11* AK28 91 PEG_D2R_C_N<11> 1 2 PEG_D2R_N<11> OUT 8 91
A2 PEX_IOVDDQ7 AG18 1UF
10%
0.1UF
20%
0.1UF
20% 91 8 IN PEG_R2D_C_N<11> C8043 1 2 10% 16V X5R 402
A7 PEX_IOVDDQ8 AG22
2 6.3V
CERM 2 10V
CERM 2 10V
CERM
10% 16V X5R 402
C8079 0.1uF 1 2
B7 PEX_IOVDDQ9 AG23 402 402 402 PEG_D2R_P<12> OUT 8 9 91
C5 PEG_R2D_C_P<12> C8044 0.1uF 1 2 PEG_R2D_P<12> PEG_D2R_C_P<12> 10% 16V X5R 402

NC PEX_IOVDDQ10 AG24 91 9 8 IN 91 AP29 PEX_RX12 PEX_TX12 AK29 91
C7 AG25 10% 16V X5R 40291 PEG_R2D_N<12> AN29 AL29 PEG_D2R_C_N<12> C8080 0.1uF 1 2 PEG_D2R_N<12>
PEX_IOVDDQ11 PEX_RX12* PEX_TX12* 91
OUT 8 91
D5 PEG_R2D_C_N<12> C8045 0.1uF 1 2 10% 16V X5R 402

PEX_IOVDDQ12 AG26 91 8 IN
D6 PEX_IOVDDQ13 AJ14 L8015 10% 16V X5R 402
C8081 0.1uF 1 2 PEG_D2R_P<13>
120 mA: GT216 A01 DG v3 01/09 100NH-700MA-0.14OHM 0.1uF OUT 8 9 91
D7 PEX_IOVDDQ14 AJ15
91 9 8 IN PEG_R2D_C_P<13> C8046 1 2 91 PEG_R2D_P<13> AN31 PEX_RX13 PEX_TX13 AM29 91 PEG_D2R_C_P<13> 10% 16V X5R 402
E5 PEX_IOVDDQ15 AJ19 PP1V1_GPU_PEX_PLLVDD_F 1 2
10% 16V X5R 40291 C8082 0.1uF 1 2
MIN_LINE_WIDTH=0.25 mm PEG_R2D_N<13> AP31 PEX_RX13* PEX_TX13* AM30 91 PEG_D2R_C_N<13> PEG_D2R_N<13> 8 91
B F4
G5
PEX_IOVDDQ16
PEX_IOVDDQ17
AJ21
AJ22
VOLTAGE=1.1V 1 C8017 1
0603
C8016 C8015 1 91 8 IN PEG_R2D_C_N<13> C8047 0.1uF 1 2

10% 16V X5R 402
10% 16V X5R 402
OUT
B
1UF 4.7UF 4.7UF C8083 0.1uF 1 2 PEG_D2R_P<14>
J18 PEX_IOVDDQ18 AJ24 10% 20% 20% OUT 8 9 91
6.3V C8048 0.1uF
J19 PEX_IOVDDQ19 AJ25 2 CERM 2 6.3V
CERM
6.3V 2
CERM 91 9 8 IN PEG_R2D_C_P<14> 1 2 91 PEG_R2D_P<14> AR31 PEX_RX14 PEX_TX14 AM31 91 PEG_D2R_C_P<14> 10% 16V X5R 402
402 603 603 10% 16V X5R 40291 PEG_R2D_N<14> PEG_D2R_C_N<14> C8084 0.1uF 1 2 PEG_D2R_N<14>
J25 PEX_IOVDDQ20 AJ27 AR32 PEX_RX14* PEX_TX14* AM32 91
OUT 8 91
PEG_R2D_C_N<14> C8049 0.1uF 1 2 10% 16V X5R 402

J26 PEX_IOVDDQ21 AK18 91 8 IN
10% 16V X5R 402 0.1uF
AA4 PEX_IOVDDQ22 AK20 C8085 1 2 PEG_D2R_P<15> OUT 8 9 91
AB4 PEX_IOVDDQ23 AK23
PEG_R2D_C_P<15> C8050 0.1uF 1 2 PEG_R2D_P<15> AR34 AN32 PEG_D2R_C_P<15> 10% 16V X5R 402
91 9 8 IN 91 PEX_RX15 PEX_TX15 91
AC5 PEX_IOVDDQ24 AK26 10% 16V X5R 40291 PEG_R2D_N<15> AP34 PEG_D2R_C_N<15> C8086 0.1uF 1 2 PEG_D2R_N<15>
PEX_RX15* PEX_TX15* AP32 91
OUT 8 91
Y4 PEX_IOVDDQ25 AL16
PEG_R2D_C_N<15> C8051 0.1uF 1 2 10% 16V X5R 402
91 8 IN
AG20 10% 16V X5R 402
NO STUFF
R8060
D35 200
VDD_SENSE PEX_PLLVDD 94 17 IN PEG_CLK100M_P AR16 PEX_REFCLK PEX_TSTCLK_OUT AJ17 PEX_TSTCLK_P 1 2
P7 AG14
94 17 IN PEG_CLK100M_N AR17 PEX_REFCLK* PEX_TSTCLK_OUT* AJ18 PEX_TSTCLK_N 1%
1/16W
E35 R8050 MF-LF
GND_SENSE VDD_SENSE AD20 GPU_VDD_SENSE 82 R8020 0 2.49K2 402
R7 87 8 IN EG_RESET_L 1 2 GPU_RESET_R_L AM16 PEX_RST* PEX_TERMP AG21 PEX_TERMP_PD 1
GND_SENSE AD19 GPU_GND_SENSE 82 5% 1%
A4 BUFRST* 1/16W 1/16W
MF-LF AR13 PEX_CLKREQ* MF-LF
402 AG19 402
87 8 PEX_CLKREQ_L PEX_SVDD_3V3 F7
BI
1 C8013 1 C8012
4.7UF 0.1UF
10% 10%
NC_GPU_BUFRST_L PP3V3_S0GPU 6.3V 2 16V
OUT 6
84 82 81 80 79 72 7 6
R8021 2 X5R-CERM
603
X5R
402
1
10K 2
5%
A 1/16W
MF-LF
402
NO STUFF SYNC_MASTER=K17_REF SYNC_DATE=06/15/2009 A
0 2 PAGE TITLE
PP1V05_S0GPU R8012 PP3V3R1V1_GPU_PEX_SVDD
86 81 79 76 74 7 6 1
5% MIN_LINE_WIDTH=0.30MM NV GT216 PCI-E
1/16W MIN_NECK_WIDTH=0.20MM DRAWING NUMBER SIZE
MF-LF VOLTAGE=3.3V
402
R8013 1
0 2
REVISION
R
5%
<E4LABEL>
1/16W
MF-LF
402 THE INFORMATION CONTAINED HEREIN IS THE
<BRANCH>
80 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
Power aliases required by this page: U8000
- =PPVCORE_GPU U8000 NV-GT216
BGA
- =PP1V8_GPU_FBVDDQ
NV-GT216 (8 OF 9)
BGA
(9 OF 9) B3 V18
Signal aliases required by this page: 82
7 6 PPVCORE_GPU L11 V19 B6 V20
(NONE) 49
L12 OMIT V21 B9 OMIT V22
???A @ ???/???MHz Core/Mem Clk for VDD
BOM options provided by this page: L13 V23 B12 V24
(NONE) L14 V25 B15 V31
1 C8100 1 C8101 1 C8102 L15 W11 B21 Y11
1UF 0.22UF 0.22UF L16 W12 B24 Y13
D
10%
10V
2 X5R
402
10%
6.3V
2 CERM-X5R
402
10%
6.3V
2 CERM-X5R
402
L17 W13 B27 Y15 D
L18 W14 B30 Y17
L19 W15 B33 Y19
L20 W16 C2 Y21
L21 W17 C34 Y23
L22 W18 E6 Y25
L23 W19 E9 AA2
L24 AD24 E12 AA5
1 C8103 1 C8104 1 C8105 1 C8106 1 C8107 L25 W21 E15 AA11
0.1UF 0.047UF 0.047UF 0.047UF 0.022UF
10% 10% 10% 10% 10% M12 W22 E18 AA12
16V 16V 16V 16V 16V
2 X7R-CERM 2 X7R 2 X7R 2 X7R 2 CERM-X5R
402 402 402 402 402 M14 W23 E24 AA13
M16 W24 E27 AA14
M18 W25 E30 AA15
M20 Y12 F2 AA16
1 C8108 1 C8109 1 C8110 1 C8111 1 C8112 M22 Y14 F5 AA17
0.022UF 0.022UF 0.015UF 0.015UF 0.01UF M24 Y16 F31 AA18
10% 10% 10% 10% 10%
16V 16V 16V 16V 25V P11 Y18 F34 AA19
2 CERM-X5R 2 CERM-X5R 2 X7R 2 X7R 2 X7R
402 402 402 402 402 P13 Y20 J2 AA20
P15 Y22 J5 AA21
P17 Y24 J31 AA22
P19 VDD VDD AB11 J34 AA23
1 C8113 1 C8114 1 C8115 1 C8116 1 C8117 P21 AB13 L9 AA24
0.01UF 0.01UF 0.01UF 0.01UF 0.01UF
10% 10% 10% 10% 10% P23 AB15 M2 AA25
25V 25V 25V 25V 25V
2 X7R 2 X7R 2 X7R 2 X7R 2 X7R
402 402 402 402 402 P25 AB17 M5 AA34
R11 AB19 M11 AB12
R12 AB21 M13 AB14
C 1 C8118 1 C8119
R13
R14
AB23
AB25
M15
M17
AB16
AB18 C
0.0068UF 0.0047UF R15 AC11 M19 AB20
10% 10%
2 25V
CERM 2 25V
CERM R16 AC12 M21 AB22
402 402 R17 AC13 M23 AB24
R18 AC14 M25 AC9
R19 AC15 M31 AD2
R20 AC16 M34 AD5
R21 AC17 N11 AD11
R22 AC18 N12 AD13
R23 AC19 N13 AD15
R24 AC20 N14 AD17
R25 AC21 N15 AD21
T12 AC22 N16 AD23
T14 AC23 N17 GND GND AD25
T16 AC24 N18 AD31
78 77 76 56 50 8 7 6 PP1V8R1V55_S0GPU_ISNS T18 AC25 N19 AD34
T20 AD12 N20 AE11
T22 AD14 N21 AE12
T24 AD16 N22 AE13
V11 AD18 N23 AE14
Nvidia PRD for GB-128 uses 4x4.7uF, 8x0.47uF, 16x0.1uF
V13 AD22 N24 AE15
V15 W20 N25 AE16
???A @ ???MHz 1.8V GDDR3
V17 P12 AE17
P14 AE18
P16 AE19
C8150 1 P18 AE20
4.7UF
B 20%
6.3V 2
CERM
P20 AE21 B
603 P22 AE22
OMIT P24 AE23
R2 AE24
R5 AE25
C8156 1 C8157 1 C8158 1 C8159 1 C8160 1 U8000 R31 AG2
4.7UF 0.1UF 0.1UF 0.1UF 0.047UF R34 AG5
20% 20% 20% 20% 10% NV-GT216
6.3V 10V 10V 10V 16V BGA T11 AG31
CERM 2 CERM 2 CERM 2 CERM 2 X7R 2
(7 OF 9)
603 402 402 402 402 T13 AG34
B18 J20
T15 AK2
J17 J21
T17 AK5
U27 J22
T19 AP33
C8162 1 C8163 1 C8164 1 C8165 1 C8166 1 AB27 J23
T21 AK31
0.047UF 0.047UF 0.01UF 0.01UF 0.01UF AB29 J24
10% 10% 10% 10% 10% T23 AK34
16V 16V 25V 25V 25V AC27 J29
X7R 2 X7R 2 X7R 2 X7R 2 X7R 2 T25 AL6
402 402 402 402 402 AD27 N27
U11 AL9
AE27 P27
U12 AL12
AJ28 R27
FBVDDQ FBVDDQ U13 AL15
E21 T27
U14 AL18
G8 U29
U15 AL21
G9 V27
U16 AL24
G17 V29
U17 AL27
G18 V34
U18 AL30
G22 W27
U19 AN2
H29 Y27
U20 AN34
J14 AA27
U21 AP3
A J15
J16
AA29
AA31
U22 AP6 SYNC_MASTER=K17_REF SYNC_DATE=06/15/2009 A
U23 AP9 PAGE TITLE
U24 AP12 NV GT216 CORE/FB POWER

U25 AP15 DRAWING NUMBER SIZE
V2 AP18
V5 AP21 REVISION
R
V9 AP24 <E4LABEL>
V12 AP27 NOTICE OF PROPRIETARY PROPERTY: BRANCH
V14 AP30 THE INFORMATION CONTAINED HEREIN IS THE
<BRANCH>
V16 K9 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
AK14 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
81 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
- =PP1V2_GPU_FBPLLAVDD
- =PP1V8_GPU_FBIO
OMIT
U8000
(NONE) NV-GT216
BGA
BOM options provided by this page: (4 OF 9)
(NONE) 98 78 BI FB_B_DQ<0> B13 FBC_D00 FBC_CMD0 C17 FB_B_LMA<4> OUT 78 98
98 78 BI FB_B_DQ<1> D13 FBC_D01 FBC_CMD1 B19 FB_B_RAS_L OUT 78 98
OMIT 98 78 FB_B_DQ<2> A13 FBC_D02 FBC_CMD2 D18 FB_B_LMA<5> 78 98
D U8000
98 78
BI
BI FB_B_DQ<3> A14 FBC_D03 FBC_CMD3 F21 FB_B_BA<1>
OUT
OUT 78 98 D
98 78 BI FB_B_DQ<4> C16 FBC_D04 FBC_CMD4 A23 FB_B_UMA<2> OUT 78 98
NV-GT216 98 78 BI FB_B_DQ<5> B16 FBC_D05 FBC_CMD5 D21 FB_B_UMA<4> OUT 78 98
BGA
(3 OF 9) 98 78 BI FB_B_DQ<6> A17 FBC_D06 FBC_CMD6 B23 FB_B_UMA<3> OUT 78 98
98 77 BI FB_A_DQ<0> L32 FBA_D00 FBA_CMD0 V32 FB_A_LMA<4> OUT 77 98 98 78 BI FB_B_DQ<7> D16 FBC_D07 FBC_CMD7 E20 FB_B_UCKE OUT 78 98
98 77 BI FB_A_DQ<1> N33 FBA_D01 FBA_CMD1 W31 FB_A_RAS_L OUT 77 98 98 78 BI FB_B_DQ<8> C13 FBC_D08 FBC_CMD8 G21 FB_B_UCS0_L OUT 78
FB_A_DQ<2> FB_A_LMA<5> FB_B_DQ<9> FB_B_MA<11> 1

98 77 BI L33 FBA_D02 FBA_CMD2 U31 OUT 77 98 98 78 BI B11 FBC_D09 FBC_CMD9 F20 OUT 78 98
R8252
98 77 BI FB_A_DQ<3> N34 FBA_D03 FBA_CMD3 Y32 FB_A_BA<1> OUT 77 98 98 78 BI FB_B_DQ<10> C11 FBC_D10 FBC_CMD10 F19 FB_B_LCAS_L OUT 78 98 10K
5%
98 77 BI FB_A_DQ<4> N35 FBA_D04 FBA_CMD4 AB35 FB_A_UMA<2> OUT 77 98 98 78 BI FB_B_DQ<11> A11 FBC_D11 FBC_CMD11 F23 FB_B_WE_L OUT 78 98 1/16W
MF-LF
98 77 BI FB_A_DQ<5> P35 FBA_D05 FBA_CMD5 AB34 FB_A_UMA<4> OUT 77 98 98 78 BI FB_B_DQ<12> C10 FBC_D12 FBC_CMD12 A22 FB_B_BA<0> OUT 78 98
2 402
98 77 BI FB_A_DQ<6> P33 FBA_D06 FBA_CMD6 W35 FB_A_UMA<3> OUT 77 98 98 78 BI FB_B_DQ<13> C8 FBC_D13 FBC_CMD13 C22 FB_B_UMA<5> OUT 78 98
98 77 BI FB_A_DQ<7> P34 FBA_D07 FBA_CMD7 W33 FB_A_UCKE OUT 77 98 98 78 BI FB_B_DQ<14> B8 FBC_D14 FBC_CMD14 B17 FB_B_MA<12> OUT 78 98
98 77 BI FB_A_DQ<8> K35 FBA_D08 FBA_CMD8 W30 FB_A_UCS0_L OUT 77 98 78 BI FB_B_DQ<15> A8 FBC_D15 FBC_CMD15 F24 FB_B_DRAM_RST OUT 78 98
FB_A_DQ<9> FB_A_MA<11> 1 FB_B_DQ<16> FB_B_MA<7>

98 77 BI K33 FBA_D09 FBA_CMD9 T34 OUT 77 98 R8203 98 78 BI E8 FBC_D16 FBC_CMD16 C25 OUT 78 98
1
98 77 BI FB_A_DQ<10> K34 FBA_D10 FBA_CMD10 T35 FB_A_LCAS_L OUT 77 98 10K 98 78 BI FB_B_DQ<17> F8 FBC_D17 FBC_CMD17 E22 FB_B_MA<10> OUT 78 98 R8250
5%
98 77 BI FB_A_DQ<11> H33 FBA_D11 FBA_CMD11 AB31 FB_A_WE_L OUT 77 98 1/16W 98 78 BI FB_B_DQ<18> F10 FBC_D18 FBC_CMD18 C20 FB_B_LCKE OUT 78 98 10K
MF-LF 5%
98 77 BI FB_A_DQ<12> G34 FBA_D12 FBA_CMD12 Y30 FB_A_BA<0> OUT 77 98
2 402 98 78 BI FB_B_DQ<19> F9 FBC_D19 FBC_CMD19 B22 FB_B_MA<0> OUT 78 98 1/16W
1 MF-LF
98 77 BI FB_A_DQ<13> G33 FBA_D13 FBA_CMD13 Y34 FB_A_UMA<5> OUT 77 98 98 78 BI FB_B_DQ<20> F12 FBC_D20 FBC_CMD20 A19 FB_B_MA<9> OUT 78 98
R8251 2 402
98 77 BI FB_A_DQ<14> E34 FBA_D14 FBA_CMD14 W32 FB_A_MA<12> OUT 77 98 98 78 BI FB_B_DQ<21> D8 FBC_D21 FBC_CMD21 D22 FB_B_MA<6> OUT 78 98 10K
5%
98 77 BI FB_A_DQ<15> E33 FBA_D15 FBA_CMD15 AA30 FB_A_DRAM_RST OUT 77 98 98 78 BI FB_B_DQ<22> D11 FBC_D22 FBC_CMD22 D20 FB_B_LMA<2> OUT 78 98 1/16W
MF-LF
98 77 BI FB_A_DQ<16> G31 FBA_D16 FBA_CMD16 AA32 FB_A_MA<7> OUT 77 98 98 78 BI FB_B_DQ<23> E11 FBC_D23 FBC_CMD23 E19 FB_B_MA<8> OUT 78 98
2 402
FB_A_DQ<17> FB_A_MA<10> 1 FB_B_DQ<24> FB_B_LMA<3>
98 77 BI F30 FBA_D17 FBA_CMD17 Y33 OUT 77 98
R8200 98 78 BI D12 FBC_D24 FBC_CMD24 D19 OUT 78 98
98 77 BI FB_A_DQ<18> G30 FBA_D18 FBA_CMD18 U32 FB_A_LCKE OUT 77 98 10K 98 78 BI FB_B_DQ<25> E13 FBC_D25 FBC_CMD25 F18 FB_B_MA<1> OUT 78 98
5%
98 77 BI FB_A_DQ<19> G32 FBA_D19 FBA_CMD19 Y31 FB_A_MA<0> OUT 77 98 1/16W 98 78 BI FB_B_DQ<26> F13 FBC_D26 FBC_CMD26 C19 NC_FBB_MA<13> OUT 80
1 MF-LF
98 77 BI FB_A_DQ<20> K30 FBA_D20 FBA_CMD20 U34 FB_A_MA<9> OUT 77 98
R8201 2 402 98 78 BI FB_B_DQ<27> F14 FBC_D27 FBC_CMD27 F22 FB_B_BA<2> OUT 78 98
98 77 BI FB_A_DQ<21> K32 FBA_D21 FBA_CMD21 Y35 FB_A_MA<6> OUT 77 98 10K 98 78 BI FB_B_DQ<28> F15 FBC_D28 FBC_CMD28 C23 NC_FB_B_UCS1_L 80
5%
FB_A_DQ<22> FB_A_LMA<2> FB_B_DQ<29> FB_B_LCS0_L
C 98 77
98 77
BI
BI FB_A_DQ<23>
H30
K31
FBA_D22
FBA_D23
FBA_CMD22
FBA_CMD23
W34
V30 FB_A_MA<8>
OUT
OUT
77 98
77 98
1/16W
MF-LF
2 402
98 78
98 78
BI
BI FB_B_DQ<30>
E16
F16
FBC_D29
FBC_D30
FBC_CMD29
FBC_CMD30
B20
A20
78 98
NC_FB_B_LCS1_L 80 C
98 77 BI FB_A_DQ<24> L31 FBA_D24 FBA_CMD24 U35 FB_A_LMA<3> OUT 77 98 98 78 BI FB_B_DQ<31> F17 FBC_D31
FBC_CLK0 E17 FB_B_CLK_P<0> OUT 78 98
98 77 BI FB_A_DQ<25> L30 FBA_D25 FBA_CMD25 U30 FB_A_MA<1> OUT 77 98 98 78 BI FB_B_DQ<32> D29 FBC_D32
FBC_CLK0* D17 FB_B_CLK_N<0> OUT 78 98
98 77 BI FB_A_DQ<26> M32 FBA_D26 FBA_CMD26 U33 NC_FBA_MA<13> OUT 80 98 78 BI FB_B_DQ<33> F27 FBC_D33
FBC_CLK1 D23 FB_B_CLK_P<1> OUT 78 98
98 77 BI FB_A_DQ<27> N30 FBA_D27 FBA_CMD27 AB30 FB_A_BA<2> OUT 77 98 98 78 BI FB_B_DQ<34> F28 FBC_D34
FBC_CLK1* E23 FB_B_CLK_N<1> OUT 78 98
98 77 BI FB_A_DQ<28> M30 FBA_D28 FBA_CMD28 AB33 NC_FB_A_UCS1_L 80 98 78 BI FB_B_DQ<35> E28 FBC_D35
98 77 BI FB_A_DQ<29> P31 FBA_D29 FBA_CMD29 T33 FB_A_LCS0_L 77 98 98 78 BI FB_B_DQ<36> D26 FBC_D36
FBC_DQM0 A16 FB_B_DQM_L<0> BI 78 98
98 77 BI FB_A_DQ<30> R32 FBA_D30 FBA_CMD30 W29 NC_FB_A_LCS1_L 80 98 78 BI FB_B_DQ<37> F25 FBC_D37
FBC_DQM1 D10 FB_B_DQM_L<1> BI 78 98
98 77 BI FB_A_DQ<31> R30 FBA_D31 98 78 BI FB_B_DQ<38> D24 FBC_D38
FBA_CLK0 T32 FB_A_CLK_P<0> OUT 77 98 FBC_DQM2 F11 FB_B_DQM_L<2> BI 78 98
98 77 BI FB_A_DQ<32> AG30 FBA_D32 98 78 BI FB_B_DQ<39> E25 FBC_D39
FBA_CLK0* T31 FB_A_CLK_N<0> OUT 77 98 FBC_DQM3 D15 FB_B_DQM_L<3> BI 78 98
98 77 BI FB_A_DQ<33> AG32 FBA_D33 98 78 BI FB_B_DQ<40> E32 FBC_D40
FBA_CLK1 AC31 FB_A_CLK_P<1> OUT 77 98 FBC_DQM4 D27 FB_B_DQM_L<4> BI 78 98
98 77 BI FB_A_DQ<34> AH31 FBA_D34 98 78 BI FB_B_DQ<41> F32 FBC_D41
FBA_CLK1* AC30 FB_A_CLK_N<1> OUT 77 98 FBC_DQM5 D34 FB_B_DQM_L<5> BI 78 98
98 77 BI FB_A_DQ<35> AF31 FBA_D35 98 78 BI FB_B_DQ<42> D33 FBC_D42
FBC_DQM6 A34 FB_B_DQM_L<6> BI 78 98
98 77 BI FB_A_DQ<36> AF30 FBA_D36 98 78 BI FB_B_DQ<43> E31 FBC_D43
FBA_DQM0 P32 FB_A_DQM_L<0> BI 77 98 FBC_DQM7 D28 FB_B_DQM_L<7> BI 78 98
98 77 BI FB_A_DQ<37> AE30 FBA_D37 98 78 BI FB_B_DQ<44> C33 FBC_D44
FBA_DQM1 H34 FB_A_DQM_L<1> BI 77 98
98 77 BI FB_A_DQ<38> AC32 FBA_D38 98 78 BI FB_B_DQ<45> F29 FBC_D45
FBA_DQM2 J30 FB_A_DQM_L<2> BI 77 98 FBC_DQS_RN0 B14 FB_B_RDQS<0> IN 78 98
98 77 BI FB_A_DQ<39> AD30 FBA_D39 98 78 BI FB_B_DQ<46> D30 FBC_D46
FBA_DQM3 P30 FB_A_DQM_L<3> BI 77 98 FBC_DQS_RN1 B10 FB_B_RDQS<1> IN 78 98
98 77 BI FB_A_DQ<40> AN33 FBA_D40 98 78 BI FB_B_DQ<47> E29 FBC_D47
FBA_DQM4 AF32 FB_A_DQM_L<4> BI 77 98 FBC_DQS_RN2 D9 FB_B_RDQS<2> IN 78 98
98 77 BI FB_A_DQ<41> AL31 FBA_D41 98 78 BI FB_B_DQ<48> B29 FBC_D48
FBA_DQM5 AL32 FB_A_DQM_L<5> BI 77 98 FBC_DQS_RN3 E14 FB_B_RDQS<3> IN 78 98
98 77 BI FB_A_DQ<42> AM33 FBA_D42 98 78 BI FB_B_DQ<49> C31 FBC_D49
FBA_DQM6 AL34 FB_A_DQM_L<6> BI 77 98 FBC_DQS_RN4 F26 FB_B_RDQS<4> IN 78 98
98 77 BI FB_A_DQ<43> AL33 FBA_D43 98 78 BI FB_B_DQ<50> C29 FBC_D50
FBA_DQM7 AF35 FB_A_DQM_L<7> BI 77 98 FBC_DQS_RN5 D31 FB_B_RDQS<5> IN 78 98
98 77 BI FB_A_DQ<44> AK30 FBA_D44 98 78 BI FB_B_DQ<51> B31 FBC_D51
FBC_DQS_RN6 A31 FB_B_RDQS<6> IN 78 98
98 77 BI FB_A_DQ<45> AK32 FBA_D45 98 78 BI FB_B_DQ<52> C32 FBC_D52
FBA_DQS_RN0 L35 FB_A_RDQS<0> IN 77 98 FBC_DQS_RN7 A26 FB_B_RDQS<7> IN 78 98
98 77 BI FB_A_DQ<46> AJ30 FBA_D46 98 78 BI FB_B_DQ<53> B32 FBC_D53
FBA_DQS_RN1 G35 FB_A_RDQS<1> IN 77 98
98 77 BI FB_A_DQ<47> AH30 FBA_D47 98 78 BI FB_B_DQ<54> B35 FBC_D54
FBA_DQS_RN2 H31 FB_A_RDQS<2> IN 77 98 FBC_DQS_WP0 C14 FB_B_WDQS<0> OUT 78 98
98 77 FB_A_DQ<48> AH33 FBA_D48 86 81 79 74 7 6 PP1V05_S0GPU 98 78 FB_B_DQ<55> B34 FBC_D55
B 98 77
BI
BI FB_A_DQ<49> AH35 FBA_D49
FBA_DQS_RN3
FBA_DQS_RN4
N32
AD32
FB_A_RDQS<3>
FB_A_RDQS<4>
IN
IN
77 98
77 98
98 78
BI
BI FB_B_DQ<56> A29 FBC_D56
FBC_DQS_WP1
FBC_DQS_WP2
A10
E10
FB_B_WDQS<1>
FB_B_WDQS<2>
OUT
OUT
78 98
78 98
B
98 77 BI FB_A_DQ<50> AH34 FBA_D50 CRITICAL 98 78 BI FB_B_DQ<57> B28 FBC_D57
FBA_DQS_RN5 AJ31 FB_A_RDQS<5> IN 77 98 FBC_DQS_WP3 D14 FB_B_WDQS<3> OUT 78 98
FB_A_DQ<51> AH32 FBA_D51 FB_B_DQ<58> A28 FBC_D58
98 77 BI
FB_A_DQ<52> AJ33 FBA_D52
FBA_DQS_RN6 AJ35 FB_A_RDQS<6> IN 77 98 L8200 98 78 BI
FB_B_DQ<59> C28 FBC_D59
FBC_DQS_WP4 E26 FB_B_WDQS<4> OUT 78 98
98 77 BI
FBA_DQS_RN7 AC34 FB_A_RDQS<7> 77 98
300-OHM-0.5A 98 78 BI
FBC_DQS_WP5 D32 FB_B_WDQS<5> 78 98 50 8 7 6 PP1V8R1V55_S0GPU_ISNS
FB_A_DQ<53> IN FB_B_DQ<60> OUT
98 77 BI AL35 FBA_D53 98 78 BI C26 FBC_D60 78 77 76 75 56
1 2 FBC_DQS_WP6 A32 FB_B_WDQS<6> OUT 78 98
98 77 BI FB_A_DQ<54> AM34 FBA_D54 98 78 BI FB_B_DQ<61> D25 FBC_D61
98 77 BI FB_A_DQ<55> AM35 FBA_D55
FBA_DQS_WP0 L34 FB_A_WDQS<0> OUT 77 98 0603-1
98 78 BI FB_B_DQ<62> B25 FBC_D62
FBC_DQS_WP7 B26 FB_B_WDQS<7> OUT 78 98
R82951
FBA_DQS_WP1 H35 FB_A_WDQS<1> 1.07K
98 77 BI FB_A_DQ<56> AF33 FBA_D56
FBA_DQS_WP2 J32 FB_A_WDQS<2>
OUT 77 98
1 C8202 1 C8200 1 C8201 98 78 BI FB_B_DQ<63> A25 FBC_D63 1%
1/16W
98 77 BI FB_A_DQ<57> AE32 FBA_D57
OUT 77 98
1UF 4.7UF 4.7UF MF-LF
N31 FB_A_WDQS<3> 10% 10% 10%
98 77 BI FB_A_DQ<58> AF34 FBA_D58
FBA_DQS_WP3 OUT 77 98
2 6.3V 2 6.3V 2 6.3V NCG11 402 2
AE31 FB_A_WDQS<4> CERM X5R-CERM X5R-CERM FB_B_UCAS_L
98 77 BI FB_A_DQ<59> AE35 FBA_D59
FBA_DQS_WP4 OUT 77 98
402 603 603 NCG12 FBC_DEBUG G19 OUT 78 98
FBA_DQS_WP5 AJ32 FB_A_WDQS<5> OUT 77 98

NCG14
98 77 BI FB_A_DQ<60> AE34 FBA_D60 FB_VREF J27 GPU_FB_VREF
FBA_DQS_WP6 AJ34 FB_A_WDQS<6> OUT 77 98 78 77 76 75 56 50 8 7 6 PP1V8R1V55_S0GPU_ISNS NCG15
98 77 BI FB_A_DQ<61> AE33 FBA_D61 NC
FBA_DQS_WP7 AC33 FB_A_WDQS<7> OUT 77 98
NCG24
98 77 BI FB_A_DQ<62> AB32 FBA_D62
R82901 NCG25
R82961
98 77 BI FB_A_DQ<63> AC35 FBA_D63 FB_DLLAVDD AG27 PP1V1_GPU_FBPLLAVDD_F MIN_LINE_WIDTH=0.2 MM 2.49K
MIN_NECK_WIDTH=0.2 MM 56.2 NCG27 1%
FB_PLLAVDD AF27 VOLTAGE=1.1V 1% 1/16W
NCP29 1/16W
MF-LF NCG28 MF-LF
402 2
NCR29 FBA_DEBUG T30 FB_A_UCAS_L OUT 77 98 402 2
NCL29 FB_CAL_PD_VDDQ K27 FBCAL_PD_VDDQ

NCM29 FB_CAL_PU_GND L27 FBCAL_PU_GND PLACE_NEAR=U8000.K27:3mm
AD29 NC
NC FB_CAL_TERM_GND M27 FBCAL_TERM_GND
AE29
NC
AG29
NC R82921 R82911
31.6
AH29
NC 40.2 1% PLACE_NEAR=U8000.L27:3mm
1% 1/16W
1/16W MF-LF
MF-LF 402 2
402 2
A PLACE_NEAR=U8000.M27:3mm
PAGE TITLE
NV GT216 FRAME BUFFER I/F

DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
82 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT OMIT
Page Notes
PP1V8R1V55_S0GPU_ISNS CRITICAL PP1V8R1V55_S0GPU_ISNS CRITICAL
76 75 56 50 8 7 6 78 77 76 75 56 50 8 7 6 Power aliases required by this page:
78 77
A2 VDD0 VSS0 A3 A2 VDD0 VSS0 A3 - =PP1V8_S0_FB_VDD
A11 VDD1
U8400 VSS1 A10 A11 VDD1
U8450 VSS1 A10 - =PP1V8_S0_FB_VREFA
BGA BGA
C8400 1 1 C8401 1 C8402 1 C8403 1 C8404 F1 VDD2 (2 OF 2) VSS2 G1 C8450 1 1 C8451 1 C8452 1 C8453 1 C8454 F1 VDD2 (2 OF 2) VSS2 G1
10UF 0.1uF 0.1uF 0.1uF 0.1uF 10UF 0.1uF 0.1uF 0.1uF 0.1uF Signal aliases required by this page:
K4J10324QD-HC11
K4J10324QD-HC11
F12 G12 F12 G12
32MX32-900MHZ-MFH
32MX32-900MHZ-MFH
20% 10% 10% 10% 10% VDD3 VSS3 20% 10% 10% 10% 10% VDD3 VSS3
6.3V 2 (NONE)
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R M1 VDD4 VSS4 L1 6.3V 2
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R M1 VDD4 VSS4 L1
603 402 402 402 402 M12 VDD5 VSS5 L12 603 402 402 402 402 M12 VDD5 VSS5 L12 BOM options provided by this page:
V2 VDD6 VSS6 V3 V2 VDD6 VSS6 V3 VRAM4
V11 VDD7 VSS7 V10 V11 VDD7 VSS7 V10
D
K1 VDDA0
K12 VDDA1
VSSA0 J1
VSSA1 J12
K1 VDDA0
K12 VDDA1
VSSA0 J1
VSSA1 J12
D
A1 VDDQ0 VSSQ0 B1 A1 VDDQ0 VSSQ0 B1
1 C8410 1 C8415 A12 VDDQ1 VSSQ1 B4
1 C8460 1 C8465 A12 VDDQ1 VSSQ1 B4
0.1uF 0.1uF 0.1uF 0.1uF
10% 10% C1 VDDQ2 VSSQ2 B9 10% 10% C1 VDDQ2 VSSQ2 B9
2 16V
X5R 2 16V
X5R B12 2 16V
X5R 2 16V
X5R B12
402 402 C4 VDDQ3 VSSQ3 402 402 C4 VDDQ3 VSSQ3
U8400.J1 U8400.J12 C9 VDDQ4 VSSQ4 D1 U8400.J1 U8400.J12 C9 VDDQ4 VSSQ4 D1
Connect to designated pin, then GND Connect to designated pin, then GND
C12 VDDQ5 VSSQ5 D4 C12 VDDQ5 VSSQ5 D4
E1 VDDQ6 VSSQ6 D9 E1 VDDQ6 VSSQ6 D9
76 75 56 50 8 7 6 PP1V8R1V55_S0GPU_ISNS D12 78 77 76 75 56 50 8 7 6 PP1V8R1V55_S0GPU_ISNS D12
78 77 E4 VDDQ7 VSSQ7 E4 VDDQ7 VSSQ7
E9 VDDQ8 VSSQ8 G2 E9 VDDQ8 VSSQ8 G2
C8420 1 1 C8421 1 C8422 1 C8423 1 C8424 1 C8425 1 C8426 J4 VDDQ10 VSSQ10 L2 C8470 1 1 C8471 1 C8472 1 C8473 1 C8474 1 C8475 1 C8476 J4 VDDQ10 VSSQ10 L2
10UF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 10UF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
20% 10% 10% 10% 10% 10% 10% J9 VDDQ11 VSSQ11 L11 20% 10% 10% 10% 10% 10% 10% J9 VDDQ11 VSSQ11 L11
6.3V 2 2 16V 2 16V 2 16V 2 16V 2 16V 2 16V 6.3V 2 2 16V 2 16V 2 16V 2 16V 2 16V 2 16V
X5R X5R X5R X5R X5R X5R X5R N1 VDDQ12 VSSQ12 P1 X5R X5R X5R X5R X5R X5R X5R N1 VDDQ12 VSSQ12 P1
603 402 402 402 402 402 402 603 402 402 402 402 402 402
N4 VDDQ13 VSSQ13 P4 N4 VDDQ13 VSSQ13 P4
77 32 8 GPU_FB_A_VREF_DIV N12 VDDQ15 VSSQ15 P12 77 32 8 GPU_FB_A_VREF_DIV N12 VDDQ15 VSSQ15 P12
R1 VDDQ16 VSSQ16 T1 R1 VDDQ16 VSSQ16 T1
1 1
R8430 R8433 R4 VDDQ17 VSSQ17 T4 R84801 R84831 R4 VDDQ17 VSSQ17 T4
549 549 R9 VDDQ18 VSSQ18 T9 549 549 R9 VDDQ18 VSSQ18 T9
1% 1% R12 T12 1% 1% R12 T12
1/16W 1/16W VDDQ19 VSSQ19 1/16W 1/16W VDDQ19 VSSQ19
402 2 402 2 V1 VDDQ20 402 2 402 2 V1 VDDQ20
V12 VDDQ21 V12 VDDQ21
FB_A0_VREF H1 VREF0 FB_A1_VREF H1 VREF0

FB_A2_VREF H12 VREF1 FB_A3_VREF H12 VREF1
C C8431 R84341 C8432 C8481 R84841 C8482
C
R84311 R84321 1
0.01UF
R84351 1
0.01UF
R84811 R84821 1
0.01uF
R84851 1
0.01uF
1.33K 931 10% 1.33K 931 10% 1.33K 931 10% 1.33K 931 10%
1% 1% 1% 1% 1% 1% 1% 1%
1/16W 1/16W 2 16V
CERM 1/16W 1/16W 2 16V
CERM 1/16W 1/16W 2 16V
CERM 1/16W 1/16W 2 16V
CERM
MF-LF MF-LF 402 MF-LF MF-LF 402 MF-LF MF-LF 402 MF-LF MF-LF 402
402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2
FB_A2_VREF_UNTERM_L FB_A3_VREF_UNTERM_L
FB_A0_VREF_UNTERM_L FB_A1_VREF_UNTERM_L
FB_A_CLK0_TERM FB_A_CLK1_TERM
VOLTAGE=0.9V D 6 D 3 VOLTAGE=0.9V D 6 D 3
VRAM4 VRAM4 Q8400 Q8400 VRAM4 VRAM4 Q8450 Q8450
R8440 1
R8442 1
R8444 1
R8446 1 SSM6N15FEAPE SSM6N15FEAPE R8490 1
R8492 1
R8494 1
R8496 1 C8496 1 SSM6N15FEAPE SSM6N15FEAPE
1K 121 121 243 C8446 1 SOT563 SOT563
1K 121 121 243 0.01UF SOT563 SOT563
5% 1% 1% 1% 0.01UF 79 78 77 FB_VREF_UNTERM 5% 1% 1% 1% 10% 79 78 77 FB_VREF_UNTERM
1/16W 1/16W 1/16W 1/16W 10% IN
1/16W 1/16W 1/16W 1/16W 16V IN
MF-LF MF-LF MF-LF MF-LF 16V 80
CERM 2 80
402 2 402 2 402 2 402 2 CERM 2 2 G 5 G

MF-LF
402 2
MF-LF
402 2
MF-LF
402 2
MF-LF
402 2 402 2 G 5 G
402 S 1 S 4 S 1 S 4
VRAM4 VRAM4 VRAM4 VRAM4
1 1 1 1 1 1
R8443 R8445 R8447 R8493 R8495 R8497
121 121 243 OMIT 121 121 243 OMIT
1% 1% 1% 1% 1% 1%
1/16W 1/16W 1/16W CRITICAL 1/16W 1/16W 1/16W CRITICAL
MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF
2 402 2 402 2 402 2 402 2 402 2 402
98 77 76 IN FB_A_MA<0> K9 A0 U8400 DM0 E3 FB_A_DQM_L<1> IN 76 98 98 77 76 IN FB_A_MA<0> K9 A0 U8450 DM0 E3 FB_A_DQM_L<6> IN 76 98
98 77 76 IN FB_A_MA<1> H11 A1 BGA DM1 E10 FB_A_DQM_L<2> IN 76 98 98 77 76 IN FB_A_MA<1> H11 A1 BGA DM1 E10 FB_A_DQM_L<7> IN 76 98
98 76 IN FB_A_LMA<2> K10 A2 (1 OF 2) DM2 N10 FB_A_DQM_L<3> IN 76 98 98 76 IN FB_A_UMA<2> K10 A2 (1 OF 2) DM2 N10 FB_A_DQM_L<5> IN 76 98
32MX32-900MHZ-MFH
K4J10324QD-HC11
32MX32-900MHZ-MFH
K4J10324QD-HC11
98 76 IN FB_A_LMA<3> M9 A3 DM3 N3 FB_A_DQM_L<0> IN 76 98 98 76 IN FB_A_UMA<3> M9 A3 DM3 N3 FB_A_DQM_L<4> IN 76 98
MFHIGH
MFHIGH
98 76 IN FB_A_LMA<4> K4 A4 98 76 IN FB_A_UMA<4> K4 A4
DQ0 B2 FB_A_DQ<11> BI 76 98 DQ0 B2 FB_A_DQ<48> BI 76 98
98 76 IN FB_A_LMA<5> H2 A5 98 76 IN FB_A_UMA<5> H2 A5
DQ1 B3 FB_A_DQ<14> 76 98 DQ1 B3 FB_A_DQ<51> 76 98
B 98 77 76
98 77 76
IN
IN
FB_A_MA<6>
FB_A_MA<7>
K3
L4
A6
A7
DQ2 C2 FB_A_DQ<15>
BI
BI 76 98
98 77 76
98 77 76
IN
IN
FB_A_MA<6>
FB_A_MA<7>
K3
L4
A6
A7
DQ2 C2 FB_A_DQ<55>
BI
BI 76 98 B
DQ3 C3 FB_A_DQ<13> BI 76 98 DQ3 C3 FB_A_DQ<54> BI 76 98
98 77 76 IN FB_A_MA<8> K2 A8/AP 98 77 76 IN FB_A_MA<8> K2 A8/AP
DQ4 E2 FB_A_DQ<10> BI 76 98 DQ4 E2 FB_A_DQ<52> BI 76 98
98 77 76 IN FB_A_MA<9> M4 A9 98 77 76 IN FB_A_MA<9> M4 A9
DQ5 F3 FB_A_DQ<12> BI 76 98 DQ5 F3 FB_A_DQ<50> BI 76 98
98 77 76 IN FB_A_MA<10> K11 A10 98 77 76 IN FB_A_MA<10> K11 A10
DQ6 F2 FB_A_DQ<8> BI 76 98 DQ6 F2 FB_A_DQ<53> BI 76 98
98 77 76 IN FB_A_MA<11> L9 A11 98 77 76 IN FB_A_MA<11> L9 A11
DQ7 G3 FB_A_DQ<9> BI 76 98 DQ7 G3 FB_A_DQ<49> BI 76 98
98 76 IN FB_A_LCKE H9 CKE 98 76 IN FB_A_UCKE H9 CKE
98 77 76 IN FB_A_MA<12> J3 A12/CS1* 98 77 76 IN FB_A_MA<12> J3 A12/CS1*
98 76 IN FB_A_CLK_P<0> J11 CK DQ10 C11 FB_A_DQ<19> BI 76 98 98 76 IN FB_A_CLK_P<1> J11 CK DQ10 C11 FB_A_DQ<63> BI 76 98
98 76 IN FB_A_CLK_N<0> J10 CK* DQ11 C10 FB_A_DQ<22> BI 76 98 98 76 IN FB_A_CLK_N<1> J10 CK* DQ11 C10 FB_A_DQ<60> BI 76 98
98 76 IN FB_A_LCS0_L F4 CS0* DQ12 E11 FB_A_DQ<18> BI 76 98 76 IN FB_A_UCS0_L F4 CS0* DQ12 E11 FB_A_DQ<58> BI 76 98
MFHIGH
MFHIGH
98 77 76 IN FB_A_WE_L H4 WE* DQ13 F10 FB_A_DQ<20> BI 76 98 98 77 76 IN FB_A_WE_L H4 WE* DQ13 F10 FB_A_DQ<56> BI 76 98
98 76 IN FB_A_LCAS_L F9 CAS* DQ14 F11 FB_A_DQ<23> BI 76 98 98 76 IN FB_A_UCAS_L F9 CAS* DQ14 F11 FB_A_DQ<59> BI 76 98
98 77 76 IN FB_A_RAS_L H10 RAS* DQ15 G10 FB_A_DQ<21> BI 76 98 98 77 76 IN FB_A_RAS_L H10 RAS* DQ15 G10 FB_A_DQ<61> BI 76 98
FB_A0_ZQ A4 ZQ DQ16 M11 FB_A_DQ<26> BI 76 98 FB_A1_ZQ A4 ZQ DQ16 M11 FB_A_DQ<46> BI 76 98
FB_A0_MF A9 MF DQ17 L10 FB_A_DQ<24> BI 76 98 FB_A1_MF A9 MF DQ17 L10 FB_A_DQ<47> BI 76 98
FB_A0_SEN V4 SEN DQ18 N11 FB_A_DQ<28> BI 76 98 FB_A1_SEN V4 SEN DQ18 N11 FB_A_DQ<44> BI 76 98
98 77 76 IN FB_A_DRAM_RST V9 RESET DQ19 M10 FB_A_DQ<25> BI 76 98 98 77 76 IN FB_A_DRAM_RST V9 RESET DQ19 M10 FB_A_DQ<41> BI 76 98
DQ20 R11 FB_A_DQ<29> BI 76 98 DQ20 R11 FB_A_DQ<45> BI 76 98

98 76 OUT FB_A_RDQS<1> D3 RDQS0 98 76 OUT FB_A_RDQS<6> D3 RDQS0
DQ21 R10 FB_A_DQ<27> BI 76 98 DQ21 R10 FB_A_DQ<42> BI 76 98
98 76 OUT FB_A_RDQS<2> D10 RDQS1 98 76 OUT FB_A_RDQS<7> D10 RDQS1
DQ22 T11 FB_A_DQ<30> BI 76 98 DQ22 T11 FB_A_DQ<43> BI 76 98
98 76 OUT FB_A_RDQS<3> P10 RDQS2 98 76 OUT FB_A_RDQS<5> P10 RDQS2
DQ23 T10 FB_A_DQ<31> BI 76 98 DQ23 T10 FB_A_DQ<40> BI 76 98
98 76 OUT FB_A_RDQS<0> P3 RDQS3 98 76 OUT FB_A_RDQS<4> P3 RDQS3
DQ24 M2 FB_A_DQ<2> BI 76 98 DQ24 M2 FB_A_DQ<35> BI 76 98
98 76 IN FB_A_WDQS<1> D2 WDQS0 DQ25 L3 FB_A_DQ<3> BI 76 98 98 76 IN FB_A_WDQS<6> D2 WDQS0 DQ25 L3 FB_A_DQ<34> BI 76 98
98 76 IN FB_A_WDQS<2> D11 WDQS1 DQ26 N2 FB_A_DQ<0> BI 76 98 98 76 IN FB_A_WDQS<7> D11 WDQS1 DQ26 N2 FB_A_DQ<33> BI 76 98
FB_A_WDQS<3> P11 M3 FB_A_DQ<4> FB_A_WDQS<5> P11 M3 FB_A_DQ<32>

A 98 76
98 76
IN
IN FB_A_WDQS<0> P2
WDQS2
WDQS3
DQ27
DQ28 R2 FB_A_DQ<1>
BI
BI
76 98
76 98
98 76
98 76
IN
IN FB_A_WDQS<4> P2
WDQS2
WDQS3
DQ27
DQ28 R2 FB_A_DQ<39>
BI
BI
76 98
76
98
DQ29 R3 FB_A_DQ<5> BI 76 98 DQ29 R3 FB_A_DQ<36> BI
PAGE TITLE
FB_A_BA<0> FB_A_BA<0>
G9 BA0 G9 BA0
GDDR3 Frame Buffer A (Top)
MFHIGH
MFHIGH
98 77 76 IN 98 77 76 IN
DQ30 T2 FB_A_DQ<6> BI 76 98 DQ30 T2 FB_A_DQ<38> BI
98 77 76 IN FB_A_BA<1> G4 BA1 98 77 76 IN FB_A_BA<1> G4 BA1
DQ31 T3 FB_A_DQ<7> BI 76 98 DQ31 T3 FB_A_DQ<37> BI 76 DRAWING NUMBER SIZE
FB_A_BA<2> H3 BA2 FB_A_BA<2> H3 BA2 98
98 77 76 IN 98 77 76 IN
J2 RFU J2 RFU REVISION
NC NC R
<E4LABEL>
R84481 1
R8449 1 1 NOTICE OF PROPRIETARY PROPERTY: BRANCH
243 100 R8498 R8499
1%
1/16W
5%
1/16W 243 100
<BRANCH>
MF-LF MF-LF 1% 5% THE POSESSOR AGREES TO THE FOLLOWING: PAGE
402 2 2 402 1/16W 1/16W
MF-LF
402 2
MF-LF I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 84 OF 132
2 402 II NOT TO REPRODUCE OR COPY IT
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT OMIT
Page Notes
PP1V8R1V55_S0GPU_ISNS CRITICAL PP1V8R1V55_S0GPU_ISNS CRITICAL
76 75 56 50 8 7 6 78 77 76 75 56 50 8 7 6 Power aliases required by this page:
78 77
A2 VDD0 VSS0 A3 A2 VDD0 VSS0 A3 - =PP1V8_S0_FB_VDD
A11 VDD1
U8500 VSS1 A10 A11 VDD1
U8550 VSS1 A10 - =PP1V8_S0_FB_VREF_B
BGA BGA
C8500 1 1 C8501 1 C8502 1 C8503 1 C8504 F1 VDD2 (2 OF 2) VSS2 G1 C8550 1 1 C8551 1 C8552 1 C8553 1 C8554 F1 VDD2 (2 OF 2) VSS2 G1
10UF 0.1uF 0.1uF 0.1uF 0.1uF 10UF 0.1uF 0.1uF 0.1uF 0.1uF Signal aliases required by this page:
K4J10324QD-HC11
K4J10324QD-HC11
F12 G12 F12 G12
32MX32-900MHZ-MFH
32MX32-900MHZ-MFH
20% 10% 10% 10% 10% VDD3 VSS3 20% 10% 10% 10% 10% VDD3 VSS3
6.3V 2 (NONE)
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R
M1 VDD4 VSS4 L1 6.3V 2
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R
M1 VDD4 VSS4 L1
603 402 402 402 402 M12 VDD5 VSS5 L12 603 402 402 402 402 M12 VDD5 VSS5 L12 BOM options provided by this page:
V2 VDD6 VSS6 V3 V2 VDD6 VSS6 V3 VRAM4
V11 VDD7 VSS7 V10 V11 VDD7 VSS7 V10
D
K1 VDDA0
K12 VDDA1
VSSA0 J1
VSSA1 J12
K1 VDDA0
K12 VDDA1
VSSA0 J1
VSSA1 J12
D
A1 VDDQ0 VSSQ0 B1 A1 VDDQ0 VSSQ0 B1
1 C8510 1 C8515 A12 VDDQ1 VSSQ1 B4
1 C8560 1 C8565 A12 VDDQ1 VSSQ1 B4
0.1uF 0.1uF 0.1uF 0.1uF
10% 10% C1 VDDQ2 VSSQ2 B9 10% 10% C1 VDDQ2 VSSQ2 B9
2 16V
X5R 2 16V
X5R B12 2 16V
X5R 2 16V
X5R B12
402 402 C4 VDDQ3 VSSQ3 402 402 C4 VDDQ3 VSSQ3
U8500.J1 U8500.J12 C9 VDDQ4 VSSQ4 D1 U8500.J1 U8500.J12 C9 VDDQ4 VSSQ4 D1
Connect to designated pin, then GND Connect to designated pin, then GND
C12 VDDQ5 VSSQ5 D4 C12 VDDQ5 VSSQ5 D4
E1 VDDQ6 VSSQ6 D9 E1 VDDQ6 VSSQ6 D9
76 75 56 50 8 7 6 PP1V8R1V55_S0GPU_ISNS D12 78 77 76 75 56 50 8 7 6 PP1V8R1V55_S0GPU_ISNS D12
78 77 E4 VDDQ7 VSSQ7 E4 VDDQ7 VSSQ7
C8520 1 1 C8521 1 C8522 1 C8523 1 C8524 1 C8525 1 C8526 J4 VDDQ10 VSSQ10 L2 C8570 1 1 C8571 1 C8572 1 C8573 1 C8574 1 C8575 1 C8576 J4 VDDQ10 VSSQ10 L2
10UF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 10UF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
20% 10% 10% 10% 10% 10% 10% J9 VDDQ11 VSSQ11 L11 20% 10% 10% 10% 10% 10% 10% J9 VDDQ11 VSSQ11 L11
6.3V 2 2 16V 2 16V 2 16V 2 16V 2 16V 2 16V 6.3V 2 2 16V 2 16V 2 16V 2 16V 2 16V 2 16V
X5R X5R X5R X5R X5R X5R X5R N1 VDDQ12 VSSQ12 P1 X5R X5R X5R X5R X5R X5R X5R N1 VDDQ12 VSSQ12 P1
603 402 402 402 402 402 402 603 402 402 402 402 402 402
78 32 8 GPU_FB_B_VREF_DIV N12 VDDQ15 VSSQ15 P12 78 32 8 GPU_FB_B_VREF_DIV N12 VDDQ15 VSSQ15 P12
R1 VDDQ16 VSSQ16 T1 R1 VDDQ16 VSSQ16 T1
1
R8530 R4 VDDQ17 VSSQ17 T4 R85801 R4 VDDQ17 VSSQ17 T4
549
1% R85331 R9 VDDQ18 VSSQ18 T9 549
1% R85831 R9 VDDQ18 VSSQ18 T9
1/16W 549 R12 VDDQ19 VSSQ19 T12 1/16W 549 R12 VDDQ19 VSSQ19 T12
MF-LF 1% MF-LF 1%
402 2 1/16W V1 VDDQ20 402 2 1/16W V1 VDDQ20
MF-LF V12 MF-LF V12
402 2 VDDQ21 402 2 VDDQ21
FB_B0_VREF H1 VREF0 FB_B1_VREF H1 VREF0

FB_B2_VREF H12 VREF1 FB_B3_VREF H12 VREF1
C C8531 R85341 C8532 C8581 R85841 C8582
C
R85311 R85321 1
0.01uF
R85351 1
0.01uF
R85811 R85821 1
0.01uF
R85851 1
0.01uF
1.33K 931 10% 1.33K 931 10% 1.33K 931 10% 1.33K 931 10%
1% 1% 1% 1% 1% 1% 1% 1%
1/16W 1/16W 2 16V
CERM 1/16W 1/16W 2 16V
CERM 1/16W 1/16W 2 16V
CERM 1/16W 1/16W 2 16V
CERM
MF-LF MF-LF 402 MF-LF MF-LF 402 MF-LF MF-LF 402 MF-LF MF-LF 402
402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2
FB_B2_VREF_UNTERM_L FB_B3_VREF_UNTERM_L
FB_B0_VREF_UNTERM_L FB_B1_VREF_UNTERM_L
FB_B_CLK0_TERM FB_B_CLK1_TERM
VOLTAGE=0.9V D 6 D 3 VOLTAGE=0.9V D 6 D 3
VRAM4 VRAM4 Q8500 Q8500 VRAM4 VRAM4 Q8550 Q8550
R8540 1
R8542 1
R8544 1
R8546 1 C8546 1 SSM6N15FEAPE SSM6N15FEAPE R8590 1
R8592 1
R8594 1
R8596 1 C8596 1 SSM6N15FEAPE SSM6N15FEAPE
SOT563 SOT563 SOT563 SOT563
1K 121 121 243 0.01UF 1K 121 121 243 0.01UF
5% 1% 1% 1% 10% 79 78 77 FB_VREF_UNTERM 5% 1% 1% 1% 10% 79 78 77 FB_VREF_UNTERM
1/16W 1/16W 1/16W 1/16W 16V IN 16V IN
MF-LF MF-LF MF-LF MF-LF CERM 2 80 1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF CERM 2 80
402 2 402 2 402 2 402 2 402 2 G 5 G 402 2 402 2 402 2 402 2 402 2 G 5 G
S 1 S 4 S 1 S 4
VRAM4 VRAM4 VRAM4 VRAM4
1 1 1 1 1 1
R8543 R8545 R8547 R8593 R8595 R8597
121 121 243 OMIT 121 121 243 OMIT
1% 1% 1% 1% 1% 1%
1/16W 1/16W 1/16W CRITICAL 1/16W 1/16W 1/16W CRITICAL
MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF
2 402 2 402 2 402 2 402 2 402 2 402
98 78 76 IN FB_B_MA<0> K9 A0 U8500 DM0 E3 FB_B_DQM_L<1> IN 76 98 98 78 76 IN FB_B_MA<0> K9 A0 U8550 DM0 E3 FB_B_DQM_L<5> IN 76 98
98 78 76 IN FB_B_MA<1> H11 A1 BGA DM1 E10 FB_B_DQM_L<2> IN 76 98 98 78 76 IN FB_B_MA<1> H11 A1 BGA DM1 E10 FB_B_DQM_L<7> IN 76 98
98 76 IN FB_B_LMA<2> K10 A2 (1 OF 2) DM2 N10 FB_B_DQM_L<3> IN 76 98 98 76 IN FB_B_UMA<2> K10 A2 (1 OF 2) DM2 N10 FB_B_DQM_L<4> IN 76 98
32MX32-900MHZ-MFH
K4J10324QD-HC11
32MX32-900MHZ-MFH
K4J10324QD-HC11
98 76 IN FB_B_LMA<3> M9 A3 DM3 N3 FB_B_DQM_L<0> IN 76 98 98 76 IN FB_B_UMA<3> M9 A3 DM3 N3 FB_B_DQM_L<6> IN 76 98
MFHIGH
MFHIGH
98 76 IN FB_B_LMA<4> K4 A4 98 76 IN FB_B_UMA<4> K4 A4
DQ0 B2 FB_B_DQ<15> BI 76 98 DQ0 B2 FB_B_DQ<45> BI 76 98
98 76 IN FB_B_LMA<5> H2 A5 98 76 IN FB_B_UMA<5> H2 A5
DQ1 B3 FB_B_DQ<9> 76 98 DQ1 B3 FB_B_DQ<46> 76 98
B 98 78 76
98 78 76
IN
IN
FB_B_MA<6>
FB_B_MA<7>
K3
L4
A6
A7
DQ2 C2 FB_B_DQ<14>
BI
BI 76 98
98 78 76
98 78 76
IN
IN
FB_B_MA<6>
FB_B_MA<7>
K3
L4
A6
A7
DQ2 C2 FB_B_DQ<47>
BI
BI 76 98 B
DQ3 C3 FB_B_DQ<11> BI 76 98 DQ3 C3 FB_B_DQ<43> BI 76 98
98 78 76 IN FB_B_MA<8> K2 A8/AP 98 78 76 IN FB_B_MA<8> K2 A8/AP
DQ4 E2 FB_B_DQ<13> BI 76 98 DQ4 E2 FB_B_DQ<42> BI 76 98
98 78 76 IN FB_B_MA<9> M4 A9 98 78 76 IN FB_B_MA<9> M4 A9
DQ5 F3 FB_B_DQ<12> BI 76 98 DQ5 F3 FB_B_DQ<40> BI 76 98
98 78 76 IN FB_B_MA<10> K11 A10 98 78 76 IN FB_B_MA<10> K11 A10
DQ6 F2 FB_B_DQ<10> BI 76 98 DQ6 F2 FB_B_DQ<41> BI 76 98
98 78 76 IN FB_B_MA<11> L9 A11 98 78 76 IN FB_B_MA<11> L9 A11
DQ7 G3 FB_B_DQ<8> BI 76 98 DQ7 G3 FB_B_DQ<44> BI 76 98
98 76 IN FB_B_LCKE H9 CKE 98 76 IN FB_B_UCKE H9 CKE
98 78 76 IN FB_B_MA<12> J3 A12/CS1* 98 78 76 IN FB_B_MA<12> J3 A12/CS1*
98 76 IN FB_B_CLK_P<0> J11 CK DQ10 C11 FB_B_DQ<21> BI 76 98 98 76 IN FB_B_CLK_P<1> J11 CK DQ10 C11 FB_B_DQ<60> BI 76 98
98 76 IN FB_B_CLK_N<0> J10 CK* DQ11 C10 FB_B_DQ<17> BI 76 98 98 76 IN FB_B_CLK_N<1> J10 CK* DQ11 C10 FB_B_DQ<61> BI 76 98
98 76 IN FB_B_LCS0_L F4 CS0* DQ12 E11 FB_B_DQ<22> BI 76 98 76 IN FB_B_UCS0_L F4 CS0* DQ12 E11 FB_B_DQ<62> BI 76 98
MFHIGH
MFHIGH
98 78 76 IN FB_B_WE_L H4 WE* DQ13 F10 FB_B_DQ<18> BI 76 98 98 78 76 IN FB_B_WE_L H4 WE* DQ13 F10 FB_B_DQ<57> BI 76 98
98 76 IN FB_B_LCAS_L F9 CAS* DQ14 F11 FB_B_DQ<23> BI 76 98 98 76 IN FB_B_UCAS_L F9 CAS* DQ14 F11 FB_B_DQ<63> BI 76 98
98 78 76 IN FB_B_RAS_L H10 RAS* DQ15 G10 FB_B_DQ<20> BI 76 98 98 78 76 IN FB_B_RAS_L H10 RAS* DQ15 G10 FB_B_DQ<58> BI 76 98
FB_B0_ZQ A4 ZQ DQ16 M11 FB_B_DQ<29> BI 76 98 FB_B1_ZQ A4 ZQ DQ16 M11 FB_B_DQ<36> BI 76 98
FB_B0_MF A9 MF DQ17 L10 FB_B_DQ<27> BI 76 98 FB_B1_MF A9 MF DQ17 L10 FB_B_DQ<38> BI 76 98
FB_B0_SEN V4 SEN DQ18 N11 FB_B_DQ<24> BI 76 98 FB_B1_SEN V4 SEN DQ18 N11 FB_B_DQ<37> BI 76 98
98 78 76 IN FB_B_DRAM_RST V9 RESET DQ19 M10 FB_B_DQ<25> BI 76 98 98 78 76 IN FB_B_DRAM_RST V9 RESET DQ19 M10 FB_B_DQ<39> BI 76 98
DQ20 R11 FB_B_DQ<30> BI 76 98 DQ20 R11 FB_B_DQ<35> BI 76 98

98 76 OUT FB_B_RDQS<1> D3 RDQS0 98 76 OUT FB_B_RDQS<5> D3 RDQS0
DQ21 R10 FB_B_DQ<28> BI 76 98 DQ21 R10 FB_B_DQ<34> BI 76 98
98 76 OUT FB_B_RDQS<2> D10 RDQS1 98 76 OUT FB_B_RDQS<7> D10 RDQS1
DQ22 T11 FB_B_DQ<31> BI 76 98 DQ22 T11 FB_B_DQ<32> BI 76 98
98 76 OUT FB_B_RDQS<3> P10 RDQS2 98 76 OUT FB_B_RDQS<4> P10 RDQS2
DQ23 T10 FB_B_DQ<26> BI 76 98 DQ23 T10 FB_B_DQ<33> BI 76 98
98 76 OUT FB_B_RDQS<0> P3 RDQS3 98 76 OUT FB_B_RDQS<6> P3 RDQS3
DQ24 M2 FB_B_DQ<4> BI 76 98 DQ24 M2 FB_B_DQ<48> BI 76 98
98 76 IN FB_B_WDQS<1> D2 WDQS0 DQ25 L3 FB_B_DQ<3> BI 76 98 98 76 IN FB_B_WDQS<5> D2 WDQS0 DQ25 L3 FB_B_DQ<50> BI 76 98
98 76 IN FB_B_WDQS<2> D11 WDQS1 DQ26 N2 FB_B_DQ<0> BI 76 98 98 76 IN FB_B_WDQS<7> D11 WDQS1 DQ26 N2 FB_B_DQ<54> BI 76 98
FB_B_WDQS<3> P11 M3 FB_B_DQ<2> FB_B_WDQS<4> P11 M3 FB_B_DQ<49>

A 98 76
98 76
IN
IN FB_B_WDQS<0> P2
WDQS2
WDQS3
DQ27
DQ28 R2 FB_B_DQ<1>
BI
BI
76 98
76 98
98 76
98 76
IN
IN FB_B_WDQS<6> P2
WDQS2
WDQS3
DQ27
DQ28 R2 FB_B_DQ<51>
BI
BI
76 98
76 98 SYNC_MASTER=K17_REF SYNC_DATE=06/15/2009 A
DQ29 R3 FB_B_DQ<6> BI 76 98 DQ29 R3 FB_B_DQ<55> BI
PAGE TITLE
FB_B_BA<0> FB_B_BA<0>
G9 BA0 G9 BA0
GDDR3 Frame Buffer B (Top)
MFHIGH
MFHIGH
98 78 76 IN 98 78 76 IN
DQ30 T2 FB_B_DQ<7> BI 76 98 DQ30 T2 FB_B_DQ<52> BI
98 78 76 IN FB_B_BA<1> G4 BA1 98 78 76 IN FB_B_BA<1> G4 BA1
DQ31 T3 FB_B_DQ<5> BI 76 98 DQ31 T3 FB_B_DQ<53> BI 76 98 DRAWING NUMBER SIZE
FB_B_BA<2> H3 BA2 FB_B_BA<2> H3 BA2
98 78 76 IN 98 78 76 IN
J2 RFU J2 RFU REVISION
NC NC R
R85981 1
R8599 <E4LABEL>
R85481 1
R8549 243 100 NOTICE OF PROPRIETARY PROPERTY: BRANCH
243 100 1% 5%
1%
1/16W
5%
1/16W
1/16W
MF-LF
1/16W
MF-LF
<BRANCH>
MF-LF MF-LF 402 2 2 402 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
402 2 2 402 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
85 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes 110mA OMIT
- =PP3V3_GPU_VDD33 U8000
- =PP3V3_GPI_MIO
NV-GT216
BGA
- =PP1V2_GPU_PLLVDD (6 OF 9)
- =PP1V2_GPU_H_PLLVDD 84 82 81 80 79 74 72 7 6 PP3V3_S0GPU J9 GPIO0 K1 GPU_VCORE_VID3 BI 80 82
- =PP1V2_GPU_VID_PLLVDD J10 GPIO1 K2 DP_EG_HPD BI 80 84
J11 GPIO2 K3 GPU_VCORE_VID4

Signal aliases required by this page: 1 C8694 1 C8696 1 C8698 J12
VDD33
GPIO3 H3 EG_LCD_PWR_EN
BI 80 82
(NONE) 0.1UF 1UF 4.7UF BI 80 87

20% 10% 20% J13 GPIO4 H2 EG_BKLT_EN 80 87
2 10V
CERM 2 6.3V
X5R
6.3V
2 X5R-CERM1
BI
BOM options provided by this page: GPIO5 H1 GPU_VCORE_VID0 80 82
D (NONE)
402 402 402
GPIO6 H4 GPU_VCORE_VID1
BI
BI 80 82 D
GPIO7 H5 GPU_VCORE_VID2 BI 80 82
GPIO8 H6 SMC_GFX_OVERTEMP_R_L
BI 80
GPIO9 J7 TP_GPU_GSTATE<0> BI 6 80
GPIO10 K4 FB_VREF_UNTERM BI 77 78 80
GPIO11 K5 GPU_GPIO_11 BI 80
GPIO12 H7 SMC_GFX_THROTTLE_R_L
BI 80
GPIO13 J4 FBVDD_ALTVO BI 80 86
GPIO14 J6 NC_GPU_GPIO_14 BI 80
GPIO15 L1 NC_GPU_GPIO_15 BI 80
80 NC_GPU_ROM_CS_L C3 ROM_CS* GPIO16 L2 GPU_GPIO_16 BI 80
80 GPU_ROM_SCLK D4 ROM_SCLK GPIO17 L4 NC_GPU_GPIO_17 BI 80
80 GPU_ROM_SI D3 ROM_SI GPIO18 M4 NC_GPU_GPIO_18 BI 80
80 GPU_ROM_SO C4 ROM_SO GPIO19 L7 NC_GPU_GPIO_19 BI 80
GPIO20 L5 NC_GPU_GPIO_20 BI 80
1 1 NC_GPU_GPIO_21
R8696 R8697 GPIO21 K6 BI 80
40.2K 40.2K GPIO22 L6 NC_GPU_GPIO_22 BI 80

1% 1%
1/16W 1/16W GPIO23 M6 NC_GPU_GPIO_23 BI 80
MF-LF MF-LF
2 402 2 402 GPU_STRAP_REF_3V3_PDN9 MULTI_STRAP_REF0_GND
GPU_STRAP_REF_MIOB_PD
M9 MULTI_STRAP_REF1_GND
84 82 81 80 79 74 72 7 6 PP3V3_S0GPU
P9 MIOA_VDDQ_1
84 82 81 80 79 74 72 7 6 PP3V3_S0GPU
R9 MIOA_VDDQ_2
C8610 1 C8611 1 T9 MIOA_VDDQ_3
1UF 1UF U9 MIOA_VDDQ_4
R86201 1
R8621 10%
6.3V 2
10%
6.3V 2
C 49.9
1%
1/16W
49.9
1%
1/16W
CERM
402
CERM
402 AA9 MIOB_VDDQ_1
C
MF-LF MF-LF AB9 MIOB_VDDQ_2
402 2 2 402 R86161 1
R8618 W9 MIOB_VDDQ_3 JTAG_TCK AP14 TP_GPU_JTAG_TCK IN 80
10K 10K
GPU_MIOA_PD_VDDQ 79 5% 5% Y9 MIOB_VDDQ_4 JTAG_TDI AN14 TP_GPU_JTAG_TDI IN 80
1/16W 1/16W
GPU_MIOB_PD_VDDQ 79 MF-LF MF-LF JTAG_TDO AN16 TP_GPU_JTAG_TDO OUT 80
402 2 2 402 GPU_TESTMODE_PD AP35 TESTMODE
JTAG_TMS AR14 TP_GPU_JTAG_TMS IN 80
GPU_MIOA_PU_GND 79
GPU_MIOA_VREF N5 MIOA_VREF JTAG_TRST* AP16 TP_GPU_JTAG_TRST_L IN 80
GPU_MIOB_PU_GND 79
GPU_MIOB_VREF AF1 MIOB_VREF
MIOA_CLKIN N4 NC_GPU_MIOA_CLKIN IN 80
R86221 1
R8623 R86171 1
1
C8617 R8619 1 GPU_MIOA_PD_VDDQ MIOA_CLKOUT R4 NC_GPU_MIOA_CLKOUT_P
BI 80
49.9
1%
49.9
1%
10K
5% 0.1uF 10K
5%
1 C8619 R8660
10K
79
GPU_MIOA_PU_GND
U5
T5
MIOA_CAL_PD_VDDQ
MIOA_CAL_PU_GND
MIOA_CLKOUT* T4 NC_GPU_MIOA_CLKOUT_N
BI 80
1/16W 1/16W 1/16W 10% 1/16W 0.1uF 5%

79
MIOA_CTL3 P5 NC_GPU_MIOA_CTL3
2 16V
BI 80
MF-LF MF-LF MF-LF MF-LF 10% 1/16W
402 2 X5R 2 16V N2 TP_GPU_MIOA_DE
2 402 402 2 402 2 402 X5R MF-LF
GPU_MIOB_PD_VDDQ AA7 MIOB_CAL_PD_VDDQ
MIOA_DE BI 6 80
402 2 402 79
MIOA_D0 N1 TP_GPU_MIOA_D<0> 6 80
GPU_MIOB_PU_GND BI
79 AA6 MIOB_CAL_PU_GND
MIOA_D1 P4 TP_GPU_MIOA_D<1> BI 6 80
AF9 SP_PLLVDD MIOA_D5 T3 TP_GPU_MIOA_D<5> BI 6 80
65mA MIOA_D6 T2 TP_GPU_MIOA_D<6> BI 6 80

AE9 PLLVDD
MIOA_D7 T1 TP_GPU_MIOA_D<7> BI 6 80
AD9 VID_PLLVDD MIOA_D8 U4 TP_GPU_MIOA_D<8> BI 6 80
MIOA_D9 U1 TP_GPU_MIOA_D<9> BI 6 80
MIOA_D10 U2 GPU_MIOA_D<10> BI 80
MIOA_D11 U3 GPU_MIOA_D<11> BI 80
MIOA_D12 R6 GPU_MIOA_D<12> BI 80
B MIOA_D13
MIOA_D14
T6
N6
GPU_MIOA_D<13>
GPU_MIOA_D<14>
BI 80
B
L8635 MIOA_HSYNC N3
BI
NC_GPU_MIOA_HSYNC BI
80
86 81 79 76 74 7 6 PP1V05_S0GPU 100NH-700MA-0.14OHM 98 80 27 GPU_CLK27M B1 XTAL_IN

80
IN NC_GPU_MIOA_VSYNC BI
25mA MIOA_VSYNC L3 80
1 2 PP1V1_GPU_H_PLLVDD_F 8 OUT NC_GPU_XTALOUT B2 XTAL_OUT
0603 MIN_NECK_WIDTH=0.2 mm MIOB_CLKIN AE1 NC_GPU_MIOB_CLKIN IN 80
VOLTAGE=1.2V
C8637 1 C8635 1 1 C8636 MIOB_CLKOUT V4 NC_GPU_MIOB_CLKOUT_P
BI 80
4.7UF 4.7UF 1UF 80 OUT GPU_XTALOUTBUFF D1 XTAL_OUTBUFF MIOB_CLKOUT* W4 NC_GPU_MIOB_CLKOUT_N
BI 80
20% 20% 10%
6.3V 2 6.3V 2 6.3V
2 X5R MIOB_CTL3 W3 NC_GPU_MIOB_CTL3 80
CERM CERM GPU_CLK27M_SS BI
603 603 402 98 80 IN D2 XTAL_SSIN
MIOB_DE Y5 NC_GPU_MIOB_DE BI 80
MIOB_D0 Y1 NC_GPU_MIOB_D<0> BI 80
L8640 MIOB_D1 Y2 NC_GPU_MIOB_D<1> BI 80
86 81 79 76 74 7 6 PP1V05_S0GPU 100NH-700MA-0.14OHM MIOB_D2 Y3 NC_GPU_MIOB_D<2> 80

BI
50mA
1 2 PP1V1_GPU_VID_PLLVDD_F MIOB_D3 AB3 NC_GPU_MIOB_D<3> BI 80
0603 MIN_NECK_WIDTH=0.2 mm MIOB_D4 AB2 NC_GPU_MIOB_D<4> BI 80
VOLTAGE=1.2V
C8643 1 C8640 1 1 C8641 1 C8631 MIOB_D5 AB1 NC_GPU_MIOB_D<5> BI 80
4.7UF 4.7UF 1UF 0.1uF MIOB_D6 AC4 NC_GPU_MIOB_D<6> BI 80
20% 20% 10% 10%
6.3V 2 6.3V 2 6.3V
2 X5R 2 16V MIOB_D7 AC1 NC_GPU_MIOB_D<7>
CERM CERM X5R BI 80
603 603 402 402 MIOB_D8 AC2 NC_GPU_MIOB_D<8> 80
BI
MIOB_D9 AC3 NC_GPU_MIOB_D<9> BI 80
MIOB_D10 AE3 NC_GPU_MIOB_D<10> BI 80
MIOB_D11 AE2 NC_GPU_MIOB_D<11> BI 80
MIOB_D12 U6 NC_GPU_MIOB_D<12> BI 80
MIOB_D13 W6 NC_GPU_MIOB_D<13> BI 80
MIOB_D14 Y6 NC_GPU_MIOB_D<14> BI 80
80 BI GPU_STRAP<0> W5 STRAP0
GPU_STRAP<1> W7
A 80
80
BI
BI GPU_STRAP<2> V7
STRAP1
STRAP2 SYNC_MASTER=K17_REF SYNC_DATE=06/15/2009 A
MIOB_HSYNC W1 NC_GPU_MIOB_HSYNC BI 80
PAGE TITLE
MIOB_VSYNC W2 NC_GPU_MIOB_VSYNC BI 80 NV GT216 GPIO/MIO/MISC

DRAWING NUMBER SIZE
THERMDP B5 GPU_TDIODE_P
THERMDN B4 GPU_TDIODE_N
IN 51 80 99
51 80 99 Apple Inc. <SCH_NUM> D

OUT
REVISION
R
<E4LABEL>
<BRANCH>
86 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Renamed signals Unused signals
Native Func Native Func 80 79 TP_GPU_JTAG_TCK TP_GPU_JTAG_TCK 79 80
GPIOs GPIOs MAKE_BASE=TRUE
GP HPDE 80 79 TP_GPU_JTAG_TDI TP_GPU_JTAG_TDI 79 80
82
79 GPU_VCORE_VID3 GPU_VCORE_VID3 79 80 82 80 79 NC_GPU_GPIO_15 NC_GPU_GPIO_15 79 80 98 80 79 27 GPU_CLK27M GPU_CLK27M 27 79 80 98 MAKE_BASE=TRUE
80 MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
HPDC DVI_MODE0 80 79 TP_GPU_JTAG_TDO TP_GPU_JTAG_TDO 79 80
84
79 DP_EG_HPD DP_EG_HPD IN 79 80 84 79 GPU_GPIO_16 EG_DP_CA_DET 80 98 80 79 GPU_CLK27M_SS GPU_CLK27M_SS 79 80 98 MAKE_BASE=TRUE
80 MAKE_BASE=TRUE MAKE_BASE=TRUE
LCD0_BL_PWM HDMI_DETECT0 80 79 TP_GPU_JTAG_TMS TP_GPU_JTAG_TMS 79 80
82
79 GPU_VCORE_VID4 GPU_VCORE_VID4 79 80 82 80 79 NC_GPU_GPIO_17 NC_GPU_GPIO_17 79 80 99 80 79 51 GPU_TDIODE_P GPU_TDIODE_P 51 79 80 99 MAKE_BASE=TRUE
LCD0_VDD DVI_MODE1 80 79 TP_GPU_JTAG_TRST_L TP_GPU_JTAG_TRST_L 79 80
87
79 EG_LCD_PWR_EN EG_LCD_PWR_EN 79 80 87 80 79 NC_GPU_GPIO_18 NC_GPU_GPIO_18 79 80 99 80 79 51 GPU_TDIODE_N GPU_TDIODE_N 51 79 80 99 MAKE_BASE=TRUE
LCD0_BL_EN HDMI_DETECT1
87
79 EG_BKLT_EN EG_BKLT_EN 79 80 87 80 79 NC_GPU_GPIO_19 NC_GPU_GPIO_19 79 80
80 MAKE_BASE=TRUE MAKE_BASE=TRUE
VID0 HPDD
82
79 GPU_VCORE_VID0 GPU_VCORE_VID0 79 80 82 80 79 NC_GPU_GPIO_20 NC_GPU_GPIO_20 79 80 84 81 80 LVDS_EG_DDC_CLK LVDS_EG_DDC_CLK 80 81 84 NC_FBA_MA<13> NC_FBA_MA<13> 76 80
D
80
82
79 GPU_VCORE_VID1 VID1
MAKE_BASE=TRUE
GPU_VCORE_VID1 79 80 82 80 79 NC_GPU_GPIO_21 HPDF
MAKE_BASE=TRUE
NC_GPU_GPIO_21 79 80 84 81 80
MAKE_BASE=TRUE
LVDS_EG_DDC_DATA LVDS_EG_DDC_DATA 80 81 84
MAKE_BASE=TRUE
NC_FBB_MA<13>
NO_TEST=TRUE
NC_FBB_MA<13> 76 80
D
80 MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
VID2/MEM_VID SWAPRDY_A
82
79 GPU_VCORE_VID2 GPU_VCORE_VID2 79 80 82 80 79 NC_GPU_GPIO_22 NC_GPU_GPIO_22 79 80 84 81 80 DP_EG_DDC_CLK DP_EG_DDC_CLK 80 81 84
GP
80 79 NC_GPU_GPIO_23 NC_GPU_GPIO_23 79 80 84 81 80 DP_EG_DDC_DATA DP_EG_DDC_DATA 80 81 84
MAKE_BASE=TRUE
NO_TEST=TRUE MAKE_BASE=TRUE
THERM
79 SMC_GFX_OVERTEMP_R_L SMC_GFX_OVERTEMP_R_L 79 80
80 MAKE_BASE=TRUE Unused I2C Buses
FAN_PWM
80 79 6 TP_GPU_GSTATE<0> TP_GPU_GSTATE<0> 6 79 80 80 76 NC_FB_B_UCS1_L NC_FB_B_UCS1_L 76 80
MEM_VREF
79
77 FB_VREF_UNTERM FB_VREF_UNTERM 77 78 79 80 81 80 NC_GPU_I2CC_SCL NC_GPU_I2CC_SCL 80 81
78
80
SLI_SYNC
79 GPU_GPIO_11 TP_GPU_GSTATE<1> OUT 6 81 80 NC_GPU_I2CC_SDA NC_GPU_I2CC_SDA 80 81 76 NC_FB_B_LCS1_L NC_FB_B_LCS1_L 76 80
MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE 80 MAKE_BASE=TRUE NO_TEST=TRUE
AC_DET
79 SMC_GFX_THROTTLE_R_L SMC_GFX_THROTTLE_R_L OUT 79 80 80 79 NC_GPU_ROM_CS_L NC_GPU_ROM_CS_L 79 80
80 MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
PWR_CTL0
86
79 FBVDD_ALTVO FBVDD_ALTVO OUT 79 80 86 80 76 NC_FB_A_UCS1_L NC_FB_A_UCS1_L 76 80
PWR_CTL1
79 NC_GPU_GPIO_14 NC_GPU_GPIO_14 79 80 80 76 NC_FB_A_LCS1_L NC_FB_A_LCS1_L 76 80
Config Straps
Physical 81 80 NC_GPU_I2CH_SCL NC_GPU_I2CH_SCL 80 81
Strapping Pin Strapping Bit 3 Strapping Bit 2 Strapping Bit 1 Strapping Bit 0
81 80 NC_GPU_I2CH_SDA NC_GPU_I2CH_SDA 80 81 80 NC_LVDS_EG_B_CLK_P NC_LVDS_EG_B_CLK_P 80 81
MAKE_BASE=TRUE NO_TEST=TRUE 81 MAKE_BASE=TRUE
84 82 81 80 79 74 72 7 6 PP3V3_S0GPU ROM_SO XCLK_417 FB_0_BAR_SIZE SMB_ALT_ADDR VGA_DEVICE
81 80 NC_LVDS_EG_B_CLK_N NC_LVDS_EG_B_CLK_N 80 81
I2CS ties into SMBus connection page MAKE_BASE=TRUE
ROM_SCLK PCI_DEVID[4] SUB_VENDOR SLOT_CLK_CFG PEX_PLL_EN_TERM
OMIT NO STUFF NO STUFF (I2CS requires pullups even if not used) 98 81 80 NC_LVDS_EG_A_DATA_P<3> NC_LVDS_EG_A_DATA_P<3> 80 81 98
R87071 R8709 1
R87111 ROM_SI RAMCFG[3] RAMCFG[2] RAMCFG[1] RAMCFG[0]
98 81 80 NC_LVDS_EG_A_DATA_N<3> NC_LVDS_EG_A_DATA_N<3> 80 81 98
2.0K 4.99K 15.0K MAKE_BASE=TRUE NO_TEST=TRUE
5% 1% 1% STRAP 2 PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
1/16W 1/16W 1/16W 98 81 80 NC_LVDS_EG_B_DATA_P<3> NC_LVDS_EG_B_DATA_P<3> 80 81 98
MF-LF MF-LF MF-LF MAKE_BASE=TRUE NO_TEST=TRUE
402 2 402 2 402 2 STRAP 1 3GIO_PADCFG[3] 3GIO_PADCFG[2] 3GIO_PADCFG[1] 3GIO_PADCFG[0]
NC_LVDS_EG_B_DATA_N<3> NC_LVDS_EG_B_DATA_N<3>
C 79 GPU_ROM_SI STRAP 0 USER[3] USER[2] USER[1] USER[0]
98 81 80
80 81
98
C
OUT
79 IN GPU_ROM_SO
79 IN GPU_ROM_SCLK
G96 MIOA_DE and MIOA_D<9..0> are used as Debug Port.
Strap S1/S2 Bit[3:0] PU/PD Rval Strap S1/S2 Bit[3:0] PU/PD Rval PCI_DEVID[4:0]=0x14
OMIT
1 1 1 0 0000 PD 5k 8 1000 PU 5k 80 79 NC_GPU_MIOA_CLKOUT_P NC_GPU_MIOA_CLKOUT_P 79 80
R8708 R8710 R8712 1 0001 PD 10k 9 1001 PU 10k
45.3K 10K 15.0K 80 79 NC_GPU_MIOA_CLKOUT_N NC_GPU_MIOA_CLKOUT_N 79 80
1% 1% 1% 2 0010 PD 15k (HYN 256) A 1010 PU 15k MAKE_BASE=TRUE NO_TEST=TRUE
1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF 3 0011 PD 20k (SAM 256) B 1011 PU 20k 80 79 NC_GPU_MIOA_CTL3 NC_GPU_MIOA_CTL3 79 80
402 2 402 2 402 2 MAKE_BASE=TRUE NO_TEST=TRUE
4 0100 PD 25k (SAM 512) C 1100 PU 25k
80 79 6 TP_GPU_MIOA_DE TP_GPU_MIOA_DE 6 79 80
5 0101 PD 30k D 1101 PU 30k MAKE_BASE=TRUE
6 0110 PD 35k (HYN 512) E 1110 PU 35k 79 6 TP_GPU_MIOA_D<9..0> GPU_MIOA_D<9..0>
MAKE_BASE=TRUE
7 0111 PD 45k F 1111 PU 45k
80 79 NC_GPU_MIOA_CLKIN NC_GPU_MIOA_CLKIN 79 80
84 82 81 80 79 74 72 7 6 PP3V3_S0GPU
NC_GPU_MIOA_D<14..10> GPU_MIOA_D<14..10> 79
80 79 NC_GPU_MIOA_HSYNC NC_GPU_MIOA_HSYNC 79 80
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION MAKE_BASE=TRUE NO_TEST=TRUE
R87011 R87031 R87051 80 79 NC_GPU_MIOA_VSYNC NC_GPU_MIOA_VSYNC 79 80
45.3K 34.8K 10K 114S0353 1 RES,MTL FILM,1/16W,24.9K,1,0402,SMD,LF R8708 VRAM_512_SAMSUNG MAKE_BASE=TRUE NO_TEST=TRUE
1% 1% 1%
1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF 114S0368 1 RES,MTL FILM,1/16W,35.7K,1,0402,SMD,LF R8708 VRAM_512_HYNIX 80 79 NC_GPU_MIOB_CLKIN NC_GPU_MIOB_CLKIN 79 80
114S0343 1 RES,MTL FILM,1/16W,20.0K,1,0402,SMD,LF R8708 VRAM_256_SAMSUNG 80 79 NC_GPU_MIOB_CLKOUT_P NC_GPU_MIOB_CLKOUT_P 79 80
79 BI GPU_STRAP<0>
114S0331 1 RES,MTL FILM,1/16W,15.0K,1,0402,SMD,LF R8708 VRAM_256_HYNIX 80 79 NC_GPU_MIOB_CLKOUT_N NC_GPU_MIOB_CLKOUT_N 79 80
79 BI GPU_STRAP<1>
80 79 NC_GPU_MIOB_CTL3 NC_GPU_MIOB_CTL3 79 80
79 GPU_STRAP<2>
B BI
NO STUFF NO STUFF NO STUFF

80 79 NC_GPU_MIOB_DE
NC_GPU_MIOB_DE 79 80
B
1 1 1 79 NC_GPU_MIOB_D<14..0> NO_TEST=TRUE GPU_MIOB_D<14..0>
R8702 R8704 R8706 MAKE_BASE=TRUE
2.0K 10K 24.9K 80 79 NC_GPU_MIOB_VSYNC NC_GPU_MIOB_VSYNC 79 80
5% 1% 1%
68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6 PP3V3_S0 MAKE_BASE=TRUE NO_TEST=TRUE
1/16W 1/16W 1/16W 47 46 42 40 37 34 30 28 27 26
MF-LF MF-LF MF-LF 99 88 87 85 84 83 73 72 69
80 79 NC_GPU_MIOB_HSYNC NC_GPU_MIOB_HSYNC 79 80
84 82 81 80 79 74 72 7 6 PP3V3_S0GPU
R87501 R87511 R87521 R87531 Unused Clocks

2.2K 2.2K 4.7K 4.7K
5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W 98 80 79 GPU_CLK27M_SS
402 2 402 2 402 402 84 82 81 80 79 74 72 7 6 PP3V3_S0GPU 79 GPU_XTALOUTBUFF
2 2 GPU_SS_INT
1 1
R8796 R8797 R87801 R87811
84 81 80 IN DP_EG_DDC_CLK 2.2K 2.2K 10K 10K
5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W
84 81 80 BI DP_EG_DDC_DATA MF-LF MF-LF MF-LF MF-LF
402 402 402 2 402 2
84 82 81 80 79 74 72 7 6 PP3V3_S0GPU 2 2
84 18 8 IN DP_IG_DDC_CLK NO STUFF
DP_CA_DET_EG_FET SMC_GFX_OVERTEMP_R_L R8798 0 1 2 SMC_GFX_OVERTEMP_L
80 79 OUT 45
DP_CA_DET_EG_FET Q8742 84 18 8 BI DP_IG_DDC_DATA 5% 1/16W MF-LF 402
R87421 SOD-VESM-HF 80 79 SMC_GFX_THROTTLE_R_L R8799 0 1 2 SMC_GFX_THROTTLE_L
OUT 45
5% 1/16W MF-LF 402
100K SSM3K15FV
1
1% EG_LCD_PWR_EN OUT 79 80 87
1/16W
G
MF-LF
402 2 EG_BKLT_EN OUT 79 80 87
S
80 EG_DP_CA_DET DP_CA_DET IN 84 85 87 FBVDD_ALTVO OUT 79 80 86
A
3
A
2
FB_VREF_UNTERM OUT 77 78 79 80 SYNC_MASTER=K17_REF SYNC_DATE=06/15/2009

PAGE TITLE
R8743
0
1
R8792 R8793R8794 R8795 1 1 NO STUFF
1 GT216 GPIOS & STRAPS
1 2 DP_CA_DET_EG IN 87 10K 10K 10K 10K DRAWING NUMBER SIZE
5% 5% 5% 5%
5%
1/16W
1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF Apple Inc. <SCH_NUM> D
MF-LF 402 402 402 402 REVISION
402 R
DP_CA_DET_EG_PLD
2 2 2 2 <E4LABEL>
<BRANCH>
Isolation FETs for DP MUX inputs THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
87 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes CRITICAL
Sum of peak currents: 240mA
L8800
- =PP1V8_GPU_IFPX 72 7 6 PP1V8_GPUIFPX 300-OHM-0.5A ?mA peak per diff pair
?mA peak for all pairs

- =PP3V3_GPU_IFPCD_IOVDD
1 2 PP1V8_GPU_IFPAB_IOVDD_F
0603-1
VOLTAGE=1.8V
C8800 1 C8801 1 C8803 1
OMIT
4.7UF 0.1UF 0.1UF
(NONE)
20% 20% 20%
6.3V 10V 10V
CERM 2
603
CERM 2
402
CERM 2
402
U8000
BOM options provided by this page: NV-GT216
(NONE) BGA
81 79 76 74 7 6 PP1V05_S0GPU Place at AG9 Place at AG10 (5 OF 9)
D
86
AG9 IFPA_IOVDD IFPA_TXC AM11 LVDS_EG_A_CLK_P OUT 87 98 D
AG10 IFPB_IOVDD IFPA_TXC* AM12 LVDS_EG_A_CLK_N OUT 87 98
GPU_IFPEF_RSET 81 L8805 81 PP1V1_GPU_IFPCD_IOVDD_F AJ8 IFPC_IOVDD

IFPA_TXD0 AM8 LVDS_EG_A_DATA_P<0>
180-OHM-1.5A AK8 IFPD_IOVDD OUT 87 98
GPU_IFPC_RSET 81 80mA peak IFPA_TXD0* AL8 LVDS_EG_A_DATA_N<0> OUT 87 98

1 2 PP1V1_GPU_IFPAB_PLLVDD_F 81 PP1V1_GPU_IFPEF_IOVDD_F AE7 IFPE_IOVDD
GPU_IFPAB_RSET 81 0603 MIN_LINE_WIDTH=0.3 mm IFPA_TXD1 AM10 LVDS_EG_A_DATA_P<1> OUT 87 98
MIN_NECK_WIDTH=0.2 mm AD7 IFPF_IOVDD
GPU_IFPD_RSET 81 VOLTAGE=1.1V IFPA_TXD1* AM9 LVDS_EG_A_DATA_N<1>
C8805 1 C8806 1 AK9 IFPAB_PLLVDD IFPA_TXD2 AK10 LVDS_EG_A_DATA_P<2>
OUT 87 98
4.7UF 1UF OUT 87 98

20% 10% 81 GPU_IFPAB_RSET AJ11 IFPAB_RSET IFPA_TXD2* AL10 LVDS_EG_A_DATA_N<2> 87 98
6.3V 2 6.3V 2 OUT
CERM CERM IFPA_TXD3 AK11 NC_LVDS_EG_A_DATA_P<3>OUT 80 98
603 402 81 PP3V3_GPU_IFPC_PLLVDD_F AJ9 IFPC_PLLVDD
1 1 1 1 NC_LVDS_EG_A_DATA_N<3>OUT
R8855 R8850 R8851 R8858 81 GPU_IFPC_RSET AK7 IFPC_RSET
IFPA_TXD3* AL11 80 98
1K 1K 1K 1K
1% 1% 1% 1% IFPB_TXC AP13 NC_LVDS_EG_B_CLK_P OUT 80
1/16W 1/16W 1/16W 1/16W 81 PP1V8_GPU_IFPEF_PLLVDD_F AJ6 IFPEF_PLLVDD
MF-LF MF-LF MF-LF MF-LF IFPB_TXC* AN13 NC_LVDS_EG_B_CLK_N OUT 80
2 402 2 402 2 402 2 402 81 GPU_IFPEF_RSET AL1 IFPEF_RSET
IFPB_TXD4 AN8 LVDS_EG_B_DATA_P<0> OUT 87 98
L8810 IFPB_TXD4* AP8 LVDS_EG_B_DATA_N<0> OUT 87 98

180-OHM-1.5A ?mA peak per diff pair
IFPB_TXD5 AP10 LVDS_EG_B_DATA_P<1> 87 98
OUT
?mA peak for all pairs
86 81 79 76 74 7 6 PP1V05_S0GPU 1 2 PP1V1_GPU_IFPCD_IOVDD_F 81 IFPB_TXD5* AN10 LVDS_EG_B_DATA_N<1> OUT 87 98
0603 MIN_NECK_WIDTH=0.1 mm IFPB_TXD6 AR11 LVDS_EG_B_DATA_P<2> OUT 87 98
VOLTAGE=1.1V
C8810 1 C8811 1 C8813 1 84 80 BI LVDS_EG_DDC_CLK G1 I2CA_SCL IFPB_TXD6* AR10 LVDS_EG_B_DATA_N<2> OUT 87 98
4.7UF 0.1UF 0.1UF 84 80 BI LVDS_EG_DDC_DATA G4 I2CA_SDA IFPB_TXD7 AN11 NC_LVDS_EG_B_DATA_P<3>OUT 80 98
20% 20% 20%
6.3V 2 10V 10V AP11 NC_LVDS_EG_B_DATA_N<3>OUT
CERM CERM 2 CERM 2 IFPB_TXD7* 80 98
603 402 402
IFPC_AUX_I2CW_SCL AP2 DP_EG_AUX_CH_P OUT 84 98
Place at AJ8 Place at AK8 IFPC_AUX_I2CW_SDA* AN3 DP_EG_AUX_CH_N OUT 84 98
80 BI NC_GPU_I2CC_SCL E3 I2CC_SCL
CRITICAL I2CS must be pulled up if not used IFPC_L0 AM7 DP_EG_ML_P<0> OUT 84 98
80 BI NC_GPU_I2CC_SDA E4 I2CC_SDA NO STUFF NO STUFF
IFPC_L0* AM6 DP_EG_ML_N<0>
L8815 I2CS addr fixed at 0x9E,0x9F OUT 84 98
R88611 1
C 300-OHM-0.5A
160mA peak
IFPC_L1
IFPC_L1*
AL5
AM5
DP_EG_ML_P<1>
DP_EG_ML_N<1>
OUT 84 98
84 98
1K
5%
R8860
1K
5%
C
PP3V3_S0GPU 1 2 PP3V3_GPU_IFPC_PLLVDD_F OUT
84 82 81 80 79 74 72 7 6 81 1/16W 1/16W
0603-1 MIN_LINE_WIDTH=0.3 mm IFPC_L2 AM3 DP_EG_ML_P<2> OUT 84 98 MF-LF MF-LF
MIN_NECK_WIDTH=0.2 mm 402 2 2 402
VOLTAGE=3.3V 97 51 48 45 SMBUS_SMC_0_S0_SCL E2 I2CS_SCL IFPC_L2* AM4 DP_EG_ML_N<2> 84 98
C8815 1 C8816 1 BI
SMBUS_SMC_0_S0_SDA E1 I2CS_SDA IFPC_L3 AP1 DP_EG_ML_P<3>
OUT
PP1V1_GPU_IFPEF_IOVDD_F 81
4.7UF 1UF 97 51 48 45 BI OUT 84 98
MIN_LINE_WIDTH=0.4 mm 20% 10% IFPC_L3* AR2 DP_EG_ML_N<3>

MIN_NECK_WIDTH=0.1 mm 6.3V 2 6.3V 2 I2CS must be pulled up if not used. OUT 84 98
VOLTAGE=1.1V CERM CERM

603 402 I2CS addr fixed at 0x9E,0x9F IFPD_AUX_I2CX_SCL AP4NC
IFPD_AUX_I2CX_SDA* AN4NC
PP1V8_GPU_IFPEF_PLLVDD_F 81
MIN_LINE_WIDTH=0.4 mm 80 BI NC_GPU_I2CH_SDA F6 I2CH_SCL
MIN_NECK_WIDTH=0.1 mm IFPD_L0 AR8NC
VOLTAGE=1.8V 80 BI NC_GPU_I2CH_SCL G6 I2CH_SDA
Power inputs must be pulled down if not used IFPD_L0* AR7NC
IFPD_L1 AP7NC
1
R8856 1R8857 IFPD_L1* AN7NC
10K 10K IFPD_L2 AN5NC
5% 5% 84 80 BI DP_EG_DDC_CLK G3 I2CB_SCL
1/16W 1/16W IFPD_L2* AP5NC
MF-LF MF-LF 84 80 BI DP_EG_DDC_DATA G2 I2CB_SDA
2 402 2 402 IFPD_L3 AR5NC
IFPD_L3* AR4NC
IFPE_AUX_I2CY_SCL AE4NC
IFPE_AUX_I2CY_SDA* AD4NC
IFPE_L0 AH6NC
IFPE_L0* AH5NC
IFPE_L1 AH4NC
IFPE_L1* AG4NC
IFPE_L2 AF4NC
IFPE_L2* AF5NC
B IFPE_L3
IFPE_L3*
AE6NC
AE5NC
B
IFPF_AUX_I2CZ_SCL AF3NC
IFPF_AUX_I2CZ_SDA* AF2NC
IFPF_L0 AL2NC
IFPF_L0* AL3NC
IFPF_L1 AJ3NC
IFPF_L1* AJ2NC
IFPF_L2 AJ1NC
IFPF_L2* AH1NC
IFPF_L3 AH2NC
IFPF_L3* AH3NC
AJ12 DACA_VDD DACA_RED AM15

NC
DACA_GREEN AM14
NC
DACA_BLUE AL14
NC
PP3V3_S0GPU
AK12 DACA_VREF
NC DACA_HSYNC AM13
NC 6 7 72 74 79 80 81 82 84
AK13 DACA_RSET
NC DACA_VSYNC AL13
NC
1
R8859
GPU_DACA_VDD AG7 DACB_VDD DACB_RED AK4NC 10K
5%
GPU_DACB_VDD DACB_GREEN AL4NC 1/16W
MF-LF
PP1V8_GPU_IFPD_PLLVDD DACB_BLUE AJ4NC 2 402
MIN_NECK_WIDTH=0.1 mm NCAK6 DACB_VREF
1 VOLTAGE=1.8V NCAH7 DACB_RSET CEC AB5 GPU_CEC
A R8852 1R8853 1R8854
10K
5%
10K
5%
10K
5% AC6 IFPD_PLLVDD
SYNC_MASTER=K17_REF
PAGE TITLE
SYNC_DATE=06/15/2009 A
1/16W 1/16W 1/16W
MF-LF
2 402
MF-LF
2 402
MF-LF
2 402 NV GT216 VIDEO INTERFACES
DRAWING NUMBER SIZE
DACB_HSYNC AM1NC
81 GPU_IFPD_RSET AB6 IFPD_RSET DACB_VSYNC AM2NC REVISION
R
<E4LABEL>
<BRANCH>
88 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
GPU VCore Regulator
72 67 66
54 46 44
31 7 6 PP5V_S3 R8911
43 42 33 1
61 58 56
101 1 2 PP5V_S3_GFXIMVP6_PVCC
5% MIN_NECK_WIDTH=0.2MM
1/16W VOLTAGE=5V
MF-LF
402
C8902 1 1 C8903
2.2UF 0.01uF 86 70 69 67 66 65 49 40 7 6 PPBUS_G3H
20% 10% 89
10V 2 16V
X5R-CERM 2 CERM CRITICAL
402 402 1 C8932 CRITICAL CRITICAL
C8930 1 1UF
10% C8933 1
1
C8931 1
C8935
68UF
20% 2 25V
1 C8934 15UF 15UF
R8904 16V
POLY-TANT 2
X5R
603-1
1UF
10%
0.001UF
10%
20% 20%
10 2 16V 2 16V
D
1
1%
2 PP5V_S3_GFXIMVP6_VDD
D3L 25V 2
X5R
603-1
50V
2 X7R
402
TANT
SM
TANT
SM D
1/16W VOLTAGE=5V
MF-LF
402 1 C8901
1uF
16
22
10%
2 10V
X5R
R89301
402 VDD PVCC
1K
5%
1/16W
R8905 CRITICAL
MF-LF
402 2
5
150K 1
2 GFXIMVP6_RBIAS 1 RBIAS U8900 VIN 14 GFXIMVP6_VIN D
CRITICAL
MIN_LINE_WIDTH=0.3MM MIN_LINE_WIDTH=0.3MM
1% QFN
1/16W
MF-LF C8904
MIN_NECK_WIDTH=0.2MM MIN_NECK_WIDTH=0.2MM
GFXIMVP6_UGATE 4 G
Q8950
ISL6263C UGATE 18
CSD58856Q5A
402 0.033UF MIN_LINE_WIDTH=0.6MM MLP5X6-LFPAK-Q5A
2 1 MIN_NECK_WIDTH=0.2MM
GFXIMVP6_SOFT 2 SOFT GATE_NODE=TRUE DIDT=TRUE
10% MIN_NECK_WIDTH=0.2MM BOOT 17 GFXIMVP6_BOOT S
16V MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM CRITICAL
X5R
402 DIDT=TRUE C8956 1 1 2 3 R8940
GFXIMVP6_IMON 28 IMON 0.22UF CRITICAL Vout = 0.75V - 0.90V
50 OUT 10% 0.001
PM_ALL_GPU_PGOOD PGOOD
16V 2
X7R L8920 1%
1W
87 86 73 8 OUT 31
603 0.56UH-31A MF-1
84 82
79 74 72 7 6 PP3V3_S0GPU 82 GFXIMVP6_VID0 23 VID0 0612
81 80 PHASE 19 GFXIMVP6_PHASE 1 2 PPVCORE_GPU_REG_R 2 1 PPVCORE_GPU 6 7 49 75 82
82 GFXIMVP6_VID1 24 VID1 MIN_LINE_WIDTH=0.6MM MIN_LINE_WIDTH=0.6MM
R89071 1
R8910 82 GFXIMVP6_VID2 25 VID2
SWITCH_NODE=TRUE
FDU1040D-SM MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.2V
4 3
C8966 1 CRITICAL 30A max output
10K 10K DIDT=TRUE 10UF
PPVCORE_GPU 5%
1/16W
5%
1/16W
82 GFXIMVP6_VID3 26 VID3 5
C8969 1 C8968 1 20% C8942 1 (L8920 limit)
82 75 49 7 6
MF-LF MF-LF GFXIMVP6_VID4 27 VID4 CRITICAL 10UF 6.3V 2 330UF
82
0.001UF 20% X5R 20%
402 2 2 402 87 73 IN EG_RAIL3_EN 29 VR_ON 21 GFXIMVP6_LGATE
D Q8951 10%
50V 2
6.3V 2
X5R
603 2.0V
POLY-TANT 2 3
1 LGATE CSD58857Q5 X7R 603
R8924 GFXIMVP6_AF_EN 30 AF_EN MIN_LINE_WIDTH=0.6MM D2T-SM2
100 GFXIMVP6_FDE 32 FDE
GATE_NODE=TRUE
4 G MLP5X6-LFPAK-Q5 402 1 C8965 CRITICAL
1% DIDT=TRUE 1 C8967 10UF
20% 1
1/16W
MF-LF 4.7UF 2 6.3V
X5R
C8943
10% 330UF
C PLACE_NEAR=U8900.8:7mm
402 2
GFXIMVP6_VSEN_P 8 VSEN
S 6.3V
2 X5R-CERM
603
603 20%
3 2 2.0V
POLY-TANT
C
R8920 GFXIMVP6_VSEN_N 9 RTN 1 2 3 D2T-SM2
GPU_VDD_SENSE 1
20 2
74
VOLTAGE=1.25V
5%
1/16W 1 C8920
1 C8923 C8921 1
MF-LF 0.001UF 0.001UF
402 0.001UF 10% 10%
10% 2 50V 50V
CERM 2
2 50V
CERM
CERM
402 402
1 C8953
R8908 402 (GFXIMVP6_AGND) 680pF
10%
20
74 GPU_GND_SENSE 1 2 2 50V
CERM GFXIMVP6_PHASE_VSUM
MIN_NECK_WIDTH=0.20 mm GFXIMVP6_VW 4 VW 402 MIN_LINE_WIDTH=0.3MM
MIN_LINE_WIDTH=0.25 mm 5% MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.3MM
VOLTAGE=0V 1/16W MIN_NECK_WIDTH=0.2MM
MF-LF 1
402 R8909 1 C8922
7.15K
1
PLACE_NEAR=U8900.9:7mm 0.001UF
R8925
1%
1/16W 10%
2 50V
R89031
100 C8950 MF-LF
402 2 X7R
402 1%
1K
1% 330PF 1/16W
1/16W 2 1 MF-LF
MF-LF GFXIMVP6_COMP_RC GFXIMVP6_COMP 5 COMP 402 2
402 MIN_LINE_WIDTH=0.3MM MIN_LINE_WIDTH=0.3MM VO 12 GFXIMVP6_VO
MIN_NECK_WIDTH=0.3MM 10% MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.3MM
2
1 50V
R8950 CERM 1 C8952 R8900
150K
1%
402
330PF
10% OCSET 3 GFXIMVP6_OCSET 1
7.32K2 GPU VCore Setpoints
1/16W 50V MIN_LINE_WIDTH=0.3MM
MF-LF 2 CERM MIN_NECK_WIDTH=0.2MM 1%
1/16W VID4 VID3 VID2 VID1 VID0 Max Batt Balanced Max perf
2 402 402 MF-LF
Voltage
GFXIMVP6_VSUM 402
GFXIMVP6_FB 6 FB MIN_LINE_WIDTH=0.3MM
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM 1 0 1 0 1 0.74675V K18 -
MIN_NECK_WIDTH=0.2MM ISP 13 C8906 1
1 GFXIMVP6_DFB 330PF
1
R8951 R8953 ISN 11
MIN_LINE_WIDTH=0.3MM 5%
50V 2
1 0 0 1 0 0.82400V - K18 -
3.01K MIN_NECK_WIDTH=0.2MM COG
150 1% 402 0 1 1 1 1 0.90125V - - K18
1% 1/16W
B 1/16W
MF-LF
402 0.0068UF
C8951 MF-LF
2 402 R8902 2 1
R8901 B
2
GFXIMVP6_VDIFF_RC 1 2 GFXIMVP6_VDIFF 7
ICOMP 10 9.76K 9.09K (PPVCORE_GPU_REG)
VDIFF 1% 1%
MIN_LINE_WIDTH=0.3MM MIN_LINE_WIDTH=0.3MM 1/16W 1/16W
MIN_NECK_WIDTH=0.3MM 10%
25V
PGND VSS THRM_PAD
MF-LF
402 C8971 MF-LF
2 402
CERM
1
68PF
402 GFXIMVP6_DROOP 1 2
20
15
33
353S2289 5%
50V C8972 1
CERM 0.001UF
402-1 10%
50V
CERM 2
GND_GFXIMVP6_AGND 402
VOLTAGE=0V
XW8900
SM
84 82 81 80 79 74 72 7 6 PP3V3_S0GPU
1 2
R8986 PLACE_NEAR=U8900.33:2mm
K18 Default Vcore Setpoints
0 TABLE_BOMGROUP_HEAD
80 79 IN GPU_VCORE_VID0 2 1 BOM GROUP BOM OPTIONS

5% TABLE_BOMGROUP_ITEM
1/16W GPUVID_0P75V GPUVID4_1,GPUVID3_0,GPUVID2_1,GPUVID1_0,GPUVID0_1

MF-LF GPUVID0_1 GPUVID1_1 GPUVID2_1 GPUVID3_1 GPUVID4_1
402 TABLE_BOMGROUP_ITEM
R8990 R89871 R89841 R89821 R89951 R89911 GPUVID_0P82V GPUVID4_1,GPUVID3_0,GPUVID2_0,GPUVID1_1,GPUVID0_0

2.2K 2.2K 2.2K 2.2K 2.2K TABLE_BOMGROUP_ITEM
0 5% 5% 5% 5% 5% GPUVID_0P90V GPUVID4_0,GPUVID3_1,GPUVID2_1,GPUVID1_1,GPUVID0_1
80 79 IN GPU_VCORE_VID1 1 2 1/16W 1/16W 1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF MF-LF MF-LF
5% 402 2 402 2 402 2 402 2 402 2
1/16W
MF-LF GFXIMVP6_VID0 82
402
GFXIMVP6_VID1 82
R8993 GFXIMVP6_VID2 82
0 GFXIMVP6_VID3
A 80 79 IN GPU_VCORE_VID2 1
5%
2
GFXIMVP6_VID4
82
82 SYNC_MASTER=K18_POWER SYNC_DATE=07/14/2009 A
1/16W PAGE TITLE
MF-LF
402
GPUVID0_0 GPUVID1_0 GPUVID2_0 GPUVID3_0 GPUVID4_0
GPU (GT216) CORE SUPPLY
R8994 R89881 R89851 R89831 R89961 R89921
DRAWING NUMBER SIZE
80 79 GPU_VCORE_VID3 1
0 2 2.2K 2.2K 2.2K 2.2K 2.2K Apple Inc. <SCH_NUM> D
IN
5% 5% 5% 5% 5% REVISION
5% 1/16W 1/16W 1/16W 1/16W 1/16W R
1/16W
MF-LF
MF-LF
402 2
MF-LF
402 2
MF-LF
402 2
MF-LF
402 2
MF-LF
402 2
<E4LABEL>
402 NOTICE OF PROPRIETARY PROPERTY: BRANCH
R8998 THE INFORMATION CONTAINED HEREIN IS THE

<BRANCH>
0 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
GPU_VCORE_VID4 1 2
80 79 IN
5%
89 OF 132
1/16W III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
MF-LF
402 IV ALL RIGHTS RESERVED 82 OF 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
87 IN LCD_PWR_EN
R90941
10K
5%
1/16W
MF-LF
LCD (LVDS) INTERFACE
402 2
CRITICAL
U9000 CRITICAL
FPF1009
1 ON MFET-2X2 L9000
FERR-250-OHM
31 27 23 21 20 19 18 17 7 6 PP3V3_S5 2 VIN_1 VOUT_1 4 PP3V3_SW_LCD_UF 1 2
99 85 73 72 71 66 57 35 MIN_LINE_WIDTH=0.5 mm SM
3 VIN_2 VOUT_2 5 VOLTAGE=3.3V
GND THRM
PAD 1 C9011 1 C9012 C9001 1 C9002 1
1 C9009 0.1UF 0.001UF
6 7 0.1UF 10UF 10% 10%
0.1UF 10% 20% 16V 2 50V 2
10%
16V 2 16V
X5R 2 6.3V
X5R
X5R
402
X7R
402
2 X5R 402 603
402 CRITICAL
J9000
20474-040E-11
F-RT-SM
41
68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
PP3V3_S0 42
C
99 88 87 85 84 80 73 72 69
1
C
100K pull-ups are for
R90101 1
R9011 6 PP3V3_SW_LCD 2
100K 100K MIN_LINE_WIDTH=0.5 mm 3
no-panel case (development). 5% 5% MIN_NECK_WIDTH=0.25 mm
1/16W 1/16W VOLTAGE=3.3V 4
Panel has 2K pull-ups MF-LF MF-LF
402 2 2 402 5
NC
84 6 LVDS_DDC_CLK 6
84 6 LVDS_DDC_DATA 7
98 84 6 LVDS_CONN_A_DATA_N<0> 8
C9010 1 98 84 6 LVDS_CONN_A_DATA_P<0> 9
0.001UF 10
10%
50V 2 LVDS_CONN_A_DATA_N<1> 11
X7R 98 84 6
402 98 84 6 LVDS_CONN_A_DATA_P<1> 12
CRITICAL 13
L9010
90-OHM-100MA LVDS_CONN_A_DATA_N<2> 14
98 84 6
DLP11S 15
SYM_VER-1
98 84 6 LVDS_CONN_A_DATA_P<2>
98 84 LVDS_CONN_A_CLK_N 4 3 16
98 6 LVDS_CONN_A_CLK_F_N 17
98 6 LVDS_CONN_A_CLK_F_P 18
98 84 LVDS_CONN_A_CLK_P 1 2
19
Place close to the connector 98 84 6 LVDS_CONN_B_DATA_N<0> 20
98 84 6 LVDS_CONN_B_DATA_P<0> 21
22
98 84 6 LVDS_CONN_B_DATA_N<1> 23
98 84 6 LVDS_CONN_B_DATA_P<1> 24
CRITICAL 25
L9011
B 90-OHM-100MA
DLP11S
SYM_VER-1
98 84 6
98 84 6
LVDS_CONN_B_DATA_N<2>
LVDS_CONN_B_DATA_P<2>
26
27 B
98 84 LVDS_CONN_B_CLK_N 4 3 28
LVDS_CONN_B_CLK_F_N
98 6 29
LVDS_CONN_B_CLK_F_P
98 6 30
98 84 LVDS_CONN_B_CLK_P 1 2
88 6 LED_RETURN_6 31
Place close to the connector 88 6 LED_RETURN_5 32
LED_RETURN_1 36 518S0651
88 6
37
NC
38
39
88 56 6 PPVOUT_S0_LCDBKLT 40
C9000 1 43
0.001UF 44
10%
50V
CERM 2
402
PAGE TITLE
LVDS Display Connector

DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
90 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
DisplayPort Mux
69 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6 PP3V3_S0
47 46 42 40 37 34 30 28 27 26
99 88 87 85 84 83 80 73 72
LVDS Transmitter Termination
A2
J4
1 C9320 1 C9321
0.1UF 0.1UF
93 8 DP_IG_ML_P<0> B4 DIN1_0+ VDD 20% 20%
IN
All emulated LVDS outputs require this termination 2 10V
CERM 2 10V
CERM
93 8 IN DP_IG_ML_N<0> A4 DIN1_0- 402 402
D PLACE_NEAR=U9600.A6:7mm
R9320
93 8 IN DP_IG_ML_P<1> B5 DIN1_1+ U9320
CBTL06141EE
D
93 8 IN DP_IG_ML_N<1> A5 DIN1_1-
357 BGA
98 87 IN LVDS_A_CLK_P 1 2 LVDS_CONN_A_CLK_P OUT 83 98
93 8 IN DP_IG_ML_P<2> B6 DIN1_2+ CRITICAL
1%
1/16W 93 8 IN DP_IG_ML_N<2> A6 DIN1_2-
MF-LF
402
93 8 IN DP_IG_ML_P<3> A8 DIN1_3+ DOUT_0+ B2 DP_ML_P<0> OUT 85 98
93 8 DP_IG_ML_N<3> A9 DIN1_3- DOUT_0- B1 DP_ML_N<0> 85 98

IN OUT
PLACE_NEAR=U9600.A7:7mm C9330 1 2 99 DP_IG_AUX_CH_C_P
R9322 93 18 8 BI DP_IG_AUX_CH_P 10% 16V X5R 402 H9 DAUX1+
357 0.1uF
LVDS_A_CLK_N 1 2 LVDS_CONN_A_CLK_N DP_IG_AUX_CH_N J9 DAUX1-
98 87 IN
1%
OUT 83 98 93 18 8 BI C9331 1 2 99 DP_IG_AUX_CH_C_N
10% 16V X5R 402
DOUT_1+ D2 DP_ML_P<1> OUT 85 98
1/16W 80 18 8 IN DP_IG_DDC_CLK 0.1uF H8 DDC_CLK1 DOUT_1- D1 DP_ML_N<1> OUT 85 98

MF-LF
402 R9325 80 18 8 BI DP_IG_DDC_DATA J8 DDC_DAT1
LVDS_A_DATA_P<0> 1
357 2 LVDS_CONN_A_DATA_P<0>
98 87 IN OUT 6 83 98
18 8 DP_IG_HPD J2 HPD_1
1% OUT E2 DP_ML_P<2>
PLACE_NEAR=U9600.A8:7mm DOUT_2+ OUT 85 98
1/16W
MF-LF DOUT_2- E1 DP_ML_N<2> 85 98
402 OUT
98 81 IN DP_EG_ML_P<0> B8 DIN2_0+
R93041 98 81 IN DP_EG_ML_N<0> B9 DIN2_0-
100K F2 DP_ML_P<3>
PLACE_NEAR=U9600.B9:7mm R9327 5%
1/16W 98 81 IN DP_EG_ML_P<1> D8 DIN2_1+
DOUT_3+ OUT 85 98
357 MF-LF D9 DOUT_3- F1 DP_ML_N<3> OUT 85 98

98 87 IN LVDS_A_DATA_N<0> 1 2 LVDS_CONN_A_DATA_N<0> OUT 6 83 98 402 2 98 81 IN DP_EG_ML_N<1> DIN2_1-
1%
1/16W 98 81 DP_EG_ML_P<2> E8 DIN2_2+
IN
R9330 MF-LF
402 98 81 IN DP_EG_ML_N<2> E9 DIN2_2- AUX+ H2 DP_AUX_CH_C_P BI 85 98
357
98 87 IN LVDS_A_DATA_P<1> 1 2 LVDS_CONN_A_DATA_P<1> OUT 6 83 98 AUX- H1 DP_AUX_CH_C_N BI 85 98
98 81 IN DP_EG_ML_P<3> F8 DIN2_3+
1%
PLACE_NEAR=U9600.A9:7mm 1/16W DP_EG_ML_N<3> F9 DIN2_3-
MF-LF
98 81 IN PLACE_NEAR=U9320.J1:3mm
402
DP_EG_AUX_CH_P
C9335 1 2 98 DP_EG_AUX_CH_C_P
H6
98 81 BI 10% 16V X5R 402 DAUX2+
0.1uF R9307
DP_EG_AUX_CH_N J6
C PLACE_NEAR=U9600.C10:7mm R9332
98 81
81 80
BI
DP_EG_DDC_CLK
C9336
0.1uF
1 2 98 DP_EG_AUX_CH_C_N
10% 16V X5R 402 H5
DAUX2-
DDC_CLK2
HPDIN J1 DP_HPD_R 1
1K 2 DP_HOTPLUG_DET
IN 84 85 87
C
IN
357 5%
98 87 IN LVDS_A_DATA_N<1> 1 2 LVDS_CONN_A_DATA_N<1> OUT 6 83 98 81 80 BI DP_EG_DDC_DATA J5 DDC_DAT2 1/16W
MF-LF
1% 402
1/16W 80 79 OUT DP_EG_HPD H3 HPD_2
MF-LF
402 R9335 LO=PORT1 LO=AUX_CH
357 HI=PORT2 HI=DDC
98 87 IN LVDS_A_DATA_P<2> 1 2 LVDS_CONN_A_DATA_P<2> OUT 6 83 98
R9305 1 87 IN DP_MUX_SEL_EG A1 GPU_SEL DDC_AUX_SEL C2 DP_CA_DET IN 80 85 87
1%
PLACE_NEAR=U9600.B10:7mm 1/16W
MF-LF
100K DP_MUX_XSD_L B7 G2
5% 99
XSD* TST0
402 1/16W GND
MF-LF
68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6
47 46 42 40 37 34 30 28 27 26
PP3V3_S0 DPMUX_EN_HPD DPMUX_EN_HPD
402 2 88 87 85 84 83 80 73 72 69
R93011 1 C9301
B3
C8
G8
H4
H7
DPMUX_EN_S0&DPMUX_EN_PLD 1UF
PLACE_NEAR=U9600.A10:7mm R9337 10K
357 R93021 1%
1/16W
10%
2 6.3V
98 87 IN LVDS_A_DATA_N<2> 1 2 LVDS_CONN_A_DATA_N<2> OUT 6 83 98 10K MF-LF CERM-X5R
402
1% 402 2
1% 1/16W
1/16W DPMUX_EN_PLD MF-LF
DP_HOTPLUG_DET
R9340 MF-LF
402
R9303
402 2 87 85 84 OUT
MAKE_BASE=TRUE
357
98 87 IN LVDS_B_CLK_P 1 2 LVDS_CONN_B_CLK_P OUT 83 98 0
87 IN DP_MUX_EN 1 2
1%
1/16W 5%
PLACE_NEAR=U9600.C8:7mm MF-LF 1/16W
402 MF-LF
402
PLACE_NEAR=U9600.C9:7mm R9342
357
98 87 IN LVDS_B_CLK_N 1 2 LVDS_CONN_B_CLK_N OUT 83 98
1%
1/16W
MF-LF
402 R9345
357
98 87 LVDS_B_DATA_P<0> 1 2 LVDS_CONN_B_DATA_P<0> 6 83 98
B IN OUT
B
PLACE_NEAR=U9600.A2:7mm
1%
1/16W
MF-LF
402
LVDS DDC MUX
82 81 80 79 74 72 7 6 PP3V3_S0GPU
PLACE_NEAR=U9600.A3:7mm R9347
357
98 87 IN LVDS_B_DATA_N<0> 1 2 LVDS_CONN_B_DATA_N<0> OUT 6 83 98
1%
1/16W R93701 1
R9371
R9350 MF-LF 20K 20K
402 69 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6 PP3V3_S0 5% 5%
357 47 46 42 40 37 34 30 28 27 26 1/16W 1/16W
98 87 IN LVDS_B_DATA_P<1> 1 2 LVDS_CONN_B_DATA_P<1> OUT 6 83 98
99 88 87 85 84 83 80 73 72
MF-LF MF-LF
402 2 2 402
1%
PLACE_NEAR=U9600.A1:7mm 1/16W
MF-LF
402 C9370 1 R93721 1
R9373
0.1UF 20K 20K
20% 14 5% 5%
10V 1/16W 1/16W
CERM 2 VCC MF-LF MF-LF
PLACE_NEAR=U9600.B3:7mm R9352 402
U9370 402 2 2 402
LVDS_B_DATA_N<1> 1
357 2 LVDS_CONN_B_DATA_N<1> LVDS_DDC_SEL_EG 13 QFN1 1 LVDS_EG_DDC_CLK
98 87 6 83 98 87 80 81
IN OUT IN C1 A1 2 IN
SN74LV4066A
1%
1/16W B1
MF-LF
402 R9355 87 IN LVDS_DDC_SEL_IG 5
C2 A2 3
4 LVDS_IG_DDC_CLK IN 18
LVDS_B_DATA_P<2> 1
357 2 LVDS_CONN_B_DATA_P<2> LVDS_DDC_CLK
98 87 6 83 98 6 83
IN OUT B2 OUT
1%
PLACE_NEAR=U9600.C5:7mm 1/16W 6 8 LVDS_EG_DDC_DATA 80 81
MF-LF C3 A3 BI
402 9
B3
12
C4 A4
11 LVDS_IG_DDC_DATA BI 18
R9357 B4 10 LVDS_DDC_DATA BI 6 83
357 GND THRM

A 98 87 IN LVDS_B_DATA_N<2> 1
1%
2 LVDS_CONN_B_DATA_N<2> OUT 6 83 98
7 15 CRITICAL
1/16W PAGE TITLE
PLACE_NEAR=U9600.A5:7mm MF-LF
402 Muxed Graphics Support
DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
93 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Port Power Switch

DP_ESD
DP_ESD
CRITICAL
CRITICAL
D CRITICAL
D9410 D9410
RCLAMP0524P
D
RCLAMP0524P
U9480
TPS2051B
L9400
FERR-120-OHM-3A SLP2510P8
SLP2510P8
SOT23 1
31 27 23 21 20 19 18 17 7 6 PP3V3_S5 5 IN OUT PP3V3_S0_DPILIM 1 2 PP3V3_S0_DPPWR
99 83 73 72 71 66 57 35 MIN_LINE_WIDTH=0.38 MM MIN_LINE_WIDTH=0.38 MM 2 IO IO 1
MIN_NECK_WIDTH=0.20 MM 0603 MIN_NECK_WIDTH=0.20 MM 5 IO IO 4
PM_SLP_S3_L 4 EN OC* 3 TP_DPPWR_OC_L VOLTAGE=3.3V VOLTAGE=3.3V 9 NC NC 10
73 45 31 18 6 IN
GND
1 C9400 6 NC NC 7
0.01UF
GND
2
GND
20%
2 50V
CERM
603 3
3
CRITICAL CRITICAL
C9480 1 1 C9481 C9485 1 1 C9486 1
10UF 0.1UF
0.1UF 22UF C9487
20%
6.3V 2
20%
20% 100UF
X5R 2 10V
CERM
20%
10V 6.3V 20%
603 402 CERM 2
402
2 X5R-CERM
603
2 6.3V
POLY-TANT R94201
CASE-B2-SM 100K
5%
1/16W
MF-LF
402 2 NO STUFF
R9400 0 1 2
5% 1/16W MF-LF 402
NO STUFF
NO STUFF R9430 0 1 2
R9401 0 1 2
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
HDMI_CEC CRITICAL NO STUFF
J9400 R9431 0 1 2
5% 1/16W MF-LF 402
NO STUFF DSPLYPRT-M97-1 CRITICAL
R9403 0 1 2 F-RT-THSM
FL9400
5% 1/16W MF-LF 402 12-OHM-100MA
NO STUFF
C R9413 0 1 2
5% 1/16W MF-LF 402
BOT ROW TOP ROW 98 DP_ML_CONN_P<0> 1
TCM1210-4SM
SYM_VER-2 4
98 DP_ML_C_P<0> C9410 1 2 DP_ML_P<0>
C
1 TH PINS SM PINS IN 84 98
R9425 CRITICAL 98 DP_ML_CONN_N<0> 10% 16V X5R 402
2
HOT_PLUG_DETECT GND
1 0.1uF
1M
5%
FL9403
12-OHM-100MA
4
CONFIG1
3 FL9401
12-OHM-100MA
2 3 98 DP_ML_C_N<0> C9411 1 2 DP_ML_N<0> IN 84 98
1/16W ML_LANE0P 10% 16V X5R 402
MF-LF 4
TCM1210-4SM
1
6
CONFIG2 ML_LANE0N
5 TCM1210-4SM 0.1uF
2 402
SYM_VER-2
DP_ML_CONN_P<1> 1 SYM_VER-2 4
98 84 IN DP_ML_P<3> C9414 1 2 98 DP_ML_C_P<3>
10% 16V X5R 402
98 DP_ML_CONN_P<3> 8
GND GND
7
98
98 DP_ML_C_P<1> C9412 1 2 DP_ML_P<1>
10% 16V X5R 402 IN 84 98
0.1uF 10 ML_LANE3P ML_LANE1P

9 0.1uF
98 84 IN DP_ML_N<3> C9415 1 2 98 DP_ML_C_N<3> 3 2 98 DP_ML_CONN_N<3> 12
ML_LANE3N 11 98 DP_ML_CONN_N<1> 2 3 FL9402 98 DP_ML_C_N<1> C9413 1 2 DP_ML_N<1> IN 84 98
10% 16V X5R 402 ML_LANE1N 12-OHM-100MA 10% 16V X5R 402
0.1uF 14
GND GND
13 CRITICAL 1
TCM1210-4SM
SYM_VER-2 4
0.1uF
98 84 BI DP_AUX_CH_C_P 16 AUX_CHP ML_LANE2P
15 98 DP_ML_CONN_P<2> 98 DP_ML_C_P<2> C9416 1 2 DP_ML_P<2> IN 84 98
10% 16V X5R 402
18
AUX_CHN ML_LANE2N
17 0.1uF
98 84 BI DP_AUX_CH_C_N 20 DP_PWR RETURN
19 98 DP_ML_CONN_N<2> 2 3 98 DP_ML_C_N<2> C9417 1 2 DP_ML_N<2>
10% 16V X5R 402
IN 84 98
99 88 87 85 84 DP_ESD CRITICAL 0.1uF
58 54 52 51 50 48 47 46
25 24 23 21 20 19 18 17 7 6 PP3V3_S0
42 40 37 34 30 28 27 26
83 80 73 72 69 68 63 62
CRITICAL SHIELD PINS
R94431 R94421 D9411 22 21 NO STUFF
100K RCLAMP0524P R9402 0
5% 100K SLP2510P8
1 2
1/16W
MF-LF
5%
1/16W
R94211 NO STUFF
5% 1/16W MF-LF 402
402 2 MF-LF 100K R9432 0 1 2
402 2 5%
87 84 80 OUT DP_CA_DET 1/16W 2 IO 5% 1/16W MF-LF 402
MF-LF IO 1
6 402 2
9 NC NC 10
Q9440 D
GND
2N7002DW-X-G DP_ESD
SOT-363
S G 2 DP_CA_DET_L_Q CRITICAL DP_ESD
3
3
D9400 CRITICAL
1 RCLAMP0504F
SC70-6-1
D9411
Q9440 D RCLAMP0524P
B 2N7002DW-X-G
DP_CA_DET_Q
SOT-363
S G 5 1
6
SLP2510P8
B
DP to DVI/HDMI 5 IO IO 4
4
R94221 Cable Adapter 2 5
6 NC NC 7
1M (CA) has 100k
5%
GND
Q9440 must have Drain to Gate leakage of <500nA and Gate to Source resistance of >5MOhm 1/16W pull-up to DP_PWR. 4
MF-LF 3
402 2
3
88 87 85 84 83 80 73
52 51 50 48 47 46 42
25 24 23 21 20 19 18 17 7 6 PP3V3_S0
40 37 34 30 28 27 26
72 69 68 63 62 58 54
99
R9445 1
10K R9444 1
5% 10K
1/16W 5%
MF-LF 1/16W
402 MF-LF
2
402
87 84 OUT DP_HOTPLUG_DET 2
D
Q9441
2N7002DW-X-G
SOT-363
S G 2 DP_HPD_L_Q
3
1
Q9441 D
2N7002DW-X-G
SOT-363
S G 5 DP_HPD_Q
A 4 DP Source must pull SYNC_MASTER=K17_REF SYNC_DATE=06/15/2009 A
R9423 1 down HPD input with PAGE TITLE
100K
5%
1/16W
greater than or equal DisplayPort Connector
MF-LF to 100K (DPv1.1a). DRAWING NUMBER SIZE
402
2
REVISION
R
<E4LABEL>
<BRANCH>
94 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
1V05 S0 GPU FET

D D
21 20 18 17 15 13 12 10 7 6 PP1V05_S0
73 70 40 26 25 24 23
70 69 68 54 52 47 42 23 7 6 PP5V_S0
88 86 72
C9550 1
0.1UF 1.05V FB FET
1
20%
10V
2 VCC 5
CERM
402 376S0827 MOSFET AON6400L
U9550 D CRITICAL
CHANNEL N-TYPE
SLG5AP020 Q9550
EG_RAIL1_EN 2 TDFN
87 73 IN ON D 5 4 G AON6400L RDS(ON) 1.8 mOhm @4.5V
CRITICAL DFN5X6
3 SHDN* G 7 P1V05_FB_GATE LOADING 3.83 A (EDP)
6 S
S
PG 8 1 2 3
THRM
GND PAD
9
PP1V05_S0GPU 6 7 74 76 79 81
PM_ALL_GPU_PGOOD OUT 8 73 82 86 87
C C
1V8 / 1V55 / 1V35 S0 FRAMEBUFFER REGULATOR
82 70 69 67 66 65 49 40 7 6 PPBUS_G3H
89
TABLE_5_HEAD CRITICAL
C9590 1
1 C9595
TABLE_5_ITEM
68UF 1UF
2
114S0336 1 RES,1/16W,16.9K,1%,0402,LF R9588 FB1V35 10%
20%
16V 2 2 25V
X5R CRITICAL
Q9560
TABLE_5_ITEM
POLY-TANT 603-1 D1
114S0357 1 RES,1/16W,27.4K,1%,0402,LF R9589 FB1V35 CASE-D2E-SM
R9580 RJK0384DPA
1 G1 WPAK
FB_1V8_S0_VBST 0
1 2
FB_1V8_S0_VBST_RC 152S0518
MIN_NECK_WIDTH=0.2 mm S1/D2 7
MIN_LINE_WIDTH=0.6 mm 5% MIN_LINE_WIDTH=0.6 mm
1/16W
MF-LF
MIN_NECK_WIDTH=0.2 mm CRITICAL
PP5V_S0
402 L9560
70 69 68 54 52 47 42 23 7 6
88 86 72 C9580 6 G2 2.2UH-8.0A
1 0.1UF 1 2
VBST 10
C9501 1 CRITICAL 10%
V5IN 7
50V S2 PCMB065T-SM
FB VDD 10UF
20%
X7R
2 603-1
5
10V
FBVDD_ALTVO Regulator Output X5R 2
603
U9500 PP1V8R1V55_S0GPU_ISNS_R 6 7 50
0 1.35 / 1.55 V
R9587 TPS51217 PLACE_NEAR=L9560.2:3mm Vout = 1.806V
1 C9565
B 1 1.80 V
87 73 72 IN
EG_RAIL4_EN 1
1K 2 P1V8FB_EN_R 3 EN
DSC
PGOOD 1 PM_ALL_GPU_PGOOD OUT 8 73 82 86 87
XW9565
2 10UF
20% 7A max output B
5% 353S2739 SM 2 6.3V
X5R (Q9560 limit?)
FB_1V8_S0_VFB 1/16W 4 VFB DRVH 9 FB_1V8_S0_DRVH 603
FB1V55 MF-LF GATE_NODE=TRUE DIDT=TRUE MIN_LINE_WIDTH=0.6MM
FB_1V8_S0_TRIP
402
2 TRIP
MIN_NECK_WIDTH=0.2MM 1 f = 340 kHz
R9589 1 SW 8
FB_1V8_S0_LL CRITICAL
51.1K FB_1V8_S0_TRAN SWITCH_NODE=TRUE DIDT=TRUE MIN_LINE_WIDTH=0.6MM 1
1%
1/16W
5 TRAN DRVL 6 MIN_NECK_WIDTH=0.2MM C9560
MF-LF 330UF
402 20%
FB_1V8_S0_DRVL 2.0V
2 C9586 THRM GATE_NODE=TRUE DIDT=TRUE MIN_LINE_WIDTH=0.6MM POLY-TANT 2
FB_1V8_S0_VFB_R 1 47PF PAD MIN_NECK_WIDTH=0.2MM B2-SM
CERM
11
5%
Q9581 FB1V55 1
R9585 50V
402
SSM3K15FV D 3 1 40.2K
2
SOD-VESM-HF R9588 1% FB_1V8_S0_VFB_XW
13K 1/16W
1% MF-LF
1/16W 2 402
FB_1V8_S0_TRAN_R
MF-LF 1
2 402 PLACE_NEAR=U9500.2:3mm R9586 1
1 G S 2 1K R9571
FBVDD_ALTVO 5%
1/16W
20.5K 1 C9570
MF-LF 1%
80 79 IN 1/16W 1000PF
2 402 MF-LF 5%
2 402 25V
2 NP0-C0G
GND (GND) 402
(FB_1V8_S0_VFB)
PAGE TITLE
1V8 / 1V55 FB Power Supply

DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
95 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
87 85 84 83
R9600
68 63 62
48 47 46
28 27 26
19 18 17 7
24 23 21
40 37 34
54 52 51
58
42
25
6
20
30
50
PP3V3_S0 1
0
5%
2
GMUX CPLD GMUXPLL_1V8
R9611
0
LVDS Receiver Termination
80 73 72 69 1/16W 72 71 58 24 23 21 16 12 7 6 PP1V8_S0 1 2 PP3V3R1V8_S0_GMUX
99 88 MF-LF 87 MIN_LINE_WIDTH=0.4 mm
402 PP3V3_S0_GMUX_R 5% MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.4 mm 1/16W VOLTAGE=3.3V
VOLTAGE=3.3V
MF-LF
402 93 87 18 LVDS_IG_A_CLK_P R9650 100 1 2 PLACE_NEAR=U9600.H3:5mm LVDS_IG_A_CLK_N 18 87 93
1 C9610 1 C9621 1 C9622 1 C9623 1 C9624 1 C9625 1 C9626 1 C9627 1 C9628 1 C9629 99
88 87
80 73 GMUXPLL_3V3 LVDS_IG_A_DATA_P<0> R9651 100 1 2
1% 1/16W MF-LF
PLACE_NEAR=U9600.E1:5mm
402
LVDS_IG_A_DATA_N<0>
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 63 62 93 87 18 18 87 93
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 51 50
42 40 R9612 93 87 18 LVDS_IG_A_DATA_P<1> R9652 100 1 2
1% 1/16W MF-LF
PLACE_NEAR=U9600.E3:5mm
402
LVDS_IG_A_DATA_N<1> 18 87 93
2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
28 27 0 R9653 1% 1/16W MF-LF 402
402 402 402 402 402 402 402 402 402 402
23 21
17 7 6 PP3V3_S0 1 2 93 87 18 LVDS_IG_A_DATA_P<2> 100 1 2 PLACE_NEAR=U9600.G1:5mm LVDS_IG_A_DATA_N<2> 18 87 93
20 19 18
26 25 24
1% 1/16W MF-LF 402
37 34 30
48 47 46
5%
1/16W L9621 93 87 18 LVDS_IG_B_DATA_P<0> R9654 100 1 2 PLACE_NEAR=U9600.G2:5mm LVDS_IG_B_DATA_N<0> 18 87 93
58 54 52
72 69 68
85 84 83
MF-LF
402 FERR-220-OHM 93 87 18 LVDS_IG_B_DATA_P<1> R9655 100 1 2
1% 1/16W MF-LF
PLACE_NEAR=U9600.G3:5mm
402
LVDS_IG_B_DATA_N<1> 18 87 93
R9656 1% 1/16W MF-LF 402
D R9610
0
PP1V8_S0_GMUX_R
PP3V3R1V8_S0_GMUX_ULC_VCCPLL
1
0402
2
93 87 18 LVDS_IG_B_DATA_P<2> 100 1 2 PLACE_NEAR=U9600.B2:5mm
1% 1/16W MF-LF 402
LVDS_IG_B_DATA_N<2> 18 87 93
D
87 72 71
16 12 7 6
58 24 23 21
PP1V8_S0 1 2
1 C9611 1 C9612 1 C9613 1 C9614 1 C9615 1 C9616 1 C9617 VOLTAGE=1.8V VOLTAGE=3.3V 1 C9631 LVDS_EG_A_CLK_P R9660 100 1 2 PLACE_NEAR=U9600.J12:5mm LVDS_EG_A_CLK_N
0.1UF 98 87 81 81 87 98
5%
1/16W 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 20% 98 87 81 LVDS_EG_A_DATA_P<0> R9661 100 1 2
1% 1/16W MF-LF 402
PLACE_NEAR=U9600.D13:5mm LVDS_EG_A_DATA_N<0> 81 87 98
MF-LF 20%
10V
20%
10V
20%
10V
20%
10V
20%
10V
20%
10V
20%
10V 2 10V
CERM R9662 1% 1/16W MF-LF 402
402 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 402 98 87 81 LVDS_EG_A_DATA_P<1> 100 1 2 PLACE_NEAR=U9600.E14:5mm LVDS_EG_A_DATA_N<1> 81 87 98
402 402 402 402 402 402 402 98 87 81 LVDS_EG_A_DATA_P<2> R9663 100 1 2
1% 1/16W MF-LF 402
PLACE_NEAR=U9600.F12:5mm LVDS_EG_A_DATA_N<2> 81 87 98
L9620 1% 1/16W MF-LF 402
FERR-220-OHM
98 87 81 LVDS_EG_B_DATA_P<0> R9664 100 1 2 PLACE_NEAR=U9600.G14:5mm LVDS_EG_B_DATA_N<0> 81 87 98
PP3V3R1V8_S0_GMUX_LRC_VCCPLL 1 2
98 87 81 LVDS_EG_B_DATA_P<1> R9665 100 1 2
1% 1/16W MF-LF 402
PLACE_NEAR=U9600.G13:5mm LVDS_EG_B_DATA_N<1> 81 87 98
72 7 6 PP1V2_S0 MIN_LINE_WIDTH=0.4 mm R9666 1% 1/16W MF-LF 402
MIN_NECK_WIDTH=0.09 mm 0402 98 87 81 LVDS_EG_B_DATA_P<2> 100 1 2 PLACE_NEAR=U9600.H12:5mm LVDS_EG_B_DATA_N<2> 81 87 98
VOLTAGE=3.3V 1% 1/16W MF-LF 402
1 C9630 SIGNAL_MODEL=EMPTY
0.1UF PP3V3_S0
C9600 1 1 C9604 1 C9605 1 C9606 1 C9607 1 C9608 1 C9609 20%
4.7UF
20%
4V
20%
10V
0.1UF 0.1UF
20%
10V
20%
10V
0.1UF 0.1UF
20%
10V
0.1UF
20%
2 10V
20%
2 10V
0.1UF
10V
2 CERM
402 Required Pullups
X5R 2
402
2 CERM
402
2 CERM
402
2 CERM
402
2 CERM
402
CERM
402
CERM
402 87 GMUX_DEBUG_RESET_L R9680 1K 1 2
5% 1/16W MF-LF 402
87 EG_PWRSEQ_EN R9684 1K 1 2
5% 1/16W MF-LF 402
B11
J13
N11
C11
J14
A12
C14
F13
M12
K12
P11
C4
J3
P8
J2
M8
B5
B7
M9
M3
N5
M1
C3
F2
A4
99 88 87
69 68 63 62 58 54
42 40 37 34 30
20 19 18 17 7
28
6 PP3V3_S0
27 26 25 24 23
52 51 50 48 47
21
46
NO STUFF
VCCIO0
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
ULC_VCCPLL
LRC_VCCPLL
85 84 83 80 73 72 VCC VCCAUX VCCJ
R96401 1
R9645 R96791
87 25 20 JTAG_GMUX_TCK K14 TCK 10K
10K 10K JTAG_GMUX_TDI SILK_PART=GMUX_RST 1%
1% 1% 87 19 L13 TDI 1/16W
1/16W 1/16W MF-LF
MF-LF MF-LF 87 20 JTAG_GMUX_TDO K13 TDO 402 2
402 2 2 402 JTAG_GMUX_TMS OMIT
87 19 L12 TMS
GMUX_TOE K2
CRITICAL
TOE
C NO STUFF NO STUFF
GMUX_CFG0 K1 CFG0 U9600
XP25-5
Required Pulldowns C
89 8 OUT LCD_BKLT_EN P2 PB7A CSBGA PT7A A2 LVDS_B_DATA_P<0> OUT 84 98 87 84 DP_MUX_SEL_EG R9681 10K 1 2
R96411 1
R9646 88 87 6 OUT LCD_BKLT_PWM N2 PB7B PT7B A3 LVDS_B_DATA_N<0> OUT 84 98
5% 1/16W MF-LF 402
10K 10K
LVDS_DDC_SEL_EG P4 PB14A A1 LVDS_B_DATA_P<1>
1%
1/16W
1%
1/16W
87 84 OUT
LVDS_DDC_SEL_IG N4
PT8A
B3 LVDS_B_DATA_N<1>
OUT 84 98
87 84 LVDS_DDC_SEL_IG R9682 10K 1 2
MF-LF MF-LF 87 84 OUT PB14B PT8B OUT 84 98 5% 1/16W MF-LF 402
402 2 2 402 84 OUT DP_MUX_EN N3 PB15A (OD) PT9A C5 LVDS_B_DATA_P<2> OUT 84 98
87 84 OUT DP_MUX_SEL_EG M4 PB15B PT9B A5 LVDS_B_DATA_N<2> OUT 84 98 87 84 LVDS_DDC_SEL_EG R9683 10K 1 2

5% 1/16W MF-LF 402
BANK5
87 74 8 OUT EG_RESET_L P5 PB16A PT14A B6 EG_PWRSEQ_EN IN 87 (Use open-drain PGOOD output to hold off the start of the GPU PWRSEQ until the first GPU rail’s source is valid)
EG_RAIL1_EN GMUX_DEBUG_RESET_L NO STUFF
M5 PB16B PT14B C7
87 86 73 OUT IN 87
EG_RESET_L R9691 100K 1 2
BANK0
87 74 8
87 73 72 OUT EG_RAIL2_EN P6 PB17A PT15A A6 LVDS_A_CLK_P OUT 84 98 5% 1/16W MF-LF 402
EG_RAIL3_EN M6 PB17B PT15B A7 LVDS_A_CLK_N
87 82 73 OUT
EG_RAIL4_EN P7 C8 LVDS_B_CLK_P
OUT 84 98
88 87 6 LCD_BKLT_PWM R9693 100K 1 2
87 86 73 72 OUT PB18A PT16A OUT 84 98 5% 1/16W MF-LF 402
17 8 OUT PEG_CLKREQ_L M7 PB18B (OD) PT16B C9 LVDS_B_CLK_N OUT 84 98
80 OUT DP_CA_DET_EG N7 PB19A PT17A A8 LVDS_A_DATA_P<0> OUT 84 98
CRITICAL 87 83 OUT LCD_PWR_EN N8 PB19B PT17B B9 LVDS_A_DATA_N<0> OUT 84 98
J9600 94 47 45 17 6 BI LPC_AD<0> P9 PB20A PT18A A9 LVDS_A_DATA_P<1> OUT 84 98
1909782 94 47 45 17 6 BI LPC_AD<1> N9 PB20B PT18B C10 LVDS_A_DATA_N<1> OUT 84 98

M-RT-SM
7
94 47 45 17 6 BI LPC_AD<2> P10 PB26A PT19A B10 LVDS_A_DATA_P<2> OUT 84 98
BANK4
94 47 45 17 6 BI LPC_AD<3> M10 PB26B PT19B A10 LVDS_A_DATA_N<2> OUT 84 98
GMUX_JTAG_CONN
50 51 52 54 58 62 63 68 69 72 47 45 94
17 6 BI LPC_FRAME_L P12 PB27A PT20A A11 GND
1 PP3V3_S0
BANK1
6 7 17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48 94 47 27 6
IN LPCPLUS_RESET_L P13 PB27B PT20B B12 GND
2 JTAG_GMUX_TDO 73 80 83 84 85 87 88 99
27 IN LPC_CLK33M_GMUX N12 PB28A PT28A B13 GND
3 JTAG_GMUX_TDI 19 87
20 OUT GMUX_INT P14 PB28B PT28B A13 GND
4 JTAG_GMUX_TMS 19 87 87 86 73 EG_RAIL1_EN
5
93 87 18 IN LVDS_IG_B_DATA_P<2> B1 PL2A PR2A A14 DP_CA_DET IN 80 84 85
6 JTAG_GMUX_TCK 20 25 87
93 87 18 LVDS_IG_B_DATA_N<2> B2 PL2B PR2B B14 DP_HOTPLUG_DET 84 85 87 73 72 EG_RAIL2_EN
B 8
IN
GMUX_PL10A C2 PL6A PR6A D12 LVDS_EG_A_DATA_P<0>
IN
IN 81 87 98 B
TP_GMUX_PL10B D3 PL6B PR6B D13 LVDS_EG_A_DATA_N<0> IN 81 87 98
87 82 73 EG_RAIL3_EN
93 87 18 IN LVDS_IG_A_DATA_P<0> D1 PL7A PR7A D14 LVDS_EG_A_DATA_P<1> IN 81 87 98
93 87 18 IN LVDS_IG_A_DATA_N<0> E1 PL7B PR7B E14 LVDS_EG_A_DATA_N<1> IN 81 87 98
93 87 18 IN LVDS_IG_A_DATA_P<1> D2 PL8A PR8A E12 LVDS_EG_A_DATA_P<2> IN 81 87 98 87 86 73 72 EG_RAIL4_EN

BANK7
BANK2
93 87 18 IN LVDS_IG_A_DATA_N<1> E3 PL8B PR8B F12 LVDS_EG_A_DATA_N<2> IN 81 87 98
NO STUFF 87 83 LCD_PWR_EN
93 87 18 IN LVDS_IG_A_DATA_P<2> F1 PL9A PR9A F14 LVDS_EG_B_DATA_P<0> IN 81 87 98
R96471 93 87 18 IN LVDS_IG_A_DATA_N<2> G1 PL9B PR9B G14 LVDS_EG_B_DATA_N<0> IN 81 87 98
1 1
10K R9672 R9674
1% 93 87 18 IN LVDS_IG_B_DATA_P<0> F3 PL10A PR10A G12 LVDS_EG_B_DATA_P<1> IN 81 87 98
1/16W
LVDS_IG_B_DATA_N<0> LVDS_EG_B_DATA_N<1>
4.7K 4.7K
MF-LF 93 87 18 IN G2 PL10B PR10B G13 IN 81 87 98 5% 5%
402 2 1/16W 1/16W
93 87 18 IN LVDS_IG_B_DATA_P<1> H2 PL11A PR11A H13 LVDS_EG_B_DATA_P<2> IN 81 87 98 MF-LF MF-LF
1 2402 1 402
93 87 18 IN LVDS_IG_B_DATA_N<1> G3 PL11B PR11B H12 LVDS_EG_B_DATA_N<2> IN 81 87 98
R9678 1 R9671 R9673 2
93 87 18 IN LVDS_IG_A_CLK_P H1 PL12A PR12A H14 LVDS_EG_A_CLK_P IN 81 87 98 4.7K 4.7K 4.7K
5% 5% 5%
93 87 18 IN LVDS_IG_A_CLK_N H3 PL12B PR12B J12 LVDS_EG_A_CLK_N IN 81 87 98 1/16W 1/16W 1/16W
TP_LVDS_MUX_SEL_EG LVDS_IG_PANEL_PWR MF-LF MF-LF MF-LF
8 OUT L1 PL14A PR14A L14 IN 8 18 402 2 2402 2402
BANK3
88 87 GMUX_VSYNC L3 PL14B PR14B M13 EG_LCD_PWR_EN IN 79 80

BANK6
27 IN GMUX_RESET_L K3 PL15A PR24A N14 LVDS_IG_BKL_ON IN 8 18
88 87 GMUX_VSYNC L2 PL15B PR24B N13 EG_BKLT_EN 79 80 GMUX_S3_PD_GND

ULC_GNDPLL
LRC_GNDPLL
IN
86 82 73 8 IN PM_ALL_GPU_PGOOD N1 PL25A
PEX_CLKREQ_L P1 PL25B
101 73
PP3V3_S3
GNDIO0
GNDIO1
GNDIO2
GNDIO3
GNDIO4
GNDIO5
GNDIO6
GNDIO7
74 8 IN 17 8 7 6
72 55 54 53 50 48 36 35 34 33 32 31 20 Q9607 D 3 NO STUFF
(Tie/strap low if EGPU doesn’t provide CLKREQ_L output, provide pullup to GPU rail if using CLKREQ_L output from EGPU) 1
SSM6N15FEAPE R9675
1
GND R9676 SOT563
0
100K 5%
5% 1/16W
1/16W MF-LF
J1
B8
C6
C12
C13
E13
M14
N10
N6
P3
M2
C1
E2
B4
M11
MF-LF 5 G S 4 2402
69 68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6 PP3V3_S0 2402
47 46 42 40 37 34 30 28 27 26
99 88 87 85 84 83 80 73 72
NO STUFF GMUX_S3_PD_EN
A 1
R9670 SYNC_MASTER=K17_REF SYNC_DATE=06/15/2009 A
10K PAGE TITLE
Q9607 D 6
1%
1/16W
MF-LF SSM6N15FEAPE Graphics MUX (GMUX)
SOT563
2 402 DRAWING NUMBER SIZE
GMUX_VSYNC 87 88 Apple Inc. <SCH_NUM> D

REVISION
2 G S 1 R
<E4LABEL>
ALL_SYS_PWRGD NOTICE OF PROPRIETARY PROPERTY: BRANCH
73 45 27 25 IN
<BRANCH>
96 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
*L9701, D9701, C9796, C9797, C9799, C9712 AND C9713 SHOULD ALL BE PLACED NEAR EACHOTHER.
*PPVOUT_S0_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.
* LVDS_IG_BKL_PWM SHOULD BE AWAY FROM BOOST CIRCUIT
D D
R9701
0
70 69 68 54 52 47 42 23 7 6 PP5V_S0 1 2
86 72
5% MIN_LINE_WIDTH=0.4 MM
1/16W MIN_NECK_WIDTH=0.2 MM
MF-LF VOLTAGE=5V
402
1
R9702
0
5%
1/16W
MF-LF
2 402 CRITICAL
CRITICAL
XW9700 L9701 D9701
SM
22UH-2.5A SOD-123
89 88 PPBUS_S0_LCDBKLT_PWR 1 2 PPVIN_BKL 1 2 PPBUS_S0_LCDBKLT_PWR_SW 1 2 PPVOUT_S0_LCDBKLT 6 56 83
MIN_LINE_WIDTH=0.5 MM MIN_LINE_WIDTH=0.5 MM MIN_LINE_WIDTH=0.5 MM
CRITICAL MIN_NECK_WIDTH=0.375 MM MIN_NECK_WIDTH=0.375 MM MIN_NECK_WIDTH=0.2 MM
1 C9712
1 C9713 VOLTAGE=8.4V IHLP2525CZ-SM
VOLTAGE=50V RB160M-60G CRITICAL CRITICAL VOLTAGE=50V
0.1UF NO STUFF
SWITCH_NODE=TRUE
1 C9796 1 C9797 1 C9799
10UF 10%
10% 2 25V 1 220PF 10UF 10UF
2 25V
X5R
X5R
402
R9703 10% 10% 10%
805 0 2 50V
X7R-CERM
50V
2 X5R
50V
2 X5R
5% 402 1210-1 1210-1
1/16W
MF-LF
2 402
BKL_VLDO
PPVIN_BKL_R
68 63 62 58 54 52 51 50 48
25 24 23 21 20 19 18 17 7 6PP3V3_S0 MIN_LINE_WIDTH=0.5 MM
47 46 42 40 37 34 30 28 27 26 MIN_NECK_WIDTH=0.2 MM
C
99 87 85 84 83 80 73 72 69
1 C9714
0.01UF
1 C9710
1UF
1 C9711
0.1UF
C
10% 10% 10%
2 16V
CERM 2 25V
X5R 2 16V
X5R
402 603-1 402
NO STUFF
C9741
1UF
1 2
VOLTAGE=5V
NO STUFF 10% NO STUFF
6.3V
22
23
X5R
C9740
8
402 CRITICAL
10UF R9740
1 2
47.0K2
1 VDDIO VLDO VIN
20%
6.3V
BKL_FLTR_RC 1%
1/16W U9701
X5R
MF-LF LLP
LP8545SQX
402
603
R9741 NC
6 GD SW 24
1
10K 2 R9717
BKL_FSET 5 FSET FB 21 10.2 2
5% 1 LED_RETURN_1 OUT 6 83
1/16W MIN_LINE_WIDTH=0.5 mm
MF-LF BKL_FLTR 20 FILTER OUT1 12 BKL_ISEN1 0.1% MIN_NECK_WIDTH=0.20 mm
402 MIN_LINE_WIDTH=0.5 mm 1/16W
MIN_NECK_WIDTH=0.20 mm TF
BKL_ISET 3 ISET OUT2 13 BKL_ISEN2 402
63 48 47 42 32 30 28 26 25 17 SMBUS_PCH_CLK R9753 0 1 2 BKL_SCL 10 SCLK OUT3 14 BKL_ISEN3 R9718

94 5% 1/16W MF-LF 402
10.2 2
BKL_SDA 11 SDA OUT4 16 BKL_ISEN4 1 LED_RETURN_2 OUT 6 83
MIN_NECK_WIDTH=0.20 mm 0.1% MIN_NECK_WIDTH=0.20 mm
B 48 47 42 32 30 28 26 25 17 SMBUS_PCH_DATA R9757 0 1 2 LVDS_BKL_PWM_RC 2 PWM OUT5 17 BKL_ISEN5 1/16W
TF B
94 63 5% 1/16W MF-LF 402
402
TP_BKL_FAULT 7 FAULT OUT6 18 BKL_ISEN6
R9731 R9719
89 88 PPBUS_S0_LCDBKLT_PWR 6 BKLT_EN 4 EN VSYNC 19 BKL_VSYNC_R 10.2 2
1 2
1 LED_RETURN_3 OUT 6 83
301K NO STUFF MIN_LINE_WIDTH=0.5 mm MIN_LINE_WIDTH=0.5 mm
1% NO STUFF 1 1 MIN_NECK_WIDTH=0.20 mm 0.1% MIN_NECK_WIDTH=0.20 mm
R9715 R9755 R9754 1/16W
1 GND_SW
1/16W 1 C9723 TF
2
9 GND_S
15 GND_L
MF-LF 10K 0 402
402 0.1UF 100K 5% 5%
10% 1% (EEPROM should set EN_I_RES=1) THRM
25V
2 X5R 1/16W PAD 1/16W
MF-LF
1/16W
MF-LF R9720
402 MF-LF
402 R97141 2 402 2 402 1
10.2 2
LED_RETURN_4
25
6 83
1
16.2K OUT
I_LED=23.2Ma MIN_LINE_WIDTH=0.5 mm
0.1%
1% MIN_NECK_WIDTH=0.20 mm MIN_NECK_WIDTH=0.20 mm
1/16W I_LED=369/Riset 1/16W
TF
MF-LF
402 2 402
R9704 R97161 Fpwm=9.62KhZ R9721
90.9K
LCD_BKLT_PWM 1
0 2 1% details in spec 1
10.2 2 LED_RETURN_5
87 6 IN 1/16W OUT 6 83
MF-LF MIN_LINE_WIDTH=0.5 mm MIN_LINE_WIDTH=0.5 mm
5% 402 2 MIN_NECK_WIDTH=0.20 mm 0.1% MIN_NECK_WIDTH=0.20 mm
1/16W
MF-LF
NO STUFF 1/16W
TF
402 1 C9704 402
R9704 SHOULD BE 47K IF RC FILTER IS USED 5%
33PF XW9710
SM R9722
50V
2 CERM 10.2 2
402 BKL_SGND 1 2 1 LED_RETURN_6 OUT 6 83
MIN_NECK_WIDTH=0.20 mm 0.1% MIN_NECK_WIDTH=0.20 mm
1/16W
TF
402
GMUX_VSYNC IN 87
A SYNC_MASTER=K18_BKLT SYNC_DATE=07/29/2009 A
PAGE TITLE
LCD BACKLIGHT DRIVER

DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
97 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CRITICAL
Q9806
FDC638APZ_SBMS001 PPBUS S0 LCDBkLT FET
CRITICAL SSOT6-HF
F9800
1 2 5 6
MOSFET FDC638APZ
2AMP-32V
4
82 70 69 67 66 65 49 40 7 6 PPBUS_G3H 1 2 PPBUS_S0_LCDBKLT_FUSED CHANNEL P-TYPE
D
86 IN
0402-HF
VOLTAGE=12.6V R9808 RDS(ON) 43 mOhm @4.5V
D
301K
1 C9802
1% 0.1UF LOADING 0.4 A (EDP)
10%
3
1/16W 16V
MF-LF 2 X5R
2 402 402
PBUS_S0_LCDBKLT_EN_DIV
1
R9809
147K
1%
1/16W
MF-LF
2 402
PBUS_S0_LCDBKLT_EN_L
Q9807 D 3
SSM6N15FEAPE
SOT563
5 G S 4 PPBUS_S0_LCDBKLT_PWR
OUT 88
89 87 8 IN LCD_BKLT_EN MIN_LINE_WIDTH=0.4 mm
BKLT_EN_L MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V
Q9807 D 6
SSM6N15FEAPE
SOT563
C 27 BKLT_PLT_RST_L 2 G S 1
C
IN
B B
LCD_BKLT_EN 8 87 89
1
R9840
4.7K
5%
1/16W
MF-LF
2 402
PAGE TITLE
LCD Backlight Support

DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>

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8 7 6 5 4 3 2 1

SCHEM,WHITE_ARROW,MLB,K18 <REV> <ECN> <ECO_DESCRIPTION> <ECODATE>

Table of Contents MASTER SMC Support K18_SENSORS CPU Constraints K17_REF

BOM Configuration K17_REF Current Sensing K18_SENSORS Ethernet Constraints K17_REF

Power Aliases MASTER Fan Connectors K19_MLB SMC Constraints K17_REF

PCH Grounds K17_REF 1.5V DDR3 Supply K18_POWER

PCH Non-GFX Decoupling K17_REF CPU IMVP VCore Regulator K18_POWER

CPU/PCH GFX Decoupling K17_REF GFX IMVP VCore Regulator K18_POWER

Clock (CK505) K17_MLB Misc Power Supplies K18_POWER

Chipset Support K17_REF Power FETs K18_POWER

DDR3 SO-DIMM Connector A MASTER Power Control K17_REF

DDR3 Byte/Bit Swaps MASTER NV GT216 PCI-E K17_REF

Front Flex Support K19_MLB LCD Backlight Support K19_MLB

Schematic / PCB #’s

Apple Inc. REVISION

820-2850 1 PCBF,WHITE_ARROW,MLB,K18 PCB CRITICAL

GPIO FDI DMI RTC

Apple Inc. <SCH_NUM> D

Mini PCI-E E-NET E-NET J6780,6781,6782,6700,6750

K17 POWER SYSTEM ARCHITECTURE SMC PWRGD

SMC_BATT_ISENSE GPUVCORE_EN GPUVCORE_PGOOD (PAGE 69)

ISL9522 SMC_CPU_ISENSE SYS_RERST#

1.103V(L/H) R5413 VOUT2 PPVTT_S0_DDR_LDO SM_DRAMPWROK

VIN P5VS0_EN P1V2GMUX_EN

U1800 LCD_BKLT_EN APP001 (PAGE 70)

RC P1V5DDR_EN THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc. <SCH_NUM> D

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

639-0952 PCBA,2.0G,512SAM_VRAM,K18 K18_COMMON,CPU_2_4GHZ,FB_256_SAMSUNG,K18_PVT,EEEE_DCJ7 138S0603 138S0602 ALL Murata alt to Samsung

D 639-0957 PCBA,2.4G,512HYN_VRAM,K18 K18_COMMON,CPU_2_66GHZ,FB_512_HYNIX,K18_PVT,EEEE_DCJF

353S2805 353S2603 ALL Fairchild wafer option

333S0542 333S0507 ALL Samsung I die alt to H

128S0264 128S0257 ALL Sanyo alt to Kemet

K18 BOM GROUPS TABLE_BOMGROUP_HEAD

K18_COMMON ALTERNATE,COMMON,K18_COMMON1,K18_COMMON2,K18_PROGPARTS,USBHUB_2061,RDRV:8515A2,DCI 128S0305 128S0294 ALL 6.3V alt to 11V Sanyo

BOM GROUP BOM OPTIONS

Bar Code Labels / EEE #’s

341T0233 1 IC,SMC,K18 U4900 CRITICAL SMC_PROG

335S0610 1 IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP U6100 CRITICAL BOOTROM_BLANK

341S2562 1 IC,EFI ROM,DEVELOPMENT,K18 U6100 CRITICAL BOOTROM_PROG

341S2384 1 IR,ENCORE II, CY7C63833-LFXC U4800 CRITICAL

336S0025 1 IC,XP2-5,HF,CPLD,BLANK U9600 CRITICAL GMUX_5K_BLANK

341S2566 1 IC,CPLD,LATTICE,132CSBGA,K18 U9600 CRITICAL GMUX_PROG

333S0535 4 IC,SDRAM,GDDR3,32MX32,1000MHZ,136 FBGA U8400,U8450,U8500,U8550 CRITICAL VRAM_512_HYNIX Apple Inc. <SCH_NUM> D

085-1404 1 K18 MLB DEVELOPMENT DEVEL CRITICAL DEVEL_BOM

I722 TRUE TP_ISSP_SCLK_P1_1 8 53

J6780 (MIC CONN) TRUE WS_KBD14 TRUE SMC_ONOFF_L

SPKRCONN_L_OUT_P I1063 TRUE SMBUS_SMC_A_S3_SCL 6 33 45 48 54 97 NC_DP_IG_D_AUXN MAKE_BASE=TRUE

SPKRCONN_R_OUT_N I1066 TRUE CONN_USB2_BT_P 33 99 17 6 NC_HDA_SDIN3 TRUE NC_HDA_SDIN3 6 17 MAKE_BASE=TRUE

SPKRCONN_S_OUT_P I1065 TRUE CONN_USB2_BT_N 33 99 MAKE_BASE=TRUE

C J9000 (LVDS CONN)

TRUE PP3V3_ENET 7 27 37 73 MAKE_BASE=TRUE NC_PCH_NC4 TRUE NC_PCH_NC4

TRUE PP3V3_FW_FWPHY 7 39 40 41 MAKE_BASE=TRUE NC_PCH_NC5 TRUE NC_PCH_NC5

I616 TRUE PP3V3_S5

TRUE PP3V42_G3H 6 7 17 21 23 43 45 46 47 48 49 MAKE_BASE=TRUE 20 6 NC_PCH_TP14 TRUE NC_PCH_TP14 6 20

J4501 (SATA HDD CONN) TRUE PCH_VSS_NCTF<15> 20 94

I1146 TRUE SMC_KDBLED_PRESENT_L 54 I1140 TRUE

6 17 Apple Inc. <SCH_NUM> D

FUNC_TEST 17 6 NC_PCIE_PE7_R2D_CP TRUE

STDOFF-4.5OD.98H-1.1-3.48-TH 91 74 9 PEG_R2D_C_P<15..0> =PEG_R2D_C_P<0..15>

1 84 18 8 DP_IG_HPD DP_IG_HPD 8 18 84 93 36 34 8 USB_SDCARD_P USB_SDCARD_P 8 34 36 93

SH0911 53 8 6 TP_ISSP_SCLK_P1_1 TP_ISSP_SCLK_P1_1 6 8 53

Apple Inc. <SCH_NUM> D