17EC322 CMOS VLSI DESIGN 3/0/0/3

Nature of Course :G (Theory & Analytical)

Pre requisites 17EC305- Digital Electronics
Course Objectives:
1 Introduce the basics of Integrated Circuits and fabrication process.
2 Familiarize the basics of CMOS transistors and its characteristics
3 Gain knowledge on CMOS logic structures
4 Impart knowledge on various combinational and sequential logic design.
5 Introduce concepts on semiconductor memories.
Course Outcomes:
Upon completion of the course, students shall have ability to
C602.1 Understand the basics of VLSI circuits and its impact in Industry. [R ]
C602.2 Analyzing the various CMOS fabrication techniques and applying for
[AP]
layout.
C602.3 Analyze the MOS transistor equations for presence of parasitic
[AN]
components.
C602.4 Design of various CMOS logic structures for analyzing at transistor level. [AN]
C602.5 Construction of Combinational and Sequential logic design based on
[AP]
timing analysis
C602.6 Analyzing the various semiconductor memories [AN]
Course Contents:
Issues and Challenges in Digital IC Design: Design hierarchy, Layers of abstraction, Integration
density and Moore’s law, VLSI design flow, MOS Transistor: Review of NMOS, PMOS, CMOS
Transistor, Second Order effects, CMOS Logic: Basic gates, Complex Gates, MOSFET fabrication:
NMOS Fabrication, CMOS P-well and N-well process, Silicon on Insulator, Stick Diagram, Layout
Diagram, Layout Design rules. Circuit Characterization: MOS Device Equations, CMOS Inverter
(DC Characteristics), Estimation of Resistance and Capacitance, Switching characteristics, Power
dissipation, CMOS Logic structures: Pseudo-nMOS, Dynamic CMOS, Clocked CMOS, Domino Logic,
Combinational Logic Design: Static CMOS , Ratioed Circuits, Pass Transistor, Transmission gate,
Cascade Voltage Switch Logic , Dynamic Logic Circuits. Sequential Circuits Design:
Classification, Parameters, Static Latches and Register, Race Condition, Dynamic Latches and
Registers, Two Phase vs. Single Phase clock designs, VHDL modelling for combinational and
sequential circuits.
Total Hours: 45
Text Books:
1 A.Pucknell, Kamran Eshraghian, “Basic VLSI Design”, Third Edition, Prentice Hall of
India, 2007.
2 N.Weste, K.Eshraghian, “Principles of CMOS VLSI Design”, Second Edition, Addision
Wesley, 2016
3 J.M. Rabaey, A. Chandrakasan and B. Nikolic, Digital Integrated Circuits- A Design
Perspective, Third Edition,Prentice Hall of India, 2016
Reference Books:
1 J. P. Uyemura, Introduction to VLSI Circuits and Systems, John Wiley & Sons (Asia),
2015.
2 W. Wolf, Modern VLSI Design - System on Chip design, Third Edition, Pearson
 Education, 2015.
3 D. A. Hodges, H. G. Jackson, R. Saleh, Analysis and Design of Digital Integrated
Circuits in Deep submicron Technology, Third Edition, McGraw Hill, 2005.
Web References:
1 https://www.tutorialspoint.com/vlsi_design/
2
https://electronicsforu.com/resources/learn-electronics/vlsi-developments-ic-
fabrication

3 http://www.vlsi-expert.com/p/vlsi-basic.html
4
https://www.engineersgarage.com/articles/vlsi-design-future
Online Resources:
1
https://www.youtube.com/watch?v=9SnR3M3CIm4

2
https://www.techopedia.com/definition/714/very-large-scale-integration-vlsi

3 www.techulator.com › Resources › Electronics › Circuits & Components

4 www.almamapper.com/library/notes/vlsi-electronics/
Assessment Methods & Levels (based on Blooms ’Taxonomy)
Formative assessment based on Capstone Model (Max. Marks:20)
Course
Bloom’s Level Assessment Component Marks
Outcome
C602.1 Remember Quiz 3
C602.2 Apply Group Assignment 3
C602.3 Understand Group Assignment 3
C602.4 Apply Problem solving 3
C602.5 Apply Simulation Exercise 3
C602.6 Apply Design 5
Summative assessment based on Continuous and End Semester Examination
Continuous Assessment End Semester
Bloom’s Level Examination[60
CIA1[6 Marks] CIA2[6 Marks] CIA3[8 Marks]
Marks]
Remember 20 20 10 10
Understand 60 40 40 40
Apply 20 40 30 30
Analyse - - 20 20
Evaluate - - - -
Create - - - -