ECEN 607 (ESS)

Texas A&M University

Edgar Sánchez-Sinencio
TI J. Kilby Chair Professor

1
Next we review the conventional Op Amp Design
frequency response compensation techniques
and also we introduced a simple LV Current-
Mode based Op Amp using resistors as
transconductors. Difference Differential
Amplifiers are also introduced.

2
 UNCOMPENSATED CMOS OPERATIONAL AMPLIFIER
VDD
M3 M4 1
M6
C p1 2 v o1 Node 3 is a low impedance
Vin M1 M2  High M8
V Cp2
in Impedance 3 vo
M5 M7 CL
Vbs M9

VSS AV3 ~ 1
M1=M2; M3=M4

Ignoring zeros we can model this topology as:

Vin + Input io1 1 Second io2 2 3

Output vo
 Stage Stage Stage
V -
R o1 C p1 Ro 2 Cp2 Ro 3 CL
in

g m1  gm6 g o 2  g 04 go6  go7

AV1 0   ; AV2 0   ;  p1  ;  p2 
g o1  g o 3 go6  go7 C p1 C p2
AV 1 0  AV 2 0  AV 3 0  g
AVT s   ;  p3  m 8
1  s  p1 1  s  p2 1  s  p3  CL
3
3
UNCOMPENSATED CMOS OPERATIONAL AMPLIFIER STABILITY
ISSUES

• The low frequency voltage gain is high enough for a number of

applications.

• The open loop poles are far from the origin, this can cause stability
problems for closed loop applications.

• Closed loop poles might end very close to the jw axis and some in
the RHP.

• How to tackle this stability problem will be discussed next.

4
Two-Stage Uncompensated Amplifier
VDD

M3 M4
M6

Io I o
2 2
M2 I6
 M1 
vin vin Ig
Vout

Io I7

M7
M5
VSS
Uncompensated Operational Amplifier
g m2 g m6 Large voltage gain
 A V  A V1A V 2 
g 02  g 04 g 06  g 07
 Poles are close to the j axis causing stability problems 5
5
 Employing a simple capacitor will split correctly the poles but will generate a
Zero in the RHP.

Using an RC compensation can eliminate the zero and split poles. The resistor
can be implemented with transistor in the ohmic region.
VDD

M3 M4 M8
A M6
M1
 M1 M2 0
Vout
v in CC M11 B
M9
M5
M7
v bias

VSS

Improved internally compensated CMOS operational

amplifier. Better bias for the output stage (M8 and M9)
6
Analog and Mixed Signal Center, TAMU (ESS) 6
A variation at the output stage with class – AB is shown below.
VDD
 -
M3 M4 vDS4 v GS6

M9 + I6
+
Io I o M6
2 2 v GS 9
  IL
vin M1 M2 v in M8
CL
CC
I10
Io
M7
+
Vbias v GS 7
M5 M10 -

VSS

CMOS op-amp with class-AB output stage and RC pole splitting.

7
7
“Pole Splitting” can be carried out with a compensation capacitor
feedback and a voltage buffer as shown below

M3 M4 M8
M10 M12
Ibias Out
  CC
vin M1 M2 vin

M7
M6 M9
M5 M11

Two-Stage amplifier with source follower compensation scheme

• Without M12 and M11 a zero in the PRH

• With buffer (voltage follower), zero is eliminated and pole splitting

8
(due to CC ) is kept. 8
An Improved Frequency Compensation
Technique for CMOS Operational Amplifiers
using Current Buffers

ECEN 607 (ESS)

Courtesy of Hatem Osman
Background.-
Two-Stage Op-amp with Miller compensation
• The first stage is a differential-input/single-ended output stage, and
the second stage is a class A or class AB inverting output stage.

Cc
• DC Gain
VIN,p
gm1 VOUT
VIN,n gm2

ro1 Cp ro2 CL

• Transfer Function

• Pole/zero locations

RHP zero

Dominant Pole

Non-dominant Pole
 Two-Stage Op-amp with Miller compensation
• Pole Splitting Cc
• Pole/zero locations
VIN,p
gm1 VOUT
VIN,n gm2

ro1 Cp ro2 CL

• Pole-zero position diagram

Increasing Cc achieves sufficient pole-splitting thus improving the PM. However, the
larger Cc shifts the RHP zero to lower frequencies thus ruining the PM.
 Miller Op-amp with Nulling Resistance
• Introducing a small series resistance in series with Cc may cancel the
RHP zero or shift it to the LHP.
Rc Cc
• Pole/zero locations
VIN,p
gm1 VOUT
VIN,n gm2

ro1 Cp ro2 CL

No zero
LHP zero – Can be used to cancel the
first non-dominant pole.

• Disadvantages:
• To achieve a sufficient phase margin, second pole cross-over of the unity gain
frequency should be avoided.

Thus, the Op-amp stability is severely degraded for capacitive loads of the same
order as compensation capacitor.
 Improved compensation technique
• The RHP zero is a result of the feed-forward path through Cc.

Cc

VIN,p V1
gm1 VOUT
VIN,n gm2

ro1 Cp ro2 CL

• The RHP zero can be eliminated if we cut the feed-forward path

and make the compensation capacitor unidirectional.
Virtual Ground

Cc
VIN,p V1
gm1 VOUT
VIN,n gm2

ro1 Cp ro2 CL
 Improved compensation technique

Virtual Ground

Cc • DC Gain
VIN,p V1
gm1 VOUT
VIN,n gm2

ro1 Cp ro2 CL

Dominant Pole

Non-dominant Pole
 Improved compensation technique

Miller compensation with nulling Improved compensation technique

resistance
Dominant pole Dominant pole

Non-dominant pole Non-dominant pole

Gain-bandwidth product Gain-bandwidth product

Phase margin Phase margin

 Circuit Implementation
• Miller compensation with nulling resistance.
VDD

VB,p VB,p
Mp,0 Mp,2

VIN,n VIN,p
Mp,1 Mp,1

Rc Cc VOUT

CL
Mn,1 Mn,1 Mn,2

VSS

• Improved compensation technique.

VDD

VB,p VB,p VB,p

Mp,0 Mp,3 Mp,2

Cc
VIN,n VIN,p
Mp,1 Mp,1
Mp,4
VOUT

CL
Mn,1 Mn,1 VB,n
Mn,3 Mn,2

VSS
 Other performance parameters- PSR
• Miller compensation with nulling resistance.
VDD

VB,p VB,p
Mp,0 Mp,2

VIN,n VIN,p
Mp,1 Mp,1

Rc Cc VOUT

VSS PSR
CL -20log(Av,0)

Mn,1 Mn,1 Mn,2 freq

fp1

VSS

• Improved compensation technique.

VDD

VB,p VB,p VB,p

Mp,0 Mp,3 Mp,2

Cc
VIN,n VIN,p
Mp,1 Mp,1
Mp,4

VSS PSR
VOUT

-20log(Av,0)
CL freq
Mn,1 Mn,1 VB,n fp1 1/ro1Cp GBW
Mn,3 Mn,2
• Better PSR at high
VSS frequencies.
 Design Example – Miller Compensation
• Design an OTA with GBW > 5MHz, CL=10pF, PM>70, and SR> 2
V/µs. • Choose Cc=CL/2= 5 pF.
VDD
• GBW > 5MHz
VB,p VB,p
Mp,0 Mp,2
• SR > 2 V/µS
VIN,n VIN,p
Mp,1 Mp,1

Rc VOUT • PM > 70°

Cc

CL
Mn,1 Mn,1 Mn,2 Let

VSS
Then

• Choose Rc > 1/gm2

 Design Example – Miller Compensation
• Simulation results

OL Transfer function Negative supply rejection

Positive supply rejection Transient step response

 Design Example – Miller Compensation
• Capacitive load driving capability

• PM > 70° for CL < 15 pF.

 Design Example – Improved Compensation
• Design an OTA with GBW > 5MHz, CL=10pF, PM>70, and SR> 2
V/µs. • Choose Cc=CL/2= 5 pF.
• GBW > 5MHz
VDD

VB,p VB,p VB,p

Mp,0 Mp,3 Mp,2 • SR > 2 V/µS
Cc
VIN,n VIN,p
Mp,1 Mp,1
Mp,4 In order to make the current transformer
VOUT biased during slewing interval

CL
Mn,1 Mn,1 VB,n
Mn,3 Mn,2 • PM > 70°

VSS
Let

Then

 Let’s use gm2=6gm1 like the miller Op-

amp to make a comparison between
the capacitive driving capability.
 For the same capacitive load driving
capability, the second stage will
consume less current making it suitable
for low power applications
 Design Example – Improved Compensation
• Simulation results

OL Transfer function Negative supply rejection

Positive supply rejection Transient step response

 Design Example – Improved Compensation
• Capacitive load driving capability

• PM > 70° for CL < 100 pF.

 Design Example – Improved Compensation
• Summary of Simulation results
Parameter Spec Miller Improved
Compensation Compensation
GBW > 5MHz 5.5 MHz 6 MHz

PM > 70° 75° 87.6°

SR+ > 2 V/µs 2.75 V/µs 3 V/µs

SR- > 2 V/µs 3 V/µs 3.15 V/µs

PSR- - -65.6 dB -51.9 dB

At (0-3.1 kHz) At (0-245.4 kHz)
PSR+ - -97.2 dB -37.2 dB
At (0-44 kHz) At (0-538.9 kHz)
DC gain - 64.5 dB 51.3 dB

Current - 80 µA 110 µA
consumption
Capacitive load - PM > 70° for PM > 70° for
driving capability CL < 15 pF CL < 100 pF
Using another current buffer Op Amp topology.

M3 M4 M7 M8

Ibias M12
 
v in M1 M2 v in
M11 Vout
CC

M6 M9 M10
M5

Two-Stage amplifier with Current Buffer compensation scheme.

• Improve SR at the expense of power consumption.

25
25
Differential Output Two Stage Amp with a capacitor compensation
with a current Buffer ( Common Gate)

26
27
Note that this and previous structure are fully differential but this approach
could be used for single output topologies.

Compensation using a current buffer ( current gain)

Note that the current-mirror introduces an extra inversion which must be taken
into consideration for the single ended version.
P.J. Hurst, Lewis, S.H. ; Keane, J.P. ; Aram, F. ; Dyer, K.C.
“ Miller compensation using current buffers in fully differential CMOS two-stage operational
amplifiers” IEEE Transactions on Circuits and Systems I, Volume: 51 , Issue: 2, Feb. 2004

28
 Besides the above zero the
amp has three poles

Elements of Current-Mirror Cc compensated

Note that the common-gate and current mirror topologies under ideal case are
almost identical, however in practice the one using current-mirrors is more power hungry
and has a larger parasitic capacitance CB

29
 Summary for Two Stage Op Amp Architecture Designs
• Roots close to the j axis for uncompensated
Q6
s p1 s p
Vin Vin CL
2

I bias
 I ss • Potentially unstable for some values of CL
Vbias
Q5 Q7 Ibias = CLSR*2.5

Q6
Q9 • Improved output stage optimal bias of Q6 and Q7
Vin
• No significant change of pole locations.
Vin Vo
I bias Av (0) -> +
 I ss
Vbias Q10
Q7 Av () -> -
Q5

Q6
Q9 Vo
Pole splitting => one dominant pole
Vin Vin CC  s
s p1 p2
z1
I bias
 I ss Q7 z1 Phase deteriorates phase margin
Vbias Q10
Q5 The good and the bad news
30
Analog and Mixed Signal Center, TAMU (ESS)
Two possible solutions to cancel z1 and keeping sp2 > t =GBW and sp1 small

Vo Vo

Vin Vin CC CL Q10

CC

I ss I ss
Q11
Vbias Vbias

Internally Compensated
Internally Compensated
with unity gain buffer
with RC CC
(Q10, Q11)
Operational Amplifier (conventional) Architectures.

Reader.- See the internally Op Amp compensated with current gain

buffer in previous pages
31
Analog and Mixed Signal Center, TAMU (ESS)
 Compared to two-stage Op Amp, folded cascode Op Amp has:
• Improved input common-mode range (ICMR)
• Improved power supply rejection (PSR)
• Push-pull output stage
• Self compensation

Folded-cascode Op Amp broken into stages

[Allen] 32
 Folded Cascode OpAmp

 The extended ICMR is achieved

 The bias currents I4 and I5 should be designed such that I6 and I7 never
goes to zero (i.e. 𝐼4,5 = 1.2𝐼3 → 1.5𝐼3 )
 Poor noise performance: In addition to the input transistors, transistors M4,5
and M10,11 generate significant current noise

33
 Small Signal Analysis

RA and RB are the resistances looking into the sources of M6 and M7

𝑟𝑑𝑠6 +1 𝑔𝑚10 1 𝑑𝑠7 𝑟 +𝑅𝐼𝐼 𝑅𝐼𝐼
𝑅𝐴 = ≈𝑔 and 𝑅𝐵 = 1+𝑔 ≈𝑔 where 𝑅𝐼𝐼 = 𝑔𝑚9 𝑟𝑑𝑠9 𝑟𝑑𝑠11
1+𝑔𝑚6 𝑟𝑑𝑠6 𝑚6 𝑚7 𝑟𝑑𝑠7 𝑚7 𝑟𝑑𝑠7

The currents 𝑖7 and 𝑖10 is expressed as

𝑔 (𝑟 𝑟𝑑𝑠5 ) 𝑣𝑖𝑛 𝑔 𝑣𝑖𝑛 𝑅𝐵
𝑖7 = 𝑅𝑚2+(𝑟𝑑𝑠2 𝑚2
= 𝑘+1 where 𝑘=𝑟
𝐵 𝑑𝑠2 𝑟𝑑𝑠5 ) 2 2 𝑑𝑠2 𝑟𝑑𝑠5
𝑔 (𝑟 𝑟𝑑𝑠4 ) 𝑣𝑖𝑛 𝑣𝑖𝑛
𝑖10 = − 𝑅𝑚1+(𝑟𝑑𝑠1 ≈ −𝑔𝑚1
𝐴 𝑑𝑠1 𝑟𝑑𝑠4 ) 2 2
Thus, the transfer function can be found as follows
𝑣𝑜𝑢𝑡 𝑔𝑚1 𝑔𝑚2 2+𝑘
= + 𝑅𝑜𝑢𝑡 = 𝑔 𝑅
𝑣𝑖𝑛 2 2 𝑘+1 2 + 2𝑘 𝑚1 𝑜𝑢𝑡
Where
𝑅𝑜𝑢𝑡 = 𝑔𝑚9 𝑟𝑑𝑠9 𝑟𝑑𝑠11 𝑔𝑚7 𝑟𝑑𝑠7 𝑟𝑑𝑠2 𝑟𝑑𝑠5
Where 𝑘 is the low-frequency unbalance factor
34
 Frequency Response
 The frequency response is dominated primarily by the output pole due to the high
output impedance
−1
𝑃𝑜𝑢𝑡 =
𝑅𝑜𝑢𝑡 𝐶𝑜𝑢𝑡
 In order to have sufficient phase margin, all other pole should be located will above
the GBW
1 𝑔𝑚6
Pole at source of M6 (Folding node) 𝑃𝐴 = − 𝑅 ≈ −𝐶
𝐴 𝐶𝑔𝑠 +2𝐶𝑏𝑑 𝑔𝑠 +2𝐶𝑏𝑑
1 𝑔𝑚7
Pole at source of M7 (Folding node) 𝑃𝐵 = − 𝑅 ≈ −𝐶
𝐵 𝐶𝑔𝑠 +2𝐶𝑏𝑑 𝑔𝑠 +2𝐶𝑏𝑑
𝑔
Pole at drain of M6 𝑃6 = − 2𝐶 𝑚10
𝑔𝑠 +2𝐶𝑏𝑑
𝑔𝑚8 𝑟𝑑𝑠8 𝑔𝑚10
Pole at source of M8 𝑃8 = − 𝐶𝑔𝑠 +𝐶𝑏𝑑
𝑔𝑚9
Pole at source of M9 𝑃9 = − 𝐶
𝑔𝑠 +𝐶𝑏𝑑

 Remarks:
We assumed 𝑅𝐵 ≈ 1 𝑔𝑚7 because at high frequency, where this pole has influence,
𝐶𝑜𝑢𝑡 shunts the drain of 𝑀7 to ground.
35
 Power Supply Rejection

The following model is used to calculate the

negative PSR
• The gate, source and drain of M11 varies with VSS
• The gate, source of M9 varies with Vss

The transfer function 𝑉𝑜𝑢𝑡 𝑉𝑠𝑠 can be found as

𝑉𝑜𝑢𝑡 𝑠𝐶𝑔𝑑9 𝑅𝑜𝑢𝑡
=
𝑉𝑠𝑠 𝑠𝐶𝑜𝑢𝑡 𝑅𝑜𝑢𝑡 +1

𝑃𝑆𝑅𝑅− can be calculated

𝐴𝑣 [Allen]
𝑃𝑆𝑅𝑅− =
𝑉𝑜𝑢𝑡 𝑉𝑠𝑠
Output stage of folded cascode OpAmp
36
 Power Supply Rejection

[Allen]

 At low frequency, we assume that other source of 𝑉𝑠𝑠 injection becomes

significant
 Low frequency PSRR- is at least as large as the magnitude of the
differential voltage gain 𝐴𝑣
 PSRR+ can be derived similarly: the primary source of injection is through 37
 Slew Rate

𝐼3
𝑆𝑅 + = 𝑆𝑅− =
𝐶𝐿
 The bias currents 𝐼4,5 should be designed such that 𝐼6,7 never goes to zero
𝐼4,5 = 1.2𝐼3 → 1.5𝐼5

38
 Maximum Available Output Swing

𝑉𝑜𝑢𝑡 𝑚𝑎𝑥 = 𝑉𝐷𝐷 − 𝑉𝑆𝐷5 − 𝑉𝑆𝐷7

𝑉𝑜𝑢𝑡 𝑚𝑖𝑛 = 𝑉𝑠𝑠 + 𝑉𝐷𝑆9 + 𝑉𝐷𝑆11
 The output common mode level 𝑉𝑜𝑐𝑚 is often dictated by the circuit that
interface with the amplifier (e.g. 𝑉𝑜𝑐𝑚 = 𝑉𝐷𝐷 2)

39
 Noise Analysis
 The noise current of M1, M4 and M10 goes directly to the output
 At low and medium frequencies, noise contribution of the cascode
transistors (M6 and M8) can be neglected
 Total output noise current becomes
2
𝑖𝑜𝑢𝑡 = 8𝐾𝑇𝛾 𝑔𝑚1 + 𝑔𝑚4 + 𝑔𝑚10
 Input referred noise density
2 8𝐾𝑇𝛾 𝑔𝑚4 𝑔𝑚10
𝑣𝑛,𝑖𝑛 = 1+ +
𝑔𝑚1 𝑔𝑚1 𝑔𝑚1

Half circuit model

40
 Folded Cascode Op Amp Design Procedure
 Design approach for the folded cascode Op Amp using long-channel model

[Allen]
41
 Design Example
 Design a folded cascode Op Amp to comply with the following
specifications using 0.18μm CMOS technology

Parameter Spec
Slew rate > 10 V μs
Load Capacitor 10pF
Power Supply ±1 V
Max/Min Output Voltage ±0.5 V
GBW > 10 MHz
Min Input CM Voltage −0.3 V
Max Input CM Voltage 1V
Differential Voltage Gain > 60 dB
Power Dissipation < 2 mW

42
 Design Example (Cont.)
 Solution:
 From the value of the slew rate we can get I3
I3 = SR × CL > 10 × 106 10 × 10−12  I3 ≥ 100μA
Select I3 = 120μA
 𝐼4,5 will be designed such that 𝐼6,7 never goes to zero
I4 = I5 = 1.2I3 to 1.5I3
Select I4 = I5 = 1.25I3 = 150μA
 Knowing 𝐼4 and 𝐼3 , we can get the quiescent, min, and max values of 𝐼6,7
𝐼6,𝑄 = 𝐼7,𝑄 = 𝐼4 − 0.5𝐼3 = 90𝜇𝐴
𝐼6 𝑚𝑖𝑛 = 𝐼7 𝑚𝑖𝑛 = 𝐼4 − 𝐼3 = 20𝜇𝐴
𝐼6 𝑚𝑎𝑥 = 𝐼7 𝑚𝑎𝑥 = 𝐼4 = 150𝜇𝐴
 From the min and maximum output voltages we can get overdrive voltage of
transistors 𝑀4−11
𝑉𝑆𝐷𝑠𝑎𝑡 4−7 𝑚𝑎𝑥 = 0.5 𝑉𝐷𝐷 − 𝑉𝑜𝑢𝑡 𝑚𝑎𝑥 = 0.25 𝑉
𝑉𝐷𝑆𝑠𝑎𝑡 8−11 𝑚𝑎𝑥 = 0.5 𝑉𝑜𝑢𝑡 𝑚𝑖𝑛 − 𝑉𝑆𝑆 = 0.25 𝑉

43
 Design Example (Cont.)
 The value of 𝐺𝐵 gives 𝑔𝑚1,2
𝑔𝑚1,2 = 𝐺𝐵 × 𝐶𝐿 ≥ 628.3 𝜇𝐴 𝑉
Thus, choose 𝑔𝑚1,2 = 700 𝜇𝐴 𝑉
From 𝑔𝑚1,2 and 𝐼1,2 , we can obtain 𝑉𝐷𝑆𝑠𝑎𝑡(1,2)
2𝐼1 𝐼
𝑉𝐷𝑆𝑠𝑎𝑡 1,2 =𝑔 = 𝑔 3 = 0.17 𝑉
𝑚1 𝑚1

 The minimum input common mode voltage defines 𝑉𝐷𝑆𝑠𝑎𝑡3

𝑉𝑖𝑐𝑚 𝑚𝑖𝑛 = 𝑉𝑆𝑆 + 𝑉𝐷𝑆𝑠𝑎𝑡(3) + 𝑉𝑇𝑛 + 𝑉𝐷𝑆𝑠𝑎𝑡 1
Thus, 𝑉𝐷𝑆𝑠𝑎𝑡 3 = 0.13𝜇𝐴 for 𝑉𝑇𝑛 = 0.4 𝑉

 We need to check that the maximum input common mode voltage is satisfied
𝑉𝑖𝑐𝑚 𝑚𝑎𝑥 = 𝑉𝐷𝐷 − 𝑉𝑆𝐷𝑠𝑎𝑡 4 + 𝑉𝑇𝑛 = 1.15 𝑉  Meets the spec

44
 Design Example (Cont.)
 Now, we have the bias currents 𝐼𝐷 and overdrive voltage 𝑉𝐷𝑆𝑠𝑎𝑡 of all the transistors.
Thus, we can obtain 𝑊 𝐿 of all the transistors from the ACM model or square-law
model if long-channel transistors are used.

 The channel length of the transistors should be chosen to satisfy the specified
voltage gain.

 The current flowing in transistors 𝑀6−11 can have any value from 20 𝜇𝐴 to
150 𝜇𝐴 depending on the amplitude and polarity of the differential input voltage.
Therefore, they should be sized such that the worst case 𝑉𝐷𝑆𝑠𝑎𝑡 of each transistor
meets the specified limits on the output voltages.

 Bias voltages of the cascode transistors 𝑉𝑃𝐵2 and 𝑉𝑁𝐵2 are chosen such that
𝑉𝑃𝐵2

45
 Simulation Results

 DC operating point
Transistor 𝑾 𝑳 𝑰𝑫 𝝁𝑨 𝑽𝑫𝑺𝒔𝒂𝒕
𝑀1,2 18 1 120 0.13
𝑀3 24 1 60 0.16
𝑀4,5 72 1 150 0.23
𝑀6,7 72 1 90 0.23
𝑀8,9 12 1 90 0.24
𝑀10,11 12 1 90 0.24

46
 Simulation Results

 Input common-mode range

ICMR testbench

Minimum input common mode voltage is 0.28 V

47
 Simulation Results

 Output Swing

Output Swing Testbench

The gain is perfectly linear for −0.5 ≤ 𝑉𝑜𝑢𝑡 ≤ 0.5

48
 Simulation Results

 Open loop response

Open loop response testbench

𝐴𝑣 > 60 𝑑𝐵
𝐺𝐵 > 10 𝑀𝐻𝑧

49
 Simulation Results

 Slew Rate

Slew-rate testbench

𝑆𝑅+ , 𝑆𝑅− > 10 𝑉 𝜇𝑠

50
 Simulation Results

 PSRR

PSRR+ testbench PSRR- testbench

51
 Summary of Results
 The following simulation results for 𝐶𝐿 = 10𝑝𝐹, 𝑉𝐷𝐷 = 1 𝑉 and 𝑉𝑆𝑆 = −1𝑉

Parameter Spec Simulation

SR+ > 10 V μs 11.3 V μs
SR- > 10 V μs 11.18 V μs
Max/Min Output Voltage ±0.5 V −0.65 → 0.61 𝑉
GBW > 10 MHz 10.7 𝑀𝐻𝑧
Min Input CM Voltage −0.3 V −0.28 𝑉
Max Input CM Voltage 1V 1𝑉
Differential Voltage Gain > 60 dB 62 𝑑𝐵
PSRR+ - 65.64 𝑑𝐵
PSRR- - 75.86 𝑑𝐵
Power Dissipation < 2 mW 840 𝜇𝑊

52
Techniques for Wideband Amplifiers
Focus the improvement in the load of the differential pair
R
Current Mirror Frequency Dependent
at the output load Current Mirror (FDCM)
CF >> Cgs
Conventional Wideband Alternative 0.1K < R < 1K
CF

Ib
CF

Low Frequency
Behavior
High Frequency
Behavior

T. Itakura and T. Iida, “A Feedforward Technique with Frequency-Dependent Current Mirrors for a Low-Voltage
Wideband Amplifier,” IEEE J. Solid-State Circuits, Vol. 31, No.6, pp. 847-849, June 1996. 53
An example of its use:

VDD
R3 Ib
M P3
M P4
M P1
vin M P2 vin vo
CF1
CL
CF2
M P3 M n1 M n4
R1 M n2 R2
 VSS

Wideband Amplifier with Feedforward Technique

• What is the optimal value of R1 as a function og GmP3 ?

• CF1 by passes two current mirrors.
• CF2 is fed forward to the input of another FDCM and signal
is amplified.
54
Next, we discuss different families of wideband reported in the
literature.

RL RL
M n3 vo vo M n4
• An alternative is to
connect CF instead
 M n2  to nodes B to nodes A
vin M n1 vin
A A
B B
CF RSS CF

F. Centurelli et al, “A Bootstrap Technique for Wideband Amplifiers,” IEEE Trans. on Circuits
And Systesm – I, Vol. 49, No. 10, pp. 1474-1480, October 2002
55
FOLDED-CASCODE WIDEBAND AMPLIFIER ( See page 11 for cascode)

Vb4
Vb4
M P4 M P3
R F1
M P2 Vb1 Vb1 M P1
  Vb1
Vb1 vin vin Vout
 
vin vin
C F1 C F2 Vb2 CL
C LVOUT
I tail M n5 I tail
Vb 2

M n3 M n4 M n3 M n4

Conventional Folded-Cascode (FC) FC with Capacitive Feedforward

V DD

R F1 R F2
Vb1 Vb1 Vb1
I bias Vo Vin
Vo C F1 Vo
CL C F2
CL
Vb 2 Vb 2

 VSS
Differential Wideband Amplifier
56
F. Opt Eynde, W. Sansen, “A CMOS Wideband Amplifier with 800MHz Bandwidth,” IEEE Custom Integrated Circuits Conf., pp. 9.1.1-9.1.4, 1991
 VDD
io+
M12 M5 M6 M14 OP

Vbias v+ X Figure 1 io-

ON
IB IB IB IB

B OP
ib
M1 M3 M8 V- X Figure 1
ON

-
R ON OP
X
vin A
ix io- io+ Fig 2
iR
Pseudo Differential Op Amp
M13 M2 M4 M9 M10 M11
VSS iR = Vin/R
iX = - iR
Fig. 1 Transconductance Amp
Basic Structure based on current-mode IB > iR
E.K.F. Lee, “ Low-Voltage Opamp Design and Differential Difference Amplifier Design Using Linear Transconductor with Resistor Input
, “ IEEE Trans. Circuits and Systems II,vol. 47, pp 776-778, Aug. 2000 57
 VDD
Transimpedance
amplifier
Vbias

CC
vo
io+
v+
Figure 2 io- R1
v-

R1

VSS

Fig 3 VCVS Amplifier: Op Amp

io1+
v1+
Transimpedance vo
Figure 2 io1-
amplifier
v1-
io2+
v2+
Figure 2 io2-
v2- DDA
58
 References

SS Rajput, SS Jamuar, Low voltage analog circuit design techniques, IEEE Circuits and
Systems Magazine, pp. 24-42, 2002
S. Yan and E. Sánchez-Sinencio, Low Voltage Analog Circuit Design Techniques: A Tutorial,
IEICE Trans. Fundamentals, Vol. E83-A, No. 2, pp 179-196, February 2000
E. Sánchez-Sinencio and Andreas G. Andreou, Eds. “ Low-Voltage/Low-Power Integrated
Circuits and Systems “, IEEE Press, Piscataway, NJ 1999
X. Xie, M.C. Schneider, E. Sanchez-Sinencio and S.H.K. Embabi, “ Sound Design of Low
Power Nested Transconductance-Capacitance Compensation Amplifiers”, IEE
Electronics Letters, Vol. 35, pp.956-958, June 1999.
A. Rodriguez-Vazquez and E. Sánchez-Sinencio, Eds., Special Issue on Low-Voltage and
Low-Power Analog and Mixed-Signal Circuits and Systems, IEEE Trans. on Circuits
and Systems I, vol. 42, No. 11, November 1995
J. Crols, J.; Steyaert, M.; Switched-opamp: an approach to realize full CMOS switched
capacitor circuits at very low power supply voltages” IEEE Journal of Solid-State
Circuits,, Volume: 29 , Issue: 8 , Aug. 1994 Pages:936 - 942

59
Analog & Mixed-Signal Center (AMSC)
 References

Very low-voltage analog signal processing based quasi-floating gate transistors,J

Ramirez-Angulo, AJ Lopez-Martin, RG Carvajal, et all, IEEE J. Solid-State Circuits, pp
434- 442, March 2004
Low threshold CMOS circuits with low standby current
Stan, M.R. Low Power Electronics and Design, 1998. Proceedings. 1998 International Symposium
on , 10-12 Aug. 1998 Pages:97 - 99
A dynamic threshold voltage MOSFET (DTMOS) for ultra low voltage operation Assaderaghi, F.;
Sinitsky, D.; Parke, S.; Bokor, J.; Ko, P.K.; Chenming Hu;
Electron Devices Meeting, 1994. Technical Digest., International , 11-14 Dec. 1994 Pages:809 -
812
Resizing rules for MOS analog-design reuse
Galup-Montoro, C.; Schneider, M.C.; Coitinho, R.M.;
Design & Test of Computers, IEEE ,Volume: 19 , Issue: 2 , March-April 2002 Pages:50 - 58
An MOS transistor model for analog circuit design .Cunha, A.I.A.; Schneider, M.C.; Galup-
Montoro, C.; Solid-State Circuits, IEEE Journal of ,Volume: 33 , Issue: 10 , Oct. 1998
Pages:1510 – 151
Series-parallel association of FET's for high gain and high frequency applications
Galup-Montoro, C.; Schneider, M.C.; Loss, I.J.B.; Solid-State Circuits, IEEE Journal 60
of ,Volume: 29 , Issue: 9 , Sept. 1994 Pages:1094 - 1101 Analog & Mixed-Signal Center (AMSC)
 References

S. M. Mallya abd J. H. Nevin, “ Design Procedures for a Fully Differential Folded Cascode CMOS
Operational Amplifier”, IEEE J. of Solid-State Circuits, Vol 24, No. 6, pp1737-1740,
December 1989.
D. B. Ribner, M. A. Copeland. and M. Milkovic, “8OMHz low offsetfully-differential and single-
ended opamps,” in Proc. IEEE Custom Integruted Circuits Con/., 1983, pp. 74-75.
This reference discusses three different Op Amp topologies:
S. Rabii and B. A. Wooley, “ A 1.8V-V Digital Audio Sigma-Delta Modulator in 0.8-um CMOS”,
IEEE J. of Solid-State Circuits, Vol. 32, N0. 6, pp. 783-796, June 1997
CMOS Analog Circuit Design, P.E. Allen, D.R. Holberg, Oxford University Press, 3rd
Edition, 2012

61
Analog & Mixed-Signal Center (AMSC)