ABSTRACT

In this Technical era the high speed and low area of VLSI chip are very- very
essential factors. Day by day number of transistors and other active and passive elements
are growing on VLSI chip. In Integral part of the processor adders play an important role.
In this paper we are using proposed kogge-stone adders for binary addition to reduce the
size and increase the efficiency or processors speed. In proposing Kogge stone adder we
use GDI (Gate Diffusion Input) technique, which provides less components, less path
delay and better speed compare to other existing kogge stone adder and other adders.
Here we are comparing the kogge stone adders with our proposed Kogge stone adder
using GDI technique. The design and experiment can be done by the aid of Tanner EDA
tool.
INTRODUCTION:

In processors and in digital circuit designs, adder is an important component. As a

result, adder is the main area of research in VLSI system design for improving the
performance of a digital system. The performance depends on power consumption and
delay. Adders are not only used for arithmetic operations, but also for calculating
addresses and indices. Adder is the device by which two or more than two bit information
can be added. These devices are need of hour for digital signal processing and image
signal processing. The propagation delay is played a very important role for digital signal
processing, image processing and other various suitable applications. The shorter the
propagation delay, the higher the speed of the circuit and vice-versa. Propagation delay
should be minimizing as possible as, for high efficient addition. For better explanation we
can take instance for N bit addition in which generally propagation delay is occurred
highly. When we add one high bit information(A0; A1; A2; A3) to another high bit
information(B0; B1; B2; B3), carry bit(C0; C1; C2; C3) is occurred due to normally
binary addition operation. This carry propagates to next bit and now bit addition is
performed by 3 bit adder. So carry will propagate to the next bit over and over, this cause
propagation delay will be occurred. We have principal component for 2 and 3 bit addition
such as half and full adder. There another serial and parallel adder to design fast
processing adder like compressor, Ripple carry adder, look ahead adder etc.
LITERATURE SURVEY:

1. “Design of Kogge-Stone for fast addition”, Athira.T.S, Divya.R, Karthik.M,

Manikandan.A.

In this paper, we propose a Kogge-Stone Adder (KSA) with low power

consumption and delay. Usually, Ripple Carry Adders (RCA) are preferred for
addition of two N-bit numbers as these RCAs provide fast design time among all
types of conventional methods. However, RCA’s have limitation that every full
adder blocks must wait till carry bits generated from previous blocks of full adder.
In this paper we implemented Kogge-Stone Adder which is a parallel prefix form
Carry Look Ahead (CLA) adder. Parallel prefix adders (PPA) are tree based
structure which speed up the binary addition. Hence prefix adders are used for fast
addition algorithms. The experimental result shows that the addition by using
Kogge-Stone Adder reduces power consumption and delay in comparison with
other conventional logics.

2. “Design the High Speed Kogge-Stone Adder by Using MUX”, Vishal Galphat,
Nitin Lonbale ECE Deptt, SBITM, Betul, M.P.

In this Technical era the high speed and low area of VLSI chip are very-
very essential factors. Day by day number of transistors and other active and
passive elements are growing on VLSI chip. In Integral part of the processor
adders play an important role. In this paper we are using proposed kogge-stone
adders for binary addition to reduce the size and increase the efficiency or
processors speed. Proposing kogge stone adder provides less components, less
path delay and better speed compare to other existing kogge stone adder and other
adders. Here we are comparing the kogge stone adders of different-different word
 size from other adders. The design and experiment can be done by the aid of
Xilinx 14.1i Spartan 3 device family.

3. “8-Bit Carry Lookahead Logarithmic KoggeStone Adder in CMOS 0.18µm

Technology”, Ivan Bilicki, Pavel Peev.

An 8-bit carry look ahead adder was designed. The design used a
logarithmic, Kogge-Stone approach, implemented using static CMOS logic in the
0.18µm technology. The layout was also designed, and it took 3557 um2 of area.
The worst case propagation delay was found to be 741 ps. For the carry output of
the adder, the worst case delay was found to be 666ps.

4. “A Low-power Methodology for configurable wide Kogge-stone adders”, Zahi

Moudallal, Ibrahim Issa, Mohammad Mansour, Ali Chehab and Ayman Kayssi.

We propose a methodology to reconfigure a wide KoggeStone (KS) adder

that is typically used in multimedia applications in order to minimize its power-
delay product. The goal of the methodology is to enable the designer to select the
best configuration to meet specifications in terms of power consumption, delay,
and area. We measure the variations of these metrics by investigating several
combinations of smaller KS adders connected in a ripple carry architecture. We
test various adder combinations by performing HSPICE simulations in 90nm static
CMOS. The results show that a designer can choose among different adder
architectures to achieve different objectives.
Existing method:

In VLSI technology, parallel prefix adders are known to be efficient. Adders use
the combinations of logic gates to combine binary values for obtaining the sum. The
adders are sub divided according to their ability to accept and combine the digits.
Parallel-Prefix adders perform parallel addition i.e. more important in microprocessors,
DSPs, mobile devices and in other high speed applications. The reduction of logic
complexity and delay by the Parallel Prefix Adders enhance the performance with factors
like delay and power. Therefore the Parallel- Prefix adders are the suitable element in the
high speed arithmetic circuits. Parallel prefix adders (PPA) are tree based structure which
speed up the binary addition. Hence prefix adders are used for fast addition algorithms.
The experimental result shows that the addition by using Kogge-Stone Adder reduces
power consumption and delay in comparison with other conventional logics.

Proposed method:

In the proposed method to reduce the area and timing analysis we go for GDI
(Gate Diffusion Input) technique in our Kogge-Stone Adder design. GDI (Gate Diffusion
Input) - a new technique of low power digital circuit design is described. This technique
allows reducing power consumption, delay and area of digital circuits, while maintaining
low complexity of logic design. Thus by using the GDI technique the performance of our
proposed design will be improved and there will be improvement in terms of area and
time.
Module explanation:

The Kogge-Stone adder concept was developed by Peter M. Kogge and Harold S.
Stone, which they published in 1973 in a seminal paper titled. KS adder is the special and
fast adder. Kogge stone adder is comprised with three units such as preprocessing, carry
generator and post processing unit.

PARALLEL PREFIX ADDERS:

The delay of Carry-Look Ahead adders can be resolved by employing the scheme
of parallel-prefix adders. This concept is to compute small group of intermediate prefixes
and then by finding the large group of prefixes, until all the carry bits are computed.
Parallel- prefix computation carries out three vital steps is given below:

1) Compute generates & propagates signals by using no. of input bits.

2) Calculate all the carry sequence in parallel that is called prefix computation.

3) Evaluate the final sum of given inputs.

Fig: Parallel Prefix Adder Computation.

Parallel Prefix Adders basically consists of 3 stages.

1. Pre- processing stage

2. Carry generation network

3. Post processing stage.

1. Pre-Processing Stage:

At this position we compute, generate and propagate signals to the pair of each
input A and B. These signals are given by the logic equations 1&2.

Pi = Ai x-or Bi ……….(1)

GI = Ai and Bi ……….(2)

2. Carry Generation Network:

At this stage we calculate carries corresponding to each bit. The Execution of

these operations is carried out in parallel manner. Carry propagate and generate are used
as an intermediate signals. The logic equations for carry propagate and generate are
shown below.

Pi:j = Pi:kand Pk-1:j ……………(3)

Gi:j = Gi:k or (Pi:kand Gk-1:j) …..(4)

3. Post Processing Stage:

To compute the sum bits for the given input bits,the logic equationsused are given below.

Ci = (Pi and Cin) or Gi ……(5)

Si = Pi xor Ci-1 ……………(6).

KOGGE-STONE ADDER:

Kogge-stone adder is a parallel prefix formation of Carry Look-ahead Adder.

Kogge -Stone adder can be showen as a parallel prefix adder consisting of carry operator
nodes. It is the fastest adder with based on designing time. It is the common choice for
high performance adders in industry. The Kogge-Stone Adder was first developed by
Peter M. Kogge and Harold S. Stone in 1973. The construction of 2, 4-bit Kogge-Stone
Adder are shown below.

Basic building block of KSA

 Fig: Architecture of 4-bit Pipeline Kogge-Stone Tree Adder

The pipeline architecture of 4-bit Kogge-Stone tree adder (i.e. 4-bit pipeline adder) is
shown in above figure. The 4-bit pipeline adder consists of 15 BUFFER cells, 6
AND/NAND cells, 8 XOR/XNOR cells, and 5 AO/AOI cells.

BASIC GDI FUNCTIONS:

GDI method is based on the use of a simple cell as shown in Fig. At a first glance
the basic cell reminds the standard CMOS inverter, but there are some important
differences:

Fig: GDI basic cell

 GDI cell contains 3 inputs - G (common gate input of nMOS and PMOS), P (input
to the source/drain of PMOS) and N (input to the source/drain of nMOS). It must be
remarked, that not all the functions are possible in standard p-well CMOS process, but
can be successfully implemented in twin-well CMOS or SO1 technologies.
REFERANCES:

1. “Design of Kogge-Stone for fast addition”, Athira.T.S, Divya.R, Karthik.M,

Manikandan.A.

2. “Design the High Speed Kogge-Stone Adder by Using MUX”, Vishal Galphat,
Nitin Lonbale ECE Deptt, SBITM, Betul, M.P.

3. “8-Bit Carry Lookahead Logarithmic KoggeStone Adder in CMOS 0.18µm

Technology”, Ivan Bilicki, Pavel Peev.

4. “A Low-power Methodology for configurable wide Kogge-stone adders”, Zahi

Moudallal, Ibrahim Issa, Mohammad Mansour, Ali Chehab and Ayman Kayssi.