EC601 - Digital System Design

EXPERIMENT 2
KIRAN MARU (15BEC061)

Lab-2 Gate level modeling using Verilog HDL

(Date - 22/1/2020)

Aim: -
Gate level modelling is another type of design process on Verilog where the boolean
expression for a particular function is not directly assigned in the code but is
represented as a circuit consisting of gates. These gates that are already the
modules in the software are used where just the type of gate used and the
interfacing of it is written in the code.

1. 1-bit full adder using gate level modeling

module p2_1(a,b,s,c1,c2);
input a,b,c1;
output s,c2;
wire x,y,z;
xor G1(x,a,b);
xor G2(s,c1,x);

and G3(y,a,b);
and G4(z,x,c1);
or G5(c2,y,z);
endmodule

 RTL level simulation with ModelSim

  Gate level

2. z2 = a’bc + abc + a’b’c

module exptwo2(a,b,z2,c);
input a,b,c;
output z2;

wire x,y,z,w,v;

not N1(x,a);
not N2(y,b);

and G1(z,a,b,c);
and G2(w,x,b,c);
and G3(v,x,y,c);

or G4(z2,w,z,v);
endmodule

 Gate level-
  RTL level simulation using ModelSim –

Result - In this experiment, 1 bit full adder and an another function was
implemented using gate level modeling unlike the previous experiment. It
was observed that I had to go one level ahead in the design flow chart
where gate level modeling is almost at the bottom or end. I was also able
to differentiate between switch and gate level modeling and when and
how both are used depending on the ease and requirement.