Prime Time Questions
1) What's PrimeTime?
Answer:
PrimeTime is a full chip static analysis tool that can fully analyze a multimill
ion gate ASIC in a short
amount of time.
2) What files are required for PrimeTime to run?
Answer:
PrimeTime needs four types of files before you can run it:
1. Netlist file: Verilog, VHDL, EDIF
2. Delay file: SPEF(standard parasitic format, it's from STARRC or place&route t
ool), SPF, SDF(standard delay format)
3. Library file: DB ( From library vendors)
4. Constrains file: Synopsys Design Constraints(SDC) include 3 min requirement,
clock, input delay and output delay
3) Can I use script in PrimeTime?
Answer: Yes, you should use tcl( Tool command language) whenever possible.
4) What PrimeTime check?
Answer:
PrimeTime will check the following violations:
1. Setup violations: The logic is too slow compare to the clock.
With that in mind there are several things a designer can do to fix the setu
p violations.
* Reduce the amount of buffering in the path.
* Replace buffers with 2 inverters place farther apart
* Reduce larger than normal capacitance on a book s output pin
* Increase the size of books to decrease the delay through the book.
* Make sure clock uncertainty is not to large for the technology library tha
t you
are using.
* Reduce clock speed. This is a poor design technique and should be used as
a
last resort.
2. hold time violations: the logic is too fast.
To fix hold violations in the design, the designer needs to simply add mor
e delay
to the data path. This can be done by
* Adding buffers/inverter pairs/delay cells to the data path.
* Decreasing the size of certain books in the data path. It is better to red
uce the books closer to the capture flip flop because there is less likely hood
of affecting other paths and causing new errors.
* Add more capacitance to the output pin of books with light capacitance.
Fix the setup time violation first, and then hold time violation. If hold
violations are not fixed before
the chip is made, more there is nothing that can be done post fabrication to fix
hold problems unlike setup violation where the clock speed can be reduced.
3. Transition Violations:
When a signal takes too long transiting from one logic level to another, a
transition violation is reported. The violation is a function of the node resis
tance and capacitance.
The designer has two simple solutions to fix the transitions violations.
* Increase the drive capacity of the book to increase the voltage swing or d
ecrease the capacitance and resistance by moving the source gate closer to sink
gate.
* Increase the width of the route at the violation instance pin. This will d
ecrease the resistance of the route and fix the transition violation
4. Capacitance Violations:
The capacitance on a node is a combination of the fan-out of the output pi
n and
the capacitance of the net. This check ensures that the device does not drive mo
re
capacitance than the device is characterized for.
* The violation can be removed by increasing the drive strength of the book
* By buffering the some of the fan-out paths to reduce the capacitance seen
by the output pin.
5) What conditions are used to check setup violation?
Answer:
WorstCase => setup violations
BestCase => hold violations
We use the worst case delay when testing for setup violations and then we use
the best case delay when testing for hold violations.
2) If there's a timing violation in the chip, how could you verify it as setup v
iolation or hold time?
Answer:
If the test engineer slow the clock speed, the chip passed the tested. It's a se
tup time problem. If the problem did not changes, it could be hold time issue.
Setup violations occurs when the data path is too slow compared to the clock spe
ed.
The designer can fix the setup violations by reducing the delay in the data path
. Designer can also reduce the clock speed to fix the setup violation, but it is
going to be a poor design technique.
Hold violations occurs when data is too fast when compared to the clock speed. I
f hold violations are not fixed before the chip is made, lot of problem occurs u
nlike setup violation where the clock speed can be reduced. To fix hold violatio
ns, designer can add more delay to the data path.
