Synthesis Topics covered

1. Asic Flow – Mani

2. Synthesis flows - Mani
3. inputs of synthesis - Mani
4. RTL to Netlist - Babu
5. Logical Synthesis - - Babu
6. Physical synthesis – - Babu
7. Synthesis tools – Gayu
8. d/b RTL VS DEF – Gayu
9. Delay modelling & calculation – Gayu
10. Pvt conditions – sunil
11. Types of delay models - sunil
12. timing library: - sunil
a. global definition
b. cell definition
c. pin definition
13. Rtl quality and their effect on netlist – Mahesh
14. synthesis optimization priority – Mahesh
15. Why DRV is occur? - Mahesh
16. syn outputs - Nishanth
17. syn opt priority - Nishanth
18. syn qulity check – Nishanth
19. SDC (d/b pre CTS & post CTS) – Rahul
20. Synthsis optimization:
21. Data path optimization(Carry save addition transformation) – Rahul
a. Load splitting and combo logic dupilcaiton - Rahul
b. Arithmatic expression optimization - - Ram
c. Parallel constant multiplier optimization - Ram
d. Boundary optimization – Ram
e. Scan registers - Sriharika
f. Register replication - Sriharika
g. Unresolved reference in Elaborate - Sriharika
h. Adaptive retiming - Tharun
i. Area optimization - Tharun
j. Power optimization - Tharun
22. Path grouping - Vaishnavi
23. Logical Depth - Vaishnavi
24. ICG concepts - Vaishnavi
25. UPF file (CLP) – Rahul
26. LEC - Vamsi
27. with respect to pvt/Ocv/Aocv - Vamsi
28. RC delay w.r.t register & capacitor – Vamsi
29. fan out (wns ) - Vinay
 30. Scan chain reodering -Vinay
31. Multibit register/banking (logic path) - Vinay
32. load spliting(cloning) – Somnath
33. fence, guide, region --> cadence - Somnath
34. Bounds/ blockages -->icc2 - Somnath
35. CRPR/CPPR –Manasa

PPt (Each topic)

1. Topic into
2. What
3. Why
4. How
5. Where
6. Log checks for Error and Warnings, Legalization issues, If cells are not placed inside core.
7. ISSUES:-
8. Problem Statement
9. Analysis
10. Debug
11. Solution