Comprehensive List of

Comprehensive List of
VLSI Topics For

Interview Preparation
https://www.linkedin.com/in/vivek-arya-532558143
Digital Electronics
1. Binary number system
20 Logic gates
levels
3. Logic
Go combination circuits
5. Sequential
circuits
6. Finite State machines
to sequence detector
8. Frequency divider/multiplyer circuit
Clock
9.
gating concepts
10.
PAL/PLAconcept
* 11.
*
Designing of combinational circuit and
sequential
circuits MUK
using
12. Semiconductor memories
13.
Logic family
Semiconductor Physics
10 PN junction
2. BJT
3.
Doping/impurities
bands
ya Energy
5. Fermi lad
6. Diffusion 8 Driftcurrent
7.
Mobility
80 Depletion region
9. sever dioce
10 -
e-type A p-type materials

1. Ammobile ions
Basic Network theory

/8 Basic of R,4,
Basic KCL
2. of
AVL,
3. theorems
Network
4. RC fircuits
5. Filters -> LPF
HDF
BPF
BSF
APF
6. 1st order RC/RL circuits
70 Nodal analysis, mesh analysis
8. Power
analysis -
instanious power
Average powe
power factor
9. Two-portNetwork
Analog Circuit Design
/o Basic of BIT, diode
2a OPAMP - Non
inverting amplifier
->
Inverting amplifier
adder/substractor
->
->
Differentiator / Integrator
-> log/Antilog
3. Feedback amplifier
4. oscillators
50 comparator circuit
60 Schmitttrigger
7. filter deligh
80 Differential amplifier
4. Current mirror firc't
100 Basic of MOSFET
↳ operation of
mosfet
↳> I character stics
↳
Region of operation
t
↓
cutoff, triode saturation

1/0 Common source, common gate and source
follower amplifiers
12. Phase Locked loop (PLL)
CMOS VLSI Design
10 of
Basic NMOS and PMOS
2 concepts of it a
in Mos
3. Input output characterstics
7. Region of operation
50
Body effect
Ga channel length modulation
7. WIL ratio concept
8. Cmos Enverter
9. Noee Margin
100
Designing combinational logicgates
and sequential circuit in CMOS
11. CMOS Pass Transistor
190 Transmission gate concept
130 Dynamic mos design
Rationed
14.
Logic
150 power dissipation in CMOS
↳ Dynamicpower
↳ short circ't power
↳ static power
160 CMOS fabrication process (Step by step)
17. Latch up concepts
18. Driving strength
19. PVT corners
90. short channel effect
Linux/Unic
/o Features of Linon Os
20 Linux commands you disk files
and directories.
managing
30 vi editor concept
5.
4.
Linus
scripting
shell
commands
-> bash, awk, sed
programming and
scripting
languagi
10 TCL spell smipting
90 procedure in commands.
3.
TCL I grep
regular expression
50
4.
How
file handling,
contral
Rw operation
(far, foreach, while
etc)
6. List and
Basic array
7.
of C /ct
8. OOPS concept
90
10.
Array, string, pointers, functions.
Data
types
Verilog HDL
1. Verilog data
types
po Verilog operators
30
4.
Gak fuel
modelling
Data flow
modelling
Structural
So
6a Task
modelling
and function
70 Write a testbench
verilog
80
qu
Delays, event contral.
user primitives (WDP]
defined
10. Generated blocks
system Verilog
1. Data types
2. Structures, Array
3. Task sfunctions
4. IPC (Inter procss communication)
5. Semaphall
6. Mailbox
7.
8 function
Randomization
coverage
9. System verilog Assertions
10.
Program clocking Block
11. Verification Environment
Universal verification
Methodology (UVM
1 UVM Basic
rum
20 reporting
3. urm factory
4. wum
sequences
5. UVM transaction level
modelling (TLM)
6. Uum transaction
7. Uum
configuration
8. Num testbench
↳ UVM Test
↳ rum Scrowboard
↳ urm environment
↳
wum agent
4 urm monitor
4 uum Sequencer
↳ uum driver
↳ Whm bass
↳ Uhm scoreboard
9. UVm callback
DFT (Design of testability)

1. What is DFT?
2. Basic of DFT.
3. Testing of VLSI circuits
4.
50
Fault
Fault
modelling
Simulation
scan chain
6a
Boundary
7. Built
in
Self Test(BIST), LBIST, MBIST
8: scan chain concepts
9. ATPG ·Automatic Test battern
Generation)
100 scan flip-flops
Layout Design
/o knowledge of fabrication steps
40 Metal stack
concepts
30 DRC Rules
4.
fingering concepts
5. Antenna effects
60
Electromigration concepts
7.
Latup concepts
8: stickdiagram
9. conceptof tracks, grid, site rows.
100 well
proximity
Standard cell
effect (WPE)
11.
layout design
Guard
19.
ringconcepts
13. LVS
Kayout
Us schematic)
Static timing Analysis(STA)
1. Basic of timing
analysis
20 Input outputfiles far STA
3.
Timing arcs
4. Delay concept-> Net

delay
↳ cell
delay
5.
timing
models - gate day models
models
-> clay
not
60 setup /Hold concepts
7.
Fixing Setup/old Violation
I.
Timing paths
9. timing checks
10
timing exceptions
I
timing constraints
reports
10
timing
PUT
L
13. corners
140 OCU, AOCU, and POCV
15. Global Setup S Hold time
16. Skews
latency
17. multi-mode multi corner analysis
180
signal integrity concept
19. Crosstalk analysis
200 CRPR (Clock Pessimism
Reconvergente
removal)
Time
210 Borrowing concept
22. SPEF, SDC,,:lib, SDF.
23. Uncertainty, fitter, minimum pulse width.
Physical Design
1.
Physical Design flow
20
3.
Floor
planning, power planning
Placement
40 tree
clock synthesis(CTS)
Routing
5j: signolf
Fo Physical only cells
↳
Tap cells
↳ The cells
↳ filler
cells
↳ Decap cells
↳ endcapcells
8. Low power cells far
concept-UPF, special
power planning
1 isolation cells
2. Level Shifter
3. Retention registers
4. Always on cells
9. LEF, files,
DEF tent files, its, lib,V
10.
Timing library checks
11 v
LVS, DRC, ERC
120 Hard macross softmacros
130 IR Drop
140 Temperation version
15.
Congestion Analysis
power
16. analysis
170 NUT, LVT, SUT Cells
18. NDR Rules
Hard
19. Blockages ->
->soft
-> partial
20. Macro placementguidling

21 Latup-up - whatis Latch-up ?
-> Reason for it
-> How to fix it.
22. Electro Whatis eM?
migration -
-> Reason far it

-> How to fix it.
23. Antenna effect -> What is antenna effect?

-> reason far it.
How to fix it.
-
24. synthers -> Translation
->
logicoptimization
->
Mapping
25. synthesisHow
26. Goalof synthesis
27. Types of Floorplan
Extra tobiss
10 Basic FIFO concept
2. Protocols-UART, I2C, SPI, AMBA
3.
4.
Metastability
Clock domain
concept
(CDC)
crossing
5. LINT concept
6. Aptitude
70 SRAM
Memory
-
->
DRAM
-> RIW operation
8. EDA tools
↳ PNR tools-synopsys /C2
↳ timing-prime
time
I layout-cadence virtuoso
4 Simulation -
Vilinuvivado, US
↳
Synthesis-synopsys design complier

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Comprehensive List of

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Copyright:

Available Formats

Comprehensive List of

VLSI Topics For

Designing of combinational circuit and

e-type A p-type materials

Basic Network theory

cutoff, triode saturation

DFT (Design of testability)

4. Delay concept-> Net

20. Macro placementguidling

-> Reason far it

23. Antenna effect -> What is antenna effect?

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