Industrial Manual Final

LIST OF AUTHORS
Sr. # Name Date Modified Contributions

1 First Author of Electronics
Prof. Azhar
- Experiments used in this
Hussain Shah
manual.
2 First Author of Logic Design
Prof. Salman
- Experiments used in this
Aslam
manual.
3  Selection and
compilation of
experiments from
different Electronics
Manuals.
Engr. Reda
23rd Feb 2018  Modification/addition
Gelani
and formatting of
content of existing
experiments.
 Definition of rubrics
for lab assessment.
4
5
6
7
8
9
10
11
INDUSTRIAL ELECTRONICS LAB MANUAL 1

LABORATORY MANUAL
EXPERIMENTS IN
INDUSTRIAL ELECTRONICS
Revised December 2018
Engr. Reda Gelani

Assistant Professor of Electrical Engineering
University of Central Punjab, Lahore

EXPERIMENTS IN
INDUSTRIAL ELECTRONICS
Copyrights © reserved with the author.
This book or parts, thereof, may not be reproduced in any form without the
permission of the author.
Printed in Pakistan, January 2017.
PREFACE

Azhar Hussain Shah is a professor of Electrical Engineering at the University of Central Punjab
(UCP), Lahore, Pakistan. He was born in Lahore, Pakistan and got his MS Electrical Engineering
degree from Loyola University of Los-Angeles, California, USA.
Before joining the teaching profession, Azhar Hussain Shah had extensive experience in
Industrial sector and he had worked in the companies like Litton Industries, Lear Seigher
Corporation and Westing House in USA in such diverse areas as Flight Control Systems (F-16
Manned and Un-manned Aircrafts, Drones etc), Inertialy Guided and weapon delivery control
systems (Meraj Aircraft, Cobra Helicopter, Cruise Missile etc). Industrial process control and in
using sensors, controllers and final control elements (Valves, Actuators, Motor drives etc)
Azhar Hussain Shah entered teaching profession in 1980 by joining Department of Electrical
Engineering, University of Engineering & Technology, Lahore. He served as Chairman Library
and Project Director of the following projects,
1. National Library of Engineering Sciences:

Engineering University Library was made National Library of Engineering Sciences to
serve as a Center of Excellence for promotion of research activities in the field of
engineering by connecting rest of the engineering universities of Pakistan using WAN for
information exchange. Project was funded by Higher Education Commission (HEC) of
Pakistan.
2. Networking of the University of Engineering & Technology:
LAN was established in all the departments, hostels, administrative and medical
buildings using fiber optic and wireless communication systems. This project was also
funded by Higher Education Commission (HEC) of Pakistan.
Azhar Hussain Shah retired as Chairman Electrical Engineering department, University of
Engineering and Technology, Lahore in the year 2005.
Azhar Hussain Shah is also the author of Laboratory manuals as below;
1. Power Electronics
2. Instrumentation & Measurements
3. Integrated Electronic Circuits
4. Network Analysis
INTRODUCTION

This Electronics Manual presents a series of experiments in which a thorough practical
investigation is made of basic electronics components/ circuits and the principles defining their
behavior. Diodes, Transistors (BJT and FET’s), operational amplifiers and digital logic design
are the main topics of discussion. The projects are arranged in a logical sequence and the content
in each project is based upon concepts developed in preceding projects. The projects have been
planned with the following objectives:
1. To have all the essential hardware assembled on each panel so that students need not to
concern themselves with time wasting procurements of parts needed for a given
experiment.
2. To devise projects that verify the principles of electronics theory and to include self-
teaching features in the projects because of which, the students can observe a step by step
pattern or structure of related ideas. This cultivates the analytical power of students.
3. To present each project with introductory information of a theoretical nature essential for
an insight into the manner in which theory and practice are bridged.
4. At the conclusion of each project, the teacher is required to make sure that the students
write a brief report regarding the electrical principle or law under discussion, and indicate
the particular aspects of the project which reveals this law to them. It is also suggested
that in the preparation of such a report, the students should include the list of the
components involved. This will develop a familiarization with the standard nomenclature
associated with typical components.
I wish to thank Col. Zia ul Islam and Engr. Rida Gilani who made constructive changes
while teaching this course.
Azhar Hussain Shah

Author
TABLE OF CONENTS
SR. Experiment Name Page

No. No.
To Study the V-I Characteristics of a semi-conductor
1 Diode.
7
To demonstrate the use of a Semiconductor Diode as a

2 half wave-rectifier.
15
3 To demonstrate the use of a Semiconductor Diode as a 21

full wave-rectifier.
To study the use of four diodes in a bridge as a full
4 wave-rectifier.
30
To demonstrate the operation of simple capacitor filter

5 and RC filter for half wave and full Wave Rectifier.
35
To investigate the Electrical Operation of Basic

6 Logical “AND” and “OR” Gates.
43
To plot the Zener Diode Characteristics and to

7 determine the Zener regulation under varying load and 52
with varying applied voltage.
Transistor Familiarization and function behavior.
8 60
Static check out of a Transistor using an Ohm meter.
9 Common-Base Characteristics 91
Common-Emitter Characteristics /
10 95
Common-Collector Characteristics
To investigate drain characteristics of Juntction Field
11 Effect Transistors (JFET).
101
To investigate drain characteristics of Metal Oxide

12 Semiconductor Field Effect Transistor (MOSFET)
111
13 To investigate the use of op amp as: 121

a. Voltage follower
b. Inverting amplifier
c. Non inverting amplifier
To investigate the use of op amp as:
14 a. Summing circuit
129
b. Difference amplifier
To investigate and verify the operation of basic logic
15 gates
135
Design and implementation of decimal to binary

16 encoder
148
Design and Implementation of 2-to-4, 3-to-8 and BCD

17 155
to seven segment display Decoders using Logic gates.
Design and implementation of 2-to-1, 4-to-1
18 Multiplexer and 1-to-4 Demultiplexer Circuits using 165
Logic gates
EXPERIMENT # 1
TO STUDY THE CHARACTERSTICS OF A SEMI-

CONDUCTOR DIODE
EQUIPMENT:
1. Experiment Panel
2. Regulated Power Supply

3. VOAM
4. Connecting leads
INTRODUCTION:
When an N-Type semiconductor is bounded to a P-Type semiconductor, a junction is formed as

shown in Fig.1.1 (a). This is known as junction diode. The diode has a unique characteristic of
the ability to pass in one direction only. The diode symbol and physical shape are shown in
Fig.1.2 (b) and Fig1.1(c) respectively.
Figure 1.1
THE IDEAL DIODE
We begin our study of circuits by considering models of linear elements, the simplest of these
being the resistor. The volt-ampere (v-i) characteristics of ideal resistor are described by such a
simple relation, (ohm’s law), that we sometimes lose sight of its graphical interpretation. The
linear character of the resistance is evident in Fig1.2. The v-i characteristics of an ideal diode are
shown in Fig1.3. The non-linear character of the diode is clearly evident there.

Fig.1.2 The resistance element and its V-I characteristics
When the source voltage is positive, id is positive and the diode is a short circuit vd = 0), while
when Vs is negative id is zero and the diode is open circuit (Vd = Vs). The diode can be thought
of as a switch controlled by the polarity of the source voltage. The switch is closed for positive
source voltage and opens for negative source voltage.
Figure 1.3. The ideal Characteristics of a Diode
Another way to look at this element is to note that the diode conducts current only from p to n, as
shown in Fig.1.3, and conduction takes place only when the source voltage is positive. The diode
does not conduct when the source voltage is negative.
Physical diodes have inherent characteristics and limitations that cause them to differ from the
ideal. These are to be studied in the following experiment.
PROCEDURE:
1. Connect the circuit as shown in Fig.1.4.

Fig.1.4
2. Set the function and range switch of VOAM to 1.25 Volt DC.
3. Rotate the voltage control knobs on the regulated supply to full counter clockwise (ccw)
direction, and turn on the power supply.
4. Adjust the output dc voltage of the regulated power supply by carefully using the coarse and
fine voltage control knobs, until the VOAM reads 0.025 Volt. This is the voltage across
diode, Vd. Record this voltage in the appropriate column in Table 1.1
5. Measure the corresponding value of current indicated on the millimeter. This is the diode
current Id. Record this current also in an appropriate column in Table-1.1. Also record the
corresponding supply voltage in the table.
Caution: The needle of the millimeter should indicate the portion of a scale. Three
millimeters of different sizes are installed on the experiment panel. Use a millimeter of
appropriate range always.
6. Perform step 4 and 5 repeatedly. Increase the diode voltage Vd in small increments of an
appropriate size, so as to get a smooth curve v between Vd and Id.
Fig.1.5
7. Connect the circuit shown in Fig.1.5.
8. Set the function and range switch of VOAM to 50 Volt DC.

9. Rotate the voltage control knobs on the regulated supply to full converter clockwise (ccw)
direction, and turn on the power supply.
10. Adjust the output dc voltage of the regulated power supply by carefully using the coarse and
fine voltage control knobs, until the VOAM reads 1 Volt. This is the voltage across diode,
Vd. Record this voltage in the appropriate column in Table 1.2
13. Perform step 11 and 12 repeatedly. Increase the diode voltage Vd in small increments of an
appropriate size, so as to get a smooth curve v between Vd and Id.
14. Set the output voltage of the power supply equal to zero by rotating the voltage control knobs
in fully counter clockwise direction, and turn the power supply off.
OBSERVATION AND CALCULATIONS:

TABLE 1.1
Diode Diode DC Diode Power Power Power
Voltage Current Supply Forward Dissipated Dissipated Supplied
(Vd) (Id) Voltage Residence in Diode in
(Vs) Resistor

Diode Diode DC Diode Power Power Power
Voltage Current Supply Forward Dissipated Dissipated Supplied
(Vd) (Id) Vo0ltage Residence in Diode in Resistor
(Vs)

GRAPH
1. Calculate for remaining columns of Table 1.1 and Table 1.2

2. Draw V-I characteristics of the diode under test, using the information collected in Table 1.1
and Table 1.2 on the same graph paper. Take care of the signs of V d and Id for forward and
reverse bias conditions of the diode. Use appropriate scales to accommodate the readings in
first and third quadrants. Label each portion of the characteristic properly.
3. From the forward characteristics, what is the value of cut-in-voltage of the diode.
_______ Volt.
4. Repeat the above experiment for the extra diode supplied to you.
5. From the forward characteristics, what is the value of cut in voltage of the second diode.
_______ Volt.
CONCLUSION
____________________________________________________________________________
____________________________________________________________________________
____________________________________________________________________________
____________________________________________________________________________
Task:
After going through questions and answers related to the experiment, submit a separate report
which should include the analysis of the result of the experiment.
Teacher / Supervisor’s Signature: __________________________________
Date: ____________________________
EXPERIMENT # 2
TO DEMONSTRATE THE USE OF A SEMICONDUCTOR
DIODE AS A HALF WAVE RECTIFIER
EQUIPMENT:
1. Experimental Panel
2. Oscilloscope
3. VOAM
4. Connecting Leads
THEORY REFRESHER:
One of the principal applications of the diode is in the production of a DC
voltage from an AC supply, a process called rectification. A rectifying circuit converts AC
voltage into pulsating DC voltage. Fig2-1 shows half-wave rectifier circuits using an ideal diode
and the resulting half-wave rectified output voltages developed. When the input AC voltage is
positive (-ve to -ve is measured from top to bottom of the voltage source) for the circuit
connection of fig-1a, the polarity of voltage across the diode will cause the diode to conduct, that
is the voltage across the diode is +ve to –ve from anode to cathode and in the case of ideal diode
the forward resistance is zero. The positive half cycle of the input signal then appears across the
resistor as shown in fig2.1.a. When the input voltage is negative (measured from top to bottom of
the voltage source) in fig2.1.a, the diode is reversed biased, having then infinite resistance and
appearing as an open circuit. Since there can be no current flow during the complete time that the
voltage at the input causes the diode to be reverse biased, the voltage across the resistor is zero.
The resulting output signal across the resistor due to half cycle of diode conduction and the lack
of signal during the half cycle of diode non-conduction is shown in Fig2.1.a.
Fig2.1.a Positive Half wave rectifier circuit

Fig2.1.b Positive Half wave rectifier circuit
Notice that although this signal is not steady DC (it is pulsating DC), it nevertheless has an
average positive value 1. If the sinusoidal voltage from the power line were applied to a DC
voltmeter the reading obtained would be zero. With the pulsating DC applied to a DC meter
there will be reading representing the average of the applied signal. For the diode connection of
Fig2.1.a, the diode allows only the positive half cycle to appear at the output. Reversing the
direction of the diode as shown in Fig2.1.b, results in only the negative half cycles.
HALF-WAVE AVERAGE DC VOLTAGE:
To determine the average value of the rectified signal, we can calculate the area under the curve
of Fig2-2 and divide this value by the period of the rectified wave form. To calculate the area
under the half cycle of the rectified signal we must integrate the rectified signal.
Fig2-2 Half wave rectified Voltage showing DC value

Doing this process and dividing by the period results in
V dc =0.318 V m (half wave)

Where V dc =average value of the rectified voltage
V m = maximum (peak) value of AC voltage.
HALF-WAVE PEAK INVERSE VOLTAGE (PIV):

An important diode rating is the peak inverse voltage, PIV of the diode (the maximum voltage
across the diode in the direction to block current flow). For the half wave rectifier circuit of fig2-
3 the peak voltage across the diode when the diode is reverse biased is equal to V m in the value.
PROCEDURE:
1. Connect the circuit as shown in Fig2-3 and see that the current indicated on M3 is within
the range of meter. The voltmeter should also read properly.
2. Connect one of the probe of oscilloscope across the output terminals (AC input to the
circuit) of the voltage transformer. Connect the second probe across the load resistor R7.
Caution: Leave the ground lead of one of the probe open.
3. Turn on the oscilloscope and set the channel selector to “Dual” and type of coupling to
“DC” and view both of the beams simultaneously, with voltage sensitivity set to 5
volts/cm.
Fig2-3 Half wave rectifier circuit

4. If one of the beam is displaying half wave rectified output, your circuit is functioning
properly, then go ahead with the rest of the procedure. Otherwise go to step one and
recheck your connections.
5. Set the function and range switch of VOAM at 10 volts AC.
6. Measure the AC voltage Vac across the output terminals of the voltage transfer, using
VOAM, VOAM will read the rms value of the AC input voltage.
Vac(rms)=______________ volt.
7. Calculate the peak value, Vp of the AC input voltage. Also calculate the average (half
wave) value of the ac input voltage.
Vav(input)=______________ volts. Vp(calculated)=___________volts.
8. Measure the peak value of the output voltage Vp with the help of oscilloscope and
calculate Vav(output) thereform.
Vp(measured)=______________ volts. Vp(output)=__________ volts.
9. Measure the DC current indicated on the ammeter M3.
Idc= ________________mA.
10. Measure the DC voltage across the load resistor R7 with the help of VOAM.
Vdc= ________________mA.
11. Calculate the peak current Ip through the diode and the load resistor R7.
Ip= ________________mA.
12. Calculate the DC output voltage across the load resistor R7 using V av =I dc × R 7 . Compare
this value with the value of the V av measured in step 8.
Vav=______________ volts
13. Calculate the DC current Iav through the load resistor R7 using V av found in step 12 and
also check that this value corresponds with the value of Idc measured in step 9.
Iav=______________ mA
14. From the peak value Vp of the AC input voltage obtained in step 7, calculate the average
value of the input voltage by using the expression.

Vav(input)=______________ volts. Vav(input)=___________ volts.
15. Refer to step 8 for the output voltage developed across R7. Subtract this value from the
average value of the input voltage V av obtained in step 7. The difference of these
twovalues is the average voltage drop across the diode.
Vdiode=______________ volts
16. Refer to the I-V characteristics obtained in experiment 1. Determine the voltage drop
across the diode which corresponds to the DC current through the diode, obtained in step
8.
Vdiode(calculated)=___________ volts
17. While the coupling switch is in DC position. Draw the waveforms displayed on the
oscilloscope in scope chart shown on the next page. Indicate the peak, rms and average
values of the half wave rectified output voltage wave form as well as the input voltage
waveform.
Vp=______________ volts. Vp-p=______________ volts.
Vrms=______________ volts. Vavg(input)=_________ volts.
Output voltage waveform:

Vp=______________ volts. V avg(ouput)=___________ volts
Vrms(input)=______________ volts

Fig2-4 Scope Chart
18. Connect one probe of the oscilloscope across the diode, (the ground lead at the node
between diode & M3). Remove the second probe. Observe the wave form and measure
the peak value. This is the peak inverse voltage (PIV) across the diode.
CONCLUSION:
Please attach the separate sheet.

1. Define and calculate the efficiency of the half-wave rectifier circuit shown in Fig.2.1.
Assume ideal diodes.
2. Define and calculate the percentage ripple in the half-wave rectifier circuit shown in
Fig.2.1. Assume ideal diodes.
3. What is meant by PIV rating of a diode. What is the value of PIV required in a half-wave
rectifier circuit.
4. Compare all corresponding calculated and measured values obtained in this experiment.
Give explanation of your answers.

______________________________________________________________________
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________
Task:
Teacher / Supervisor’s Signature: ______________________
Date: _________________________
EXPERIMENT # 3
TO DEMONSTRATE THE USE OF TWO SEMICONDUCTOR
DIODES AS FULL-WAVE RECTIFICATION
EQUIPMENT:
1. Experiment Panel.
2. Oscilloscope.
3. VOAM.
4. Connecting Leads.
THEORY REFRESHER:
INTRODUCTION
In the previous experiment we note that although an average voltage is obtained using a half-
wave rectifier, no voltage is develop for the half of the cycle. Using two diodes as shown in
Fig3.1 (a), it is possible to rectify a sinusoidal signal to obtain one having the same polarity for
each of the half cycles of input signal. This is called full-wave rectification and it provides a
signal that has twice the dc value as compared to the previous half wave rectifier circuit. The full
wave rectifier circuit of Fig 3.1(a) requires a center tapped transformer and two diodes to
develop a full wave rectified output voltage.
Fig.3.1 (a) Full Wave Rectification Circuit Fig 3.1 (b) Equivalent Circuit

The circuit operation can be explained qualitatively if the ideal transformer is eliminated by
redrawing Fig 3.1(a) as shown in Fig 3.1(b). In this figure the transformer is seen to reflect the
ac source from the primary into the center tapped secondary circuit. When Vi is positive D1 is a
short circuit and D2 is an open circuit. When Vi is negative, D1 is an open circuit and D2 is a
short circuit. In each case the load current is in the same direction as shown in Fig 3.1 , and since
one or the other of the diodes D1 and D2 is short circuit on each alternate half cycle, the load
voltage can be written vL=[vi]. The currents and the wave forms are given in Fig.3.2.
Fig. 3.2
FULL-WAVE AVERAGE (DC) VOLTAGE

To determine the average value of the rectified signal we can calculate the area under the curve
of Fig3.3 and divide this value by the period of the rectified waveform. To calculate the area
under the full-cycle curve of the rectified signal we must integrate the rectified signal. Doing the
process and dividing by the period results in
Vdc=2(0.318Vm)=0.636Vm (full wave)

Where Vdc= average value of the rectified voltage and
Vm= maximum (peak) value of ac voltage.

Fig.3.3 Full-wave rectified voltage showing DC voltage
FULL-WAVE PEAK INVERSE VOLTAGE
The full-wave rectifier circuit of Fig3.1 has the advantage of developing a larger dc voltage for
the same peak voltage rating. It has however the disadvantage of requiring a diode rating of
twice the peak inverse voltage, and the center tapped transformer having twice the overall
voltage rating.
PROCEDURE:
1. Connect the circuit as shown in Fig.3.4 and see that the current indicated on M3 is
within the range of the meter. The voltmeter should also read properly.
2. Connect one of the probes of the oscilloscope across the output terminals (ac input to the
circuit) of the voltage transformer. Connect the second probe to the load resistor R7.
Leave the ground lead one of the probe open.

3. Turn on the oscilloscope and set the channel selector to “Dual: and the type of coupling
to “DC” and view both of beams simultaneously with voltage sensitivity set to 5
volts/cm.
4. If one the beams is displaying full-wave rectified output, your circuit is functioning
properly, then go ahead with the reset of the procedure. Other go to the step one and
recheck your connections.
5. Set the function and range switch of VOAM at 10 volts ac.
Fig-3.4 Full wave rectifier circuit.
6. Use VOAM to measure the ac voltage Vac across the output terminals of the voltage
transformer. VOAM will read the rms value of the ac voltages.
Vac(a-b) = _______________ volts.
Vac(b-c) = _______________ volts.

7. Measure the dc current Idc, indicated on milliammeter M3. This will be equal to the
average value of the full-wave rectified current Iav, through the load resistor R7.
Idc = _________________ mA.
8. Measure the dc voltage Vdc, across the load resistor, R7 indicated by the dc voltmeter
on the experiment panel. Also check that this value corresponds with the value of Vav
obtained in step 10.
Vdc = __________________ volts.
9. Calculate the peak value, vp of the ac input voltages measured in step 6.
Vp(a-b) = __________________ volts.
Vp(b-c) = __________________ volts.
10. Calculate the peak current Ip, through the load resistor R7, from the current measured in
step 7.
Ip = _________________ mA.
11. Calculate the average value of the full-wave rectified output voltage across the load
resistor R7. This is given by:
Vav = Idc*R7 = ___________ volts.
12. Calculate the output dc voltage across the load resistor, R7 by using.
Vdc = 0.636*Vp
Vdc = _________________ volts.
Vav = _________________ volts.
13. Refer to the step 8 for the average value of the output dc voltage develop across R7.
Subtract this value from the dc value of the input voltage Vdc obtained in step 12. The
difference of these two values is the average voltage drop across the diode in the forward
direction.
Vdiode = ________________ volts.
14. Refer to v-I characteristic obtained in experiment-1. Determine the voltage drop across
the diode which corresponds to the dc current through the diode, obtained in step7. How

would you this value with the value of Vdiode obtained in step 13. See question at the
end.
Vdiode(cal) = ________________ volts.
oscilloscope in Scope chart shown on the next page. Indicate the peak , rms and the
average values of the full-wave rectified output voltage waveform as well as the input
voltage waveform.
Input Voltage Waveform:

Vp(a-b) = _____________ volts.
Peak to Peak Voltage Vp-p = _____________ volts.
Vrms = _____________ volts.
Average Voltage Vav = _____________ volts.
Output Voltage Waveform:
Vp = _______________ volts.
Vav = _______________ volts.

Vrms = _____________ volts.
16. Connect probes of the oscilloscope across the diodes, (the ground lead at the node
between diodes and M3). Don’t connect the ground lead of the second probe. Draw the
waveforms and measure the peak values. These are the PIV values across the diodes.
PIV D1 = ________________ volts.
PIV D2 = ________________ volts.
CONCLUSION:
Please attach the separate sheet.
1. Define and calculate the efficiency of the full-wave rectifier circuit shown in Fig.3.1.
Assume ideal diodes.
2. Define and calculate the percentage ripple in the full-wave rectifier circuit shown in
Fig.3.1. Assume ideal diodes.

3. Why is the value of PIV in full-wave rectifier circuit, twice that for the half-wave circuit.
4. Compare the values obtained in step 8, 11, and 12. Explain your answers.
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________
Task:
After going through questions and answers related to the experiment, submit a separate
report which should include the analysis of the result of the experiment.
Teacher / Supervisor’s Signature: ______________________
Date: _________________________

EXPERIMENT # 4
TO STUDY THE USE OF FOUR DIODES (IN A BRIDGE) AS A

FULL-WAVE RECTIFIER.

EQUIPMENT:
1. Experiment Panel
2. Oscilloscope
3. VOAM
4. Connecting Leads
THEORY REFRESHER
Another circuit variation of a full-wave rectifier is the bridge circuit of Fig 4.1.
This circuit requires four diodes for full-wave rectification but the transformer used, is not
center-tapped and develops a maximum voltage of only V m. In addition, the diode PIV rating is
also one half of the two-diode full-wave rectifier circuit.
Fig. 4.1 Full-wave bridge rectifier circuit and its waveform

In considering how the circuit operates, one must understand how the conduction
and conduction paths are formed during each half of the ac cycle. During the positive half-cycle
the voltage across the transformer secondary (measured from top to bottom) is positive and the
conduction path is through D1 - R - D3. Since these diodes are forward biased, the voltage across
each is zero volts and the peak voltage from the transformer appears across load resistor, R, at
this time.

At the same time the voltage polarity is such as to reverse bias diodes D2 and D4. Therefore, the
non-conduction path during the positive half-cycle, will be through D 2 - R - D4. Load resistor has
a voltage developed across it by the current flowing through the conducting path of the diodes D 1
and D3.
SUMMARY
To summarize the operation of the bridge rectifier circuit, the addition of two extra diodes above
the number in the center-tapped full-wave circuit provides improvement in two main factors.
First, the transformer used need not to be center-tapped, requiring a maximum voltage across the
transformer of Vm. Second, the peak inverse voltage (PIV) required of each diode is half that for
the center-tapped full-wave circuit, only Vm. For low values of secondary maximum voltage the
center-tapped full wave circuit will be acceptable, whereas for high values of maximum
secondary voltage, the use of the bridge to reduce the maximum transformer rating and diode
PIV rating is usually necessary.
PROCEDURE:
1. Connect the circuit as shown in Fig-4.2 and see that the current indicated on M 3 is within the
range of the meter. The voltmeter should also read properly.
Fig. 4.2 Full-wave bridge rectifier circuit.

2. Connect one of the probes of the oscilloscope across the output terminals (ac input to the
circuit) of the voltage transformer. Connect the second probe across the load resistor R 7.
Leave the ground lead of one of the probes open.
3. Turn on the oscilloscope and set the channel selector to “CH 2” and type of coupling to “DC”
and view, the beam across R7, with voltage sensitivity set to 5 volts/cm.
4. If the beam is displaying full-wave rectified output, your circuits is functioning properly, and
then go ahead with the rest of the procedure. Otherwise go to step one and recheck your
connections.
5. Set the function and range switch of VOAM at 10 volts ac.
6. Use VOAM to measure the ac voltage Vac across the output terminals of the voltage
transformer. VOAM will read the rms value of the ac voltages.
Vac = __________ volts.
7. Measure the dc current Idc, indicated on milliammeter M3. This will be equal to the average
value of the full-wave rectified current, Iav, through the load resistor R7.
Idc = __________ mA.
8. Measure the dc voltage Vdc, across the load resistor, R7, indicated by the dc voltmeter M4, on
the experiment panel.
Vdc = __________ volts.
9. Calculate the paek value, Vp, of the ac input voltages measured in step 6.

Vp = __________ volts.
10. Calculate the peak current Ip, through the load resistor, R7, from the current measured in
step7.
11. Calculate the average value of the full-wave rectified output voltage across the load resistor,
R7, also check that this value corresponds with the value of V dc obtained in step 8. This is
given by equation given in observation and calculations.
Vav (out) = __________ volts.
12. Calculate the dc value (half-cycle average) of the input voltage from the maximum value of
Vp by equation given in observation and calculations.
Vdc (in) = __________ volts.
13. Refer to step 8 for the average value of the output dc voltage developed across R7. Subtract
this value from the dc value of the input voltage Vdc obtained in step 12.
Vdiff = __________ volts.
14. Refer to the v-I characteristic obtained in Experiment-1. Determine the voltage drop across
the diode which corresponds to the dc current through the diode, obtained in step 7.
Vdiode = __________ volts.
oscilloscope in Scope Chart shown. Indicate the peak, rms and average values of the full-
wave rectified output voltage waveform as well as the input voltage waveforms on scope
chart-1.
Input Voltage Waveform:

Vp = __________ volts. Vp-p = __________ volts.
Vrms = __________ volts. Vav = __________ volts.
Output Voltage Waveform:
Vp = __________ volts. Vav = __________ volts. Vrms = __________ volts.
16. Connect the probes of the oscilloscope at the nodes between D 1 & D2 and D3 & D4. Connect
the ground lead of one of the node between D 2 & D3. Draw the waveforms and measure the
peak values on scope chart-2. These are the PIV values across the diodes.
PIVD2 = __________ volts.
PIVD3 = __________ volts.
OBSERVATIONS AND CALCULATIONS:
Vav = Idc X R7 & Vdc = 0.636 X R7

GRAPH:
Scope Chart-1
Scope Chart-2
CONCLUSIONS
1. Compare all the rectifier circuits. Discuss merits and demerits of each. Assume ideal diodes.

2. Draw the conduction and non-conduction paths during positive as well as negative half-
cycles of the input ac signals.
3. Why is the value of PIV in a bridge rectifier circuit, half than that of the center-tapped full-
wave circuit?
4. Compare the values obtained instep 8, 11, 12? Explain your answer.
______________________________________________________________________
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______________________________________________________________________
Task:

EXPERIMENT # 5
Date: ____________________________
TO DEMONSTARTE THE OPERATION OF SIMPLE

CAPACITOR FILTER AND RC FILTER FOR HALF WAVE
AND FULL WAVE RECTIFIERS
EQUIPMENT:
5. Electronics-I Panel
6. Oscilloscope
7. VOAM
8. Connecting Leads
THEORY REFRESHER
A rectifier circuit will convert an ac voltage of zero average value to one that has
a non-zero average. However, the resulting pulsating dc voltage is not pure dc. This pulsating dc

source can be used to charge a battery or to run a dc motor but it cannot be used as a voltage
supply circuit for tape recorder or radio. The pulsating dc will result in a 50 or 100 Hz signal
appearing in the output, thereby making the operation of the overall circuit poor. For these
applications, as well as for many more, the output dc will have to be much “smoother” than that
of the pulsating dc obtained directly from half wave or full wave rectifier circuit.
SIMPLE CAPACITOR FILTER
A popular filter circuit is the simple capacitor filter shown in Figure-5.1. The capacitor is
connected across the output of the rectifier and the dc output voltage is available across the
capacitor.
The purpose of obtaining the dc voltage is to provide this voltage for use by other electronic
circuits, which then constitute a load on the voltage supply. Hence there will always be some
load on the filter.
Fig. 5.1 Rectifier circuit block diagram.

Figur5.2 (a) shows the rectifier output voltage of a full wave rectifier circuit before the signal is
filtered and Figure5.2 (b) shows the resulting waveform after the capacitor is connected across
the rectifier output. The filtered output voltage has a dc level with some ripple voltage riding on
it.
Fig. 5.2 Rectifier circuit with waveforms.
Figure5.3 shows the output waveform approximated by straight line charge and discharge.
Fig. 5.3 Rectifier approximated output waveform.

From the analysis of the above voltage waveform the relations given in observations and
calculations column can be obtained.
RC FILTER
It is possible to further reduce the amount of ripple across a filter capacitor while reducing the dc
voltage by using an additional RC filter as shown in Figure 5.4. The purpose of the added
network is to pass as much of dc component of the voltage across C1 and to attenuate as much of
the ac component of the ripple as possible.
Fig. 5.4 RC filter.

The operation of RC filter for full wave rectifier circuit is shown in Figure 5.5. Since the
rectifier feeds directly into the average current drawn from the supply, the voltage developed
across capacitor C1 is then further filtered by the resistor capacitor (R, C2) providing an output
voltage having less percentage of ripple than that across C1.

Fig. 5.5 RC filter.
The load, represented by resistor RL, draws dc current through resistor R with an output dc
voltage across the load being somewhat less than across C1 due to the voltage drop across R.
PROCEDURE:
1. Connect the circuit as shown in Fig5.6.
Fig. 5.6 RC filter.
2. Set the VOAM at 10 volts ac range and measure the input ac voltage.

Vac = __________ volts.
3. Measure and record the dc load current as indicated by M3.

Idc = __________ mAmps.
4. Calibrate the oscilloscope, observe the input and output waveforms and draw the
waveforms in graphs-1 (a) & (b).
Vo = __________ volts.
5. Measure the peak to peak ripple voltage as accurately as possible and record.
Vr (p-p) = __________ volts.
6. Calculate the ripple voltage using the formula and compare the result with step-5.
Vr (p-p) = __________ volts.
7. Replace R6 of 1K ohms with R8 of 470 ohms and measure peak to peak ripple.
Vr (p-p) = __________ volts.
8. Connect C9 in parallel with C2 and measure peak to peak ripple.
Vr (p-p) = __________ volts.

9. Connect the circuit per Figure5.7.

Fig. 5.7 Rectifier.
10. Repeat procedure steps 5, 7 and 8 for the circuit of figure-7 and record the results in
Table5.1.
11. Connect the circuit per figure-9.
Fig. 5.9 RC filter with rectifier.
12. Measure and record the dc voltage at point-A and point-B.
A = __________ volts. B = __________ volts.

13. Measure the peak to peak ripple voltage at point-A and point-B with oscilloscope and
record.
A = __________ volts. B = __________ volts.
14. Calculate the dc voltage and ripple voltage at point-A and point-B and compare with the
measured voltage and give your comments.
OBSERVATIONS AND CALCULATIONS:
From the analysis of Figure-5.3 voltage waveform the following relations can be obtained
V r ( p− p)
Vdc = Vm -
2
I dc V dc
Vr(p-p) = 2 fC = 2 fC R
L
Table 5.1
CIRCUIT Vr (p-p) RIPPLE FREQUENCY
Step 5 Step 7 Step 8
HALF WAVE
FULL WAVE

GRAPH:
Vo
Scope Chart-1

CONCLUSIONS
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Task:
Date: ____________________________

EXPERIMENT # 6
TO INVESTIGATE THE ELECTRICAL OPERATION OF BASIC

LOGICAL “AND” AND “OR” GATES
EQUIPMENT:
1. Experiment Panel
2. DC Power Supply
3. Signal Generator
4. VOAM
5. Connecting Leads
THEORY REFRESHER:
Logical Gates can be constructed from almost any type of switching device. In this experiment
the logical gates are constructed using semiconductor diodes.
Two types of logical gates that are widely used in digital computers are AND gates and OR
gates.
AND GATE:
An AND Gate must satisfy the following two logical conditions.
1. When all of its inputs are TRUE, the AND gate output must be TRUE.
2. If any input is FALSE, the AND gtae output must be FALSE.
A truth table can be constructed for an AND gate. Assume that a TRUE input is defined as “1”,
AND a FALSE input is defined as “0”.

Table 8. 1
INPUT A INPUT B OUTPUT
0 0 0
0 1 0
1 0 0
1 1 1

An AND gate may have as many inputs as required dependent only upon the electrical
limitations of the gate circuit.
An AND gate can be represented by a logical or Boolean equation. For instance, the function of
a two input AND gate may be expressed as follows:
A+B=X
The equation is read, “If A and B are TRUE, then X is TRUE”, or simply “X is equal to A AND
B”. Notice that X is the output of gate, and A and B are the inputs. The dot “.” Symbol is used to
represent the AND function. It is customary however, not to show the dot between the two
letters, but to simply place the letters side by side as “AB”.
The AND gate can also be represented by a graphical symbol as shown in figure 1.
Figure 8.1
The AND gate may actually be constructed using diodes as shown in Figure 8.2.

Figure 8.2
Assume in Figure 8.2 that TRUE= +5 volts, and FALSE = 0 volts. When both inputs to the
AND gate shown in Figure- 2 are 0 volts, both diodes are forward biased and conduct. Since the
forward drop across the diodes is very small (less than 1 volt) almost the entire +5 volts supply is
dropped across R and the output is approximately 0 volts, representing a logical FALSE. Note
that even if one of the inputs goes to +5 volts, the output will remain at 0 volts. However, when
both inputs are at -5 volts, both diodes are reversed biased and there is no current through the
resistor and hence no voltage drop across the resistor and the output will be +5 volts. It means
that the output is only TRUE when both the inputs are TRUE.
OR GATE:
An OR gate must satisfy the following two logical conditions.
1. If any input is TRUE, the OR gate output must be TRUE.

2. If all of its inputs are FALSE, the OR gate output must be FALSE.
The OR gate can also be logically demonstrated by means of a Truth Table.

Table 8.2
INPUT A INPUT B OUTPUT
0 0 0
0 1 1
1 0 1
1 1 1
The OR gate may have as many inputs as required dependent only upon the electrical limitations
of the gate circuit.
The OR gate can also be represented by a logical equation as follows:
A+B=X
The equation is read as “if Aor B is TRUE, then X is TRUE”, or simply, “X is equal to A or B”.
Notice that the plus sign “+” signifies the OR operation. The OR gate symbol is shown in Figure
8.3.
Figure 8.3

The OR gate may also be constructed using diodes as shown in Figure 8.4.
Figure 8. 4

Again assume that TRUE = +5 volts, and FALSE = 0 volts. When both inputs to the OR gate
shown in Figure- 4 are 0 volts, neither diode conducts, and the drop across R remains 0 volts
representing a FALSE output. However, when either or both of the inputs goes to
+5 volts, one or both diodes conduct causing a drop across the R. Since the diode forward drop is
small, almost the entire +5 input appears across R and the gate output is TRUE. Thus, when
either or both inputs to the OR gate are TRUE, the OR gate output is TRUE. Under the
remaining condition when both gate inputs are FALSE, the gate output is FALSE.
PROCEDURE:
PART- 1 “AND” GATE:
1. Connect the circuit shown in Figure-8. 5
Figure 8.5
2. Measure and record the values of Vo for all the combinations of values of A & B in Table
8.3.
Table 8. 3

A (VOLTS) B (VOLTS) Vo (VOLTS)
0 0
0 +5
+5 0
+5 +5

3. Apply ac signal of 4 volts peak to peak, 1 KHz. Sine wave at input A.
4. Apply 0 volts at input B; measure and record the output Vo.

5. Apply +5 volts at input B, measure and record the output Vo.
PART- 2 “OR” GATE
6. Connect the circuit as shown in Figure 8.6.
Figure- 8.6
7. Measure and record the values of Vo for all the combinations of values of A and B in
Table 8.4.
Table 8.4
A (VOLTS) B (VOLTS) Vo (VOLTS)
0 0
0 +5
+5 0
+5 +5

8. Apply ac signal of 4 volts peak to peak, 1 KHz. Sine wave at input A.
9. Measure and record the output voltage Vo for input B at 0 volts.
10. Measure and record the output voltage Vo for input B at +5 volts.
11. Write down your comments about the results of procedure steps 4, 5, 9 and 10.
OBSERVATIONS AND CALCULATIONS
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CONCLUSIONS:
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Task:
Date: ____________________________

EXPERIMENT # 7
TO PLOT THE ZENER DIODE CHARACTERISTICS AND TO

DETERMINE THE ZENER REGULATION UNDER
VARYING LOAD AND WITH VARYING APPLIED
VOLTAGE
EQUIPMENT:
1. Experiment Panel
2. VOAM
3. Oscilloscope
4. Variable dc supply
5. Connecting Leads
THEORY REFRESHER:
Zener diodes are semiconductors pn-junction diodes with controlled reverse bias properties
which make them extremely useful in many applications, especially as voltage reference
devices. A typical VI characteristic is shown in Figure 10.1.

Figure 10.1
In most applications, the Zener diode operates in the break down region. A typical
application is a simple voltage regulator circuit shown in Figure 10.2.
Figure 10. 2
If input supply voltage is greater than the Zener diode break down voltage, the diode breaks
down and the voltage across the diode remains nearly constant. Resistance R limits the current
through the Zener diode to save it from burning.

PROCEDURE:
PART- 1 CHARACTERISTICS
Figure 10.3
2. Turn on the dc supply. Slowly adjust the dc supply and measure the zener diode
voltage with the help of VOAM and record in Table 10.1.
Table 10.1
Iz (mA) Vz (Volts) Vin (Volts)
0.5
1.0
2.0
4.0
6.0
8.0

10.0
15.0
20.0
30.0
You will observe that the Zener voltage variation is very small as compared to input
voltage variation.
3. Draw the VI characteristics from Table- 1 on the graph paper.
PART- II REGULATION:
4. Connect the circuit as in Figure 10.4.
Figure 10.4

5. Set R1 to maximum resistance.
6. Adjust the input supply at 20 volts.
7. Vary R1 and adjust IL indicated on M2 as shown in Table- 2, measure and record the
voltages and currents in Table 8.2.
8. Observe that when the load current approaches the total current, the voltage across the
load begins to decrease and the regulation is lost.
9. Plot Thevenin Equivalent Load T1, Thevenin Equivalent Voltage Vton a graph paper
and find thevenin’s equivalent circuit resistance and source voltage from the plot.
10. Rth ________________ ohms, Vth ______________ volts
Table 8.2
I load (mA) I total (mA) Vin (Volts) Vz (Volts) Iz (mA)
10

Figure 10.5
12. Adjust the variable dc voltage per Table- 3 and enter the current indicated on M3 and
load voltage across R2.
Table 10.3
Vs (Volts) IT (mA) VL (Volts)
15
16
17
18
19
20
25

13. Make the input voltage equal to Zener voltage, slowly decrease the applied voltage to
zero and observe that the Zener voltage follows the applied voltage since the Zener
diode no longer regulate.
PART- III RIPPLE REDUCTION
14. Connect the circuit as Figure 10.6.
Figure 10.6
15. Connect the oscilloscope across the filter capacitor C2 and measure the peak to peak
ripple voltage. _____________ volts
16. Connect the oscilloscope across the output terminals (across R2), measure and record
peak to peak ripple voltage at the output terminals. _________ volts
17. Measure and record the current indicated on m2, which is the load current for the
filter capacitor C2. ____________ mA.
18. Calculate the ripple voltage across filter capacitor C2 using the relationship.
IL
V r ( p− p)=
f .C

19. Write down your comments about the results of Table 1, 2, 3 and procedure step 15.
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CONCLUSIONS:
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______________________________________________________________________

Task:
Date: ____________________________
EXPERIMENT # 8

TRANSISTOR FAMILIARIZATION AND JUNCTION
BEHAVIOUR
PURPOSE
1. To familiarize the student with transistor biasing and circuit connections.

2. To investigate the behavior of the transistor emitter base junction and the collector base
junction under forward and reverse bias conditions.
EQUIPMENT:
1. Experiment Panel
2. VOAM
3. Connecting leads
INTRODUCTION:
There are two types of BJTs; one is called as NPN and the other as PNP. Both silicon and
germanium semiconductors are used for making NPN and PNP devices. However, silicon
semiconductor is extensively used because of its superior characteristics at higher temperature.

Figure 11.1 (a) An NPN – BJT with its circuit symbol on left. (b) A PNP-BJT with its circuit symbol on left. Double plus
sign on n (or P) shows heaviest doping. One plus sign shows heavy doping and no sign shows light doping
The collector region has the largest area, next comes the emitter region which is fairly large but
the base region has the smallest area. There are two junctions, one between the emitter and the
base (BEJ), the other between base and collector (BCJ) each associated with their depletion
region. The depletion layers extend more in the base-region compared to emitter and collector
regions because depletion layer always extends more in the highly doped region compared to the
heavily doped region, as a mobile carrier, say an electron crosses from N to P side (where N-
region is heavily doped and P- region is lightly doped), it will have to travel a long distance to
find a hole to recombine.
The schematic symbols for PNP and NPN transistors are shown to the left of Fig.11.1 (a) and (b)
where the element with arrow is the emitter and its symmetrical counterpart is the collector. The
PNP transistor is characterized by the fact that the emitter arrow points to the base, where as the
arrow points away from the base in NPN type. Note the electron current flow inside the transistor
is opposite to the direction of the arrow.
BIASING OF JUNCTIONS
Since a bipolar junction transistor has two junctions, Base emitter junction (BEJ) and Base
collector junction (BCJ), so there are four possibilities of biasing them and they result into four
modes of operation of a transistor. These four modes are:

1. Saturation mode where BEJ and BCJ are both forward biased.
2. Active mode (amplification mode) where BEJ is forward biased and BCJ is reverse
biased.
3. Cut off mode, where BEJ and BCJ are both reverse biased.
4. Inverse mode, where BEJ is reverse biased and BCJ is forward biased.
We shall mainly be concerned in this course with active mode of operation or amplification
mode which is used for amplification of voltage or current signals or both.
TRANSISTOR EMITTER-BASE JUNCTION
The emitter base junction of a PNP transistor is forward biased whenever the emitter is made
positive with respect to the base. This junction is reverse biased when emitter is negative with
respect to the base. These conditions are illustrated in fig. 2a and 2b respectively.
FIGURE 11.2 (a): Emitter- Base Junction Forward Biased

FIGURE 11.2 (b): Emitter – Base Junction Reverse Biased
Transistor bias is a flow of current rather than voltage since it is the movement of carriers
through the P-N junction which determines the transistor’s operation point.
It is useful to remember that a transistor junction is forward biased when the positive “P”
terminal of the bias battery is connected to the “P” material of the junction and the negative “N”
terminal of the bias battery is connected to the N material. This rule applies to both emitter base
and collector base junction of both PNP and NPN transistor.
TRANSISTOR COLLECTOR-BASE JUNCTION
The collector base junction of a PNP transistor is forward biased whenever the collector is
positive with respect to the base and reverse biased when collector is negative with respect to the
base. These conditions are illustrated in Fig11.3a and 11.3b.

FIGURE 11.3(a): Collector – Base Junction Forward Biased
FIGURE 11.3(b): Collector Base Junction Reverse Biased
TRANSISTOR ACTION IN ACTIVE MODE

When BEJ and BCJ of a transistor are either forward biased or reverse biased one at a time,
while leaving the other junction unbiased each of them behave as a PN-junction diode. Once we
bias both the junction of a transistor simultaneously then a very surprising thing happens.
The base emitter junction (BEJ) is forward biased. The holes of P-types emitter will move to N-
type base, where they are treated as minority carriers (N-type base has holes as minority
carriers). The holes are in abundance near the BEJ compared to a very few holes (thermally
generated) near the BCJ. Such an imbalance will always result in diffusion of holes from BEJ
towards BCJ.
Since BCJ is reverse-biased so its associated electric field will help the holes (minority carriers
in base) to be swept across the BCJ and migrate to collector region. Since the base region is very
thin and lightly doped, so most of the holes coming from emitter region will eventually be able to
reach the collector region, however there will always be a few holes which will not be able to
reach the collector region and will combine with electrons (majority carriers in N-type) and
constitute base current. Refer to fig. 4, when 10 holes cross from emitter into base, one hole
combines with one electron in base and the remaining 9 holes diffuse towards BCJ and finally
reach the collector region which amounts to an imbalance charge condition in collector region,
so that 9 additional holes in collector region will be pulled out of collector region by the negative
terminal of VCC. This will restore the original charge balance in the collector region. Similarly,
the positive terminal of Vcc will be forced to point 9 holes to leave. In the mean time 1 hole that
combines with 1 electron in the base region amount to a loss of one negative charge in the base
region. Therefore, one electron must enter into the base region which is provided by the negative
terminal of VEE which will pull one hole out of the base region.

FIGURE 11.4: An actively biased PNP- transistor. The BEJ is forward biased by VEE and the BCJ is reverse-biased by
Vcc. The two switches S1 and S2 are closed. The depletion region across BEJ is reduced but across BOJ is enlarged.
TRANSISTORS SYMBOLS, BASING AND MOUNTING
There are many types of transistors. These may be classified according to the basic material from
which they are formed. In this category we find germanium and silicon resistors. Most transistors
are now made of silicon. Transistor may be classified also according to the process by which
they are constructed.
Here we find various types of junction transistors such as grown junction, alloy junction, drifted
field, mesa, epitaxial mesa and planar transistors and point contact transistors. Transistors my
also be classified according to the number of elements. Thus there are the triodes, or three
element transistors and the tetrode or four element transistors. Transistors may also be classified
according to their ability to dissipate power. Here we find wide range from the low power (less
than go mw) to the high power (2w and higher) type.

FIGURE 11.5 some transistor shapes
Transistors come in different shapes and sizes (see Fig.11.5). There are variations also in the
basing arguments and in the manner of mounting the transistor in the circuit. Some are socket
mounted, confirm to the physical basing of the transistor. Some transistors have flexible leads for
soldering directly into the circuit.
Two methods are generally used for bringing transistor connections out of the envelope. The first
employs long, flexible leads. An example of this is the transistor shown in Fig. 11.6a. The three
leads are all in line and may be identified as emitter, base and collector in the order shown. The
collector spacing is greater than that of two elements. A variation of this system also uses three
in line leads. The collector is identified by a red dot which is painted close to it on the transistor
case as in Fig.11.6b. The usual method for connecting the transistor of Fig. 11.3a and b into the
circuit is to solder the flexible leads to the proper terminals in the circuit.
The second method uses rigid pins for bringing transistor connections out of the envelope as in
Fig (a). This is a plug in type of transistor and requires a matching socket to hold it. Another
basing arrangement permits the selection of either the first or second mounting method. In this
case, the transistor is supplied with flexible leads welded to rigid base pins.

FIGURE 11.6: Methods of identifying transistor leads
The supplied with flexible leads welded to rigid base pins. The flexible leads are used if the
transistor is to be soldered into the circuit. If a socket is to be used, the flexible leads are easily
removed with a pair of cutters. A triangular type of socket and basing arrangement used on other
socket mounted transistors (Fig. 11.4b and c) is also used. The connection layout duplicates the
accepted transistor diagram configuration.
FIGURE 11.7(a): Plug in transistor, Triangular biasing identification (b): Biasing diagram (Bottom View) (c): Socket

FIGURE 11.8: Typical transistor biasing and socket arrangements. Other physical arrangements of transistor biasing
and socket arrangements are shown in Figure -8
Transistors are rated according to their ability to dissipate power. Thus a transistor used as a low
level audio amplifier may have a power rating which is low, say 50MW. A transistor used as an
output amplifier must have a higher wattage rating. The casings of power transistors are
especially designed to permit ready cooling. For example, some power transistors use radial fins
for conducting heat away (see Fig. 11.8). Other types use a metal shell which mounts onto the
metal chasis of the equipment where it is employed. This transistor has the collector connected to
the transistor housing. The chasis then conducts the heat away. This type of transistor has a
higher power rating when physically clamped onto the metal chasis as described and a lower
power rating when mounted of the chasis. Good design technique requires that transistors be
mounted in the coolest part of the chasis.

Fans are sometimes installed inside equipment to cool off the transistors and other components.
The following list gives the symbols used to denote transistor parameters:-
Symbols Definitions
Ic Collector Current
IE Emitter Current
IB Base Current
VC Voltage at collector
VE Voltage at emitter
VB Voltage at base
Vcc Supply voltage to the collector
VEE Supply voltage to the emitter
VBB Supply Voltage to the base
ICB Collector-to-base current {(the second subscript may be
VKJ Circuit Voltage between elements
VCB Voltage between collector and base

PHYSICAL HANDLING OF TRANSISTOR
Though they are sturdy devices, transistor may be easily damaged if improperly handled. Thus
you should exercise great care in working with low power transistor employing flexible leads.
Since these leads are fragile and easily broken. The same precaution applies to the handling of
transistor components. These components have been miniaturized and leads may be easily
broken if not handled carefully. For maximum life, the transistor and associated components
used in this and subsequent experiments should be permanently mounted on experiment panel. A
short circuit from base to collector, in an operating circuit will almost always destroy a transistor.
A meter probe or a tool short-circuiting a pair of terminals may thus destroy a transistor.
At this point you must be cautioned against inserting transistor into a circuit, or removing
transistor from a circuit, with power ON. This practice may permanently damage a transistor
because of HIGH transient currents which may develop. A good rule to follow is to be certain
that power is off before inserting a transistor or any other component or removing it from circuit.
OTHER PRECAUTIONS
Collector bias and voltage values: Be certain that the polarity of bias voltage on
the collector is correct before applying power. The collector must be reverse biased. Moreover,
the voltage on the collector and emitter must not exceed the values specified. You should
therefore measure these voltages and adjust them for proper value before applying power to the
circuit.
Check of circuit connections: All connections should be checked against the

circuit diagram before power is applied. Transistor should be connected to a voltage source
without some limiting resistance in the circuit.

Transistor soldering: Soldering of transistor where necessary should be accomplished quickly.
Low-wattage irons (25 W) are recommended. Transistor pigtails should be kept as long as
possible consistent with circuit design consideration to reduce heat transfer. The same type of
heat sink should be used when soldering transistor leads in a circuit as when soldering
germanium diodes. An effective heat sink is created when long nose pliers are used for grasping
the transistor pigtail between the transistor body and the point of heat application as in Fig 11.9.
Figure 11.9: Pliers act as heat sink when transistors are soldered in circuit
Voltage Measurements: All test equipment should be isolated from power line. If the equipment
is not isolated, a transistor transformer should be used. In making voltage measurements in
transistor circuits, care should be taken to minimize the possibility of accidental short circuits
between closely spaced terminals. Accidental short circuits may apply improper or excessive
voltage to the transistor elements and may destroy the transistor.

Resistance Measurements: Transistor may be damaged during resistance measurements. Thus, if
a shunt type ohm meter is used on low resistance ranges, it may supply excessive current to the
transistor and destroy it. You must follow cautious in making ohm meter checks in transistor
circuits. A good rule to follow is to check the ohm meter leads potential and polarity before
checking transistor junctions. Also if it is necessary to check resistance of components in a
transistor circuit, the transistor should be removed first if it is a plug in type. When resistance
measurements with the transistor in circuit are made, allowance must be made for conduction
through the transistor. A recommended method is to make two sets of resistance measurements,
reversing the ohm meter leads for the required reading. The higher reading is more correct
because on the higher reading the transistor was reverse biased.
Electronic voltmeters (EVMs) frequently contain a low power ohm (LP Ω) function, specifically
designing for making resistance measurements in transistor circuits. On the LP Ω function there
is insufficient voltage developed to forward bias transistor junctions. Hence the LP Ω function is
used for resistance measurements in circuits containing solid state devices.
Use of Signal Generators as a Signal Source in Transistor Circuits: Excessive signal-

generator output may destroy a transistor signal generator output should be set at minimum at the
start of signal function. As an additional safety measure, the generator should not be coupled
directly into the circuit. Loose capacitive coupling, wherever possible, it is recommended.
PART 1 – FORWARD BIAS BEHAVIOUR OF THE EMITTER BASE JUNCTION
PROCEDURE:
1. Connect the circuit as shown in fig.10 on the experiment panel. Note that the collector of Q1
transistor is not connected. S1 off as shown in fig until so instructed.
2. As a safety precaution, to prevent damage to the meter, momentarily S1 on to verify the

proper circuit connections have been made and meter polarity has been observed.

3. When proper meter polarity has been verified, turn S1 on. Measure and record the current
indicated on M2.
FIGURE 11.10: Forward Bias Connection
4. Since the emitter-base junction is forward biased by the 1.5v cell, the forward current is
limited principally by the 3.3k resistor. (The internal resistance of a1.5 volt dry cell is about 1
ohm or less and may be ignored)
a) Calculate the dc voltage drop across the emitter-base junction in this forward-bias
connection as follows:
VEB= VEE – (IE × RI)
Where VEB = d – c voltage drop from emitter to base
VEE= emitter circuit supply voltage = 1.5 volts
II= emitter circuit current
RI= 3.3K

Note that the small voltage drop across the emitter base junction in the forward bias
conditions confirms that the emitter current is limited principally by the external 3.3K series
resistor.
b) Measure the dc voltage drop across the emitter base junction with a VOAM set on the
lowest dc voltage range.
Observe that the voltage obtained with the VOAM may be lower than the calculated value
since the battery voltage may be slightly less than the assumed 1.5 volts.
5. Use the value of VEB obtained in the previous step 4a to calculate the forward resistance of
the emitter base junction as follows:
REB = VEB/IE
Where REB = the emitter base forward resistance
Note that the emitter=base junction, when forward biased, represents a relatively low
resistance compared with that of the 3.3K limiting resistor. The resistance value obtained for R EB
is merely representative of the order of magnitude of emitter-base forward resistance, since the
junction resistance is nonlinear and varies with the amount of current through the junction. This
effect is investigated in a subsequent experiment.
PART 2- REVERSE-BIAS BEHAVIOUR OF THE EMITTER-BASE JUNCTION:
1. Connect the circuit shown in fig.11 substituting the microammeter M1 for M2 as the current
meter. As a safety precaution, DO NOT turns S2 on until the meter polarity and maximum
current have been checked.
Note If the transistor is not defective (internally short-circuited) the current

indication will be very small, less than 10 micro amps

FIGURE 11.11: Reverse Bias Connection
PART -3 FORWARD-BIAS BEHAVIOUR OF THE COLLECTOR-BIAS JUNCTION:
PROCEDURE:
1. Connect the circuit shown in Fig.11.12. Connect X and Y after the meter current and polarity
have been checked by momentarily connecting jumper across X and Y.
FIGURE 11.12: Forward-Bias Connection
2. Measure and record the current indicate do M2.

Since the collector-base junction is forward-biased by the 1.5V cell the forward current is
limited principally by the 3.3K resistor.
3. a) Calculate the dc voltage drop across the collector-base junction in the forward bias
condition as follows:
VCB = VCC – (IC × RL)
Where VBC = dc voltage drop from base to collector
VCC = collector circuit supply voltage =1.5V
IC = collector circuit current
RL = 3.3K
b) Use the value of VCB obtained in the previous step to calculate the forward resistance of the
collector base junction.
RCB = VCB/IC ………………Ohms
Where RCB = the collector-base forward resistance
Note that the collector-base junction, when forward biased, represents a relatively low
resistance compared with that of the 3.3K limiting resistor. Also note that the collector-base
junction resistance value is in the same order of magnitude as the emitter-base junction resistance
which was obtained in part1, step 5

When proper meter operation has been verified, turn S1 on.
Resistance R16 was included on the circuit for meter protection. However, if the current is less
than 10 micro amps, then in order to permit a more valid comparison with the forward-bias
connection, connect a shorting jumper across R16 only so that the 3.3K resistor is the limiting
resistor in the circuit. Observe that the current does not increase appreciably. Record this value
of current.
………………. micro amps
4. Now connect an additional shorting jumper across the 3.3K resistor and observe that the
measured current does not change. This means that the reverse current is limited almost
entirely by the high reverse resistance of the emitter-base junction.
5. Using the value of reverse current recorded in step3; calculate the dc voltage drop across the
emitter-base junction in the reverse-bias condition as follows:
VBE= VEE – (IEO × RL)
Where VEE= dc voltage drop base to emitter
VEE= emitter circuit supply voltage =1.5 volts
IEO= reverse emitter current (with open collector)
RL= 3.3K
Note that practically all the voltages of the cell is dropped across the junction itself.
6. Assuming VBE= VEE= 1.5 volts, calculate the approximate reverse resistance of the emitter-
base junction form.
RBE= 1.5 volts/IEO
Where RBE= the emitter-base reverse resistance

………………ohms
The high resistance value obtained is an indication of the order of magnitude of the
emitter-base reverse resistance.
7. Determine the ratio of forward current to reverse current for the emitter-base junction, and
express the ratio with a denominator of I.
CAUTION:
The maximum reverse-bias voltage which can be safely applied to the emitter-bias
junction varies from transistor to transistor but may be as low as few volts. Therefore, always
refer to a transistor manual before applying any value if reverse voltage above 2 volts to the
emitter-base junction.
PART 4- REVERSE-BIAS BEHAVIOUR OF THE COLLECTOR-BIAS JUNCTION:
1. Connect the circuit shown in Fig 11.13 substituting the micro ammeter M1 for M2 as shown
as the current meter. As a safety precaution keep s2 off until the meter polarity and maximum
current have been checked. Note if the transistor is not defective (internally short-circuited)
the current indication will be very small, less the 10 micro amps.

FIGURE 11.13
2. When proper meter connection has been verified, turn S2 on.
3. Resistor R16 is again included in the circuit for meter protection. However, if the current is
less 10 micro amps, then in order to permit a more valid comparison with the forward-bias
connection, connect a shorting jumper across R16 only. So that 3.3K resistor is the limiting
resistor in the circuit. Observe that the current does not increase appreciably. Record this value
of current.
…………….micro amps
Compare this value of current with that obtained in step 3, part 2
4. Now connect an additional shorting jumper across the 3.3K resistor and observe that the
measured current does not change. This means that the reverse current is limited almost entirely
by the high reverse resistance of the collector-base junction.
5. Using the value of reverse current recorded in step 3, calculate the dc voltage drop across the
collector-base junction in the reverse-bias condition as follows:

VCB = VCC – (ICO × RL)
Where VCB = dc voltage drop from collector to base
VCC = collector circuit supply voltage
ICO = reverse collector current (with open emitter)
RI = 3.3K
Note that practically all the supply voltage is dropped across the junction itself.
6. Assuming VCB = VCC = 1.5 volts, calculate the approximate reverse resistance of collector-
base junction form:
RCB= 1.5 volts/ICO
……………..ohms
Where RCB= the collector-base reverse resistance
Note particularly, the high order of magnitude of the collector-base reverse resistance.
8. Determine the ratio of forward current to reverse current for the collector-base junction and
express the ratio with a denominator of 1.
CONCLUSION:
Conclude your results explaining the following:
Relationship between applied voltage drop 3.3K series limiting resistor and the
forward and reverse-bias conditions
Difference in the magnitude of the forward and reverse resistance values
Difference between collector-base and emitter –base junction

Collector-base reverse current (ICO)
CONCLUSION
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STATIC CHECKOUT OF A TRANSISTOR USING AN

OHMMETER

EQUIPMENT:
1. Experiment panel.
2. Two VOAM’s
3. Connecting leads.
THEORY REFRESHER:
It is possible to perform static checkout of a transistor using an ordinary ohmmeter. The

ohmmeter used maybe that included as part of either a VTVM or a VOAM.
The ohmmeter is used to indicate the forward and reverse resistance across each diode junction
of the transistor with the voltage source within the ohmmeter serving as the forward or reverse
biased, depending on how the ohmmeter leads are connected. The ohmmeter test will not check
out a transistor dynamically. that is, under ac or transient conditions, it can be used to detect
whether or not the transistor is internally shorted or otherwise seriously damaged.
The transistors are easily damaged by improper applied voltages. The following procedure
describe in detail the precaution required to avoid damaging transistors when performing a static
checkout using conventional test equipment. It should be noted that difference in magnitude of
forward and reverse resistance value in an indication that each transistor functioning properly as
diode.

PART - 1 TEST QEQUIPMENT ANALYSIS
Before using the ohmmeter to check a transistor, it is necessary to determine the polarity and
magnitude of the ohmmeter voltage source. (An ohmmeter contains a voltage source whose
polarity may not be apparent from the markings on the test leads.) This means that a negative test
lead or common lead of VOAM is not always connected (internally) to the negative side of
ohmmeter voltage source.
1. To determine which test lead of the ohmmeter is, infect, the negative test lead, set the
ohmmeter on its lowest resistance range. (Rx1) and connect the ohmmeter leads across a
voltmeter. If the common lead (or the lead marked “minus”) of the ohmmeter is not
connected to the negative side of the ohmmeter voltage source as indicated by the voltmeter
test, either switch the ohmmeter or mark the common lead in somewhere to indicate its actual
polarity when used on the ohmmeter function.
2. With the voltmeter still connected to the ohmmeter leads, switch the ohmmeter through its
resistance ranges to determine whether the polarity of the ohmmeter voltage source is same
for all ranges. Record the polarity and magnitude of the voltage source for each resistance
range in Table 12.1.
TABLE 12.1
RANGE VOLTAGE COLOR OF NEGATIVE LEAD

Rx1
R x 10
R x 1000
R x 10,000
Rx 1Meg.

1. The information obtained in Table 12.1 should indicate that the magnitude of the ohmmeter
voltage source and possibly the polarity is not the same for all resistance ranges.
2. Note that the checks of the ohmmeter voltage do not indicate the amount of current which
will flow through a resistance being measured. This is because the current is a function of (1)
the magnitude of ohmmeter voltage source. (2) the value of resistor under test and (3) the
value of series resistance within the ohmmeter itself.
3. To determine the approximate current which would flow through both junctions of a
typical transistor under forward-bias conditions for each of the ohmmeter ranges?
Perform the following steps.

4. Connect the circuit shown in Figure 12.1. Using M3 and R7 on the panel. (The 22-ohm
resistor is selected because it approximates the forward resistance of a transistor junction
under certain conditions of ohmmeter source voltage and source resistance) thus some idea is
obtained of the magnitude of current which would flow if transistor were connected in the
circuit.

Figure 12.1
5. Switch the ohmmeter through its ranges and record the current flowing through the
22-ohm resistor as indicated on the ammeter for each range.
6. Record the values obtained in Table 12.2.
TABLE 2
RANGE CIRCUIT CURRENT MILLIAMPERES

Rx1
R x 10
R x 1000
R x 10,000
Rx 1Meg.
PART - 2 TRANSISTORS CHECKOUT
In checking the forward and reverse resistances of transistor emitter-base and collector base
junctions, there are a number of considerations which determine the selection of the proper
resistance range. These are summarized as follows:-
1. Emitter-Base Junction
a) For an emitter-base junction forward-resistance check, select a resistance range
with an ohmmeter source voltage not in excess of 2 volts. This resistance range

should produce in the test circuit of Figure 1, a current not in excess of 5 ma.
(Usually, the most suitable range is R x 1000).
b) For an emitter-base junction reverse-resistance check, select a range with a

source voltage not in excess of 2 volts since this junction is easily driven into
the Zener region. The reverse current is not a consideration because of the
normally high reverse resistance of the emitter-base junction.
2. Collector-Base Junction
a) For a collector-base junction forward-resistance check, select a range with a
source voltage not in excess of 2 volts. This resistance range should produce a
current preferably on the order of 5 mili-amperes.
b) For a collector-base junction reverse-resistance check, select a range with a

source voltage not in excess of 7.5 volts. The reverse current is not a
consideration because of the normally high reverse resistance of the collector-
base junction.
PROCEDURE:
FORWARD-RESISTANCE CHECK OF THE EMITTER-BASE JUNCTION
1. Consider the circuit shown in Figure 12.2. To perform a forward resistance check of the
transistor emitter-base junction, first select a proper ohmmeter range on the basis of the
information in Table I and 2 and in accordance with the Transistor checkout principles
outlined above.
2. To check the forward resistances of the emitter-base junction of the PNP transistor
connect the circuit shown in Figure12.2 without connecting the ohmmeter. Then
momentarily connect the ohmmeter as shown observing proper lead polarity. Do not allow
the ohmmeter to remain connected across the junction any longer than necessary to observe

the reading. The 22-ohm resistor is retained in the test circuit to limit the circuit current in
the event of a shorted junction. In practice, the 22-ohm resistor and current meter are not
used and the ohmmeter is connected directly across the transistor junction.
3. Note in Figure-12.2 that the ohmmeter positive lead is connected to P-type material
and that the ohmmeter negative lead is connected to N-type material.
4. Read the indicated resistance and then subtract 22 ohms from this value to obtain the
approximate emitter-base forward-bias resistance. Record this value.
___________________ Ohms
5. While the value of measured resistance is affected by the selected range, this value is
generally less than 1000 ohms for a good transistor. (This resistance value may be
as low as 20 ohms)
6. To check the forward resistance of the collector-base junction of a PNP transistor,

leave the ohmmeter on the selected resistance range and momentarily connect the
ohmmeter leads in the circuit as shown in Figure-3.
7. Read the approximate indicated resistance and record

___________________ Ohms
For a good transistor the collector-base forward resistance is generally less than 1000
ohms.
Note in Figure12.3 that the positive lead of the ohmmeter is again connected to P-type
material and the negative lead to the N-type material. The indicated collector-base forward
resistance should be on the same order as the emitter-base resistance.
8. To check the emitter-base reverse resistance of a PNP transistor, select a resistance

range on the basis of the information given in Table 1 and in accordance with the
transistor checkout principles outlined previously. Make certain that the source voltage
in the ohmmeter is not greater than 2 volts, since at the instant the reverse voltage is
applied and before reverse current begins to flow the entire source voltage appears
across the junction. Consequently, if the voltage is in excess of 2 volts, reverse
breakdown or "punch-through" is possible.
9. Connect the ohmmeter to the emitter and base leads as shown in Figure-12.4.
(Reverse Current is normally so small that the milliammeter is not used to observe the
reverse current. Consequently, the 22-ohm resistor is not required.)

10. Note in .Figure-12.4 that for a reverse resistance check, the positive test lead of the
ohmmeter is connected to N-type Material and the negative test lead to P-type material.
Read and record the indicated resistance.
_______________ Ohms
This resistance should be several orders of magnitude greater than the forward
resistance, but again may vary with the selected range.
1. To check the collector-base reverse resistance of a PNP transistor, select a

resistance range on the basis of the information given in Table 12.1 and the
information given previously. Make certain that the source voltage in the
ohmmeter is not greater than 7.5 volts. Since the collector-base junction is
designed to withstand higher reverse voltages the ohmmeter source voltage may
be higher, thus a more readable indication is possible on the higher resistance
range.

2. Connect the ohmmeter to the collector and base leads as shown in Figure 12.5.
Figure – 12.5
Note again that for a reverse resistance check, the positive lead is connected to N-type
material and the negative test lead to P-type material Record the indicated resistance.
__________________ Ohms
The indicated resistance should be on the same order as that of the emitter-base resistance.
The forward and reverse-resistance checks for an NPN transistor are performed in the same
manner as those for a PNP, except that the ohmmeter leads arc reversed to the transistor in
each case. Note, however, for forward resistance checks for either PNP or NPN transistors the
positive lead of the ohmmeter voltage source is connected to P-type material and the negative
lead to N-type material. Also for reverse resistance checks in both PNP and NPN transistors
the positive lead is connected to N-material and the negative lead to P-material. The proper
ohmmeter connections for both types of transistors we summarized in the following table.
Check through the table and confirm the connections.

TABLE 12.3
TRANSISTOR TYPE: PNP
FORWARD RESISTANCE OHMMETER CONNECTIONS

Positive Lead + Negative Lead -
Emitter-Base Emitter (P) Base (N)
Collector-Base Collector (P) Base (N)
REVERSE RESISTANCE
Emitter-Base Base (N) Emitter (P)
Collector-Base Base (N) Collector (P)
TRANSISTOR TYPE: NPN
FORWARD RESISTANCE OHMMETER CONNECTIONS

Emitter-Base Base (P) Emitter (N)
Collector-Base Base (P) Collector (N)
REVERSE RESISTANCE
Emitter-Base Emitter (N) Base (P)
Collector-Base Collector (N) Base (P)

CONCLUSIONS:
The transistor forward and reverse resistance checks outlined in the foregoing procedure provide
a simple but effective means of checking transistors for short or other principal defects prior to
connecting the transistors into circuits. Note that the foregoing resistance checks are not intended
to provide a quantitative measurement of the value of forward or reverse resistance, but rather
serve to verily the proper-relative magnitude between the two. The difference in the magnitude
of the forward am reverse resistance values obtained indicates that a junction is functioning
properly as a diode
The foregoing results indicate the Rx 1000 range for either a VTVM or VOAM is normally most
satisfactory for forward and reverse checks since this range has the highest value of internal
limiting resistance for the lowest ohmmeter source voltage. Note that the forward resistance of
the EB and CB are very similar. Furthermore, this is frequently the case with many transistor
types. This is because the resistance is in the thin region rather than in the emitter or collector
body material. However, the collector body resistance is normally less than the emitter body
resistance although the difference is not easily measurable.
The foregoing checks may also be used to determine the type (PNP or NPN) of an unidentified
transistor. For example, if a forward resistance condition is evident with the ohmmeter positive
lead connected to the base and the negative lead on the collector or emitter. The transistor is an
NPN type.
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Task:
EXPERIMENT # 9
Date: ____________________________
COMMON BASE CHARACTERISTICS
EQUIPMENT
2. Two variable dc power supplies (0-40V)
3. VOAM
THEORY REFRESHER:
In bipolar transistor circuits, one of the three transistor terminals must be connected to the
ground. Later, in amplifier circuits, it will be apparent that the input signal and the output
signal have this terminal in common. The three different choices of common terminals
determine three different biasing configurations. Each configuration has its own particular
characteristic curve for both the input circuitry and the output circuitry.
In the common base configuration, the base is grounded and the input current and voltage
are the emitter current IE and the base-to-emitter voltage V BE, respectively. The output current
and voltage are the collector current I E and the collector-to-base voltage V CB, respectively.
The ratio of collector current to emitter current is called the current gain α :
α = IC/IE
Figure-13.1 shows typical input characteristics of a common base transistor. These

characteristics display the relationship of input current LE to input voltage VBE for
different output voltages VCB:

Figure13.2 shows typical output characteristics of a common base transistor. These
characteristics display the relationship of output current I C to output voltage V CB for
different input currents I E
Figure – 13.2
PROCEDURE:
1. To measure the transistors common base input characteristics, connect the

following circuit:

Figure 13.3
2.Adjust VCC to obtain VCB of 5V. Then adjust VEE to obtain VBE of 0V as shown in table-1. VCC may
have to be readjusted to retain the desired value for VCB. Measure and record V RE, which can be
used to determine the emitter current IE. Repeat the procedure for all values of V BE in the
corresponding column of Table 13.1.
3.Repeat procedure 2 for each values of VCB shown in Table 13.1.
4.To measure the transistors common base output characteristics, connect the following circuit:
Figure – 13.4
5. Adjust VEE to obtain IE of 1mA ( VRE = 1V ) . Adjust VCC to obtain VCB as shown, in table-
2. The polarity of VCC may have to be reversed or readjusted to obtain the desired values
for both IE and VCB. Measure and record VRC which can be used to determine the collector
current IC.
6. Repeat procedure 5 for all values of IE in Table-13.2.
7. Calculate and record the values of IE in Table-13.1. Using this information, plot the
common base input characteristics as shown to Figure-13.1.
8. Calculate and record the values of IC in Table-13.2. Using this information, plot the
common base output characteristic as shown in Figure-13.2
9. Using the values of the output characteristic obtained in the third column (I E. = 3mA) of
table-2, calculate the common base current gain for each setting, of V CB. Explain why it
is different in different regions of the characteristic.

10. Another name for the “active region” of a transistor's output characteristics is the “linear
region”. Explain the name “linear region”, in terms of IC and IE, using the plot obtained
from step 8.

TABLE – 13.1
VCB = 5V VCB = 15V VCB = 25V
VBE VRE IE=VRE/RE VBE VRE IE=VRE/RE VBE VRE IE=VRE/RE
0V 0V 0V
0.2V 0.2V 0.2V
0.3V
0.3V 0.3V
0.3V 0.3V
0.3V
0.4V 0.4V 0.4V
0.5V 0.5V 0.5V
0.6V 0.6V 0.6V
TABLE – 13.2
VCB IE = 1mA IE = 2mA IE = 3mA IE = 4mA IE = 5mA
VRC IC=VRC/RC VRC IC=VRC/RC VRC IC=VRC/RC VRC IC=VRC/RC VRC IC=VRC/RC
-
0.65
-0.5V
-0.0V
10.0
V
15.0
V

CONCLUSIONS
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Task:
Date: ____________________________
EXPERIMENT 10
COMMON EMITTER / COMMON COLLECTOR

CHARACTERISTICS
EQUIPMENT:
2. Two VOAM’s

THEORY REFRESHER:
The transistor bias arrangement used most frequently is called the common emitter configuration, in
which the emitter terminal is grounded. In the common emitter configuration the input current and
voltage are I B and VBE respectively. The output current and voltage are I C and VCE. The ratio of the
collector current to base current is called the current gain, β:
β = I C/IB
The relationship between β and α is:
β = α/(1 – α)
Figure-I shows the input characteristics of the common emitter -biasing configurations. These
characteristics display the relationship between base current and base to emitter voltage for a
constant collector to emitter voltage:
The other important bias method is the common collector configuration. This configuration will be
used in an amplifier requiring high input resistance and low output resistance.
Figure-14.2 shows the input characteristics of the common collector biasing configuration.
Characteristics display the relationship between base current and collector to base voltage for a
constant collector to emitter voltage.

Figure-14.3 shows the output .characteristics of the common emitter configuration. The common
collector output characteristics are similar except the vertical axis is I E ( I E I C ). These
characteristics display collector (or emitter) current versus collector to emitter voltage, for a constant
base current:
PROCEDURE:
1. To determine the input characteristics of the common emitter configuration, connect the
following circuit:
V CC = 10V

Figure – 14.4
2. Adjust R13 and R17 potentiometers to set V CE and V BE as shown in Table-14.1.
Measure and record the voltage across the R 6 resistor V RB , for each combination of
VCE and VBE in Table-14.1. It may be necessary use two VOAMS in order to keep V CE
constant.
3. To determine the output characteristics of the common emitter configuration, set the R17
potentiometer in the circuit of Figure-14.4 to its maximum setting. This will cause V CE to
decrease to approximately 0V. Then adjust R 13 potentiometer to set I B to some value of
microampere. Next adjust the R 17 potentiometer for all values of V CE in Table-14.2
making sure that IB remains constant.
4. Measure and record in Table-14.2 the voltage across the R 5 resistor VRC for each
combination of VCE and IB in Table-14.2.
5. To measure the input characteristics of the common collector configuration, connect

the following circuit:

6. By carefully adjust R13 and R17 potentiometer, set the voltage VCE and VCB as shown in table-
3. Both VCE, and VCB are very sensitive to the potentiometer settings.
7. Measure and record to Table 14.3 the voltage across the R6 resistor, VRB which can be used
to calculate the current IB.
8. Calculate the value of IB in Table 14.3, and plot the input characteristics of the common
emitter bias circuit using the values of Table14.1.
9. Calculate the values of IC in Table 14.2, and plot the output characteristics of the common
emitter bias current using the values of Table 14.2.
10. Calculate the values of IB in table-3, and plot the input characteristics of the common
collector bias circuit using the values of Table 14.3
11. For each value VCE in Table 14.2, calculate the value of β for the output characteristics
corresponding solo for some required value.

12. Calculate α for each of the values of β in step 11.
VCE = 3V VCE = 5V
TABLE – VBE VRB IB=VRB/RB VBE VRB IB=VRB/RB 14.2
IB = 10µA IB = 20µA IB = 30µA IB = 40µA IB = 50µA

(V) (V) (µA) (V) (V) (µA)
VCE VR0.63V
IC=VRC VR IC=VRC VR 0.63V
IC=VRC VRC IC=VRC VR IC=VRC
C C C C
0.64V/RC /RC 0.64V
/RC RC
/ /RC
0.2V 0.65V 0.65V
0.4V
0.66V 0.66V
0.8V
1V
3V
5V
TABLE –14. 3
VCE = 3V VCE = 5V VCE = 7V
VCB VRB IB=VRB/RB VCB VRB IB=VRB/RB VCB VRB IB=VRB/RB
(V) (V) (µA) (V) (V) (µA) (V) (V) (µA)

2.4V 2.4V 2.4V
2.38V 2.38V 2.38V
2.36V 2.36V 2.36V
2.34V 2.34V 2.34V

CONCLUSIONS
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Task:
Date: ____________________________

EXPERIMENT # 11
THE JUNCTION FILED EFFECT TRANSISTOR (JFET)

CHARACTERISTICS
PURPOSE:
To investigate the behavior of the JFET’s drain to source, gate to source voltages on drain
current under forward and reverse bias conditions.
EQUIPMENT:
1- Experiment panel
2- VOAM
3- Connecting Leads
THEORY REFRESHER:
The field effect transistor (FET) is a voltage sensitive device which has extremely high input impedance
as well as high output impedance. It is available in two type, the diffused junction filed effect transistor
(JFET) and the insulated gate field effect transistor (also called the metal oxide semiconductor) IGFET or
MOSFET. An N-Channel JFET is shown schematically and with its circuit symbol in Figure -15.1 (a, b).

Figure 15.1-A Figure 15.1-B
The three elements of the transistor are called the source, the drain and the gate. The conducting path
between the source and the drain is called the channel p-type JFETs, in which the channel is type and the
gate is n-type, are also available. Terminal leads for the drain and the source make ohmic contacts at both
ends of the channel. They are not semiconductor junctions, but the P-type material, called gate, which is
embedded on both sides of the channel form a semiconductor junction which drives the name junction
FET.
In the FET the drain corresponds to the collector of a bipolar transistor, the source to the emitter, and the
gate to the base. However, the operation of a JFET is completely different from a bipolar transistor. The
chief operational difference is that drain current (ID) in the JFET is controlled by gate to source voltage
(VGS), whereas collect current in the bipolar transistor is controlled by base current.
To understand the operation of JFET, assume the source and the gates to be alt ground potential. Now let
us study the effect of placing a small positive potential on the drain. Since there is positive voltage
between drain and source, current will flow from the drain to the source. Negligible current flows
between source (or drain) and gate, since the diode formed by the channel to gate junction is reverse
biased.
The amount of current flowing from the drain to the source depends initially on the drain to source
potential difference VDS and resistance of N material in the channel between the drain and the source.
This resistance is a function of the doping of the N material and the channel width, length, and thickness.

Figure 15.2
As the drain potential VDS is increased, the diode formed by the channel gate junction is further reverse
biased. Figure 1-C shows a reversed biased diode. Initially, the holes in the P material flow toward the
negative terminal of VDD, and electron in the N material flow toward the positive terminal of VDD. This
result is the formation of a central region of length 1, which is void of free charges. Since the region
contained within 1 has been depleted of free charges, it is called the depletion region. As the reverse
voltage is increased, the free charges move father form the junction and the effective separation length.
Figure 15.3
This result is directly applicable to the JFET under consideration. Figure 1-D, E and F show space charge
regions in the FET for several values of VDS.
In figure 1-D as VDS increases, the depletion region increases, causing narrowing of the channel. The
channel area decrease, resulting in an increase in channel resistance, hence the current decreases, show in
figure 1-G.

When VDS = VPO, the depletion region on each side of the channel join together, as shown in Figure
15.4.
The voltage VPO is called the “Pinch-Off” voltage since it pinches off the channel connection between
drain and source.
Figure 15.4 Figure 15.5
The Figure 15.5, the drain voltage VDS is larger than the Pinch Off voltage. In this region the depletion
area thickens. However, the potential at a point remains essentially at the pinch-off voltage VPO. Thus
the current ID remains almost constant as VDS increases above VPO. This is shown in Figure 15.6.
In Figure 15.6, the drain current ID increases rapidly as VDS increases toward VPO. Above VPO the
current tends to level off at IPO and then rises slowly, when VDS equals the breakdown voltage VDSS,
an avalanche breakdown occurs, and the current again rises rapidly.

Figure 15.6
Now consider drain source voltage fixed and varying the gate source voltage. As the gate source voltage
is made negative, the P-N junction is reverse biased, increasing the depletion region between the gate and
the source. This decreases the channel width, increasing the channel resistance. The current therefore
decreases.
When the gate voltage is made positive, the depletion region decreases until, for large positive gate
voltages, the channel opens. Then the PN junction between gate and source becomes forward biased and
current flows from the gate to source.
A typical set of Vi output characteristics for the JFET is shown in Figure 15.7 with gate to source voltage
as the parameter.
The pinch-off voltage is 5V when VGS = 0, and the drain current at this point is 10ma. As the gate
potential decreases, the pinch off voltage also decreases. The drain source voltage at which pinch-off
occurs is approximately given by the equation.
VDS (at pinch off) = VPO + VGS

Figure 15.7
So at VGS = 0, VDS = VPO. The form Vi characteristics shown in figure 1-J, the pinch off voltage is
zero when VGS = -5V. At this negative potential no drain current flows. Figure 1-J also show VDSS, the
breakdown voltage for VFS = 0, it also show the breakdown voltages for arbitrary VGS.
It shows that breakdown voltage is a function of gate to source. This is given by the equation.
VDSS (for arbitrary VGS) ≈ VDSS (breakdown voltage for VGS ≈ 0) + VGS. VDSS is the maximum
drain to source voltage at which the JFET can be operated safely, when VGS = 0.
The transfer function of FET is represented by:
V GS
(1− )2
ID = IDSS V PO
Now form figure 1-J, VGS = 0, ID = Io, and VGS = -5, ID = 0 are the end points of the curve, at VGS = 0
defines the maximum drain current and at VGS = -5V the minimum drain current (transistor off).
PROCEDURE:
1- Adjust power supply Neg = -15V and Pos = +15V VDS, the turn power suppy off. Connect
the circuit shown in Figure 15.8.

Figure 15.8
2- Turn potentiometers R27 and R9 fully counterclockwise and then turn on your power supply.
3- Leave potentiometer R1 fully counterclockwise so that the gate to source voltages (VGS)
applied to the FET will be zero. Measure the supply voltage with your meter. Adjust
potentiometer R9 until the drain to source voltage (VDS) is equal to 1 volt (measure this
voltage with your voltmeter).
4- Now use your voltmeter to measure the voltage across R5. Use this reading and the resistance
of R5 (100 Ohms) to calculate the FET’s drain current (ID) according to ohm’s law. Record
your calculated ID value (in milli ampere) immediately below the VDS value of 1 volt in the
table provided in Table 15.1.
VGS = 0
VDS 8
1 2 3 4 5 6 7
(Volts)
ID
Milliamperer
s
TABLE 15.1

5- Complete the Table 15.1 by adjusting VDS to the remaining values listed in the table and
recording the corresponding values of ID.
6- Now adjust potentiometer R27 so that VGS is equal to 0.25 volts (measure with your
voltmeter).
7- Without disturbing the setting of R27, adjust potentiometer R29 until VDS is equal to 1 volt
(measure VDs with your voltmeter).
8- Now use your voltmeter to measure the votls across R4. Use this voltage reading and the
resistance of R5 (100 ohms) to calculate ID according to ohm’s law. Record your calculated
ID values (in milliamperes) immediately below the VDS value of 1 volt in the Table 15.2.
VGS = 0.25 Volts
VDS 1 2 3 4 5 6 7 8
(Volts)
ID
Milliamperers
TABLE 15.2
9- Complete the Table 15.3 by adjusting V DS to the remaining values indicated and recording
the corresponding values of ID.
10- Adjust potentiometer R27 so that VGS is equal to 0.25 volts (measure with your voltmeter).
11- Without disturbing the setting of R1, adjust potentiometer R9 until VDs is equal to 1 volt
(measure with your voltmeter).
12- Use your voltmeter to measure the voltage across R5. Then use this voltage reading and

ID value (in milli amperes) immediately below the VDS value of 1 volt in the table provided
in Table 15.3.
VGS = -0.5 Volts
VDS 1 2 3 4 5 6 7 8
(Volts)
ID
Milliamperers
Table 15.3
13- Now complete the Table 15.3.
14- Adjust potentiometer R27 so that VGS is equal to 0.75 volts (measure with your voltmeter).
15- Without disturbing the setting of R1, adjust potentiometer R9 until VDs is equal to 1 volt
ID value (in milliamperes) immediately below the VDS value of 1 volt in the table provided
in Table -15.4.
VGS = 0.75 Volts
VDS 1 2 3 4 5 6 7 8
(Volts)
ID
Milliamperers
Table 15.4

17- Complete the Table 15.4
18- Now use the corresponding values of ID and VDS that you recorded in Table 15.1,2,3,4 and
to plot the drain characteristics curves on the graph paper for VGS = 0, -0.25, -2.50 and -0.75
volts.
19- Now use the set of drain characteristics curves that you plotted to determine the Trans
conductance of the FET. Select a constant of VDS that is well above the pinch-off voltage
(VP) of the device (possibly 6 or 7 volts) and observe the change in ID when VGs changes
from 0 to -0.25 volts. This will ensure that your Trans conductance value will be measured in
the pinch-off region of the device. Use the Trans conductance equation given below and
recorded your results in the space provided below.
Trans conductance = Δ ID / Δ VGS
Trans conductance = ___________
20- Turn off your power supply
21- Form the family of drain characteristics using the data, identify VPO (pinch-off voltage).
Draw transfer characteristics and explain the characteristics using your curves. Use separate
sheet.

CONCLUSIONS
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Task:
Date: ____________________________

EXPERIMENT # 12
THE METAL OXIDE SEMICONDUCTOR FIELD EFFECT

TRANSISTOR (MOSFET)
PURPOSE:
To investigate the drain characteristics of a MOSFET.
EQUIPMENT
1- Experiment panel
2- VOAM
3- Connecting Leads
THEORY REFRESHER
Metal oxide semiconductors, or MOS, functions primarily on the principle of the field effect transistor.
Simple MOS integrated circuits were produced in 1964. The development of MOS has produced several
types of MOS devices, including P-Channel, N-Channel.
P-Channel MOS
The P-Channel, metal gate MOS process is shown in Figure 16.1-A. thin slice of lightly doped
N-type silicon is the body of the MOS transistor. Two closely spaced, heavily doped P-type
regions. The source and the drain are formed within the substrate by diffusion. A thin deposited
layer of metal, called the gate, covers the area between source and the drain regions but is
electrically insulated form them and form the semiconductor substrate by a thein layer of silicon
dioxide.

Figure 16.1
The gate is control element when properly biased. This gate structure creates a conductive path or channel
between the source and the drain regions in Figure 16.1. The minimum value of gate voltage to cause
channel formation is known as the gate threshold voltage, VTH, and is dependent on the particular
manufacturing process. The P-Channel device, then, is normally off until switched on.
N-Channel MOS:
The N-Channel MOSFET can be constructed by diffusion phosphorus N-type source and drain region in
to P-type starting material as shown in Figure 16.2. The N-Channel inversion layer carrier mobility is
about three times higher than for P-Channel devices. The resulting structure is depletion mode (Normally
ON) with doping levels for the substrate comparable to P-Channel (10 15 atom /cm3).
Figure 16.2
N-Channel Silicon Gate:
Special method are employed to make N-Channel devices enhancements mode devices. Which do not
allow current to flow until a voltage greater than Vi is applied. Patterned poly-silicon material is used to
define the gate area such that the following source and drain diffusions are self-aligned to the gate with
the refractory silicon gate serving as diffusion mark.
Complementary MOS (CMOS):

The third category of MOS process is that of complementary MOS or CMOS shown in Figure 16.3. This
technology combines both P-Channel and N-Channel transistors on the same substrate. The N-Channel
transistor is usually the driver and P-Channel transistor is the load.
Figure -16.3
Only one transistor is in a quiescent logic state. This arrangement leads to an extremely low standby
power and high speed operation. Other features are high noise immunity, single power supply operation
and relative low insensitivity to temperature variation.
Silicon-on-Sapphire (SOS):
The last MOS process technique is called the SOS. Construction of the circuitry is carried out on an
insulating material such as sapphire. These devices are completely isolated. There is no capacitive
coupling between devices. This results in an order of magnitude increase in circuit performance in
comparison to conventional CMOS.
DISADVANTAGES OF THE METHOD CENTER AROUND THE PROCESS COMPLEXITY
Enhancement type MOSFET
In the enhancement type, there is no channel between the drain and source, but separating the N-type
drain and source is a P-type substrate, as in Figure -16.4. Deposited over the substrate is a very thin,

fragile layer of silicon dioxide (SiO2), an insulator. Deposited on the SiO 2 is a metallic film which acts as
the gate. Ohmic contacts are brought out for the gate, drain source and substrate. When the substrate is
internally connected to the source, there is not substrate lead.
Figure -16.4 Figure -16.5a Figure -16.5b
Form Figure -16.4 is clear that the gate is insulated from the body of the FET and for this reason the
MOSFET is also called an insulted gate FET (IGFET). Although there is no physical chancel for reasons
which will become clear, the MOSFET in Figure -16.4 is called an N-Channel enhancement type.
The gate and the substrate act as the plates of a capacitor separated by the SiO2 insulator. When the gate
is made positive relative to the source to which the substrate is connected (Figure -16.5a), the capacitor
charges. Since the gate is positive, negative charges appear in the substrate between drain and source
(Figure -16.5b), in effect creating an N-Channel which will permit current in the source to drain circuit.
The N-Channel enhancement type MOSFET conducts only when the gate is positive relative to the
source. It is cut off when there is zero or gate to source bias. For this reason it sis designated a normally
OFF MOSFET. Because the gate is insulated from the substrate, there is no DC gate current even though
the gate is positive relative to the substrate. Therefore the MOSFET is a high impedance transistor.

It should be noted that a P-Channel normally OFF MOSFET may be made by using as N-Substrate and P-
type drain and source. The symbols for N and P-Channel enhancements types are shown in Figure -16.6
(a, b). Note that broken vertical channel line indicates a normally OFF MOSFET.
Figure -16.6a Figure -16.6b
Depletion type MOSFET:
The MOSFET in Figure 16.7 is constructed like the one in Figure -16.4 with one exception. Figure -16.7
has an N-type channel, while Figure -16.4 does not. The FET in Figure -16.7 can be operated with both a
positive and a negate gate. When the gate is positive, the FET operates in the enhancement mode, when
negative, in the depletion mode.
Consider the effect of a positive gate on the charge carriers in the N-Channel of Figure -16.8. The positive
gate attracts negative charge carriers in the N-Channel (Figure -16.8b), thus increasing the conductivity of
the channel and increasing the drain current. The more positive the gate is made, the more drain current
flows. This is the enhancement mode.

When the gate is shorted to the source, that is, when there is zero gate voltage, drain current will flow in
the channel, form source to drain, if a voltage source VDD is connected as in figure -8a. The drain current
with zero gate voltage is less than the drain current with positive gate voltage. Since there is drain current,
even with O-V gate bias, this is normally ON MOSFET.
What happens when the gate is made negative relative to the source as in figure -9a? The capacitor charge
distribution on the gate and N-type channel is shown in figure -9b. Electrons on the gate repel the
negative charge carriers in the N-channel in effect depleting the channel of negative carrier and reducing
drain current. The more negative the gate, the less the drain current. When VGS is made sufficiently
negative, drain current is cut off.
Figure -16.7 Figure -16.8a
Figure -16.8b
The depletion MOSFET may be constructed with a P-channel and N substrate. The symbols for N and P-
channel depletion MOSFET are shown in Figure -16.10. Note that the vertical channel line is not broken
here because the device is normally ON. The drain curves for MOSFET are similar to those for a JFET.
Figure -16.11 shows a family of drain curves for an N-channel depletion MOSFET.

Dual Insulated Gate MOSFET:
For special application, MOSFETs may be constructed with two gates, G1 and G2, as in Figure -16.12.
This is the diagram of a four terminal 3N187 device which may be used as an amplifier for frequencies up
to 300 MHz gate 1 is at terminal 3, gate 2 at terminal 2. The drain is terminal 1, the source, terminal 4.
Note that the substrate is internally connected to eh source. Two sets of back to back diodes are built into
this device. One set of diodes is internally connected between gate 1 and the source, and the other set
between gate 2 and the source. The manufacturer states that “the diodes bypass any voltage transients
which exceed approximately ±10V”, protecting the gates against damage in normal handling use.
You will recall that the silicon dioxide insulator/MOSFET is a thin glass like deposit on the substrate.
Very fragile, it may be easily fractured by static voltages to which the MOSFET is subject in ordinary

handling. The back to back diodes connected between gates and source protect the MOSFET against
static charges and the voltage transients.
PROCEDURE:
1- Adjust power supply Neg = -15V and Pos = +15V VDC, the turn power suppy off.
Connect the circuit shown in Figure – 16.11.
Figure 16.11
2- Turn potentiometers R27 and R9 fully counterclockwise and then turn on your power
supply.
3- Leave potentiometer R1 fully counterclockwise so that the gate to source voltages (VGS)
applied to the FET will be zero. Measure the supply voltage with your meter. Adjust
potentiometer R5 until the IGFET’s drain to souce voltage VDS is equal to 0.5 volts.
4- Now use your voltmeter to measure the voltage across R5. Use this reading and the
resistance of R5 (100 Ohms) to calculate the IGFET’s drain current (ID) according to
ohm’s law. Record your calculated ID value (in milliampere) immediately below the
VDS value of 0.5V volts in the Table 16.1
VGS = 0
VDS 1 2 3 4 5 6 7 8

(Volts)
ID
Milliamperer
s
Table16.1
5- Complete the table in figure -12 by adjusting VDS to the remaining values listed in the
table and recording the corresponding values of ID.
6- Now adjust potentiometer R27 so that VGS is equal to 0.5 volts (measure with your
voltmeter).
7- Without disturbing the setting of R27, adjust potentiometer R29 until VDS is equal to 0.5
volts (measure VDs with your voltmeter).
8- Now use your voltmeter to measure the votls across R5. Use this voltage reading and the
resistance of R5 (100 ohms) to calculate ID according to ohm’s law. Record your
calculated ID values (in milli amperes) immediately below the VDS value of 0.5 volts in
the Table 16.2.
VGS = -0.5 Volts
VDS 1 2 3 4 5 6 7 8
(Volts)

ID
Milliamperers
Table16.2
9- Complete the Table 16.2 by adjusting VDS to the remaining values indicated and
recording the corresponding values of ID.
10- Turn off your power supply. Remove lead between terminal 3 of R27 and negative
terminal (-) of power supply. Connect a lead between terminal 3 of R27 and the positive
(+) terminal of the power supply.
11- Turn your power supply on. Adjust potentiometer R27 so that VGS is equal to +0.5 volts
12- Without disturbing the setting of R27, adjust potentiometer R9 until VDs is equal to 0.5
volts (measure with your voltmeter).
resistance of R5 (100 ohms) to calculate ID according to ohm’s law. Record your
calculated ID value (in milli amperes) immediately below the VDS value of 0.5 volt in
the Table 16.3
VGS = +0.5 Volts
VDS 1 2 3 4 5 6 7 8
(Volts)
ID

Milliamperers
Table 16.3
14- Now complete table in Table 16.3by performing the remaining VDS values indicated.
Should have trouble obtaining the highest value of VDS indicated (4 volts) or even the
next highest value (3 volts), do not be concerned. Simply adjust VDS as high as possible
and then determine the corresponding value of ID. However, be sure to make note of the
highest VDS value obtained as well as its corresponding ID value.
15- Use the corresponding values of VDS and ID in figure 12, 13and 14 to plot drain
characteristics curves on the graph paper for VGS = 0V, -0.5V and +0.5 V.
16- Turn off your power supply.
CONCLUSIONS
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Task:
Date: ____________________________

EXPERIMENT #13
Check use of operational amplifier as
1. Voltage follower
2. Non inverting amplifier
3. Inverting amplifier
EQUIPMENT & COMPONENTS:
1. Dual-trace- oscilloscope

2. Audio frequency generator
3. Low voltage power supply
4. Multimeter
5. Op amp 741
6. Two 56Ω and 68Ω resistors
7. 270Ω, 150Ω, 8.2KΩ , 5.6KΩ resistors
8. Breadboard
9. Wires
THEORY REFRESHER:
Voltage follower
To understand how the voltage follower operates. Consider the basic the op amp circuit
reproduced in fig (a).As in Fig (a), the output (terminal 6) is connected to the inverted input
terminal (terminal 2).
Figure (a)
With terminal 3 (non inverting input) grounded, terminal 2 and the output must also at the
ground level. If the output voltage level to moves slightly above ground level, the base voltage of
Q2 would be higher than that at the base of Q1 and consequently IC2 would increase. The increase
level of IC2 would increase the voltage drop across R C and thus push the output voltage down
until VB2 and VB1 were once again equal. Similarly, if the output were fall below ground levelV B2

would become lower than VB1. This would lower the IC2, reduce the voltage of RC, and move the
output voltage back up to ground level.
The above reasoning can also be applied to show that if the input voltage (at terminal 3) was +1V
or -1V, or almost any other level the output voltage would be virtually be same as the input.
Thus, the output follows the input.
In the voltage follower there is a very small difference between the input voltage and output
voltage due to the very high internal voltage gain of the operational amplifier. To produce an
output change there has to be a voltage difference (or differential input) at the inverting and non
inverting terminals, this means that, because the inverting terminal is connected to the output,
there is a small difference between the input and output voltage levels. To produce an output
closely equal to VI, the differential input is
Vd= Vi/M
Where ‘M’ is the internal voltage gain (or open loop gain) of the operational amplifier. The
precise output voltages;
VO=Vi-Vd
Or
VO=Vi-(Vi/M)

Where Vi/M is an error voltage. Obviously the largest value of internal gain gives the smallest
possible error
Non-inverting Amplifier
The non inverting amplifier in fig (b) behaves in a similar way to the voltage follower circuit.
The difference is instead of all of the output being fed directly to the input, only a portion is fed
back. The output voltage is potential divided across resistor R2 and R3 before it is applied to the
inverting input.
Once again, consider the condition that exists when the non inverting terminal is grounded. As
for voltage follower circuit, the inverting input terminal must also be at ground level; otherwise
any voltage difference would be amplified to move the inverting input terminal back to ground
level because the junction of R2 and R3 is connected to inverting input terminal, the voltage at
this point must also be ground level, and consequently there is 0V drop across R 3. With VR3
equals to zero, the current I2 which flows to R2 and R3 must also be zero, (neglecting the very
small bias current in to terminal 2). Thus, there is 0V drop acrossR2and this means that the output
voltage is equal to the input voltage, which is at ground level.
Now suppose that ±100mV input is applied to terminal 3. As already explained the output
voltage will move to the level that makes the feedback voltage to terminal 2 equal to the input
voltage. Because the feedback voltage is developed across resistor R3,
VR3=VI=I2R3

V0=I2 (R2+R3)
Voltage Gain Av=V0/Vi=I2 (R2+R3)/I2R3
Or Av= (R2+R3)/R3
Figure (b)
Inverting Amplifier
The inverting amplifier illustrated in fig (c) is so named, because an input applied via R 1 to the
inverting input terminal causes the output to go in the negative direction when the input is
positive-going, and vice versa.
The voltage at the inverting input terminal always remains close to the ground level, and because
the junction of R1 and R2 is connected to the inverting input terminal that junction always
remains at ground level. With VI at one end of R1 and ground potential at the other end, V I
appears across R1. Also with V0 at one end of R2 and ground at the other end, V 0 is developed
across R2 ignoring the very small current flowing into the op amp inverting input terminal, I 1
effectively flows through R1 and R2. The input and output voltages can now be express as

VI=I1R1
VO=-I1R2
And voltage gain
Av= Vo/Vi=-I1R2/I1R1
Figure (c)
PROCEDURE:
Voltage follower
1. Connect a 741 op amp to function as a voltage follower as illustrated in fig (a). Use a
supply voltage of ±9V to ±15V.
2. Connect dual-trace oscilloscope to monitor the input and output dc voltage levels.
3. Using an adjustable dc source set the input voltage to +1V, +2V and +3V, in turn.
Observe the output voltage level in each case.

4. Repeat the procedure 3 using input levels of -1V, -2V and -3V.
5. Remove the dc source from the input, and apply a ±15V, 1 KHz sinusoidal signal.
6. Measure the output circuit voltage, and not the phase relationship between input and
output.
7. Adjust the signal amplitude to 2V, and 3V, in turn, and measure the output in each
case.
Non inverting Amplifier
1. Connect a 741 op amp to function as a no inverting amplifier, as illustrated in fig
(b). Use a supply of ±9V to ±15V, and resistors of R2=8.2KΩ and R3=150Ω.
2. Connect a dual-trace oscilloscope to monitor the input and output dc voltage
level.
3. Using an adjustable dc voltage source, set the input voltage to +50mV and
+100mV, in turn. Measure the output voltage level and calculate the voltage gain
in each case.
4. Repeat procedure 3 using input levels of -50mv and -100mV.
5. Remove the dc source from the input and apply a ±25mV, 1K Hz sinusoidal
signal.
6. Measure the output and note phase relationship between input and output.
7. Adjust the signal amplitude ±50mV. Measure the output and calculate the voltage
gain.

8. Change R3 to approximately 111Ω, (use two. Series-connected 56Ω resistors.)
9. Repeat procedure 7.
Inverting Amplifier
1. Connect a 741 op-amp to function as an inverting amplifier, as illustrated in fig (c). Use a
supply of ±9V to±15V, and resistors of R1=270Ω and
R2=8.2K Ω.
2.7 Same as procedures 2 through 7 for laboratory exercise (b).
8. Change R1 to approximately 137Ω, (use two series-connected 68Ω resistors.)
9. Repeat procedure 7
CONCLUSIONS
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Task:
142
INDUSTRIAL ELECTRONICS LAB MANUAL
Date: ____________________________
EXPERIMENT # 14
To check use of operational amplifier as
1. Summing circuit.
2. Difference Amplifier.
EQUIPMENT & COMPONENTS:

1- Dual-trace oscilloscope
2- Audio frequency generator
3- Low voltage power supply
4- Multimeter
5- Op amp 741 and LF353
6- Two 270Ω, 1 KΩ, 27KΩ 1MΩ and 15KΩ resistors
7- 18KΩ, 47KΩ, 18KΩ, 560Ω and 100Ω resistors
8- Three 1.8KΩ resistors
9- Breadboard
THEORY REFRESHER:
Direct-Coupled summing circuits
Figure (c) shows a circuit that amplifies the sun of two or more inputs. This is essentially an
inverting amplifier with two inputs terminals and two inputs resistors. As with other inverting
amplifiers, the inverting input terminals of op amp behaves as a virtual ground. So,
I1=V1/R1 and I2=V2/R2

Figure (c)
All of (I1+I2) flows through resistor R3, giving
VO=-(I1+I2) R3 => - (V1/R1 +V2/R2) R3
With R1=R2,
VO=-(R3/R1)*(V1+V2) or V O=Av
(V1+V2)
When the summing circuit in fig (c) has R3=R1=R2, then Av=-1
And the output voltage is the direct sum of the input voltages (inverted)
When R3>R1 and R2, then |Av|>1
Direct-coupled Difference Amplifier:

A difference amplifier or differential amplifier, Amplifies the difference between two input
signals. The difference amplifier circuit illustrated in fig (d) is a combination inverting and non
inverting amplifiers. If input terminal 2 is grounded, the circuit operates as an inverting amplifier
and input V1 is amplified by -R2/R1. With terminal 1 grounded, R2 and R1function as feedback
components a non inverting amplifier. Input V 2 is potentially divided across resistor R3 and R4 to
give VR4 and then VR4 is amplified by (R2+R1)/R1.
R2
With V 2=0 ,V 01=− ( )
R1
∗V 1
R4
With V 1=0 ,V R 4 = ( R3 + R4 )
×V2
R 1+ R 2
And V 02= ( R1 ) ×V R 4
R 1+ R 2 R4
V 02= ( R1 )( ×
R3 + R4 )
×V 2
R2
With R3=R 1 and R4 =R2 V 02= ( )
R1
∗V 2
With both signal present V 0=V 02+V 01
R2 R2
¿ ( ) ( )
R1
∗V 2−
R1
∗V 1

R2
Giving, V 0= (V ¿ ¿ 2−V 1 )¿
R1
When R2 and R1 are equal value resistors the output is direct difference of the two inputs. By
selecting R2 greater than R1, the output can be made an amplifier version of the input difference.
Figure (d)
PROCEDURE:
Direct- Coupled summing circuits
1) Connect the inverting summing circuit, as illustrated in fig (c). Use a supply of ±15V and
1.8K ohms resistors.
2) Connect adjustable dc voltage sources to each input and connect dc voltmeter to monitor
the levels of V1, V2 and V0.

3) Set V1and V2 to several different levels to 0 between 0.1V and 1V and measure the
output level for each case to check the accuracy.
4) Change R3 to 18KΩ and repeat procedure 3using maximum input levels of 0.5V
Direct- Coupled Difference Amplifier
1) Construct the difference amplifier circuit shown in fig. (d). Use a LF353 op-amp with a
supply of ±15V and resistor values R1=R3=27KΩ , R2=R4=1MΩ .
2) Connect adjustable dc voltage sources to each input and connect dc voltmeter to monitor
the levels of V1, V2 and V0.
3) Set V1and V2 to several different levels to 0 to +50mV and -50mV. Note the level of V0
at each setting of inputs, and check the accuracy.
4) Connect another adjustable dc source between R4 and ground as illustrated in fig
(i).Investigate its effect as an output level shifter.

Figure (i)
5) Ground R4 once again connect the two terminals together, and apply a signal adjustable
dc voltage source at the inputs.
6) Adjust the input to 10V, measure the output voltage level, and calculate the common
mode gain for the circuit.

CONCLUSIONS
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____________________________________________________________________________
Task:
Date: ____________________________
EXPERIMENT#15

INTRODUCTION, VERIFICATION &TESTING
OF ALL LOGIC GATES
PURPOSE:
To learn:
1. Basic Logic gates and their operation

2. Verification and interpretation of truth tables of all Logic gates
EQUIPMENT:
1. Advanced Digital Logic Trainer

2. Digital Multimeter
3. Connecting Wires
4. IC Type 7400 Quadruple 2- input NAND gates
5. IC Type 7402 Quadruple 2- input NOR gates
6. IC Type 7404 Hex Inverters 1- input gates
7. IC Type 7408 Quadruple 2- input AND gates
8. IC Type 7432 Quadruple 2- input OR gate
9. IC Type 7486 Quadruple 2- input XOR gate
10. IC Type 74266 Quadruple 2- input XNOR gate
INTRODUCTION:
An integrated circuit (IC) is a small electronic device made out of a semiconductor material. A
semiconductor material is one which is neither a good conductor nor a good insulator.
Semiconductors make it possible to miniaturize electronic components, such as transistors.
Miniaturization not only reduces the size of components but also enables them to work faster
utilizing less energy.

Logic gates are digital circuits with one or more input and single output. They are the basic
building blocks of any logic circuit. Different logic gates are: AND, OR, NOT, NAND, NOR,
EX- OR and EX- NOR gate. There logic is briefly explained below:
AND gate:
Logic equation: Y= A.B
The output of AND gate is high only when both the inputs A and B are high.
OR gate:
Logic equation: Y= A+B
The output of OR gate is high when one of the inputs A or B is high, or both A and B are high.
NOT gate/inverter:
Logic equation: Y=A
The output of NOT gate is the complement of the input.
NAND gate:
Logic equation: Y=A.B
The output of NAND gate is high when one of the inputs or both are low.
NOR gate:
Logic equation: Y=A+B
The output of NOR gate is high when both the inputs are low.
EX-OR gate:
Logic equation: Y=A.B + A.B

The output of EX- OR gate is high when both inputs are at opposite logic levels.
EX-NOR gate:
Logic equation: Y=A.B + A.B
The output of EX-NOR gate is high only when both inputs are at same logic level.
The symbols for these gates are shown below:
Figure 1: Symbols for Logic gates

In a circuit, logic variables (values 0 and 1) can be represented as levels of voltage. The most
obvious way of representing two logic values as voltage levels is to define a threshold voltage;
any voltage below the threshold represents one logic value and voltages above the threshold
correspond to other logic value.
To implement the threshold voltage concept, a range of low and high voltage levels is defined, as
shown in figure 2. The figure indicates that voltages in the range GND to V 0, max represent logic
level 0. Similarly, the range from V1, min to VCC corresponds to logic value 1. Logic signals do not
normally assume voltages in undefined range except in transition from one logic value to the
other.

Figure 2: Representation of logic values by voltage levels
PROCEDURE:
1. Turn ON the Advanced Digital Logic trainer.

2. Connect IC 74LS00 (NAND gate IC) already present on the trainer to VCC and ground
according to the pin configuration given below.
3. Apply four combinations of input to each gate of the IC as shown in the diagram below
and complete table 1.1. Compare your results with the truth table given below.
INPUT OUTPUT
A B Gate 1 Gate1 Gate 2 Gate2 Gate 3 Gate3 Gate 4 Gate4
(V) (H/L) (V) (H/L) (V) (H/L) (V) (H/L)
L L
L H
H L
H H

Table 1.1
4. Connect IC 74LS02 (NOR gate IC) already present on the trainer to VCC and ground
5. Apply four combinations of input to each gate of the IC as shown in the figure and
complete table 1.2. Compare your results with the truth table given.
INPUT OUTPUT
(V) (H/L) (V) (H/L) (V) (H/L) (V) (H/L)
L L
L H
H L
H H
Table 1.2

6. Connect IC 74LS04 (Inverter) already present on the trainer to V CC and ground according to
the pin configuration given below.
7. Apply two combinations of input to each gate of the IC according to the diagram below and
complete table 1.3. Compare your results with the truth table given.
INPU OUTPUT
T
A Gate Gate Gate Gate Gate Gate Gate Gate Gate Gate Gate Gate
1 (V) 1 2 (V) 2 3 (V) 3 4 (V) 4 5 (V) 5 6 (V) 6
(H/L) (H/L) (H/L) (H/L) (H/L) (H/L)
H
L
Table 1.3
8. Connect IC 74LS08 (AND gate IC) already present on the trainer to VCC and ground
9. Apply four combinations of input to each gate of the IC as shown below and complete table
1.4. Compare your results with the truth table given.

INPUT OUTPUT
(V) (H/L) (V) (H/L) (V) (H/L) (V) (H/L)
L L
L H
H L
H H
Table 1.4
10. Connect IC 74LS32 (OR gate IC) already present on the trainer to VCC and ground
11. Apply four combinations of input to each gate of the IC as shown below and complete table
1.5. Compare your results with the truth table given.

INPUT OUTPUT
(V) (H/L) (V) (H/L) (V) (H/L) (V) (H/L)
L L
L H
H L
H H
Table 1.5
12. Connect IC 74LS86 (XOR gate IC) already present on the trainer to VCC and ground
13. Apply four combinations of input to each gate of the IC and complete table 1.6. Compare
your results with the truth table given.

INPUT OUTPUT
A B Gate1 Gate1 Gate2 Gate2 Gate3 Gate3 Gate4 Gate4
(V) (H/L) (V) (H/L) (V) (H/L) (V) (H/L)
L L
L H
H L
H H
Table 1.6
14. Complete the lab assignment given on the next page.

Lab Assignment (To be Designed & Implemented by the Student)
Draw the symbol and truth table of EX-NOR gate. Write down its Boolean equation with
reference to the truth table variables.
Symbol:
Boolean Equation:

Truth Table:
Draw waveform diagrams for all the above analyzed logic gates in terms of inputs and outputs
they reserve with respect to reference input waveforms.

CONCLUSION:
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
_______________________________________________________________
Task:
report which should include the analysis of the results of the experiment.
Date: ____________________________
EXPERIMENT #16

DESIGN AND IMPLEMENTATION OF DECIMAL TO BINARY
ENCODER
EQUIPMENT:

2. Connecting Wires
3. IC Type 7432 Quadruple 2- input OR gate
INTRODUCTION:
An encoder is a combinational circuit that performs the inverse operation of a decoder. If a
device output code has fewer bits than the input code has, the device is usually called an encoder
e.g. 2n – to -n, priority encoders.
The simplest encoder is 2n – to –n binary encoder, where it has only one of the 2 n inputs =1 and
the output is the n-bit binary number corresponding to the active input.
Octal to binary encoder takes 8 inputs and provides 3 outputs, thus doing the opposite of what
the 3-to-8 decoder does. At any one time, only one input line has a value of 1.
Decimal to binary encoder takes 10 inputs and provides 4 outputs, thus doing the opposite of
what the 4-to- 10 decoder does. At any one time, only one input line has a value of 1.
DECIMAL TO BINARY ENCODER:

Figure 2: Decimal to BCD Encoder Logic Circuit
For 10-4 decimal to BCD encoder with inputs D0-D9 the logic expressions of the outputs A0-A3
will be as given below:
A3 = D8 + D9
A2 = D4 + D5 + D6 + D7
A1 = D2 + D3 + D6 + D7
A0 = D1 + D3 + D5 + D7 + D9
Decimal Decimal Code Inputs BCD Code

Digits Outputs

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 A3 A2 A1 A0
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 1 0 0 0 0 0 0 0 0 0 0 0 1
2 0 0 1 0 0 0 0 0 0 0 0 0 1 0
3 0 0 0 1 0 0 0 0 0 0 0 0 1 1
4 0 0 0 0 1 0 0 0 0 0 0 1 0 0
5 0 0 0 0 0 1 0 0 0 0 0 1 0 1
6 0 0 0 0 0 0 1 0 0 0 0 1 1 0
7 0 0 0 0 0 0 0 1 0 0 0 1 1 1
8 0 0 0 0 0 0 0 0 1 0 1 0 0 0
9 0 0 0 0 0 0 0 0 0 1 1 0 0 1
Table 2: Truth Table for Decimal to Binary Encoder
PROCEDURE:
1. Connect the Advance Digital Logic Trainer to the 220V AC supply.

2. Verify all gates of 74LS32 ICs.
3. For Octal to Binary encoder, make connections as shown in figure 1 and verify the table
1.
4. As 4 input OR gate is used in figure 1 so to make 4 inputs OR gate with the help of 2
inputs OR gate follow the figure below.

Figure 3: Equivalent Circuit for 4 input OR- Gate
5. For Decimal to BCD encoder make connections as shown in figure 2 and verify the table
2.
6. As 5 input OR gate is used in figure 2 so to make 5 input OR gate with the help of 2 input
OR gate follow the figure given below
Figure 4: Equivalent Circuit of 5 input OR-Gate

Design a 4 bit Priority Encoder Logic circuit diagram.
Priority Encoder (Introduction)

______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
__________________________________________________________________
Priority Encoder Inputs Priority Encoder Outputs

D0 D1 D2 D3 Y2 Y1 Y0
Table 3: 4 Bit Priority Encoder
Logic gate based diagram of 4- bit Priority Encoder Circuit:

CONCLUSION:

______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
_______________________________________________________________
Task:
Date: ____________________________
EXPERIMENT#17
Design and Implementation of 2-to-4, 3-to-8 and BCD to seven

segment display Decoders using Logic gates.
EQUIPMENT:

2. Connecting Wires
3. IC Type 7404 Hex Inverters
5. IC Type 7447 BCD-to-Seven segment decoder/driver
INTRODUCTION:
A decoder is a logic circuit that accepts a set of inputs that represent a binary number and
activates only the output that corresponds to that input number. In other words, a decoder circuit
looks at its inputs, determines which binary number is present there, and activates the one output
that corresponds to that number; all other inputs remain inactive.
Decoder can be referred to in several ways. For example, 3 –to-8 line decoder means it has 3
input lines and 8 output lines. It can also be called binary to octal decoder or converter because it
takes a three bit binary input code and activates one of the eight (octal) outputs corresponding to
that code.
7- Segment display is used to display decimal numbers 0 to 9 and sometimes hex characters A to
G. It is called 7- segment display because it has 7 segments which glow in different
combinations to show decimal numbers from 0 to 9.
The task for this lab is to design a circuit that takes BCD input and produces an output that
makes only required segments to glow which produce the display of exactly the same number
whose BCD code has been given as input to the circuit. Therefore, it can be concluded that the
circuit will have 4 input lines and 7 output lines each being able to control one of the 7 segments
of the display.

Figure 1: 7- Segment display configuration
2 – to - 4 LINE DECODER:

Figure 2: 2-to-4 Line Decoder Logic Circuit
Table 1: 2-to-4 Line Decoder Truth Table

3-to-8 LINE DECODER:

Figure 3: 3-8 line Decoder Logic Circuit

BINARY INPUTS DECODED OUTPUTS
A B C D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
Table 2: 3-to-8 Line Decoder Truth Table
BCD TO SEVEN SEGMENT DISPLAY DECODER:

Figure 4: BCD to 7 Segment display IC based Circuit
BCD INPUTS Illuminated Segment OUTPUT

A B C D A b c d e f g (Digit Displayed)
0 0 0 0 1 1 1 1 1 1 0 0
0 0 0 1 0 1 1 0 0 0 0 1
0 0 1 0 1 1 0 1 1 0 1 2
0 0 1 1 1 1 1 1 0 0 1 3
0 1 0 0 0 1 1 0 0 1 1 4
0 1 0 1 1 0 1 1 0 1 1 5
0 1 1 0 1 0 1 1 1 1 1 6
0 1 1 1 1 1 1 0 0 0 0 7
1 0 0 0 1 1 1 1 1 1 1 8
1 0 0 1 1 1 1 1 0 1 1 9

Table 3: Truth table for BCD to Seven Segment Display Decoder
PROCEDURE:
1. Connect the Advance Digital Logic Trainer to the 220V AC supply.
2. Verify all logic gates of 74LS08 and 74LS04 ICs.
3. For 2-to-4 line decoder make connections as shown in figure 2 and verify table 1.
4. For 3-to-8 line decoder make connections as shown in figure 3 and verify table 2.
5. For BCD to 7-segment Decoder circuit make connections as shown in figure 4 and
verify table 3.

Design a block diagram based and logic gate based circuit of 4 inputs x 16 outputs decoder
using two 3 inputs x 8 outputs decoders.
Block Diagram:

Logic Gate Based Diagram:

CONCLUSION:
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
_______________________________________________________________
Task:
Date: ____________________________
Name: ---------------------------------
Registration No: ----------------------
Teacher’s Initial: ----------------------
Date performed: -----------------------
EXPERIMENT # 18
MULTIPLEXERS AND DEMULTIPLEXERS
PURPOSE:
To learn:
1. Introduction, basic principle and working of Multiplexer and

Demultiplexer

2. Design and implementation of 2-to-1, 4-to-1 Multiplexer and 1-to-4
Demultiplexer Circuits using Logic gates
EQUIPMENT:

2. Connecting Wires
3. IC Type 7404 Hex Inverters
5. IC Type 7432 Quadruple 2- input OR gates
INTRODUCTION:
Multiplex means “many into one”. Multiplexing is the process of transmitting a large number of
information units over a smaller number of channels or lines. A digital multiplexer (MUX) or
data selector is a combinational circuit that selects digital information from several sources (2n)
lines and transmits information on a single output line. The multiplexer has several data-input
lines and a single output line. The selection of a particular input line is controlled by a set of
selection lines.
It is designed to switch one of several input lines through to a single common output line by the
application of a control switch. Multiplexers operate like very fast acting multiple position rotary
switches connecting or controlling multiple input lines called “channels” one at a time to the
output.

Figure 1: Basic Multiplexing Switch
Demultiplex means “one into many”. Demultiplexing is the process of taking information from
one input and transmitting the same over several outputs. A demultiplexer is a logic circuit that
receives information on a single input and transmits the same information over several (2n)
output lines. A demultiplexer is the opposite of a multiplexer in its operation.
The functional diagram of Multiplexer and Demultiplexer is shown below. The Multiplexer
circuit has n input signals, m control signals and one output signal. The Demultiplexer circuit has
one input signal, m control signals and n output signals. The select input code determines to
which output the DATA input will be transmitted. As the serial data is changed to parallel data,
the multiplexer is also called a distributor or decoder.

Figure 2: Block diagrams of Multiplexer and Demultiplexer
2-to-1 MULTIPLEXER:
Figure 3: 2-to-1 Multiplexer Block Diagram

Figure 4: 2- Inputs to 1 –Output Multiplexer Logic Diagram
SELECT SWITCH OUTPUT

S Z
0 D0
1 D1
Table 1: 2-to-1 Multiplexer Truth Table
4-to-1 MULTIPLEXER:

Figure 5: 4-to-1 Multiplexer Block Diagram
Figure 6: 4-to-1 Multiplexer Logic Circuit Diagram
SELECT SWITCHES OUTPUT

S1 S0 Z
0 0 D0
0 1 D1
1 0 D2
1 1 D3
Table 2: 4-to-1 Multiplexer
1-to-4 DEMULTIPLEXER:

Figure 7: 1-to-4 Demultiplexer Block Diagram
Figure 8: 1-to-4 Demultiplexer Logic Circuit Diagram
ENABL INPUT SELECT DEMULTIPLEXED

E SWITHES OUTPUTS
E A S1 S0 Y3 Y2 Y1 Y0
0 X X X 0 0 0 0
1 1 0 0 0 0 0 1

1 1 0 1 0 0 1 0
1 1 1 0 0 1 0 0
1 1 1 1 1 0 0 0
Table 3: 1-4 Demultiplexer Truth table
PROCEDURE:
1. Connect the Advanced Digital Logic Trainer to the 220V AC supply.
2. Verify all gates of ICs 74LS08, 74LS08 and 74LS32.
3. For 2 input multiplexer connect the circuit as shown in figure 4 and verify table 1.
4. For 4-input multiplexer connect the circuit as shown in figure 6 and verify table 2.
5. For 1-to-4 line demultiplexer connect the circuit as shown in figure 8 and verify the table
3.

Design a Quadruple 2 inputs to 1 output line Multiplexer.

Truth table of Quadruple 2 inputs to 1 output line Multiplexer:

CONCLUSION:
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
_______________________________________________________________
Task:
Date: ____________________________


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LIST OF AUTHORS

Sr. # Name Date Modified Contributions

INDUSTRIAL ELECTRONICS LAB MANUAL 1

Engr. Reda Gelani

University of Central Punjab, Lahore

INDUSTRIAL ELECTRONICS LAB MANUAL 2

Copyrights © reserved with the author.

Printed in Pakistan, January 2017.

INDUSTRIAL ELECTRONICS LAB MANUAL 3

1. National Library of Engineering Sciences:

Azhar Hussain Shah is also the author of Laboratory manuals as below;

INDUSTRIAL ELECTRONICS LAB MANUAL 4

Azhar Hussain Shah

INDUSTRIAL ELECTRONICS LAB MANUAL 5

To demonstrate the use of a Semiconductor Diode as a

3 To demonstrate the use of a Semiconductor Diode as a 21

To demonstrate the operation of simple capacitor filter

To investigate the Electrical Operation of Basic

To plot the Zener Diode Characteristics and to

To investigate drain characteristics of Metal Oxide

13 To investigate the use of op amp as: 121

INDUSTRIAL ELECTRONICS LAB MANUAL 6

Design and implementation of decimal to binary

Design and Implementation of 2-to-4, 3-to-8 and BCD

TO STUDY THE CHARACTERSTICS OF A SEMI-

INDUSTRIAL ELECTRONICS LAB MANUAL 7

When an N-Type semiconductor is bounded to a P-Type semiconductor, a junction is formed as

THE IDEAL DIODE

INDUSTRIAL ELECTRONICS LAB MANUAL 8

Figure 1.3. The ideal Characteristics of a Diode

1. Connect the circuit as shown in Fig.1.4.

INDUSTRIAL ELECTRONICS LAB MANUAL 9

8. Set the function and range switch of VOAM to 50 Volt DC.

INDUSTRIAL ELECTRONICS LAB MANUAL 10

OBSERVATION AND CALCULATIONS:

INDUSTRIAL ELECTRONICS LAB MANUAL 11

INDUSTRIAL ELECTRONICS LAB MANUAL 12

INDUSTRIAL ELECTRONICS LAB MANUAL 13

1. Calculate for remaining columns of Table 1.1 and Table 1.2

Teacher / Supervisor’s Signature: __________________________________

Fig2.1.a Positive Half wave rectifier circuit

INDUSTRIAL ELECTRONICS LAB MANUAL 15

HALF-WAVE AVERAGE DC VOLTAGE:

Fig2-2 Half wave rectified Voltage showing DC value

V dc =0.318 V m (half wave)

INDUSTRIAL ELECTRONICS LAB MANUAL 16

V m = maximum (peak) value of AC voltage.

HALF-WAVE PEAK INVERSE VOLTAGE (PIV):

Fig2-3 Half wave rectifier circuit

Vav(input)=______________ volts. Vp(calculated)=___________volts.

INDUSTRIAL ELECTRONICS LAB MANUAL 18

Vrms=______________ volts. Vavg(input)=_________ volts.

Output voltage waveform:

INDUSTRIAL ELECTRONICS LAB MANUAL 19

Please attach the separate sheet.

INDUSTRIAL ELECTRONICS LAB MANUAL 20

Teacher / Supervisor’s Signature: ______________________

INDUSTRIAL ELECTRONICS LAB MANUAL 22

FULL-WAVE AVERAGE (DC) VOLTAGE

Vdc=2(0.318Vm)=0.636Vm (full wave)

INDUSTRIAL ELECTRONICS LAB MANUAL 23

FULL-WAVE PEAK INVERSE VOLTAGE

INDUSTRIAL ELECTRONICS LAB MANUAL 24

Vav(input)=____ volts. Vp(calculated)=_volts.

Vrms=______ volts. Vavg(input)=_ volts.

Vrms = volts. Vav = volts.

Vp = volts. Vav = volts. Vrms = __ volts.

A = volts. B = volts.

A = volts. B = volts.