This program is non restoring division implementation.

In the test bench start must be 1 through out.

Module modulus(q,r,ready,dividend,divisor,start,clk);

Input [15:0]dividend,divisor;
Input start,clk; // start to switch on the system and do the
operations only if the inputs are valid
Output q,r;
Output ready; // ready to let us know one iteration is
finished and is ready to execute next iteration.

Reg [31:0]qr;
Reg [16:0]diff;
Wire [15:0] r = qr[31:16];
Wire [15:0]q = qr[15:0];

Reg [4:0]bit;
Wire ready = !bit;
Initial bit=0;

always@ (posedge clk)

if(ready && start) begin
qr={16’d0,dividend};
bit = 16; // For 16 bit operations
end
else
begin
diff = qr[31:15] – {1’b0,divisor};
if(diff[16])
qr={qr[30:0],1’d0};
else
qr={diff[15:0],qr[14:0],1’d1};
bit = bit-1;
end
endmodule