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Copyright 2018-2019 - Maven Silicon Softech Pvt Ltd. All Rights Reserved.
This source code is an unpublished work belongs to Maven Silicon Softech Pvt Ltd.
It is considered a trade secret and is not to be divulged or used by parties who
have not received written authorization from Maven Silicon Softech Pvt Ltd.
Webpage: www.maven-silicon.com
Filename: half_adder_tb.v
Date: 01/05/2018
Email: online@maven-silicon.com
Version: 1.0
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module half_adder_tb();
reg a,b;
wire sum,carry;
integer i;
initial
begin
a = 1'b0;
b = 1'b0;
end
initial
begin
for (i=0;i<4;i=i+1)
begin
{a,b}=i;
#10;
end
end
endmodule