MICROPROCESSOR AND MICROCONTROLLER

SEMESTER-IV
YEAR: II

UNIT IV
I/O INTERFACING
PART A

1. What are the advantages of DRAM?

The advantages of DRAM are,

1. Higher packaging density
2. Lower cost
3. Less power consumption

2. How the refresh cycle is different from memory read cycle?

The refresh cycle is different from the memory read cycle in the following aspects.
(i) The memory address is not provided by the processor address bus, rather
it is generated by a refresh mechanism counter known as refresh counter.
(ii) Unlike memory read cycle, more than one memory chip may be enabled at a
time so as to reduce the number of memory refresh cycles.
(iii) The data enable control of the selected memory chip is deactivated, and
data is not allowed to appear on the system data bus during refresh.
(iv) Memory refresh is an independent regular activity.

3. What are the methods of interfacing I/O devices? (AU-Nov’06)

The two methods of interfacing general i/o devices are:

1. I/O mapped
2. Memory mapped

4. What are the modes of operation is used in 8255?

The modes of operation used in 8255 are:

1. I/O mode
(i) Mode 0 (Basic I/O)
(ii) Mode1 (Strobed I/O)
(iii) Mode 2 (Strobed bidirectional I/O)
2. BSR mode (Bit Set/ Reset Mode)
5. What are the features of mode 0 in 8255?

The features of mode 0 in 8255 are:

1. Two 8-bit ports(port a & port B) and two 4-bit ports
(port C upper and lower) are available.
2. Any port can be used as an input or output port.
3. Output ports are latched. Input ports are not latched.
4. A maximum of four ports are available so that overall 16 I/O
configurations are possible.

6. What are the features of Mode 1 in 8255?

The features of mode 1 in 8255 are:

1. Two groups- group A and group B are available for strobed data transfer.
2. Each group contains one 8-bit data I/O port and one 4-bit control/data port.
3. The 8-bit data port can be either used as input or an output port.
4. Both the inputs and outputs are latched.

7. What are the inputs and output control signals used in mode 1 of 8255?

Input control signals are: STB, IBF, INTR

Output control signals are: OBF, ACK, INTR

8. What are the features of mode 2 of 8255?

The features of mode 2 of 8255 are:

1. The single 8-bit port in group A is available.
2. The 8-bit port is bidirectional and additionally a 5-bit control bit is available.
3. Three I/O lines are available at port C.
4. Inputs and outputs both are latched.
5. The 5-bit control bit in port C is used for generating/accepting
handshake signals for the 8-bit data transfer on port A.
9. What are the different mode of operation of Timer(8253)?
(AU-May’06) (AU-NOV’06)

The different mode of operation of timer (8253) are:

1. Mode 0 (Interrupt or terminal count)
2. Mode 1 (Programmable monoshot)
3. Mode 2 (Rate generator)
4. Mode 3 (Square wave generator)
5. Mode 4 (Software triggered strobe)
6. Mode 5 (Hardware triggered strobe)

10. What is rate generator?

 Rate generator in timer mode 2 is divide by N counter. In this mode, if N is
loaded as the count value, then after N pulses the output becomes low only for one
clock cycle. The count N is reloaded and again the output becomes high and remains
so for N clock pulses.

11. What is the function of priority resolver?

The function of priority resolver unit determines the priorities of the

interrupt requests appearing simultaneously. The highest priority is selected
and stored into the corresponding ISR bit during INTA pulse.

12. What is PS/EN pin? (AU-May’07)

PS/EN pin is a dual purpose pin. When the chip is used in buffered mode, it
can be used as a buffer enable to control buffer transreceivers. If this is not used in
buffered mode then the pin is used as input to designate whether the chip is used as a
master or a slave.

13. What are the modes of 8259? (AU-May’05)

The modes of 8259 are:

1. Fully nested mode
2. End of Interrupt (EOI)
3. Automatic Rotation
4. Automatic EOI mode
5. Specific Rotation
6. Special mask mode
7. Edge/level triggered mode
8. Reading 8259 status
9. Poll command
10.Special fully nested mode
11.Buffered mode
12.Cascade mode

14. What is the function of scan counter? (AU-Nov’06)

The function of scan counter is to scan the key matrix and refresh the display
with two modes.
Encoded mode: The counter provide a binary count that is to be externally decoded
to provide the scan lines for keyboard and display.
Decoded mode: The counter internally decodes the least significant 2-bits and provides
a decoded one out of 4 scan on SL0-SL3.
15. What are operations of 8279?

The operations of 8279 are:

1. Keyboard mode
(i) Scanned keyboard mode with 2 key lock out
(ii) Scanned keyboard mode with N key rollover
(iii) Scanned keyboard special error mode
(iv) Sensor matrix mode
(v) Strobed input mode
2. Display mode
(i) Left entry mode
(ii) Right entry mode

16. List out three modes of Data Transmission. (AU-NOV’08)

The three modes of data communication are:

1. Simplex
2. Duplex
3. Half duplex

17. What is USART? ( AU-May’07)

USART is a Universal Synchronous Asynchronous Receiver and Transmitter.

It is mainly used for serial communication. It converts parallel data into a
serial stream of bits suitable for serial transmission. It also receive a serial stream
of bits and convert it into parallel data bytes to be read by a microprocessor.

18. What are the advantages of DMA? (AU-Nov’06)

The advantages of Direct Memory Access are:

(i) DMA mode of data transfer is the fastest amongst all the modes of data transfer.
(ii) In this mode, the device may transfer the data directly to/from memory without
any interference from the processor.

19. What is the function of mode set register?

The function of the mode set register is to enable the DMA channels individually
and also set the various modes of operation.

20. What are the types of operation in DMA? ( AU-May’05)

 The three types of DMA operation are,
1. Verify DMA operation
2. Write operation
3. Read operation

21. List the types of priorities used in DMA. (AU-May’06)

The types of priorities used in DMA are,

1. Fixed priority scheme
2. Rotating priority scheme.

22. Which type of decoding requires minimum hardware? (AU-APR’08)

23. What is key bouncing? (AU-APR’08)

24. Name the two modes used by the DMA processes to transfer data. (AU-NOV’06)

The two modes used by the DMA processes to transfer data are
1. Single transfer mode.
2. Block transfer mode.
3. Demand transfer mode.

26. What is the function of gate signal in 8254 timer? (AU-JUN’07)

The function of gate signal in 8254 timer is:

Gate = 1 enables counting
Gate = 0 disables counting

27. Write the format of ICW1 in 8259. (AU-JUN’07)

The format of ICW1(Initialization command word1) in 8259 is :

A0 D7 D6 D5 D4 D3 D2 D1 D0
0 A7 A6 A5 1 LTIM ADI SNGL IC4

28. 8253's OUT signal is to be used as a clock input of the desired frequency to a
particular device. Is it possible? How? (AU-NOV’09)
29. How is a memory-to-memory transfer accomplished using 8237? (AU-NOV’09)

31. What is the use of IRR (Interrupt Request Register)? (AU-NOV’08)

32. List the uses of USART. (AU-NOV’07)

The uses of USART are:

(i) At the transmission, it converts byte into eight serial bits.
(ii) At the reception, the serial bits are converted into parallel 8 bit data.
33. Describe the three major tasks needed to get meaningful information from
matrix keyboard. (AU-APR’08)
34. What are the different ways in which the 8-bit data bus of an interfacing
device can be connected to the 16 bit data bus of 8086? (AU-APR’08)
35. State the function of DSR and DTR pins in 8251. (AU-JUN’06)

36. List the features of 8259. (AU-JUN’06)

The features of 8259 are:

1. It is designed to minimize the software and real time overhead in
handling multi-level priority interrupts.
2. The 8259 can be programmed to accept either the level triggered or
the edge triggered interrupt request.
3. With the help of 8259 user can get the information of pending interrupts,
in-service interrupts and masked interrupts.

37. List the features of 8251. (AU-JUN’07)

The features of 8251 are:

1. It is an universal synchronous and asynchronous communication
controller.
2. It has built in baud rate generator.
3. It allows full duplex transmission and reception.
4. It is compatible with an extended range of Intel microprocessors.

38. What is the internal operating frequency of the 8279?How can you derive it
from any available clock signal? (AU-JUN’07)
39. Differentiate memory mapped and program controlled I/O. (AU-NOV’07)
40. What are the advantages of DRAM? (AU-NOV’07)

PART B

1. Explain in detail about DMA controller. (AU-Nov’06)

2. What is USART? Explain in detail. (AU-May’07)
3. Explain the keyboard and display controller with neat block diagram.
(AU-Nov’07, May’08)

4. Explain the programmable interrupt controller 8259 in detail. (AU-May’06) (16)

5. Explain the programmable interval timer 8253. (AU-May’06) (16)
6. Explain the parallel communication chip 8255 in detail. (AU-May’06) (16)
7. With a neat diagram, explain how 8251 is interfaced with 8085 and
used for serial communication. (AU- MAY’07) (16)
8. Describe the architecture and working of 8253. (AU- MAY’08) (12)
9. Describe the working of 8259 interrupt controller. (AU- MAY’08)
(AU- NOV’06) (10)
10. What is the use of CAS0, CAS1 and CAS2 signals? (AU- NOV’06) (4)
11. Write a program to generate triangular waveform using DAC 0800.
(AU-APR’08) (4)
12. Write an ALP to receive 100 bytes of data string serially using 8251.
(AU-APR’08) (6)
13. Draw the block diagram of Keyboard/display controller 8279 and
describe its operations. (AU-JUN’07) (AU-NOV’07) (16)
14. What is the use of DMA controller? Explain its operations with neat
block diagram. (AU-NOV’07) (16)
15. With a neat sketch and explain the operation of an Interrupt controller (8259)
(AU-NOV’06) (14)
17. Draw the block diagram of a DMA controller (8237) and explain its operation.
(AU-NOV’06) (16)
18. With the help of block diagram explain the operation of USART (8251A)
(AU-JUN’07) (10)
19. Discuss the salient features of 8259 – programmable interrupt controller.
(AU-JUN’07) (6)
20. Describe the various modes of operations in 8253 programmable interval Timer.
(AU-JUN’07) (8)
21. Explain the operation of DMA controller (8237). (AU-JUN’06) (16)
(AU-JUN’07) (8)
22. With a neat diagram discuss the various modes of operation of 8255.
(AU-JUN’07)
23. Show how two 8255 chip can be connected in an connected in an 8086-based
system to form a 16-bit port. (AU-NOV’09)
24. With a neat diagram discuss the operation of a DMA controller. Show how
such a controller can be connected in an 8086-based system. (AU-NOV’09)
24. Draw the block diagram of 8257 and explain the functions of each block.
(AU-NOV’08)
26. With a neat block diagram, explain in detail the internal architecture of 8257
and its register organization. (AU-NOV’07) (16)
27. Discuss about the architecture, Signal description and modes of operation
of 8279. (AU-NOV’07) (16)
28. Discuss how the DMA controller is interfaced with the 8085 processor.
(AU-APR’08) (16)
29. Discuss in detail about the programmable interrupt controller and its
cascading mode of operation. (AU-APR’08) (16)
31. With block diagram explain Interrupt controller. (AU-JUN’06) (16)
33. With a neat diagram ,explain how 8251 is interfaced with 8085 and used
for serial communication. (AU-JUN’07) (16)