EC304 VLSI

Syllabus
• IC Fabrication Technology,
• CMOS IC Fabrication Sequence,
• CMOS inverters, Design rules, Static CMOS
Design,
• Dynamic CMOS circuits, Pass transistor,
• Read Only Memory, Random Access Memory,
• Sense amplifiers, Adders, multipliers, Testing
of VLSI circuits.
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 Objective
• Knowledge about IC Fabrication Techniques
• Analysis and design of MOSFET and CMOS
logic circuits.

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 Text books
• Integrated Circuits by K. R. Botkar
• VLSI Technology by S M Sze
• Introduction to VLSI Circuits and Systems by
John P. Uyemura

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 VLSI
• Very-large-scale Integration
Process of creating an integrated circuit
(IC) by combining millions of MOS transistors
onto a single chip.
• 1970s when MOS integrated circuit chips were
widely adopted
• VLSI devices  microprocessor and memory
chips

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 VLSI
• Applications of ICs in high-performance
computing, controls, telecommunications,
image and video processing, and consumer
electronics has been rising at a very fast pace.

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Integrated circuit classification
Name Signification Year Number of Number of
Transistors Logic Gates

SSI Small-scale 1964 1 to 10 1 to 12

integration

MSI Medium-scale 1968 10 to 500 13 to 99

integration
.

LSI Large-scale 1971 500 to 20,000 100 to 9,999

integration
Very large- 20,000 to 10,000 to
VLSI scale 1980 1,000,000 99,999
integration
Ultra-large- 1,000,000 100,000 and
ULSI scale 1984 and more more
integration
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Evolution of Minimum Feature Size

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 VLSI advantages
• Size and weight
• Reliability
• Cost
• Power consumption
• Speed

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 VLSI Applications
• VLSI is an implementation technology for electronic circuitry -
analogue or digital
• It is concerned with forming a pattern of interconnected switches
and gates on the surface of a crystal of semiconductor
• Microprocessors
– personal computers
– microcontrollers
• Memory - DRAM / SRAM
• Special Purpose Processors - ASICS (CD players, DSP applications)
• Optical Switches
• Has made highly sophisticated control systems mass-producable
and therefore cheap
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 IC Products
• Processors
– CPU, DSP, Controllers
• Memory chips
– RAM, ROM, EEPROM
• Analog
– Mobile communication,
audio/video processing
• Programmable
– PLA, FPGA
• Embedded systems
– Used in cars, factories
– Network cards
• System-on-chip (SoC)
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 VLSI
• Semiconductor technology
• Discrete & Integrated Circuits
• Monolithic Circuits & Hybrid Circuit
• Analog IC & Digital Ics

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 Monolithic Integrated Circuits
• Is one in which all circuit components and
their inter-connections are formed on a single
thin wafer called the substrate.

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 Monolithic IC process
1. P-substrate:
– 1st step. Dimensions 25 cm long and 2.5 cm diameter.
– Bottom most layer of the circuit is made (subtrate or
wafer).
– Wafer is a polished silicon crystal cut in to required
size.
– High resistivity p-type semiconductor.

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 Monolithic IC process
2. Epitaxial Growth:
– Wafers in a diffusion furnace.
– Gas mixture containing silicon and pentavalent
atoms which is passed over the wafers.
– Thin layer of n-type semi-conductor heated on
surface.
– All passive and active components of the circuit
are fabricated.

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 Monolithic IC process
3. Insulating Layer:
– To prevent contamination, silicon dioxide formed
over the surface of the epitaxial layer.
– Pure oxygen.

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 Monolithic IC process
4. Photlithographic and Etching Process:
– Photolithographic process involves removal of
some portions of the silicon dioxide.
– To add impurities (desired components) to the
epitaxial layer.

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 Monolithic IC process
5. Component Diffusion:
– Process of fabricating the circuit components on
the wafer.
– Aluminium is used to create the required
interconnections between the components.

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 Monolithic IC process
6. Chips:
– Wafer is divided into a large
number of areas.
– Mass production is the reason for
the low cost of ICs.
– Wafer is then cut and assembled in
the required chips.
– Ceramic casing and external leads
are made after mounting the IC on
to the cover, a process called
encapsulating.
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Shrinking Device Dimensions

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Increasing Function Density

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Increasing Clock Frequency

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Decreasing Supply Voltage

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Module -1

Integrated circuits by K R Botkar

 Module – 1 (part a)
• Material Preparation
– Purification of Si,
– Crystal growth (CZ and FZ process),
– Si wafer preparation

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 Basic IC fabrication steps
• Wafer Preparation
• Oxidation
• Ion Implantation
• Chemical Vapour Deposition (CVD)
• Photolithography
• Metallization
• Packaging

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Wafer chip

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 Material Preparation
• Commonly available natural sources of silicon
are silica and silicates.
Production of Electronic Grade Silicon (EGS)

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Production of Electronic Grade Silicon
(EGS)
• Purest form of Si (99.99999999%)
• Poly crystalline material
• Impurities – B, C & residual donors.
• Raw material for the preparation of Single
Crystal Si
• Pure EGS will have doping elements in ppb
range, and carbon less than 2 ppm
• EGS is purified from MGS (Metallurgical Grade
Silicon)

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 Metallurgical Grade Si (MGS)
• 98% pure form

• Impurities
– Fe and Al

• Produced in Arc furnace

– Quartzite and carbon

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 Metallurgical Grade Si (MGS)
• Quartzite
– Relatively pure form of sand
– SiO2

• Carbon
– Coal
– Coke
– Wood chips

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 Metallurgical Grade Si (MGS)
• Overall reaction
– SiC + SiO2  Si + SiO + CO
(solid) (solid) (liquid) (gas) (gas)

• Molten Si removed from bottom of the

furnace.
• Solidified at a purity of 98%
– Purity is not enough for the manufacture of
semiconductor devices

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Production of EGS from MGS

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 Production of EGS from MGS
• MGS has to be pulverized mechanically
– Si + 3HCl  SiHCI3 + H2
(solid) (gas) (3000C) (gas) (gas)

• Impurities are formed, SiCl4 & chlorides.

• Purification process has to be done by
fractional distillation method
• Purified SiHCI3 is subjected to CVD

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 Production of EGS from MGS
• Purified  chemical vapor deposition (CVD).
– 2SiHCl3 + 2H2  2Si + 6HCl
(gas) (gas) (solid) (gas)

• At 11000C,
• To achieve high overall efficiency, a feedback
or recycling of reaction of by-products is done

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 Production of EGS from MGS
• EGS can also be produced by pyrolysis method
in which silane (SiH4) will be reacted with heat
• Main advantage of using silane instead of
trichlorosilane is the lower production cost
and less production of harmful reaction by-
products
– SiH4 + HEAT  Si + 2H2
(gas) (solid) (gas)

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 Crystal Structure and Growing
• Silicon wafer, must be single crystal, but it does
not represent an ideal crystal due to:
– The wafer has finite boundaries; thus, atoms at the
surfaces are incompletely bonded as against those in
the bulk of the wafer material
– The atoms are displaced from their ideal locations by
thermal agitation
– Real crystals have defects which are mainly classified
into:
• Point defect
• Line defect (dislocation)
• Area or planar defect
• Volume defect
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 Crystal Structure and Growing
• Though processes the EGS obtained is highly refined, it is
not suitable enough for the manufacturing IC’s.
• Single crystal Si manufacture
• Two types:
– Czochralski technique (CZ)
– Float zone (FZ) technique
• Crystal Growing
– Phase change from solid, liquid or gas
phases to crystalline solid phase
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 Crystal Structure and Growing
• Two types:
Czochralski technique Float zone (FZ)
(CZ) technique
Dominant technique for Mainly used for small
manufacturing single sized wafers
crystals
Specially suited for the Producing specialty
large wafers that are wafers that have low
currently used in IC oxygen impurity
fabrication. concentration.
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 Crystal Structure and Growing
• Various components of CZ & FZ process are
– Furnace
– Crystal pulling mechanism
– Ambient control – atmosphere
– Control system

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 Czochralski (CZ) Process
• EGS
– Still polycrystalline Si
• CZ crystal growth process
– EGS is processed to become single crystal
• Single crystal Si
– Ingot

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Czochralsky (CZ)
process

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Czochralsky (CZ) Process Apparatus
• Consists of:
– Furnace
– Crystal pulling mechanism
– Ambient control facility
– Control system circuitry

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CZ process

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 Silicon Ingot Grown by CZ Method
• Photograph
courtesy of
Kayex Corp., 300
mm Si ingot

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Silicon Ingot Grown by CZ Method

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 CZ process
• Impurities: oxygen and carbon
– Oxygen in Si arises from dissolution of curcible during
growth
– Carbon in Si arises from dissolution of its transportation
from graphite parts in furnace to melt
• p-type (B) doped CZ process  resistivity from
0.0005 to 50 ohm-cm
• n-type (As, P) doped CZ process  resistivity from
0.005 to 40 ohm-cm

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 FLOAT ZONE (FZ) PROCESSS
• Small wafer preparation

• Low oxygen impurity

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 FLOAT ZONE (FZ) PROCESSS
• With a radio frequency field both are partially
melted.
• The seed is brought up from below to make
contact with the drop of melt formed at the tip
of the poly rod.
• A necking process is carried out to establish a
dislocation free crystal before the neck is allowed
to increase in diameter to form a taper and reach
the desired diameter for steady-state growth.
• As the molten zone is moved along the
polysilicon rod, the molten silicon solidifies into a
single Crystal and, simultaneously, the material is
purified
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 Si wafer preparation
• Ingot Trimming and Slicing
• Wafer Polishing and Cleaning
• Wafer Processing Considerations

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 Ingot Trimming & Slicing
• Extreme top & bottom portions are cut off
• Surface is ground
– Constant diameter of 100, 150, or 300mm

• Crystallographic orientation flat

– Along the length of ingot

• Circular slices or wafers

– 600 – 1000 µm thick

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 Wafer Polishing and Cleaning
• When the wafer is sliced, its surface will be
heavily damaged
• Reasons for polishing are:
– To remove the damaged silicon from the sawn
surface
– To produce a highly planar or flat surface that will
be required for the photo-lithographic process
especially when flue-line geometries are involved
– To improve the parallel
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 Wafer polishing & Cleaning
• Chemical etch
– Acid mixture
• Nitric Acid
– Oxidize the surface
• Hydrofluoric Acid
– Dissolve the oxide

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 Wafer polishing & Cleaning
• Mechanical polishing
–Polished mechanically on a wheel
–Help of Al abrasive powders
–Mirror like finish

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 Wafer Processing Considerations
 Chemical Cleaning:
– Remove organic films, heavy metals & particulars

• Aqueous mixture of
– HCl – H2O2
– H2SO4 - H2O2

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 Wafer Processing Considerations
 Gettering Treatments:
• Transition group elements which act as the
metallic impurities
– Precipitated forms of these impurities are usually
silicides (electrically conductive)
– Removes the impurities or defects from the
regions in a wafer where devices are fabricated

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 Wafer Processing Considerations
• Common techniques that are used for
gettering treatment are:
I. Common mechanical abrasion methods like
lapping and sand blasting are carried out to
damage the back surface of the wafer
II. A focused heat beam from a Q-pulsed, Nd-
YAG laser is used to damage the wafer
III. Intrinsic gettering - when an impurity oxygen
precipitates, defects are generated
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 Wafer Processing Considerations
 Thermal stress minimisation:
• Wafers experience thermal stresses as they
are subjected to high-temperature furnace
– To minimise thermal stress, wafers are withdrawn
slowly from the furnace, which minimise
temperature gradient

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