74HC245

Octal 3−State Noninverting

Bus Transceiver
High−Performance Silicon−Gate CMOS
The 74HC245 is identical in pinout to the LS245. The device inputs http://onsemi.com
are compatible with standard CMOS outputs; with pull−up resistors,
they are compatible with LSTTL outputs.
MARKING
The HC245 is a 3−state noninverting transceiver that is used for DIAGRAMS
2−way asynchronous communication between data buses. The device
has an active−low Output Enable pin, which is used to place the I/O
ports into high−impedance states. The Direction control determines 20
whether data flows from A to B or from B to A. HC
20 TSSOP−20
DT SUFFIX 245
Features ALYW G
1 CASE 948E
G
• Output Drive Capability: 15 LSTTL Loads
1
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
HC245 = Device Code
• Low Input Current: 1.0 mA
A = Assembly Location
• High Noise Immunity Characteristic of CMOS Devices L = Wafer Lot
• In Compliance with the Requirements Defined by JEDEC Standard Y = Year
W = Work Week
No. 7A G = Pb−Free Package
• ESD Performance: HBM > 2000 V; Machine Model > 200 V (Note: Microdot may be in either location)
• Chip Complexity: 308 FETs or 77 Equivalent Gates
• This is a Pb−Free Device
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.

© Semiconductor Components Industries, LLC, 2007 1 Publication Order Number:

March, 2007 − Rev. 1 74HC245/D
 74HC245

DIRECTION 1 20 VCC 2 18
A1 B1
3 17
A1 2 19 OUTPUT ENABLE A2 B2
4 16
A2 3 18 B1 A3 B3
5 15
A A4 B4 B
A3 4 17 B2
DATA 6 14 DATA
PORT A5 B5 PORT
A4 5 16 B3 7 13
A6 B6
A5 6 15 B4 8 12
A7 B7
A6 7 14 B5 9 11
A8 B8
A7 8 13 B6
1
DIRECTION
A8 9 12 B7 19
OUTPUT ENABLE
GND 10 11 B8 PIN 10 = GND
PIN 20 = VCC

Figure 1. Pin Assignment Figure 2. Logic Diagram

FUNCTION TABLE
Control Inputs
Output
Enable Direction Operation
L L Data Transmitted from Bus B to Bus A
L H Data Transmitted from Bus A to Bus B
H X Buses Isolated (High−Impedance State)
X = don’t care

ORDERING INFORMATION
Device Package Shipping †
74HC245DTR2G TSSOP−20* 2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.

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 74HC245

MAXIMUM RATINGS (Note 1)

Symbol Parameter Value Unit
VCC DC Supply Voltage *0.5 to )7.0 V
VIN DC Input Voltage *0.5 to VCC )0.5 V
VOUT DC Output Voltage (Note 2) *0.5 to VCC )0.5 V
IIK DC Input Diode Current $20 mA
IOK DC Output Diode Current $35 mA
IOUT DC Output Sink Current $35 mA
ICC DC Supply Current per Supply Pin $75 mA
IGND DC Ground Current per Ground Pin $75 mA
TSTG Storage Temperature Range *65 to )150 _C
TL Lead Temperature, 1 mm from Case for 10 Seconds 260 _C
TJ Junction Temperature Under Bias )150 _C
qJA Thermal Resistance TSSOP 128 _C/W
PD Power Dissipation in Still Air at 85_C TSSOP 450 mW
MSL Moisture Sensitivity Level 1
FR Flammability Rating Oxygen Index: 30% to 35% UL 94 V−0 @ 0.125 in
VESD ESD Withstand Voltage Human Body Model (Note 3) u2000 V
Machine Model (Note 4) u200

ILATCHUP Latchup Performance Above VCC and Below GND at 85_C (Note 5) $300 mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 20 ounce copper trace with no air flow.
2. IO absolute maximum rating must observed.
3. Tested to EIA/JESD22−A114−A.
4. Tested to EIA/JESD22−A115−A.
5. Tested to EIA/JESD78.

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
TA Operating Temperature, All Package Types –55 +125 _C
tr, tf Input Rise and Fall Time VCC = 2.0 V 0 1000 ns
(Figure 3) VCC = 4.5 V 0 500
VCC = 6.0 V 0 400

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 74HC245

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit
VCC –55 to
Symbol Parameter Test Conditions V 25_C v 85_C v 125_C Unit
VIH Minimum High−Level Input Voltage Vout = VCC – 0.1 V 2.0 1.5 1.5 1.5 V
|Iout| v 20 mA 3.0 2.1 2.1 2.1
4.5 3.15 3.15 3.15
6.0 4.2 4.2 4.2
VIL Maximum Low−Level Input Voltage Vout = 0.1 V 2.0 0.5 0.5 0.5 V
|Iout| v 20 mA 3.0 0.9 0.9 0.9
4.5 1.35 1.35 1.35
6.0 1.8 1.8 1.8
VOH Minimum High−Level Output Vin = VIH 2.0 1.9 1.9 1.9 V
Voltage |Iout| v 20 mA 4.5 4.4 4.4 4.4
6.0 5.9 5.9 5.9
Vin = VIH |Iout| v 2.4 mA 3.0 2.48 2.34 2.2
|Iout| v 6.0 mA 4.5 3.98 3.84 3.7
|Iout| v 7.8 mA 6.0 5.48 5.34 5.2
VOL Maximum Low−Level Output Vin = VIL 2.0 0.1 0.1 0.1 V
Voltage |Iout| v 20 mA 4.5 0.1 0.1 0.1
6.0 0.1 0.1 0.1
Vin = VIL |Iout| v 2.4 mA 3.0 0.26 0.33 0.4
|Iout| v 6.0 mA 4.5 0.26 0.33 0.4
|Iout| v 7.8 mA 6.0 0.26 0.33 0.4
Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 mA
IOZ Maximum Three−State Leakage Output in High−Impedance State 6.0 ±0.5 ±5.0 ±10 mA
Current Vin = VIL or VIH
Vout = VCC or GND
ICC Maximum Quiescent Supply Vin = VCC or GND 6.0 4.0 40 40 mA
Current (per Package) Iout = 0 mA
6. Information on typical parametric values and high frequency or heavy load considerations can be found in the ON Semiconductor
High−Speed CMOS Data Book (DL129/D).

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

Guaranteed Limit
VCC –55 to
Symbol Parameter V 25_C v 85_C v 125_C Unit
tPLH, Maximum Propagation Delay, 2.0 75 95 110 ns
tPHL A to B, B to A 3.0 55 70 80
(Figures 1 and 3) 4.5 15 19 22
6.0 13 16 19
tPLZ, Maximum Propagation Delay, 2.0 110 140 165 ns
tPHZ Direction or Output Enable to A or B 3.0 90 110 130
(Figures 2 and 4) 4.5 22 28 33
6.0 19 24 28
tPZL, Maximum Propagation Delay, 2.0 110 140 165 ns
tPZH Output Enable to A or B 3.0 90 110 130
(Figures 2 and 4) 4.5 22 28 33
6.0 19 24 28
tTLH, Maximum Output Transition Time, 2.0 60 75 90 ns
tTHL Any Output 3.0 23 27 32
(Figures 1 and 3) 4.5 12 15 18
6.0 10 13 15
Cin Maximum Input Capacitance (Pin 1 or Pin 19) − 10 10 10 pF
Cout Maximum Three−State I/O Capacitance − 15 15 15 pF
(I/O in High−Impedance State)
7. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High−Speed
CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD Power Dissipation Capacitance (Per Transceiver Channel) (Note 8) 40 pF
8. Used to determine the no−load dynamic power consumption: P D = CPD VCC2 f + ICC VCC . For load considerations, see the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).

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 74HC245

VCC
DIRECTION 50%
GND
tr tf
VCC VCC
INPUT 90% OUTPUT 50%
A OR B 50%
10% ENABLE GND
GND
tPZL tPLZ
tPLH tPHL HIGH
OUTPUT 90% IMPEDANCE
50% 50%
B OR A A OR B
10% 10% VOL
tPZH tPHZ
tTLH tTHL 90% VOH
A OR B 50%
HIGH
IMPEDANCE

Figure 3. Switching Waveform Figure 4. Switching Waveform

TEST POINT TEST POINT

CONNECT TO VCC WHEN
OUTPUT OUTPUT 1 kW
TESTING tPLZ AND tPZL.
DEVICE DEVICE CONNECT TO GND WHEN
UNDER UNDER TESTING tPHZ AND tPZH.
TEST CL* TEST CL*

*Includes all probe and jig capacitance *Includes all probe and jig capacitance

Figure 5. Test Circuit Figure 6. Test Circuit

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 74HC245

2
A1
18
B1

3
A2
17
B2

4
A3
16
B3

5
A4
A 15 B
B4
DATA DATA
PORT PORT
6
A5
14
B5

7
A6
13
B6

8
A7
12
B7

9
A8
11
B8

1
DIRECTION

19
OUTPUT ENABLE

Figure 7. Expanded Logic Diagram

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 74HC245

PACKAGE DIMENSIONS

TSSOP−20
CASE 948E−02
ISSUE C

NOTES:
1. DIMENSIONING AND TOLERANCING PER
20X K REF

ÍÍÍÍ
K ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
0.15 (0.006) T U S 0.10 (0.004) M T U S V S K1

ÍÍÍÍ
MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE

ÍÍÍÍ
BURRS. MOLD FLASH OR GATE BURRS
20 11 J J1 SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
2X L/2 4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
B SECTION N−N INTERLEAD FLASH OR PROTRUSION
L SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
PIN 1
−U− 5. DIMENSION K DOES NOT INCLUDE
IDENT DAMBAR PROTRUSION. ALLOWABLE
N 0.25 (0.010) DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
1 10 DIMENSION AT MAXIMUM MATERIAL
CONDITION.
M 6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
0.15 (0.006) T U S 7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
A N MILLIMETERS INCHES
−V− DIM MIN MAX MIN MAX
F A 6.40 6.60 0.252 0.260
B 4.30 4.50 0.169 0.177
DETAIL E C −−− 1.20 −−− 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
−W−
C H 0.27 0.37 0.011 0.015
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
D G K 0.19 0.30 0.007 0.012
H K1 0.19 0.25 0.007 0.010
DETAIL E L 6.40 BSC 0.252 BSC
0.100 (0.004) M 0_ 8_ 0_ 8_
−T− SEATING
PLANE

SOLDERING FOOTPRINT*
7.06

0.65
PITCH

16X 16X
0.36
1.26 DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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 74HC245

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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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