74HC32

Quad 2−Input OR Gate

High−Performance Silicon−Gate CMOS
The 74HC32 is identical in pinout to the LS32. The device inputs are
compatible with Standard CMOS outputs; with pullup resistors, they
are compatible with LSTTL outputs. http://onsemi.com

Features
MARKING
• Output Drive Capability: 10 LSTTL Loads DIAGRAMS
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 2.0 to 6.0 V
14
• Low Input Current: 1.0 mA
SOIC−14 HC32G
• High Noise Immunity Characteristic of CMOS Devices 14 D SUFFIX AWLYWW
• In Compliance With the JEDEC Standard No. 7A Requirements 1 CASE 751A

• ESD Performance: HBM > 2000 V; Machine Model > 200 V 1

• Chip Complexity: 48 FETs or 12 Equivalent Gates

• These are Pb−Free Devices 14
TSSOP−14 HC
14 DT SUFFIX 32
CASE 948G ALYWG
1 G
1

HC32 = Device Code

A = Assembly Location
L, WL = Wafer Lot
Y = Year
W, WW = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)

ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.

© Semiconductor Components Industries, LLC, 2007 1 Publication Order Number:

March, 2007 − Rev. 1 74HC32/D
 74HC32

Pinout: 14−Lead Packages (Top View) LOGIC DIAGRAM

VCC B4 A4 Y4 B3 A3 Y3 1
A1 3
14 13 12 11 10 9 8 2 Y1
B1

4
A2 6
5 Y2
B2
Y = A+B
9
A3 8
1 2 3 4 5 6 7 10 Y3
B3
A1 B1 Y1 A2 B2 Y2 GND
12
A4 11
13 Y4
B4
FUNCTION TABLE
PIN 14 = VCC
Inputs Output PIN 7 = GND

A B Y
L L L
L H H
H L H
H H H

ORDERING INFORMATION
Device Package Shipping †
74HC32DR2G SOIC−14
(Pb−Free) 2500 / Tape & Reel
74HC32DTR2G TSSOP−14*
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.

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 74HC32

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS
Symbol Parameter Value Unit This device contains protection
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must
be taken to avoid applications of any
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
voltage higher than maximum rated
Iin DC Input Current, per Pin ±20 mA voltages to this high−impedance cir-
cuit. For proper operation, Vin and
Iout DC Output Current, per Pin ±25 mA
Vout should be constrained to the
ICC DC Supply Current, VCC and GND Pins ±50 mA range GND v (Vin or Vout) v VCC.
Unused inputs must always be
PD Power Dissipation in Still Air, SOIC Package† 500 mW tied to an appropriate logic voltage
TSSOP Package† 450 level (e.g., either GND or VCC).
Tstg Storage Temperature – 65 to + 150 _C Unused outputs must be left open.

TL Lead Temperature, 1 mm from Case for 10 Seconds _C

SOIC or TSSOP Package 260
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
†Derating — SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V
Vin, Vout DC Input Voltage, Output Voltage (Referenced to 0 VCC V
GND)
TA Operating Temperature, All Package Types – 55 + 125 _C
tr, tf Input Rise and Fall Time VCC = 2.0 V 0 1000 ns
(Figure 1) VCC = 4.5 V 0 500
VCC = 6.0 V 0 400

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 74HC32

DC CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit
VCC
Symbol Parameter Condition (V) −55 to 25°C ≤85°C ≤125°C Unit
VIH Minimum High−Level Input Voltage Vout = 0.1V or VCC −0.1V 2.0 1.50 1.50 1.50 V
|Iout| ≤ 20mA 3.0 2.10 2.10 2.10
4.5 3.15 3.15 3.15
6.0 4.20 4.20 4.20
VIL Maximum Low−Level Input Voltage Vout = 0.1V or VCC − 0.1V 2.0 0.50 0.50 0.50 V
|Iout| ≤ 20mA 3.0 0.90 0.90 0.90
4.5 1.35 1.35 1.35
6.0 1.80 1.80 1.80
VOH Minimum High−Level Output Vin = VIH or VIL 2.0 1.9 1.9 1.9 V
Voltage |Iout| ≤ 20mA 4.5 4.4 4.4 4.4
6.0 5.9 5.9 5.9
Vin =VIH or VIL |Iout| ≤ 2.4mA 3.0 2.48 2.34 2.20
|Iout| ≤ 4.0mA 4.5 3.98 3.84 3.70
|Iout| ≤ 5.2mA 6.0 5.48 5.34 5.20
VOL Maximum Low−Level Output Vin = VIH or VIL 2.0 0.1 0.1 0.1 V
Voltage |Iout| ≤ 20mA 4.5 0.1 0.1 0.1
6.0 0.1 0.1 0.1
Vin = VIH or VIL |Iout| ≤ 2.4mA 3.0 0.26 0.33 0.40
|Iout| ≤ 4.0mA 4.5 0.26 0.33 0.40
|Iout| ≤ 5.2mA 6.0 0.26 0.33 0.40
Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 mA
ICC Maximum Quiescent Supply Vin = VCC or GND 6.0 2.0 20 40 mA
Current (per Package) Iout = 0mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).

AC CHARACTERISTICS (CL = 50pF, Input tr = tf = 6ns)

Guaranteed Limit
VCC
Symbol Parameter (V) −55 to 25°C ≤85°C ≤125°C Unit
tPLH, Maximum Propagation Delay, Input A or B to Output Y 2.0 75 95 110 ns
tPHL (Figures 1 and 2) 3.0 30 40 55
4.5 15 19 22
6.0 13 16 19
tTLH, Maximum Output Transition Time, Any Output 2.0 75 95 110 ns
tTHL (Figures 1 and 2) 3.0 27 32 36
4.5 15 19 22
6.0 13 16 19
Cin Maximum Input Capacitance 10 10 10 pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V, VEE = 0 V

CPD Power Dissipation Capacitance (Per Buffer)* 20 pF

* Used to determine the no−load dynamic power consumption: PD = CPD VCC 2f + I VCC . For load considerations, see Chapter 2 of the
CC
ON Semiconductor High−Speed CMOS Data Book (DL129/D).

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 74HC32

tr tf
VCC
90%
INPUT 50%
A OR B
10% GND

tPLH tPHL

90%
OUTPUT Y 50%
10%

tTLH tTHL

Figure 1. Switching Waveforms

TEST
POINT

OUTPUT
DEVICE
UNDER
TEST C L*

*Includes all probe and jig capacitance

Figure 2. Test Circuit

A
Y
B

Figure 3. Expanded Logic Diagram

(1/4 of the Device)

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 74HC32

PACKAGE DIMENSIONS

SOIC−14
CASE 751A−03
ISSUE H

NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
−A− 2. CONTROLLING DIMENSION: MILLIMETER.
14 8 3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
−B− 5. DIMENSION D DOES NOT INCLUDE
P 7 PL DAMBAR PROTRUSION. ALLOWABLE
0.25 (0.010) M B M DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
1 7 CONDITION.

G MILLIMETERS INCHES
R X 45 _ F DIM MIN MAX MIN MAX
C A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
−T− F 0.40 1.25 0.016 0.049
K M J
SEATING D 14 PL G 1.27 BSC 0.050 BSC
PLANE J 0.19 0.25 0.008 0.009
0.25 (0.010) M T B S A S K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019

SOLDERING FOOTPRINT*
7X
7.04 14X
1.52
1
14X
0.58

1.27
PITCH

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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6
 74HC32

PACKAGE DIMENSIONS

TSSOP−14
CASE 948G−01
ISSUE B

NOTES:
14X K REF 1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
0.10 (0.004) M T U S V S 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
0.15 (0.006) T U S FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
N 4. DIMENSION B DOES NOT INCLUDE
0.25 (0.010)
14 8 INTERLEAD FLASH OR PROTRUSION.
2X L/2 INTERLEAD FLASH OR PROTRUSION SHALL
M NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
L B DAMBAR PROTRUSION. ALLOWABLE
−U− N DAMBAR PROTRUSION SHALL BE 0.08
PIN 1 (0.003) TOTAL IN EXCESS OF THE K
IDENT. F DIMENSION AT MAXIMUM MATERIAL
CONDITION.
1 7 6. TERMINAL NUMBERS ARE SHOWN FOR
DETAIL E REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.

ÇÇÇ
0.15 (0.006) T U S
A K
MILLIMETERS INCHES
−V− K1 DIM MIN MAX MIN MAX

ÉÉÉ
ÇÇÇ
A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177

ÉÉÉ
ÇÇÇ
J J1 C −−− 1.20 −−− 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
SECTION N−N G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
C −W− K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
0.10 (0.004) L 6.40 BSC 0.252 BSC
M 0_ 8_ 0_ 8_
−T− SEATING D G H DETAIL E
PLANE

SOLDERING FOOTPRINT*

7.06

0.65
PITCH

14X 14X
0.36
1.26
DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

http://onsemi.com
7
 74HC32

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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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