TIMERS

Dario Amaya
 TIMERS

T
IRQ IRQ

Adaptado de [2]
 TIMERS

4.294.967296
 TIMERS

𝒇𝒐𝒔𝒄
𝑼𝒑𝒅𝒂𝒕𝒆 𝑬𝒗𝒆𝒏𝒕 𝑯𝒛 =
(𝑻𝑰𝑴 → 𝑷𝑺𝑪 + 𝟏) ∗ (𝑻𝑰𝑴 → 𝑨𝑹𝑹 + 𝟏)

Register
Configuration
T
Clock Interrup Controler
Timer 5 Processor
84 MHZ IRQ IRQ IRQ NVIC

𝑓𝑜𝑠𝑐 =84MHz para el timer 5

TIM->PSC=[0->65535]
TIM->ARR=[0->2^32]
TIMERS
TIMERS
TIMERS
RCC->APB1ENR

RCC->APB2ENR
 TIM1&TIM8 control register 1 (TIMx_CR1)

Bit 0 CEN: Counter enable

0: Counter disabled
1: Counter enabled

TIM1&TIM8 DMA/interrupt enable register

(TIMx_DIER)

Bit 0 UIE: Update interrupt enable

0: Update interrupt disabled
1: Update interrupt enabled
 TIM1&TIM8 status register (TIMx_SR)

Bit 0 UIF: Update interrupt flag

0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
TIMx auto-reload register (TIMx_ARR)

TIMx prescaler (TIMx_PSC)

83999

TIM5_ver tabla

84000000
𝑼𝒑𝒅𝒂𝒕𝒆 𝑬𝒗𝒆𝒏𝒕 𝑯𝒛 = =1000Hz
(0+𝟏)∗(83999+𝟏)
𝟏
𝑻 𝒔𝒆𝒈 = 𝟏𝟎𝟎𝟎 = 𝟎. 𝟎𝟎𝟏 seg
 References
• [1] http://electronics.stackexchange.com/questions/195640/stm32f4-
tim2-timer-getting-to-1-second.
• [2] STMicroelectronics: “RM0090 Reference manual. STM32F40xxx,
STM32F41xxx, STM32F42xxx, STM32F43xxx advanced ARM-based 32-
bit MCUs”, Doc ID 018909 Rev 4. 2013. URL: http://www/st.com
TIMERS

Tomado de [2]
Tomado de [2]
[1] STMicroelectronics: “RM0090 Reference manual.
STM32F40xxx, STM32F41xxx, STM32F42xxx, STM32F43xxx
advanced ARM-based 32-bit MCUs”, Doc ID 018909 Rev 4.
2013. URL: http://www/st.com