Different library views lef & ?

Assignment 4: 300/pitch of M4 300/0.304

metal, wire & track rails diff

FLOORPLAN

1. size shape

2. IO area creation, IO pin placement

3.IP macro placement

4. Placement blockages,keepout

Die size:Macro area+std cell+blockage+io area

Chip/Die utilization:std cell+macro+IP+IO area % Die area

Std cell utilization: std cell area % (Die area -[IO+Macro+IP area])

Core area = Die area – IO area

IO port placement:

IO ports: power, gnd, signal io, clock, reset,feed through

System synchronous IF, source synchronous IF(DDR), self synchronous

Iinterface(serdes)

Feed throughs are defined for roting feasibility. PLL has ref clock input &
generates clocks outputs in phase with ref clock. Place PLL near to refclk
port. Few control inputs to the PLL. Place clock port in the center of the die

IP/MACRO placement:IO2Macro connection,Macro2Macro,Macro2Stdcell preference

order)

memories contain IO ports one side, vdd vss on other side. Memory power
connection M4 Macros don’t sit on the rows (i.e not multiple of std cell
size). Orientation of memory is very critical. Unidirectional poly (gate layer
should be horizantal or vertical all over the design). Std cells have vertical
poly.(vendor document) macros should be oiented to have vertical poly.

Apply keepout/halo around macros & Ips. Is placement blockage(1u) around

macros for routability
Ram stacking:Keep some stack(group) gap between macros based on the length.
Stack space allows area for inserting buffers (optimization) on the wires
routing in the memories. Soft placement blockage. Memories block few routing
layers. Base layers are present in the memory

Blockage: 1. Placement(keepout/halo) 2. routing blockage(hard/soft/partial %)

Channel width: Number of pins X metal pitch % (No of effective roting layer)

effective roting layer = layers/2

Power Stripe in channel: atleast pair of vdd & vss shoud be connected to
channel (area between memories). Channel width should support enough spacing
power stripe.

Avoid criss cross routes & orient memories for shortest route $ better
routability

Avoid notches & create continues core area for std cells.

Memories placed towards boundary, not in the center to create continues area
for std cells

Make sure macros don’t block IO port routing

Fix(attribute) memory placement

Checklist after Flooor plan:

1. memory overlaps 2 b avoided

2. IO ports should not be blocked

3. Ram channels should accommodate at least pair of power/gnd stripe

4. All ports/memories/Ips should be placed have fixed attribute

5. All memoriy channel have soft blockage

6. All ports & components are on grid(manufacturing,track) Port should be

placed on track

commands for checking placement violations

check_leagality check_fp_pin_assignment

Macros should be distributed evenly to avoid notches which cause routing

congestion

Power ring is to be placed before placing standard cells

POWER PLAN

1. Power consumption:Ps+Pd(Pint+psw)

2. power delivery (power mesh)

PPA: High Power requires heat sink(cost), battery limitation,

Electro migrarion: When current flows through the wire result in displacement
of the atoms of the wire from one part to other part of wire cause
thinning/thicker wire. (5/7/11 years foundry give data) resistance varies .
Current limit should not exceed some to maintin resistance changes less tha
10%) M1 W1 idc limit1 M2W2 idc limit2 Linear expansion affect width

Copper has better electromigartion effect than alluminium

IR drop & ground bounce:

Normally the highest metal layers are used for the power routing bcoz the
resistance associated will be less for the top layers

Metal layers

http://www.cs.bilkent.edu.tr/~mustafa.ozdal/cs612/slides/lecture2.pdf Good

http://www.vlsi-expert.com/2017/10/metal-layer-stack-metallization-
option1.html

http://web.engr.uky.edu/~elias/lectures/03_The_Metal_Layers.pdf G

https://www.edaboard.com/showthread.php?65382-Metal-layers-used-for-power-
routing G

http://www.vlsi-expert.com/2017/10/metal-layer-stack-metallization-
option1.html Good

https://www.utdallas.edu/~zhoud/EE6306/lecture%20slides/ASIC%202011%20Chapter
%206%20%20Physical%20Design.pdf

http://asic-soc.blogspot.com/2008/02/physical-design-questions-and-
answers.html

http://eia.udg.es/~forest/VLSI/lect.02.pdf

https://www.utdallas.edu/~zhoud/EE6306/lecture%20slides/ASIC%202011%20Chapter
%206%20%20Physical%20Design.pdf
http://www.ee.ncu.edu.tw/~jfli/VLSI/lecture/ch03.pdf

Power mesh is created so that no short between pwr & gnd take place after
placement of std cells

set_keepout_margin -type hard -all_macros _outer {2 2 2 2}

cut_rows near macros which removes site rows on the macros so that standard
cells can’t be placed

floating shapes error is reported if there is no via available to connect to

power strip. These will go after adding filler cells