Name: AYMAN ALQURASHI

Matric ID: 141912750

TITLE: Seven-segment.

LAB NO: 2

OBJECTIVE:

-Implement seven segments by using Quartus II software.

-Studying the performance of seg7 and checking the functional and timing result

VHDL code:
Pin Assignment:

Simulation Result of 7-Segment module:

Functional Simulation

When all input are zero. When bcd = 0111, there

will be four led on
There will be one led on.

Timing Simulation

Here it is same as the

functional simulation

CONCLUSION:

At the end of this expermint 7-segemnt has been sucessfuly implemented using the software and
there were no errors found.The functional result is the almost accurate one comparing to the
Timing result.
Name: AYMAN ALQURASHI

Matric ID: 141912750

TITLE: ALU

LAB NO: 2

OBJECTIVE:

-Implement seven segments by using Quartus II software.

-Studying the performance of ALU and checking the functional and timing result

VHDL code:

Pin Assignment:
Simulation Result of ALU module:

Functional Simulation

When ALU op = 001, ALU out = ain or bin

When ALU op = 001, ALU out = ain or bin
0001+0010=0011

Timing Simulation

When ALU op = 000,

ALU out = ain or bin

CONCLUSION:

At the end of this expermint ALU has been sucessfuly implemented using the software and
there were no errors found.The functional result is the almost accurate one comparing to the
Timing result.
Name: AYMAN ALQURASHI

Matric ID: 141912750

TITLE: DEBUG

LAB NO: 2

OBJECTIVE:

-Implement seven segments by using Quartus II software.

-Studying the performance of DEBUG and checking the functional and timing result

VHDL code:
Pin Assignment:

Simulation Result DEBUG_INTERFACE module:

Functional Simulation

Timing Simulation When dsel = 00,The dout = 0000&ain = 00000000

Same as functional
result
CONCLUSION:

At the end of this expermint DEBUG has been sucessfuly implemented using the software
and there were no errors found .The functional result is the almost accurate one comparing to
the Timing result.
Name: AYMAN ALQURASHI

Matric ID: 141912750

TITLE: DPU

LAB NO: 2

OBJECTIVE:

-Implement seven segments by using Quartus II software.

-Studying the performance of DPU and checking the functional and timing result

VHDL code:
Pin Assignment:

Simulation Result of DPU module:

Functional Simulation

ALUop = 010, from the code of the ALU , when ALU

=010. The output is ALUout <= Ain xor Bin

0001 xor 1001= 1001,dsel = 10,dout <= 00001001

Seg <= 0001111

Timing Simulation

Same as functional
result

Conclusion:

At the end of this expermint 7-segemnt has been sucessfuly implemented using the software
and there were no errors found.The functional result is the almost accurate one comparing to
the Timing result.