Shashwat Patel

EGCP 446

Lab 4

ASM

March 18, 2021

 Introduction

In this lab we will be creating an ASM using Vivado. Here, we will be using our previous

designs of Moore and Mealy Finite State Machines and Implementing them on FPGA boards. To

implement the Moore machine we will be creating a clock divider which will slow down our

circuit clock from 100 MHz to 1 Mhz. To implement the Mealy machine we will be creating a

clock debouncer which will produce 10ms ticks.

 Procedure/Discussion

To start this lab I first imported my design of Moore machine into vivado and then started

creating the clock divider circuit. To design the clock divider I initialised the constant value

which will slow down the clock to 1 MHz. The next step is to create a design where I add the

Moore machine and Clock divider as components then program the FPGA board with the pins

specified.

For part B, I used the same process in creating the design. I first imported my Mealy

design into vivado then started working on my debouncer code. The goal of the clock debouncer

is to produce 10ms ticks. To do so I assumed the internal clock to be 50 MHz and based on that I

did my calculations to produce 10ms ticks,

1
50 𝑀𝐻𝑧
= 0. 02 ⇒

19
(2 + 1) = 524289 ⇒ (524289 * 0. 02) ≃ 10. 485 𝑜𝑟 10. 5𝑚𝑠

Based on the calculation I decided to choose my integer value to be 19. The next step was to

create a new design where I added my debouncer and Mealy machine code as components and

programmed the FPGA board.

As a result of both Parts A and B my code worked as expected because I was successfully

able to see the behavior of both my Moore and Mealy machine on the FPGA board. There were

rarely any issues I ran into while doing this lab, one of them was converting the debouncer

VHDL code into Verilog but after a couple of tries I was able to figure that out.
 Screenshots/Simulation

Part 1 Design:

Part 1 Simulation:

For part A i took two pictures showcasing the Moore machine at its initial state and the max

value it counts up to. The LED will be showcasing the value changing during the FSM cycle.
Part 2 Design:
Part 2 Simulation:

In this part I took 4 pictures, two of them representing the function of Mealy machine by using

“UP” and button and the other two images will show the behavior of the same circuit using

“~UP”. The LED’s will showcase the values changing during the FSM cycle.
 Conclusion

In conclusion, this lab was fairly easy and the directions were pretty straightforward to

follow. From this lab I learned how to design a clock divider and a clock debouncer using

Verilog. I also learned how to program any Verilog design onto an FPGA board by generating

bitstream and programming pins. Overall the lab was easy and I got the desired results.
 References

● Lecture Slides, Video

● VHDL code for Debouncer provided in the lecture

 Appendix

Clock Divider:

`timescale 1ns / 1ps

module clkdiv(
input Clk,
input Reset,
output reg Slow_clk
);
//Assuming system clock is 1MHz
//Constant for getting signal 1 MHz
localparam constNum = 50000000;
reg [31:0] count;
always@ (posedge Clk, posedge Reset)
begin
if(Reset)
count <= 32'b0;
else if (count == constNum - 1)
count <= 32'b0;
else
count <= count + 1;
end
always@ (posedge Clk, posedge Reset)
begin
if (Reset)
Slow_clk <= 1'b0;
else if ( count == constNum - 1)
Slow_clk <= ~Slow_clk;
else
Slow_clk <= Slow_clk;
end
endmodule

Part A Design:
`timescale 1ns / 1ps

module partA(
input Clk,
input Reset,
output [3:0] Q
);
wire clock;
clkdiv div1(Clk, Reset, clock);
Moore Mo(clock, Reset, Q);
endmodule

Clock Debouncer:

`timescale 1ns / 1ps

module debounce(
input clk,
input btn,
output reg btn_clr
);
localparam N = 5000000;
reg [31:0] counter_out = 0;

always@ (posedge clk)

begin
if(counter_out == N-1)
begin
counter_out <= 0;
btn_clr <= btn;
end
else
begin
counter_out <= counter_out + 1;
btn_clr <= btn_clr;
end
end
endmodule
Part B Design:

`timescale 1ns / 1ps

module partB(
input Clk,
input Btn,
input Reset,
input up,
output [1:0] Q
);
wire clock;
debounce db(Clk, Btn, clock);
Mealy me(clock, Reset, up, Q);
endmodule

Constraints File (XDC):

set_property IOSTANDARD LVCMOS18 [get_ports Clk]

set_property IOSTANDARD LVCMOS18 [get_ports Reset]
set_property IOSTANDARD LVCMOS18 [get_ports {Q[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {Q[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {Q[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {Q[0]}]
set_property PACKAGE_PIN E3 [get_ports Clk]
set_property PACKAGE_PIN J15 [get_ports Reset]
set_property PACKAGE_PIN J13 [get_ports {Q[2]}]
set_property PACKAGE_PIN N14 [get_ports {Q[3]}]

set_property PACKAGE_PIN K15 [get_ports {Q[1]}]

set_property PACKAGE_PIN H17 [get_ports {Q[0]}]

set_property IOSTANDARD LVCMOS18 [get_ports Btn]

set_property IOSTANDARD LVCMOS18 [get_ports up]
set_property PACKAGE_PIN P18 [get_ports Btn]
set_property PACKAGE_PIN L16 [get_ports up]