5 Z80 Interrupts

S.1 Introduction

The interrupt facilities of the Z80 are, for an eight-bit device, quite complex. This
serves to enhance the versatility of the chip and provides a very good example for
study. A complete understanding of the Z80 capabilities is a useful prerequisite for
the study of any device, since the facilities of another microprocessor are quite
likely to be a subset of the Z80 facilities.
As with any processor, it is important to appreciate the response cycle of the
Z80 to an interrupt in order to predict performance. As is usually the case with
most microprocessors, the Z80 actually responds to the interrupt signal at the end
of an instruction cycle. Since the longest instruction requires 23 T states (that is,
about 9 microseconds with a 2.5 MHz clock), this represents the worst-case
interrupt response time.
A particular group of Z80 instructions, the block transfer and search group
(specifically the repeating instructions: LDIR, LDDR, CPIR and CPDR), is rather
unusual in that it may consume many thousands ofT states. This would introduce
very unacceptable interrupt response delays were it not for the manner in which
these instructions are implemented. Each instruction is fetched repeatedly, once for
each transfer7search, the registers holding the status ready for the next. This results
in the execution of each instruction being divided into many instruction cycles,
which permits interrupts to be serviced in a reasonable time.
The HALT instruction is also interesting. With some computers a HALT results
in all processor activity ceasing and a reset being required to restart. With the Z80,
in common with many other microprocessors, intenupts are still serviced when the
processor is halted. As with the block transfer and search instructions, the HALT
instruction is continually re-fetched, enabling interrupt servicing to be performed
normally. There is, however, a rather unusual feature associated with the interrup-
tion of HALT instructions. On returning from the interrupt service routine the PC
is advanced by one, which results in the program proceeding from the instruction
following the HALT. This provides a very simple mechanism for awaiting a clock
interrupt, for example.

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C. Walls, Programming Dedicated Microprocessors
© Colin Walls 1986
40 PROGRAMMING DEDICATED MICROPROCESSORS

5.2 Maskable Interrupts

The Z80 has both maskable and non-maskable interrupts (non-maskable interrupts
are covered in the next section), which are activated by two separate pins on the
chip (INT and NMI respectively).
The response to a signal on the INT pin is dependent upon whether interrupts
are enabled or disabled. If interrupts are disabled, as is the default state on reset,
there is no response at all. Interrupts may be enabled using the EI ('Enable
Interrupts') instruction. This instruction has the unusual property that it does not
take effect until after the next instruction has been completed. This is intended to
avoid unplanned nesting of interrupts by allowing the return from an interrupt
service routine to be executed with interrupts disabled. Interrupts are disabled
automatically on entry to an interrupt service routine and should normally be
re-enabled on exit. If nesting of interrupts is required then an EI may be executed,
after the context has been saved, at the beginning of the interrupt service routine.
Additionally, interrupts may be disabled using the DI ('Disable Interrupts')
instruction, at any time. This instruction takes effect immediately.
Assuming interrupts are enabled, the response from the Z80 when a signal is
asserted on the INT pin depends upon the 'interrupt mode'. This mode may be
selected using the 1M instruction. Three modes are available: mode 0 (default, 8080
series compatible, directly vectored), mode 1 (simple, directly vectored) and mode
2 (Z80 specific, indirectly vectored). The mode which is appropriate for a particular
application is primarily dependent upon the hardware configuration and is, hence,
in the hands of the hardware designer. The firmware engineer should, however, be
aware of all the possibilities, as his advice may well be sought on such matters
(Barden, 1978; Zaks, 1980; Berk, 1984).

5.2.1 Simple (Mode 1)

In this mode, after stacking the current PC, control is transferred directly to address
$38. Note that this is also the address selected by an RST 38 instruction (or mode 0
interrupt, see below). This interrupt mode is handled in a very similar manner to
NMis (see 5.3 below). The interrupt service routine should normally be terminated
by the RET instruction.

5.2.2 Direct Vectored (Mode 0)

This mode, which is the default, is included to maintain the compatibility of the
Z80 with the 8080 series of microprocessors. When an interrupt signal is received
and acknowledged by the Z80, it expects the interrupting device to 'jam' an
instruction onto the data bus in the next instruction cycle. This instruction is then
executed as if it had been read from memory. It was intended that this instruction
would be one of the RSTs, which are single bytes causing direct transfer to specific
addresses ($00, $08,$10,$18,$28,$30 and $38). These instructions are also