Digital Circuits Demultiplexer Questions

Digital Circuits Questions and Answers –
Demultiplexers (Data Distributors) – 2

This set of Digital Electronic/Circuits Multiple Choice Questions & Answers focuses on
“Demultiplexers(Data Distributors) – 2”.
1. Why is a demultiplexer called a data distributor?

a) The input will be distributed to one of the outputs
b) One of the inputs will be selected for the output
c) The output will be distributed to one of the inputs
d) None of the Mentioned
View Answer
Answer: a
Explanation: For one input, the demultiplexer gives several outputs. That is why, it is called a
data distributor.
2. Most demultiplexers facilitate which type of conversion?

a) Decimal-to-hexadecimal
b) Single input, multiple outputs
c) AC to DC
d) Odd parity to even parity
View Answer
Answer: b
Explanation: Demultiplexer converts single input into multiple outputs.
3. In 1-to-4 demultiplexer, how many select lines are required?

a) 2
b) 3
c) 4
d) 5
View Answer
Answer: a
Explanation: The formula for total no. of outputs is given by: 2^n, where n is the no. of select
lines.
4. In a multiplexer the output depends on its

a) Data inputs
b) Select inputs
c) Select outputs
View Answer
Answer: b
Explanation: As the select input changes, the output of the multiplexer varies according to that
input.
5. In 1-to-4 multiplexer, if C1 = 1 & C2 = 1, then the output will be

a) Y0
b) Y1
c) Y2
d) Y3
View Answer
Answer: d
Explanation: The output y3 = C1.C0.X.
6. How many select lines are required for a 1-to-8 demultiplexer?

a) 2
b) 3
c) 4
d) 5
View Answer
Answer: b
Explanation: The formula for total no. of outputs is given by: 2^n, where n is the no. of select
lines. In this case n = 3.
7. How many AND gates are required for a 1-to-8 multiplexer?

a) 2
b) 6
c) 4
d) 5
View Answer
Answer: c
Explanation: The number of AND gates required will be equal to the number of outputs in a
demultiplexer.
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8. Which IC is used for the implementation of 1-to-16 DEMUX?

a) IC 74154
b) IC 74155
c) IC 74139
d) IC 74138
View Answer
Answer: a
Explanation: IC 74154 is used for the implementation of 1-to-16 DEMUX, whose output is
inverted input.
MCQs on Digital Electronics
Page 1 of 35. Go to page
01․ Which of the following memories uses one transistor and one capacitor as basic memory unit
SRAM
DRAM
Both SRAM and DRAM
None
Static RAM ( Random Access Memory ) is constructed by using two or more BJT or MOSFET, one for each
stored bit. But in DRAM ( Dynamic Random Access Memory ) uses one MOSFET and one capacitor for
storing one bit. Here transistor works as a switch and the capacitor stored binary information as electric
charges.
02․ Which number system has a base of 16
Decimal
Octal
Hexadecimal
None
Decimal base = 10, Octal base = 8. Hexadecimal base = 16 ( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F ).

Where A = 10, B = 11, C = 12, D = 13, E = 14, F = 15. It is always represented by 4 bits in binary number
system by 8421 code.
03․ A latch is ________ sensitive
both level and edge
edge
level
None
A latch works on level of a clock, means when the clock is high, all the effects of input will appear on
output otherwise not. A flip-flop works on a clock edge either positive or negative, means when the
clock edge come, the effect of inputs will appear on output otherwise not.
04․ How many entries will be in the truth table of a 3 input NAND gate ?
3
6
8
9
Y = 2n Y is number of Entries in the truth table, while n is the number of inputs.
05․ How many bits are required to store one BCD digit ?
1
2
3
4
BCD (Binary coded Decimal) Number is from 0 to 9, which requires four bits to store. As the maximum
number of the system (15) can best represented by 4 bits. It is also called as 8421 code to represent
maximum number 15.
06․ In binary number system the first digit (bit) from right to left is called as
LSB, Least Significant Bit

MSB, Most Significant Bit
First Bit
Last Bit
Starting from Left to Right, the first bit is called as MSB (Most Significant Bit). It also represents the
signed or unsigned bit.
07․ In an SR latch built from NOR gates, which condition is not allowed
S=0, R=0
S=0, R=1
S=1, R=0
S=1, R=1
At S=0, R=0, Output of the latch becomes Q=0, B_bar=0, which is an unwanted state. also known as
indeterminate state.
08․ A D-flip-flop is said to be transparent when
the output is LOW
the output is HIGH
the output follows clock
the output follow input
When the clock is enabled (en=1) for a D-flip-flop, the input is appeared at the output. So the flip-flop is
said to be transparent.
09․ Which of these sets of logic gates are designated as universal gates?
NOR, NAND.
XOR, NOR, NAND.
OR, NOT, AND.
NOR, NAND, XNOR.
NAND or NOR gate can design all other logic gates. So, they are designated as universal gates.
10․ Which one of the following is not a vectored interrupt?
TRAP.
RST 7.5.
RST 6.5.
INTR.
In 8085 microprocessor TRAP, RST 7.5, RST 6.5, RST 5.5 are vectored interrupt. But RST 3 and INTR is a
non vectored interrupt.
01․ In the toggle mode a JK flip-flop has

J = 0, K = 0.
J = 1, K = 1.
J = 0, K = 1.
J = 1, K = 0.
J = 0, K = 0; no change condition between pre-state and next state. J = 0, K = 1; it is always reset

condition means next state is always 0. J = 1, K = 0; it is always set condition means next state is
always 1. J = 1, K = 1; it is toggle condition means when pre-state is 1 then next state is 0 or
when pre-state is 0 then next state is 1.
02․ A three-state buffer has the following output states
1, 0, float
High, Low, Float
Both A and B
Set, Reset, Halt
A three-state buffer when enabled output is HIGH and is LOW when disabled. And neither of
these condition, then it will be in FLOAT state.
03․ Which of the following is a digital device
Regulator of a fan
Microphone
Resistance of a material
Light switch
A light switch has two condition. ON and OFF, which is similar to that of digital conditions 1
and 0 which is the basic of Boolean algebra. Rest have Fuzzy logic.
04․ A Binary number system has how many digits.
0
1
2
10
A binary number system consists of only ONE and ZERO or can be stated as High and Low
means it has only two digits.
05․ If a Hexadecimal number needs to convert to binary. For each hexadecimal digit, there will
be how many bits
1
2
4
8
Hexadecimal number system is a base-16 number system ( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D,

E, F ). As F can be represented using 4 bits (1 1 1 1), So for each hexadecimal digit one need 4
bits.
06․ Temperature variation is a/an
Digital quantity
Analog quantity
Either Digital or Analog quantity
None
Temperature variation is not a discrete quantity respect to time. It is continuous w.r.t time. So its
an analog quantity.
07․ In Digital Logic Designs, GAL is abbreviated as
General Advance Logic
General Array Logic
Generic Advance Logic
Generic Array Logic
GAL is Generic Array Logic. It is a re programmable device used in Digital Systems.

08․ In decimal number system what is MSD
First digit from left to right
First digit from right to left
Middle digit
Mean of all digits
MSD means Most Significant Digit. It is represented by the first digit from left to right, it has the
highest weight-age out of all. It can also represent the signed or unsigned number.
09․ A digital circuit that can store on bit is a
XOR gate
flip-flop
gate
registor
A flip-flip is the basic unit for storing digital data and it can store only one bit.
10․ Stack is also known as
FIFO memory
Flash memory
LIFO memory
LILO memory
Stack is a type of memory based on Last In First Out. A data stored last will be read first.
01․ Queue is also known as
FIFO memory
LIFO memory
Flash memory
LILO memory
Queue is a type of memory based on First In First Out. A data entered first will be read first. i.e
The crowd line in front of a bank. The person came first will be served first.
02․ 1 Kilo bits are equal to
1000 bits
1024 bits
1012 bits
1008 bits
In binary, 1 kilo means 210, which is equal to 1024.

03․ A Nibble is equal to ________ bit(s)
1
2
4
8
In digital systems, bit is the smallest unit of storage consisting of either 0 or 1. Grouping of such
4 bits are called nibble and grouping of such 8 bits are called byte.
04․ If J = K (J and K are shorted) in a JK flip-flop, what circuit is made
SR flip-flop
Shorted JK flip-flop
T flip-flop
K flip-flop
A T flip-flop toggles its output when a 1 is provided at input, otherwise output does not change.
It is actually a JK flip-flop with the J and K inputs shorted.
05․ In digital systems, 1 byte is equal to ________ bit(s).
1
2
4
8
In digital systems, bit is the smallest unit of storage consisting of either 0 or 1. Grouping of such
4 bits are called nibble and grouping of such 8 bits are called byte.
06․ Which logic family provide minimum power dissipation
TTL
CMOS
ECL
JFET
Complementary Metal Oxide Semiconductor or CMOS technology provides less density as well
as less power consumption, because it does not consume any power in the OFF state which is
exception from other Transistor devices.
07․ Boolean algebra is also known as
Gate algebra
Transistor algebra
Switching algebra
Counting algebra
Switching algebra is the other name of Boolean Algebra, as it also have only two states either
ON or OFF state i.e. 1 or 0.
08․ In a T flip-flop no of input circuit is
1
2
3
4
T flip flop is made from a JK flip-flop by shorting J and K, it accepts only one input either 1 or 0.
When T = 0 Output remains the same T = 1, output toggles.
09․ A boolean function can be transformed into logical ________.
graph
map
diagram
matrix
A logical diagram can be constructed from a Boolean function representing input/output by

variables. Logical diagram is constructed by logical gates.
10․ The boolean algebra is mostly based on
Boolean theorem
De Morgans theorem
De Morpans theorem
Standard theorem
De Morgans Law or De Morgans Theorem is the basics of the Boolean Algebra.
Q1. The binary number 10101 is equivalent to decimal number …………..

1. 19
2. 12
3. 27
4. 21
Answer : 4
Q2. The universal gate is ………………
1. NAND gate
2. OR gate
3. AND gate
4. None of the above
Answer : 1
Q3. The inverter is ……………
1. NOT gate
2. OR gate
3. AND gate
Answer : 1
Q4. The inputs of a NAND gate are connected together. The resulting circuit is ………….
1. OR gate
2. AND gate
3. NOT gate
Answer : 3
Q5. The NOR gate is OR gate followed by ………………
1. AND gate
2. NAND gate
3. NOT gate
Answer : 3
Q6. The NAND gate is AND gate followed by …………………
1. NOT gate
2. OR gate
3. AND gate
Answer : 1
Q7. Digital circuit can be made by the repeated use of ………………
1. OR gates
2. NOT gates
3. NAND gates
Answer : 3
Q8. The only function of NOT gate is to ……………..
1. Stop signal
2. Invert input signal
3. Act as a universal gate
Answer : 2
Q9. When an input signal 1 is applied to a NOT gate, the output is ………………
1. 0
2. 1
3. Either 0 & 1
Answer : 1
Q10. In Boolean algebra, the bar sign (-) indicates ………………..
1. OR operation
2. AND operation
3. NOT operation
Answer : 3
Q11. The resolution of an n bit DAC with a maximum input of 5 V is 5 mV. The value
of n is …….
1. 8
2. 9
3. 10
4. 11
Answer : 3
Explanation:
(5/2N-1)1000 = 5 or N = 10
Q12. 2’s complement of binary number 0101 is ………..
1. 1011
2. 1111
3. 1101
4. 1110
Answer : 1
Explanation: 1’s complement of 0101 is 1010 and 2’s complement is 1010+1 = 1011.
Q13. An OR gate has 4 inputs. One input is high and the other three are low. The output
is …….
1. Low
2. High
3. alternately high and low
4. may be high or low depending on relative magnitude of inputs
Answer : 2
Explanation: In OR any input high means high output.
Q14. Decimal number 10 is equal to binary number ……………
1. 1110
2. 1010
3. 1001
4. 1000
Answer : 2
Explanation: 1010 = 8 + 2 = 10 in decimal.
Q15. Both OR and AND gates can have only two inputs.

1. True
2. False
Answer : 2
Explanation: Any number of inputs are possible.
Q16. A device which converts BCD to seven segments is called ……..
1. Encoder
2. Decoder
3. Multiplexer
4. None of these
Answer : 2
Explanation: Decoder converts binary/BCD to alphanumeric.
Q17. In 2’s complement representation the number 11100101 represents the decimal
number ……………
1. +37
2. -31
3. +27
4. -27
Answer : 4
Explanation:
A = 11100101. Therefore Ā = 00011010 and A’ = Ā + 1 = 00011011 = 16 + 8 + 2 + 1 = 27.

Therefore A = -27.
Q18. A decade counter skips ………..
1. binary states 1000 to 1111

4. binary states 1111 to higher
Answer : 3
Explanation: A decade counter counts from 0 to 9. It has 4 flip-flops. The states skipped are 10
to 15 or 1010 to 1111.
Q19. BCD input 1000 is fed to a 7 segment display through a BCD to 7 segment
decoder/driver. The segments which will lit up are ………….
1. a, b, d
2. a, b, c
3. all
4. a, b, g, c, d
Answer : 3
Explanation: 1000 equals decimal 8 Therefore all segments will lit up.
Q20. A ring counter with 5 flip flops will have ………. states.
1. 5
2. 10
3. 32
4. Infinite
Answer : 1
Q21. For the gate in the given figure the output will be ………..
1. 0
2. 1
3. A
4. Ā
Answer : 4
Explanation: If A = 0, Y = 1 and A = 1, Y = 0 Therefore Y = Ā.
Q22. In the expression A + BC, the total number of minterms will be ………
1. 2
2. 3
3. 4
4. 5
Answer : 4
Q23. The circuit in the given figure is a ………… gate.
1. positive logic OR gate

2. negative logic OR gate
3. negative logic AND gate
4. positive logic AND gate
Answer : 2
Explanation: Since V(1) is lower state than V(0) it is a negative logic circuit. Since diodes are
in parallel, it is an OR gate.
Q24. Which of the following is non-saturating?
1. TTL
2. CMOS
3. ECL
4. Both 1 and 2

Answer : 3
Q25. The number of digits in octal system is ………
1. 8
2. 7
3. 9
4. 10
Answer : 1
Explanation: The octal system has 8 digits 0 to 7.
Q16.
Answer : 2
Explanation:
Q26. The access time of a word in 4 MB main memory is 100 ms. The access time of a word
in a 32 kb data cache memory is 10 ns. The average data cache bit ratio is 0.95. The
efficiency of memory access time is ………
1. 9.5 ns
2. 14.5 ns
3. 20 ns
4. 95 ns
Answer : 2
Explanation: Access time = 0.95 x 10 + 0.05 x 100.
Q27. The expression Y = pM (0, 1, 3, 4) is …………..
1. POS
2. SOP
3. Hybrid
4. none of these
Answer : 1
Explanation: This is a product of sums expression.

Q28. An 8 bit DAC has a full scale output of 2 mA and full scale error of ± 0.5%. If input is
10000000 the range of outputs is ………….
1. 994 to 1014 μA
2. 990 to 1020 μA
3. 800 to 1200 μA
4. none of the above
Answer : 1
Explanation:
Q29. Decimal 43 in hexadecimal and BCD number system is respectively……. and ……..
1. B2 and 01000011
2. 2B and 01000011
3. 2B and 00110100
4. B2 and 01000100
Answer : 2
Explanation:

Q30. The circuit of the given figure realizes the function …………
Answer : 1
Explanation:

Q31. An AND gate has two inputs A and B and one inhibit input 3, Output is 1 if
1. A = 1, B = 1, S = 1
2. A = 1, B = 1, S = 0
3. A = 1, B = 0, S = 1
4. A = 1, B = 0, S = 0
Answer: 2
Explanation: All AND inputs must be 1 and inhibit 0 for output to be 1.
Q32. The greatest negative number which can be stored is 8 bit computer using 2’s
complement arithmetic is ……..
1. -256
2. -128
3. -255
4. -127
Answer: 2
Explanation: The largest negative number is 1000 0000 = -128.
Q33. A JK flip flop has tpd= 12 ns. The largest modulus of a ripple counter using these flip
flops and operating at 10 MHz is ……..
1. 16
2. 64
3. 128
4. 256
Answer: 4
Explanation:

Q34. The basic storage element in a digital system is ………….
1. flipflop
2. counter
3. multiplexer
4. encoder
Answer : 1
Explanation: Storing can be done only in memory and flip-flop is a memory element.
Q35. In a ripple counter,
1. whenever a flipflop sets to 1, the next higher FF toggles

2. whenever a flipflop sets to 0, the next higher FF remains unchanged
3. whenever a flipflop sets to 1, the next higher FF faces race condition
4. whenever a flipflop sets to 0, the next higher FF faces race condition
Answer : 1
Explanation: In a ripple counter the effect ripples through the counter.
Q36. A 12 bit ADC is used to convert analog voltage of 0 to 10 V into digital. The resolution
is ……….
1. 2.44 mV
2. 24.4 mV
3. 1.2 V
4. none of these
Answer : 1
Explanation:

Q37. For the truth table of the given figure Y = ………….
1. A+B+C
2. Ā +BC
3. Ā
4. B¯
Answer : 4
Explanation:
Q38. A full adder can be made out of …………
1. two half adders

2. two half adders and a OR gate
3. two half adders and a NOT gate
4. three half adders
Answer : 2
Q39. If the functions w, x, y, z are as follows
1. w=zx=z
2. w = z, x = y
3. w=y
4. w=y=z
Answer : 1
Q40. The output of a half adder is ……….
1. Sum
2. Sum and Carry
3. Carry
4. none of these
Answer: 2
Q41. Minimum number of 2-input NAND gates required to implement the function F =

(x + y) (Z + W) is ………..
1. 3
2. 4
3. 5
4. 6
Answer : 2
Explanation:
Q42. Which device has one input and many outputs?
1. Multiplexer
2. Demultiplexer
3. Counter
4. Flip flop
Answer: 2
Explanation: Demultiplexer takes data from one line and directs it to any of its N output
depending on the status of its select lines.
Q43. A carry look ahead adder is frequently used for addition because
1. it costs less
2. it is faster
3. it is more accurate
4. uses fewer gates
Answer: 2
Explanation:
Q27.
Answer : 1
Explanation: In look ahead carry adder the carry is directly derived from the gates when
original inputs are being added. Hence the addition is fast. This process requires more gates and
is costly.
Q44. The counter in the given figure is ………….
1. Mod 3
2. Mod 6
3. Mod 8
4. Mod 7
Answer : 2
Explanation: When counter is 110 the counter resets. Hence mod 6.
Q45. In register index addressing mode the effective address is given by ……..
1. index register value

2. sum of the index register value and the operand
3. operand
4. difference of the index register value and the operand
Answer : 2
Explanation:
4 = 22, in up scaling digit will be shifted by two bit in right direction.
Q46. 7BF16 = __________ 2
1. 0111 1011 1110
2. 0111 1011 1111
3. 0111 1011 0111
4. 0111 1011 0011
Answer : 2
Explanation:
7BF16 = 7 x 162 + 11 x 161 + 15 x 160 = 1983 in decimal = 0111 1011 1111 in binary.
Q47. For the minterm designation Y = ∑ m (1, 3, 5, 7) the complete expression is …………..
Answer : 2
Explanation:

Q48. Zero suppression is not used in actual practice.
1. True
2. False
Answer: 2
Explanation: Zero suppression is commonly used.
Q49. A counter type A/D converter contains a 4 bit binary ladder and a counter driven by
a 2 MHz clock. Then conversion time is ………..
1. 8 μ sec
2. 10 μ sec
3. 2 μ sec
4. 5 μ sec
Answer : 1
Explanation:
Q50. The hexadecimal number (3E8)16 is equal to decimal number ………
1. 1000
2. 982
3. 768
4. 323
Answer : 1
Explanation: 3 x 162 + 14 x 161 + 8 = 1000
Q51. The number of distinct Boolean expression of 4 variables is …….

1. 16
2. 256
3. 1024
4. 65536
Answer : 4
Explanation:
Q52. For the K map in the given figure the simplified Boolean expression is ……

Answer : 1
Explanation:
Q53. A memory system of size 16 k bytes is to be designed using memory chips which have
12 address lines and 4 data lines each. The number of such chips required to design the
memory system is ……….
1. 2
2. 4
3. 8
4. 18
Answer : 3
Explanation:
(16×1024×8)/(4096×4) = 8
Q54. In a 7 segment display, LEDs b and c lit up. The decimal number displayed is ……….
1. 9
2. 7
3. 3
4. 1
Answer : 1
Q55. In a BCD to 7 segment decoder the minimum and maximum number of outputs active
at any time is ….
1. 2 and 7
2. 3 and 7
3. 1 and 6
4. 3 and 6
Answer: 1
Explanation:
Minimum number of outputs when input is decimal 1 and maximum number of outputs when
input is decimal 8.
Q56. A three state switch has three outputs. These are …….. , …….. , ……….
1. low, low and high

2. low, high, high
3. low. floating, low
4. low, high, floating
Answer: 4
Q57. Maxterm designation for A + B + C is ……….
1. M0
2. M1
3. M3
4. M4
Answer: 1
Explanation: A + B + C = 000 = M0
Q58. 1’s complement of 11100110 is ……………….
1. 00011001
2. 10000001
3. 00011010
4. 00000000
Answer: 1
Explanation: By replacing 1 by 0 and 0 by 1.

Logic Gates and Networks – 1
This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses
on “Logic Gates and Networks – 1”.
1. The output of a logic gate is 1 when all the input are at logic 0 as shown below:
INPUT OUTPUT
A B C
0 0 1
0 1 0
1 0 0
1 1 0
INPUT OUTPUT
A B C
0 0 1
0 1 0
1 0 0
1 1 1
The gate is either

a) A NAND or an EX-OR
b) An OR or an EX-NOR
c) An AND or an EX-OR
d) A NOR or an EX-NOR
View Answer
Answer: d
Explanation: The output of a logic gate is 1 when all inputs are at logic 0. The gate is either a
NOR or an EX-NOR. (The truth tables for NOR and EX-NOR Gates are shown in above figure.)
2. The code where all successive numbers differ from their preceding number by single bit is
a) Binary code
b) BCD
c) Excess 3
d) Gray
View Answer
Answer: d
Explanation: The code where all successive numbers differ from their preceding number by
single bit is gray code. It is an unweighted code. The most important characteristic of this code is
that only a single bit change occurs when going from one code number to next.
3. The following switching functions are to be implemented using a decoder:

f1 = ∑m(1, 2, 4, 8, 10, 14) f2 = ∑m(2, 5, 9, 11) f3 = ∑m(2, 4, 5, 6, 7)
The minimum configuration of decoder will be
a) 2 to 4 line
b) 3 to 8 line
c) 4 to 16 line
d) 5 to 32 line
View Answer
Answer: c
Explanation: 4 to 16 line decoder as the minterms are ranging from 1 to 14.
4. How many AND gates are required to realize Y = CD + EF + G ?

a) 4
b) 5
c) 3
d) 2
View Answer
Answer: d
Explanation: To realize Y = CD + EF + G, two AND gates are required.
5. The NOR gate output will be high if the two inputs are
a) 00
b) 01
c) 10
d) 11
View Answer
6. How many two-input AND and OR gates are required to realize Y = CD+EF+G?
a) 2, 2
b) 2, 3
c) 3, 3
View Answer
Answer: a
Explanation: Y = CD + EF + G
The number of two input AND gate = 2
The number of two input OR gate = 2.
7. A universal logic gate is one which can be used to generate any logic function. Which of the
following is a universal logic gate?
a) OR
b) AND
c) XOR
d) NAND
View Answer
Answer: d
Explanation: NAND can generate any logic function.
8. A full adder logic circuit will have

a) Two inputs and one output
b) Three inputs and three outputs
c) Two inputs and two outputs
d) Three inputs and two outputs
View Answer
Answer: d
Explanation: A full adder circuit will add two bits and it will also accounts the carry input
generated in the previous stage. Thus three inputs and two outputs (Sum and Carry) are there.
9. How many two input AND gates and two input OR gates are required to realize Y = BD + CE
+ AB?
a) 1, 1
b) 4, 2
c) 3, 2
d) 2, 3
View Answer
Answer: a
Explanation: There are three product terms. So, three AND gates of two inputs are required. As
only two input OR gates are available, so two OR gates are required to get the logical sum of
three product terms.
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10. Which of following are known as universal gates?

a) NAND & NOR
b) AND & OR
c) XOR & OR
View Answer
Answer: a
Explanation: The NAND & NOR gates are known as universal gates because any digital circuit
can be realized completely by using either of these two gates.
11. The gates required to build a half adder are

a) EX-OR gate and NOR gate
b) EX-OR gate and OR gate
c) EX-OR gate and AND gate
d) Four NAND gates
View Answer
Answer: c
Explanation: The gates required to build a half adder are EX-OR gate and AND gate.

Logic Gates and Networks – 2
This set of Digital Electronic Circuits Inteview Questions and Answers for freshers focuses on
“Logic Gates and Networks-2”.
1. A single transistor can be used to build which of the following digital logic gates?
a) AND gates
b) OR gates
c) NOT gates
d) NAND gates
View Answer
Answer: c
Explanation: A transistor can be used as a switch. That is, when base is low collector is high
(input zero, output one) and base is high collector is low (input 1, output 0).
2. How many truth table entries are necessary for a four-input circuit?
a) 4
b) 8
c) 12
d) 16
View Answer
Answer: d
Explanation: For 2 inputs: 2^2 = 4 truth table entries are necessary.
3. Which input values will cause an AND logic gate to produce a HIGH output?
a) At least one input is HIGH
b) At least one input is LOW
c) All inputs are HIGH
d) All inputs are LOW
View Answer
Answer: c
Explanation: For AND gate, the output is high only when both inputs are high. That’s why the
high output in AND will occurs only when all the inputs are high.
4. Exclusive-OR (XOR) logic gates can be constructed from what other logic gates?
a) OR gates only
b) AND gates and NOT gates
c) AND gates, OR gates, and NOT gates
d) OR gates and NOT gates
View Answer
Answer: c
Explanation: Expression for XOR is: A.(B’)+(A’).B
so in the above expression the following logic gates are used: AND, OR, NOR.
5. The basic logic gate whose output is the complement of the input is the:
a) OR gate
b) AND gate
c) INVERTER gate
d) Comparator
View Answer
Answer: c
Explanation: It is also called NOT gate and it simply inverts the input.
6. The AND function can be used to ___________ and the OR function can be used to
_____________
a) Enable, disable
b) Disable, enable
c) Synchronize, energize
d) Detect, invert
View Answer
Answer: a
Explanation: Because of their multiplicity and additivity property respectively.
7. The dependency notation “>=1” inside a block stands for which operation?
a) OR
b) XOR
c) AND
d) XNOR
View Answer
Answer: a
Explanation: The dependency notation “>=1” inside a block stands for OR operation.
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8. If we use an AND gate to inhibit a signal from passing one of the inputs must be
a) LOW
b) HIGH
c) Inverted
d) Floating
View Answer
Answer: a
Explanation: AND gate means A*B and OR gate means A+B and to inhibit means to get low
signal, one of the input must be low. It means (0*1=0 or 1*0=0) we will get low output signal.
9. Logic gate circuits contain predictable gate functions that open theirs
a) Outputs
b) Inputs
c) Pre-state
View Answer
Answer: b
Explanation: Logic gate circuits contain predictable gate functions that open their inputs because
we are free to give any types of inputs.
10. How many NAND circuits are contained in a 7400 NAND IC?
a) 1
b) 2
c) 4
d) 8
View Answer
Answer: c
Explanation: 7400 IC’s pin has total 14 pin. Pin no 7 use for GND and pin no 14 used for +vcc
and remaining pins used for connections. For a NAND gate two inputs are required and one
output is obtained means for NAND gate 3 pin connections are required.
1. The format used to present the logic output for the various combinations
of logic inputs to a gate is called a(n):
Correct Truth Table.

Answer:
2. The logic gate that will have HIGH or "1" at its output when any one of
its inputs is HIGH is a(n):
Correct OR gate
Answer:
3. Which of the following equations would accurately describe a 4-input

OR gate when A = 1, B = 1, C = 0 and D = 0?
1+1+0+0=0
Your Answer:
Correct 1 + 1 + 0 + 0 = 1
Answer:
4. A NAND gate has:
Correct active high inputs and an active low output.

Answer:
5. A small circle on the output of a logic gate is used to represent the:
NOT operation.
Your
Answer:
6. Which timing diagram shown in Figure 3-1 is correct for an inverter?

Figure 3-1
Correct b
Answer:
7. Which of the symbols shown in Figure 3-2 represents an AND gate?
Figure 3-2
Correct D
Answer:
8. For a three-input AND gate, with the input waveforms as shown in

Figure 3-3, which output waveform is correct?
Figure 3-3
Correct c
Answer:
9. Which of the figures in Figure 3-4 represents an OR gate?
Figure 3-4
Correct a
Answer:
10 For a three-input OR gate, with the input waveforms as shown in Figure

. 3-5, which output waveform is correct?
Figure 3-5
Correct b
Answer:
11 Which of the figures in Figure 3-6 represents a NAND gate?

.
Correct a
Answer:
12 For a 3-input NAND gate, with the input waveforms as shown in Figure
. 3-7, which output waveform is correct?
c
Your
Answer:
13 Which of the figures in Figure 3-8 represents a NOR gate?

.
Correct d
Answer:
14 For a three-input NOR gate, with the input waveforms as shown in

. Figure 3-9, which output waveform is correct?
Correct a
Answer:
15 Which of the examples below expresses the associative law of addition:

.
A + (B + C) = (A + B) + C
Your
Answer:
16 Which of the examples below expresses the distributive law?

.
Correct A(B + C) = AB + AC
Answer:
17 Which of the following is based on DeMorgan's theorems?

.
Correct
Answer:
18 Which of the figures (a-d) is the DeMorgan equivalent of Figure 3-10e?

.
Correct a
Answer:
19
Simplify the expression using DeMorgan's theorems.
.
Your Answer:
Correct
Answer:
20 The Boolean equation for a NOR function is:

.
Correct
Answer:
21 A NOR gate with one HIGH input and one LOW input:
.
Correct will output a LOW
Answer:
22 Which logic gate does this truth table describe?

.
NOR
Your
Answer:
23 Which step in this reduction process is using DeMorgan's theorem?

.
Correct STEP 1
Answer:
24 An OR gate with inverted inputs functions as:

.
Correct a NAND.
Answer:
25 Which is not an HDL suited for programming simple programmable

. devices?
Correct VHSIC
Answer:
26 The special software application that translates from HDL into a grid of
.
1's and 0's, which can be loaded into a PLD, is called a:
compiler
Your
Answer:
27 In VHDL, the mode of a port does not define:

.
Correct the TYPE of the bit.
Answer:
28 What is the basic difference between AHDL and VHDL?

.
Correct ADHL is proprietary.
Answer:
29 In VHDL, how are the statements between BEGIN and END evaluated?
.
Correct concurrently
Answer:
Basic Logic Gates - MCQs with answers
Q1. Which component in an inverter circuit plays a crucial role in the removal of minority charge
carriers at base specifically due to sudden variation of signal between logic states?
a. Load Resistor
b. Base Inductor
c. Capacitor
d. None of the above
View Answer / Hide Answer
ANSWER: c. Capacitor
Q2. Which of the below stated application/s employ Ex-OR gate from the arithmetic functioning point
of view?
a. Matching Circuit
b. Equality Detector
c. Inequality Comparator
d. All of the above
ANSWER: d. All of the above
Q3. Which gates are sequentially cascaded or involved in an entire logic-array of AND-OR-INVERT
(AOI) configuration?
a. AND-OR-AND
b. AND-OR-NOT
c. AND-OR-NOR
d. AND-OR-EX-OR
ANSWER: b. AND-OR-NOT

Combinational Circuits
on “Combinational Circuits”.
1. Which of the circuits in figure (a to d) is the sum-of-products implementation of figure (e)?
a) a
b) b
c) c
d) d
View Answer
Answer: d
Explanation: Here, the diagram of option d contains the OR gate followed by the AND gates, so
it is in SOP form.
2. Which of the following logic expressions represents the logic diagram shown?
a) X=AB’+A’B
b) X=(AB)’+AB
c) X=(AB)’+A’B’
d) X=A’B’+AB
View Answer
Answer: d
Explanation: 1st output of AND gate is = A’B’
2nd AND gate’s output is = AB and,
OR gate’s output is = (A’B’)+(AB) = AB + A’B’.
3. The device shown here is most likely a ________
a) Comparator
b) Multiplexer
c) Inverter
d) Demultiplexer
View Answer
Answer: d
Explanation: The given diagram is demultiplexer, because it takes single input & gives many
outputs.
4. What type of logic circuit is represented by the figure shown below?
a) XOR
b) XNOR
c) AND
d) XAND
View Answer
Answer: b
Explanation: After solving the circuit we get (AB)’+AB as output, which is XNOR operation.
5. For a two-input XNOR gate, with the input waveforms as shown below, which output
waveform is correct?
a) d
b) a
c) c
d) b
View Answer
Answer: a
Explanation: When both inputs are same then the o/p is high for a XNOR gate.
i.e., A B O/P
001
010
100
1 1 1.
6. Which of the following combinations of logic gates can decode binary 1101?
a) One 4-input AND gate
b) One 4-input AND gate, one inverter
c) One 4-input AND gate, one OR gate
d) One 4-input NAND gate, one inverter
View Answer
Answer: b
Explanation: For decoding any number output must be high for that code and this is possible in
D option only.
7. What is the indication of a short to ground in the output of a driving gate?

a) Only the output of the defective gate is affected
b) There is a signal loss to all load gates
c) The node may be stuck in either the HIGH or the LOW state
d) The affected node will be stuck in the HIGH state
View Answer
Answer: b
Explanation: Short to ground in the output of a driving gate indicates of a signal loss to all load
gates.
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8. For the device shown here, assume the D input is LOW, both S inputs are LOW and the input
is LOW. What is the status of the Y’ outputs?
a) All are HIGH

b) All are LOW
c) All but are LOW
d) All but are HIGH
View Answer
Answer: d
Explanation: In the given diagram, S0 and S1 are selection bits. So,
I/P S0 S1 O/P
D = 0 0 0 Y0
D = 0 0 1 Y1
D = 0 1 0 Y2
D = 0 1 1 Y3
Hence, inputs are S0 and S1 are Low means 0, so output is Y0.
9. The carry propagation can be expressed as ________

a) Cp = AB
b) Cp = A + B
c) Cp = A XOR B
d) Cp = A + B’
View Answer
Answer: b
Explanation: This happens in parallel adders (where we try to add numbers in parallel via more
than one adders). A carry propagation occurs when carry from one adder needs to be forwarded
to other adder and that second adder is holding the computation (addition) because carry from
first adder has not come yet. So, there is a slight delay for second adder and this is known as
carry propagation.
10. 3 bits full adder contains

a) 3 combinational inputs
b) 4 combinational inputs
c) 6 combinational inputs
d) 8 combinational inputs
View Answer
Answer: d
Explanation: Three bits full adder requires 2^3 = 8 combinational circuits.
1. How many 3-line-to-8-line decoders are required for a 1-of-32 decoder?
A
1
.
B.2
C.4
D
8
.
Answer: Option C
Explanation:
No answer description available for this question. Let us discuss.

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2. Which of the figures shown below represents the exclusive-NOR gate?

A
a
.
B.b
C.c
D
d
.
Answer: Option B
Explanation:

3. Which of the circuits in figure (a to d) is the sum-of-products implementation of figure (e)?

A
a
.
B.b
C.c
D
d
.
Answer: Option D
Explanation:

4. For the device shown here, let all D inputs be LOW, both S inputs be HIGH, and the input
be LOW. What is the status of the Y output?
A
LOW
.
B.HIGH
C.Don't Care
D
Cannot be determined
.
Answer: Option A
Explanation:

5. For the device shown here, let all D inputs be LOW, both S inputs be HIGH, and the
input be HIGH. What is the status of the Y output?
A
LOW
.
B.HIGH
C.Don't Care
D
Cannot be determined
.
Answer: Option A
Explanation:

21. In VHDL, macrofunctions is/are:
A
digital circuits.
.
B.analog circuits.
C.a set of bit vectors.
D
preprogrammed TTL devices.
.
Answer: Option D
Explanation:

22. Which of the following expressions is in the product-of-sums form?

A
(A + B)(C + D)
.
B.(AB)(CD)
C.AB(CD)
D
AB + CD
.
Answer: Option A
Explanation:

23. Which of the following is an important feature of the sum-of-products form of expressions?

A
All logic circuits are reduced to nothing more than simple AND and OR operations.
.
B.The delay times are greatly reduced over other forms.
C.No signal must pass through more than two gates, not including inverters.
D The maximum number of gates that any signal must pass through is reduced by a factor of
. two.
Answer: Option A
Explanation:

24. For the device shown here, assume the D input is LOW, both S inputs are LOW, and the
input is LOW. What is the status of the outputs?
A
All are HIGH.
.
B.All are LOW.
C. All but are LOW.
D
. All but are HIGH.
Answer: Option D
Explanation:

25. An output gate is connected to four input gates; the circuit does not function. Preliminary
tests with the DMM indicate that the power is applied; scope tests show that the primary
input gate has a pulsing signal, while the interconnecting node has no signal. The four load
gates are all on different ICs. Which instrument will best help isolate the problem?
A
Current tracer
.
B.Logic probe
C.Oscilloscope
D
Logic analyzer
.
Answer: Option A
Explanation:

16. For the device shown here, assume the D input is LOW, both S inputs are HIGH, and the
input is HIGH. What is the status of the outputs?
A
All are HIGH.
.
B.All are LOW.
C. All but are LOW.
D
. All but are HIGH.
Answer: Option A
Explanation:

17. Which of the following combinations cannot be combined into K-map groups?

A
Corners in the same row
.
B.Corners in the same column
C.Diagonal corners
D
Overlapping combinations
.
Answer: Option C
Explanation:

18. As a technician you are confronted with a TTL circuit board containing dozens of IC chips.
You have taken several readings at numerous IC chips, but the readings are inconclusive
because of their erratic nature. Of the possible faults listed, select the one that most probably
is causing the problem.
A
A defective IC chip that is drawing excessive current from the power supply
.
B.A solar bridge between the inputs on the first IC chip on the board
C.An open input on the first IC chip on the board
D A defective output IC chip that has an internal open to Vcc
.
Answer: Option C
Explanation:

19. Which gate is best used as a basic comparator?

A
NOR
.
B.OR
C.Exclusive-OR
D
AND
.
Answer: Option C
Explanation:

20. The device shown here is most likely a ________.
A
comparator
.
B.multiplexer
C.demultiplexer
D
parity generator
.
Answer: Option C
Explanation:

11. The simplest equation which implements the K-map shown below is:
A
.
B.
C.
D
.
Answer: Option A
Explanation:

12. How many 1-of-16 decoders are required for decoding a 7-bit binary number?
A
5
.
B.6
C.7
D
8
.
Answer: Option D
Explanation:

13. Which of the following logic expressions represents the logic diagram shown?
A
.
B.
C.
D
.
Answer: Option D
Explanation:

14. The implementation of simplified sum-of-products expressions may be easily implemented

into actual logic circuits using all universal ________ gates with little or no increase in
circuit complexity. (Select the response for the blank space that will BEST make the
statement true.)
A
AND/OR
.
B.NAND
C.NOR
D
OR/AND
.
Answer: Option B
Explanation:

15. Which of the following statements accurately represents the two BEST methods of logic
circuit simplification?
A
Boolean algebra and Karnaugh mapping
.
B.Karnaugh mapping and circuit waveform analysis
C.Actual circuit trial and error evaluation and waveform analysis
D
Boolean algebra and actual circuit trial and error evaluation
.
Answer: Option A
Explanation:

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Home » Engineering » Digital Electronics » Combinational Logic Circuits » General Questions
Exercise :: Combinational Logic Circuits - General Questions
 Combinational Logic Circuits - General Questions

 Combinational Logic Circuits - True or False
 Combinational Logic Circuits - Filling the Blanks
6. Convert BCD 0001 0010 0110 to binary.

A.1111110
B.1111101
C.1111000
D
1111111
.
Answer: Option A
Explanation:
7. A 74HC147 priority encoder has ten active-LOW inputs and four active-LOW outputs. What
would be the state of the four outputs if inputs 4 and 5 are LOW and all other inputs are
HIGH?
A.
B.
C.
D
.
Answer: Option A
Explanation:
8. Convert BCD 0001 0111 to binary.

A.10101
B.10010
C.10001
D
11000
.
Answer: Option C
Explanation:
9. Which of the figures in figure (a to d) is equivalent to figure (e)?

A.a
B.b
C.c
D
d
.
Answer: Option B
Explanation:
10. How many data select lines are required for selecting eight inputs?
A.1
B.2
C.3
D
4
.
Answer: Option C
Explanation:
One application of a digital multiplexer is to facilitate:
 1. parity checking
 2. code conversion
 3. parallel-to-serial data conversion
 4. data generation
1) Which is the simplified equation of output for K-map consisting of four adjacent ones,
given below?
a. A B
b. BD
c. CD
d. ABD
Answer Explanation
ANSWER: CD
Explanation:
No explanation is available for this question!
2) Which is the correct order of sequence for representing the input values in K-map?
a. (00, 01, 10, 11)

b. (00, 10, 01, 11)
c. (00, 01, 11, 10)
d. (00, 10, 11, 01)
Answer Explanation
ANSWER: (00, 01, 11, 10)
Explanation:
3) Which code is used for labeling the cells of K-map?
a. Binary
b. Gray
c. BCD
d. ASCII
Answer Explanation
ANSWER: Gray
Explanation:
4) Which is the correct boolean expression for the logic circuit given below?
a. Y = (A.B) (A+ B) (A+C)

b. Y = (A.B) / (A + B) (A + C)
c. Y = (A.B) / (A + B) (A + C)
d. Y = (A.B)(A + B)(A+C)
Answer Explanation
ANSWER: Y = (A.B) (A+ B) (A+C)
Explanation:
5) For the given truth-table, what is the logical expression in the standard SOP form?
a. Y = Σm (0,1)
b. Y = Σm (1,2)
c. Y = Σm (2,3)
d. Y = Σm (3,4)
Answer Explanation
ANSWER: Y = Σm (1,2)
Explanation:
6) Which is the correct sequential order of operational steps executed in the

combinational logic circuits?
A. Operation of combinational gates over the inputs

B. Acceptance of n-different inputs
C. Generation of 'm' different outputs as per the required level
a. A, B, C
b. A, C, B
c. B, A, C
d. C, A, B
Answer Explanation
ANSWER: B, A, C
Explanation:
7) How is the relation specified between input and output in logic circuits?
a. Switching equations
b. Truth-table
c. Logic diagram
d. All of the above
Answer Explanation
ANSWER: All of the above
Explanation:
8) Which De Morgan's theorem states that the complement of a sum is equal to the
product of complements?
a. AB = A + B
b. A+B = A. B
c. A+B = A.B
d. AB = A + B
Answer Explanation
ANSWER: A+B = A. B
Explanation:
9) What does the below stated OR Law imply, while performing OR operation of an input
with '1'?
Expression of OR Law: A+ 1 = 1
a. Output will always be equal to input

b. Output will always be high
c. Output will always be low
d. Output will always be same
Answer Explanation
ANSWER: Output will always be high
Explanation:
10) Which kind of logical operation is performed by the gate shown below?

a. Logical Multiplication
b. Inversion
c. Addition/ Subtraction
d. NOT EXOR
Answer Explanation
ANSWER: Addition/ Subtraction
Explanation:
1. A ripple counter's speed is limited by the propagation delay of:
A
each flip-flop
.
B.all flip-flops and gates
C.the flip-flops only with gates
D
only circuit gates
.
Answer: Option A
Explanation:

2. To operate correctly, starting a ring counter requires:

A
clearing all the flip-flops
.
B.presetting one flip-flop and clearing all the others
C.clearing one flip-flop and presetting all the others
D
presetting all the flip-flops
.
Answer: Option B
Explanation:

3. What type of register would shift a complete binary number in one bit at a time and shift all
the stored bits out one bit at a time?
A
PIPO
.
B.SISO
C.SIPO
D
PISO
.
Answer: Option B
Explanation:

4. Synchronous counters eliminate the delay problems encountered with asynchronous (ripple)
counters because the:
A
input clock pulses are applied only to the first and last stages
.
B.input clock pulses are applied only to the last stage
C.input clock pulses are not used to activate any of the counter stages
D
input clock pulses are applied simultaneously to each stage
.
Answer: Option D
Explanation:

5. One of the major drawbacks to the use of asynchronous counters is that:

A
low-frequency applications are limited because of internal propagation delays
.
B.high-frequency applications are limited because of internal propagation delays
Asynchronous counters do not have major drawbacks and are suitable for use in high- and
C.
low-frequency counting applications.
D Asynchronous counters do not have propagation delays, which limits their use in high-
. frequency applications.
Answer: Option B
Explanation:

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Digital Circuits Questions and Answers – Flip

Flops – 1
on “Flip Flops – 1”.
1. Latches constructed with NOR and NAND gates tend to remain in the latched condition due to
which configuration feature?
a) Low input voltages
b) Synchronous operation
c) Gate impedance
d) Cross coupling
View Answer
Answer: d
Explanation: Both inputs of a latch are directly connected to the other’s output. Such types of
structure is called cross coupling and due to which latches remain in the latched condition.
2. One example of the use of an S-R flip-flop is as:

a) Transition pulse generator
b) Racer
c) Switch debouncer
d) Astable oscillator
View Answer
Answer: c
Explanation: The SR flip-flop is very effective in removing the effects of switch bounce.
3. The truth table for an S-R flip-flop has how many VALID entries?
a) 1
b) 2
c) 3
d) 4
View Answer
Answer: c
Explanation: The SR flip-flop actually has three inputs, Set, Reset and its current state.
4. When both inputs of a J-K flip-flop cycle, the output will

a) Be invalid
b) Change
c) Not change
d) Toggle
View Answer
Answer: c
Explanation: After one cycle the value of each input comes to the same value. Eg: Assume J=0
and K=1. After 1 cycle, it becomes as J=0->1->0(1 cycle complete) and K=1->0->1(1 cycle
complete).
5. Which of the following is correct for a gated D-type flip-flop?

a) The Q output is either SET or RESET as soon as the D input goes HIGH or LOW
b) The output complement follows the input when enabled
c) Only one of the inputs can be HIGH at a time
d) The output toggles if one of the inputs is held HIGH
View Answer
Answer: a
Explanation: In D flip flop, when the clock is high then the out depends on the input otherwise
reminds previous output. In a state of clock high, when D is high the output Q also high, if D is
‘0’ then output is also zero.
6. A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates?
a) AND or OR gates
b) XOR or XNOR gates
c) NOR or NAND gates
d) AND or NOR gates
View Answer
Answer: c
Explanation: The basic S-R flip-flop can be constructed by cross coupling of NOR or NAND
gates.
7. The logic circuits whose outputs at any instant of time depends only on the present input but
also on the past outputs are called
a) Combinational circuits
b) Sequential circuits
c) Latches
d) Flip-flops
View Answer
Answer: b
Explanation: In sequential circuits, the output signals are fed back to the input side. So, The
circuits whose outputs at any instant of time depends only on the present input but also on the
past outputs are called sequential circuits.
8. Whose operations are more faster among the following?

a) Combinational circuits
b) Sequential circuits
c) Latches
d) Flip-flops
View Answer
Answer: a
Explanation: Combinational circuits are often faster than sequential circuits. Since, the
combinational circuits do not require memory elements whereas the sequential circuits need
memory devices to perform their operations in sequence.
9. How many types of sequential circuits are?

a) 2
b) 3
c) 4
d) 5
View Answer
Answer: a
Explanation: There are two type of sequential circuits viz., (i) synchronous or clocked and (ii)
asynchronous or unclocked.
10. The sequential circuit is also called

a) Flip-flop
b) Latch
c) Strobe
View Answer
Answer: b
Explanation: The sequential circuit is also called a latch because both are a memory cell, which
are capable of storing one bit of information.
11. The basic latch consist of

a) Two inverters
b) Two comparators
c) Two amplifiers
View Answer
Answer: a
Explanation: The basic latch consist of two inverters. It is in the sense that if the output Q = 0
then the second output Q’ = 1 and vice versa.
12. If Q = 0, the output is said to be

a) Set
b) Reset
c) Previous state
d) Current state
View Answer
Answer: a
Explanation: If Q = 0, the output is said to be set and reset for Q’ = 1.
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13. The output of latches will remain in set/reset untill

a) The trigger pulse is given to change the state
b) Any pulse given to go into previous state
c) They don’t get any pulse more
View Answer
Answer: a
Explanation: The output of latches will remain in set/reset untill the trigger pulse is given to
change the state.
14. What is a trigger pulse?

a) A pulse that starts a cycle of operation
b) A pulse that reverses the cycle of operation
c) A pulse that prevents a cycle of operation
View Answer
Answer: a
Explanation: Trigger pulse is defined as a pulse that starts a cycle of operation.
15. The circuits of NOR based S-R latch classified as asynchronous sequential circuits, why?
a) Because of inverted outputs
b) Because of triggering functionality
c) Because of cross-coupled connection
d) Both a & b
View Answer
Answer: c
Explanation: The cross-coupled connections from the output of one gate to the input of other
gate constitute a feedback path. For this reason, the circuits of NOR based S-R latch classified as
asynchronous sequential circuits.
Sequential Logic Circuits - MCQs with answers
Q1. Which sequential circuits generate the feedback path due to the cross-coupled connection from
output of one gate to the input of another gate?
a. Synchronous
b. Asynchronous
c. Both
ANSWER: b. Asynchronous
Q2. What is/are the crucial function/s of memory elements used in the sequential circuits?
a. Storage of binary information

b. Specify the state of sequential
c. Both a & b
ANSWER: c. Both a & b
Q3. How are the sequential circuits specified in terms of time sequence?
a. By Inputs
b. By Outputs
c. By Internal states
d. All of the above

ANSWER: d. All of the above
Q4. The behaviour of synchronous sequential circuit can be predicted by defining the signals at
______.
a. discrete instants of time

b. continuous instants of time
c. sampling instants of time
d. at any instant of time
ANSWER: a. discrete instants of time
Question 1 of 13
1. Question
1 points
A ripple counter’s speed is limited by the propagation delay of:
 1. the flip-flops only with gates
 2. each flip-flop
 3. only circuit gates
 4. all flip-flops and gates
Incorrect

Digital Circuits Demultiplexer Questions

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Digital Circuits Questions and Answers –

Demultiplexers (Data Distributors) – 2

1. Why is a demultiplexer called a data distributor?

2. Most demultiplexers facilitate which type of conversion?

3. In 1-to-4 demultiplexer, how many select lines are required?

4. In a multiplexer the output depends on its

5. In 1-to-4 multiplexer, if C1 = 1 & C2 = 1, then the output will be

6. How many select lines are required for a 1-to-8 demultiplexer?

7. How many AND gates are required for a 1-to-8 multiplexer?

8. Which IC is used for the implementation of 1-to-16 DEMUX?

Both SRAM and DRAM

02․ Which number system has a base of 16

Decimal base = 10, Octal base = 8. Hexadecimal base = 16 ( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F ).

03․ A latch is ________ sensitive

both level and edge

Y = 2n Y is number of Entries in the truth table, while n is the number of inputs.

LSB, Least Significant Bit

08․ A D-flip-flop is said to be transparent when

the output is LOW

the output is HIGH

the output follows clock

the output follow input

XOR, NOR, NAND.

OR, NOT, AND.

NOR, NAND, XNOR.

10․ Which one of the following is not a vectored interrupt?

01․ In the toggle mode a JK flip-flop has

J = 0, K = 0; no change condition between pre-state and next state. J = 0, K = 1; it is always reset

Hexadecimal number system is a base-16 number system ( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D,

GAL is Generic Array Logic. It is a re programmable device used in Digital Systems.

In binary, 1 kilo means 210, which is equal to 1024.

A logical diagram can be constructed from a Boolean function representing input/output by

De Morgans Law or De Morgans Theorem is the basics of the Boolean Algebra.

Q1. The binary number 10101 is equivalent to decimal number …………..

Q2. The universal gate is ………………

Q3. The inverter is ……………

Q5. The NOR gate is OR gate followed by ………………

Q6. The NAND gate is AND gate followed by …………………

Q7. Digital circuit can be made by the repeated use of ………………

Q8. The only function of NOT gate is to ……………..

Q10. In Boolean algebra, the bar sign (-) indicates ………………..

Q12. 2’s complement of binary number 0101 is ………..

Explanation: 1’s complement of 0101 is 1010 and 2’s complement is 1010+1 = 1011.

Explanation: In OR any input high means high output.

Q14. Decimal number 10 is equal to binary number ……………

Q15. Both OR and AND gates can have only two inputs.

Explanation: Any number of inputs are possible.

Q16. A device which converts BCD to seven segments is called ……..

Explanation: Decoder converts binary/BCD to alphanumeric.

A = 11100101. Therefore Ā = 00011010 and A’ = Ā + 1 = 00011011 = 16 + 8 + 2 + 1 = 27.

Q18. A decade counter skips ………..

1. binary states 1000 to 1111

Explanation: 1000 equals decimal 8 Therefore all segments will lit up.

Explanation: If A = 0, Y = 1 and A = 1, Y = 0 Therefore Y = Ā.

Q23. The circuit in the given figure is a ………… gate.

1. positive logic OR gate

Q24. Which of the following is non-saturating?

Q25. The number of digits in octal system is ………

Explanation: The octal system has 8 digits 0 to 7.

Explanation: Access time = 0.95 x 10 + 0.05 x 100.

Q27. The expression Y = pM (0, 1, 3, 4) is …………..

Explanation: This is a product of sums expression.

Q29. Decimal 43 in hexadecimal and BCD number system is respectively……. and ……..