library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity CLK is
Port ( CLKIN : in STD_LOGIC;
CLKOUT : out STD_LOGIC);
end CLK;

architecture Behavioral of CLK is

signal Q: integer range 0 to 49999999;
signal state: std_logic;
begin
CLKOUT <= state;
process(CLKIN)
begin
if(CLKIN'event and CLKIN = '1') then
if( Q = 25000000) then
Q <= 0;
state <= not state;
else
Q <= Q + 1;
end if;
end if;
end process;
end Behavioral;
-----------------------------------------------------------------------------------
---------
library IEEE;
use IEEE.std_logic_1164.all;

entity DECODIFICADOR is
port (
a, b, c, d, e, f, g : out std_logic;
S3, S2, S1, S0 : in std_logic
);
end entity;

architecture arch of DECODIFICADOR is

begin

process (S3, S2, S1, S0)

variable SALIDA : std_logic_vector (6 downto 0);
variable ENTRADA : std_logic_vector (3 downto 0);
begin
ENTRADA(3) := S3;
ENTRADA(2) := S2;
ENTRADA(1) := S1;
ENTRADA(0) := S0;

if ENTRADA = "0000" then SALIDA := "0000001"; -- 0

elsif ENTRADA = "0001" then SALIDA := "1001111"; -- 1
elsif ENTRADA = "0010" then SALIDA := "0010010"; -- 2
elsif ENTRADA = "0011" then SALIDA := "0000110"; -- 3
elsif ENTRADA = "0100" then SALIDA := "1001100"; -- 4
elsif ENTRADA = "0101" then SALIDA := "0100100"; -- 5
elsif ENTRADA = "0110" then SALIDA := "1100000"; -- 6
 elsif ENTRADA = "0111" then SALIDA := "0001111"; -- 7
elsif ENTRADA = "1000" then SALIDA := "0000000"; -- 8
elsif ENTRADA = "1001" then SALIDA := "0001100"; -- 9
else SALIDA := "UUUUUUU";
end if;
a <= SALIDA(6);
b <= SALIDA(5);
c <= SALIDA(4);
d <= SALIDA(3);
e <= SALIDA(2);
f <= SALIDA(1);
g <= SALIDA(0);

end process;

end architecture;

-----------------------------------------------------------------------------------
----------------------
jk
library ieee;
use ieee. std_logic_1164.all;
use ieee. std_logic_arith.all;
use ieee. std_logic_unsigned.all;

entity JK_FF is
PORT( J,K,CLOCK: in std_logic;
Q, QB: out std_logic);
end JK_FF;

Architecture behavioral of JK_FF is

begin
PROCESS(CLOCK)
variable TMP: std_logic;
begin
if(CLOCK='1' and CLOCK'EVENT) then
if(J='0' and K='0')then
TMP:=TMP;
elsif(J='1' and K='1')then
TMP:= not TMP;
elsif(J='0' and K='1')then
TMP:='0';
else
TMP:='1';
end if;
end if;
Q<=TMP;
Q <=not TMP;
end PROCESS;
end behavioral;
---------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity funciones_mapas is
Port ( q3n : in STD_LOGIC;
q2n : in STD_LOGIC;
q1n : in STD_LOGIC;
 q0n : in STD_LOGIC;
q3 : in STD_LOGIC;
q2 : in STD_LOGIC;
q1 : in STD_LOGIC;
q0 : in STD_LOGIC;
y : in STD_LOGIC;
j0 : out STD_LOGIC;
k0 : out STD_LOGIC;
j1 : out STD_LOGIC;
k1 : out STD_LOGIC;
j2 : out STD_LOGIC;
k2 : out STD_LOGIC;
j3 : out STD_LOGIC;
k3 : out STD_LOGIC);
end funciones_mapas;

architecture Behavioral of funciones_mapas is

begin
process(y)
begin
if (y='1') then
j0 <= ((q3n) and (q1n) and (q0n) );
j1 <= ((q3n) and (q1n) and (q0n) );
j2 <= (((q1) and (q0))or ((q3)and(q0n)));
j3 <= ((q2) and (q1) );
k0 <= ((q3n) and (q2n) and (q0) );
k1 <= ((q2) and (q1) );
k2 <= ((q2) and (q1) );
k3 <= (q3);
elsif (y='0')then
j0 <= (((q3n)and (q2n)and(q1n))or((q2)and(q1)));
j1 <= (q3);
j2 <= (q3);
j3 <= (((q2)and (q1n)and(q0n))or((q2n)and(q1n)and(q0)));
k0 <= ((q1)and (q0));
k1 <= ((q1)and (q0));
k2 <= (((q1n)and (q0n))or((q2)and(q1)and(q0n)));
k3 <= q3;
end if;
end process;

end Behavioral;